Semiconductor devices and electronic devices

Abstract

Embodiments of the present application provide a semiconductor device and electronic apparatus, relating to the field of microelectronics technology, which can improve the tensile properties of semiconductor devices, thereby reducing the probability of performance deterioration or failure of the semiconductor devices. The semiconductor device comprises: a flexible substrate having at least one groove disposed on its surface; at least one semiconductor nanowire disposed within each groove, the semiconductor nanowire extending along the groove without adhesion between the semiconductor nanowire and the flexible substrate; each groove comprising a first accommodating region, a second accommodating region, and a third accommodating region arranged sequentially along its length, the groove width of the second accommodating region being greater than the groove width of the first accommodating region and the groove width of the third accommodating region, and the groove width being the distance between the two sidewalls of the groove.

Description

Technical Field

[0001] The present application relates to the field of microelectronics technology, and in particular to a semiconductor device and an electronic apparatus. Background Art

[0002] With the development of electronic products, more and more electronic products, especially electronic products including display screens, have flexible and bendable mechanical properties, and have good applications in scenarios such as health monitors, artificial skin, and wearable devices. Semiconductor devices are an important component of electronic products. For example, in transistors, channels are realized through semiconductor structures, and the channels in transistors play a decisive role in transistor performance. Current transistor channels can be made using nanowires, for example, but current transistors have poor tensile properties. In flexible and bendable application scenarios, semiconductor devices are easily damaged due to poor tensile properties, which leads to deterioration of the performance of semiconductor devices or even failure. Summary of the Invention

[0003] The technical solution of the present application provides a semiconductor device and an electronic device, which can improve the tensile performance of the semiconductor device, thereby reducing the probability of performance deterioration or failure of the semiconductor device.

[0004] In a first aspect, the technical solution of the present application provides a semiconductor device, comprising:

[0005] A flexible substrate, wherein at least one groove is provided on a surface of the flexible substrate;

[0006] At least one semiconductor nanowire is disposed in each groove, there is no adhesion between the semiconductor nanowire and the flexible substrate, and the semiconductor nanowire extends along the groove;

[0007] Each groove includes a first accommodating area, a second accommodating area and a third accommodating area arranged in sequence in its length direction. The groove width of the second accommodating area is greater than the groove width of the first accommodating area and the groove width of the third accommodating area. The groove width is the distance between the two side walls of the groove.

[0008] In one possible embodiment, two semiconductor nanowires are disposed in each trench;

[0009] Each groove includes a first side wall and a second side wall opposite to each other, the first side wall protrudes in the second accommodating area in a direction away from the second side wall, and the second side wall protrudes in the second accommodating area in a direction away from the first side wall;

[0010] In the first accommodating region and the third accommodating region of each trench, one semiconductor nanowire extends along the first sidewall, and another semiconductor nanowire extends along the second sidewall.

[0011] In a possible implementation manner, the first sidewall and the second sidewall in each trench are symmetrically arranged.

[0012] In one possible embodiment, the one of the two semiconductor nanowires closer to the first side wall is a first nanowire, the distance between the first nanowire and the first side wall in the first accommodating region is smaller than the distance between the first nanowire and the first side wall in the second accommodating region, and the distance between the first nanowire and the first side wall in the third accommodating region is smaller than the distance between the first nanowire and the first side wall in the second accommodating region; the one of the two semiconductor nanowires closer to the second side wall is a second nanowire, the distance between the second nanowire and the second side wall in the first accommodating region is smaller than the distance between the second nanowire and the second side wall in the second accommodating region, and the distance between the second nanowire and the second side wall in the third accommodating region is smaller than the distance between the second nanowire and the second side wall in the second accommodating region.

[0013] In a possible implementation, in the first accommodating region, the second accommodating region, and the third accommodating region of each trench, one semiconductor nanowire extends along the first sidewall, and another semiconductor nanowire extends along the second sidewall.

[0014] In a possible implementation, a plurality of grooves arranged in parallel are provided on the surface of the flexible substrate, and each groove has the same structure.

[0015] In a possible implementation, a plurality of grooves arranged in parallel are provided on the surface of the flexible substrate, and the positions of the second accommodating areas of the plurality of grooves are staggered with each other.

[0016] In one possible embodiment, the semiconductor device further includes: an insulating dielectric layer located on the surface of the flexible substrate, at least a portion of each semiconductor nanowire is located between the insulating dielectric layer and the flexible substrate; and the Young's modulus of the insulating dielectric layer is smaller than the Young's modulus of the flexible substrate.

[0017] In one possible embodiment, the semiconductor device further includes: an insulating dielectric layer located on the surface of the flexible substrate, at least a portion of each semiconductor nanowire being located between the insulating dielectric layer and the flexible substrate; and in the second accommodating area, the insulating dielectric layer and the semiconductor nanowires are spaced apart.

[0018] In one possible embodiment, each semiconductor nanowire includes two ends and a middle portion located between the two ends;

[0019] The semiconductor device further includes a gate covering a middle portion of the at least one semiconductor nanowire, with an insulating dielectric layer located between the middle portion and the gate;

[0020] The semiconductor device further includes a source and a drain, wherein the source is connected to one end of the at least one semiconductor nanowire, and the drain is connected to the other end of the at least one semiconductor nanowire.

[0021] In one possible implementation, the material of the flexible substrate includes polyimide, polyamide-imide, or nitrile-based resin.

[0022] In a possible implementation, the material of the insulating dielectric layer includes polydimethylsiloxane, polymethyl methacrylate, or thermoplastic polyurethane.

[0023] In a second aspect, the technical solution of the present application provides an electronic device comprising the above-mentioned semiconductor device.

[0024] The semiconductor device and electronic device in the embodiments of the present application are configured such that a groove is provided on a flexible substrate so that the semiconductor nanowire extends along the groove, and the groove width of the second accommodating region located in the middle portion is smaller than the width of the adjacent groove. In this way, when the semiconductor nanowire is stretched, the margin provided by the groove width in the second accommodating region allows the semiconductor nanowire to be stretched and deformed relative to the flexible substrate, thereby releasing the tension caused by the stretching process, thereby improving the tensile performance of the semiconductor device and reducing the probability of performance deterioration or failure of the semiconductor device due to bending. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;

[0026] Figure 2a This is a top view of a flexible substrate in an embodiment of the present application;

[0027] Figure 2b for Figure 2a Schematic diagram of a structure after catalytic metal deposition in the middle structure;

[0028] Figure 2c for Figure 2b A schematic diagram of a structure after the catalytic metal is treated by the middle structure;

[0029] Figure 2d for Figure 2c Schematic diagram of a structure after depositing an amorphous precursor in the medium structure;

[0030] Figure 2e for Figure 2d Schematic diagram of a structure after the growth of semiconductor nanowires in the mesostructure;

[0031] Figure 2f for Figure 2e A schematic diagram of the structure after removing excess amorphous precursor from the middle structure;

[0032] Figure 3 for Figure 2a to Figure 2f The cross-sectional structural diagrams of the figures are shown in sequence;

[0033] Figure 4a for Figure 1 A schematic diagram of a state of the middle structure in a stretched state;

[0034] Figure 4b for Figure 2f A schematic diagram of a state of the middle structure in a stretched state;

[0035] Figure 5a This is a schematic structural diagram of another semiconductor device in an embodiment of the present application;

[0036] Figure 5b This is a schematic structural diagram of another semiconductor device according to an embodiment of the present application;

[0037] Figure 6a for Figure 1 A schematic diagram of a structure after the insulating matrix layer is deposited in the middle structure;

[0038] Figure 6b for Figure 6a A schematic diagram of a cross-sectional structure;

[0039] Figure 6c for Figure 6a Another cross-sectional structural diagram of ;

[0040] Figure 7 for Figure 6a Schematic diagram of the structure after the source, drain and gate are deposited in the middle structure;

[0041] Figure 8a This is a schematic structural diagram of another semiconductor device according to an embodiment of the present application;

[0042] Figure 8b for Figure 8a A schematic diagram of a cross-sectional structure in the CC' direction;

[0043] Figure 9 Schematic diagram of the structure of two semiconductor nanowires in the embodiment of this application;

[0044] Figure 10a This is a schematic diagram of a semiconductor nanowire and trench structure in an embodiment of the present application;

[0045] Figure 10b This is a schematic diagram of another semiconductor nanowire and trench structure in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0047] Before introducing the embodiments of the present application, the problem discovery process of the prior art is first described. In order to improve the tensile performance of semiconductor devices, one method in the prior art is to make a curved channel by laser cutting. However, this channel is directly deposited on the bottom and adheres to the substrate. Compared with the substrate, the thickness of the channel is very small. Therefore, when the overall structure including the channel is bent, the stress generated by the adhesion between the channel and the substrate causes the channel to have poor tensile performance. In addition, laser cutting will degrade the edge of the channel, which will have an adverse effect on the conductive performance of the channel. Another method in the prior art is to provide a deformation by pre-stretching the substrate, prepare straight nanowires on the deformed substrate, and then compress the nanowires by releasing the substrate, thereby preparing nanowires with a curved morphology. However, the nanowires obtained by pre-stretching have large stresses, and the structure will change over time, resulting in unstable performance. The orientation of the obtained nanowires is random, making it difficult to use as a channel for a transistor. Based on the above problems, the inventors provide the technical solution of the present application. The embodiments of the technical solution of the present application are described below.

[0048] like Figure 1 As shown, an embodiment of the present application provides a semiconductor device, including: a flexible substrate 1, wherein at least one groove 11 is provided on the surface of the flexible substrate 1; at least one semiconductor nanowire 2 is provided in each groove 11, and there is no adhesion between the semiconductor nanowire 2 and the flexible substrate 1, and the semiconductor nanowire 2 extends along the groove 11; each groove 11 includes a first accommodating area P1, a second accommodating area P2 and a third accommodating area P3 arranged in sequence in its length direction, and the groove width W2 of the second accommodating area P2 is greater than the groove width W1 of the first accommodating area P1 and the groove width W3 of the third accommodating area P3, and the groove width is the distance between the two side walls of the groove 11.

[0049] Specifically, if Figures 2a to 2e and Figure 3 As shown, the following is a detailed description of the preparation process of the semiconductor device Figure 1 The structure shown in FIG, the preparation process of the semiconductor device includes:

[0050] Step 101: Figure 1 、 Figure 2a and Figure 3 As shown, a flexible substrate 1 is formed, and at least one groove 11 is formed on the surface of the flexible substrate 1;

[0051] Specifically, the material of the flexible substrate 1 may be a high-temperature resistant polymer such as polyimide, polyamide-imide, or nitrile resin. For example, a groove 11 with a depth of 80 nm to 800 nm, for example, 100 nm, is formed on the surface of the flexible substrate 1 using techniques such as photolithography and etching. The groove 11 may be formed using a dry etching process such as photolithography, inductively coupled plasma (ICP) etching, or reactive ion etching (RIE) etching, or a wet etching process using an alkaline etching system such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), an acidic etching system such as hydrofluoric acid + nitric acid (HF + HNO3), hydrofluoric acid + nitric acid + acetic acid (HF + HNO3 + CH3COOH), or an ethylenediamine catechol (EDP) etching system. For the flexible substrate 1 made of organic polymer material, all its components can react with O 2 , and the ICP process can be used to generate O 2 plasma to bombard the portion not protected by the photoresist mask, thereby forming a groove 11 with a definable morphology on the flexible substrate 1 .

[0052] Step 102: Figure 1 、 Figure 2b and Figure 3 As shown, a catalytic metal 3 is formed in the trench 11. The catalytic metal 3 may be, for example, indium In.

[0053] Step 103: Figure 2c and Figure 3 As shown, in an environment where the temperature is above the melting point of the catalytic metal 3, the catalytic metal 3 is treated with plasma to remove the oxide layer on the surface of the catalytic metal 3 and convert the catalytic metal 3 into a discrete liquid state catalytic metal 3, that is, from Figure 2b becomes Figure 2c For example, the flexible substrate 1 on which the catalytic metal 3 is deposited is placed in a plasma enhanced chemical vapor deposition (PECVD) apparatus, the temperature is raised to above the melting point of the catalytic metal 3 (approximately 200° C.), and the surface oxide layer of the catalytic metal 3 is treated using H2 plasma for, for example, 3 to 20 minutes. The catalytic metal 3 is then converted into discrete droplets of catalytic metal 3 in, for example, 3 minutes.

[0054] Step 104: Figure 1 、 Figure 2d and Figure 3 As shown, an amorphous precursor 4 is deposited on the surface of the flexible substrate 1 , and the amorphous precursor 4 contacts the catalytic metal 3 and covers the groove 11 ;

[0055] For example, the amorphous precursor 4 is deposited to a thickness of 2 nm to 100 nm in a temperature range of room temperature to 150° C., for example, the amorphous precursor 4 is deposited to a thickness of 10 nm at 100° C.

[0056] Step 105: Figure 1 、 Figure 2e 、 Figure 2f and Figure 3 As shown, the flexible substrate 1 formed with the catalytic metal 3 and the amorphous precursor 4 is annealed to make the catalytic metal 3 move along the corresponding groove 11 and absorb the amorphous precursor 4, forming semiconductor nanowires 2 along the way. Finally, the excess amorphous precursor 4 can be removed by etching process, and the following is obtained: Figure 2f The structure shown.

[0057] The annealing process in step 105 can be performed in a non-oxygen environment, and the annealing temperature is above the melting point of the catalytic metal 3, for example, 300°C. At this time, the catalytic metal 3 droplets will melt and absorb the nearby amorphous precursor 4. When the silicon atom concentration reaches a supersaturated concentration, semiconductor nanowires 2 will precipitate at the rear end of the catalytic metal 3 droplets, and the semiconductor nanowires 2 will grow along the sidewalls of the trench 11. It should be noted that Figure 3 middle Figure 2a to Figure 2d The cross-sectional views are all schematic cross-sectional views of the structure along the AA' direction. Figure 3 middle Figure 2e and 2f The cross-sectional view is a schematic diagram of the cross-sectional structure along the BB' direction. Figures 1 to 3 In the figure, only one trench 11 and two semiconductor nanowires 2 in the trench 11 are illustrated. The embodiment of the present application does not limit the number of trenches 11 and the number of semiconductor nanowires 2 in one trench 11.

[0058] Specifically, in the semiconductor device manufactured by the above process, since the semiconductor nanowire 2 extends along the groove 11, the desired semiconductor nanowire 2 can be obtained by the morphology of the groove 11, and in the embodiment of the present application, the role of the flexible substrate 1 is only to define the shape of the semiconductor nanowire 2 by the shape of the groove 11. After the semiconductor nanowire 2 is generated, there is no adhesion between the semiconductor nanowire 2 and the flexible substrate 1. The semiconductor nanowire 2 is accommodated in the groove 11 only due to the accommodating effect of the groove 11. Since the groove width W2 of the second accommodating area P2 is greater than the groove width W1 of the first accommodating area P1 and the groove width W3 of the third accommodating area P3, and the semiconductor nanowire 2 extends along the sidewall of the groove 11 during its growth, when the semiconductor device as a whole is bent or stretched, as shown in FIG. Figure 4a and Figure 4bAs shown, the stress applied by the flexible substrate 1 to the semiconductor nanowire 2 is small, and the bent semiconductor nanowire 2 is stretched and deformed relative to the flexible substrate 1, releasing the tension caused by the stretching process, wherein the portion of the semiconductor nanowire 2 in the second accommodating area P2 is close to the middle of the groove 11.

[0059] It should be noted that, in the embodiment of the present application, the final semiconductor device product may be in an unbent or unstretched state, that is, for example, the final semiconductor device may be as follows: Figure 1 In the state shown, the semiconductor nanowire 2 extends along the sidewall of the groove 11. If the semiconductor device is bent or stretched under force, the semiconductor nanowire 2 can release the tension by deformation, so it is not easy to break, thereby improving the stretching ability of the semiconductor device. In addition, the final semiconductor device product can also be in a bent or stretched state, that is, for example, the final semiconductor device can be as follows Figure 4a and Figure 4b In the state shown, at this time, although the groove 11 will be deformed due to bending or stretching, the groove width of the second accommodating area P2 will still be kept larger than the groove width of the first accommodating area P1 and the groove width of the third accommodating area P3. As for the semiconductor nanowire 2, it is already in a stretched state, and can even be in a straightened state (the straightened state of the semiconductor nanowire is not shown in the figure). However, in the process of stretching the semiconductor nanowire 2, since the tension can be released by deformation, it is not easy to break, thereby improving the stretching ability of the semiconductor device.

[0060] The semiconductor device in the embodiment of the present application is configured such that a semiconductor nanowire extends along the groove by providing a groove on a flexible substrate, and the groove width of a second accommodating region located in the middle portion is configured to be smaller than the width of an adjacent groove. In this way, when the semiconductor nanowire is stretched, the margin provided by the groove width in the second accommodating region allows the semiconductor nanowire to be stretched and deformed relative to the flexible substrate, thereby releasing the tension caused by the stretching process, thereby improving the tensile performance of the semiconductor device and reducing the probability of performance deterioration or failure of the semiconductor device due to bending.

[0061] In one possible embodiment, two semiconductor nanowires 2 are arranged in each groove 11; each groove 11 includes a first side wall 111 and a second side wall 112 relative to each other, the first side wall 111 protrudes in the direction away from the second side wall 112 in the second accommodating area P2, and the second side wall 112 protrudes in the direction away from the first side wall 111 in the second accommodating area P2; in the first accommodating area P1 and the third accommodating area P3 of each groove 11, one semiconductor nanowire 2 extends along the first side wall 111, and the other semiconductor nanowire 2 extends along the second side wall 112.

[0062] Specifically, during the growth process of the semiconductor nanowire 2, it will grow along the side wall of the groove. Therefore, the width of the groove 11 can be set to control the presence of two semiconductor nanowires 2 in one groove 11. In addition, by setting the positions of the two side walls of the groove 11, the parts of the two semiconductor nanowires 2 in the second accommodating area P2 are made to move away from each other. In this way, when the two semiconductor nanowires are stretched, the two can approach each other in the second accommodating area P2, so as to release the tension in the stretching process through this deformation.

[0063] In one possible embodiment, the first sidewall 111 and the second sidewall 112 in each groove 11 are symmetrically arranged, so that the two grown semiconductor nanowires 2 can be symmetrically arranged and have a symmetrical structure, that is, the two semiconductor nanowires 2 can have similar characteristics. For example, when the two semiconductor nanowires 2 are used as channels of the same transistor, the performance of the transistor can be improved due to their similar characteristics.

[0064] In one possible embodiment, the final semiconductor device product is in a bent or stretched state. Before the semiconductor device is stretched, the semiconductor nanowire 2 extends along the sidewall of the trench 11. However, after the semiconductor device is stretched, the semiconductor nanowire 2 is displaced relative to the sidewall of the trench 11, such as Figure 4a and Figure 4b As shown, the one of the two semiconductor nanowires 2 that is closer to the first side wall 111 is the first nanowire, and the distance H1 between the first nanowire and the first side wall 111 in the first accommodating region P1 is smaller than the distance H2 between the first nanowire and the first side wall 111 in the second accommodating region P2, and the distance H3 between the first nanowire and the first side wall 111 in the third accommodating region P3 is smaller than the distance H2 between the first nanowire and the first side wall 111 in the second accommodating region P2; the one of the two semiconductor nanowires 2 that is closer to the second side wall 112 is the second nanowire, and the distance h1 between the second nanowire and the second side wall 112 in the first accommodating region P1 is smaller than the distance h2 between the second nanowire and the second side wall 112 in the second accommodating region P2, and the distance h3 between the second nanowire and the second side wall 112 in the third accommodating region P3 is smaller than the distance h2 between the second nanowire and the second side wall 112 in the second accommodating region P2. The distance between the nanowire and the sidewall may be an average distance. For example, H1 refers to the average distance between the first nanowire in the first accommodating region P1 and the first sidewall 111 .

[0065] In a possible embodiment, the final semiconductor device product is in a state before being bent or stretched, such as Figure 1As shown, in the first accommodating area P1, the second accommodating area P2 and the third accommodating area P3 of each groove 11, one semiconductor nanowire 2 extends along the first side wall 111, and the other semiconductor nanowire extends along the second side wall, that is, in different accommodating areas, the distance between the semiconductor nanowire 2 and the side wall is slightly different.

[0066] In one possible implementation, Figure 5a As shown, the flexible substrate surface is provided with multiple grooves 11 arranged in parallel, and each groove 11 has the same structure. In this way, multiple identical groups of semiconductor nanowires 2 can be made in the multiple grooves 11, and these semiconductor nanowires 2 can have similar properties.

[0067] In one possible implementation, Figure 5b As shown, the surface of the flexible substrate is provided with a plurality of grooves 11 arranged in parallel, and the positions of the second accommodating areas P2 of the plurality of grooves 11 are staggered with each other, that is, the shapes of the grooves 11 are not completely consistent, and the obtained semiconductor nanowires 2 are not completely the same. Since the positions of the second accommodating areas P2 are staggered with each other, the distance between different grooves 11 can be closer, which improves the overall space utilization.

[0068] In one possible implementation, Figure 6a and 6b As shown, the semiconductor device further includes: an insulating dielectric layer 5 located on the surface of the flexible substrate 1, at least a portion of each semiconductor nanowire 2 is located between the insulating dielectric layer 5 and the flexible substrate 1; the Young's modulus of the insulating dielectric layer 5 is smaller than the Young's modulus of the flexible substrate 1.

[0069] Specifically, if Figure 6a and 6b As shown, if an insulating dielectric layer 5 is directly deposited on the surface of the flexible substrate 1 provided with the semiconductor nanowire 2, the insulating dielectric layer 3 will cover the groove 11 and the surrounding of the semiconductor nanowire 2. If the Young's modulus of the insulating dielectric layer 5 is large, when the entire semiconductor device is stretched, the semiconductor nanowire 2 covered by the insulating dielectric layer 5 may be damaged by force due to the limiting effect of the insulating dielectric layer 5. In addition, if the Young's modulus of the insulating matrix layer 3 is large, the semiconductor nanowire 2 may also be damaged due to collision with the flexible substrate 1. Therefore, the Young's modulus of the insulating dielectric layer 5 is set to be smaller than the Young's modulus of the flexible substrate 1. When the semiconductor device is stretched, even if the insulating dielectric layer 5 contacts the semiconductor nanowire 2 in the groove 11, it still has a large tensile property, so that the semiconductor nanowire 2 half-covered by it deforms relative to the flexible substrate 1 when stretched, releasing the tension caused by the stretching process, that is, improving the tensile performance of the semiconductor device, thereby reducing the probability of performance deterioration or failure of the semiconductor device due to bending.

[0070] In one possible implementation, Figure 6a and Figure 6c As shown, the semiconductor device further includes: an insulating dielectric layer 5 located on the surface of the flexible substrate 1, at least a portion of each semiconductor nanowire 2 is located between the insulating dielectric layer 5 and the flexible substrate 1; in the second accommodating area P2, the insulating dielectric layer 5 and the semiconductor nanowire 2 are spaced apart.

[0071] Specifically, in order to avoid the stress effect of the insulating dielectric layer 5 on the semiconductor nanowire 2 and improve the tensile performance of the semiconductor device, the insulating dielectric layer 5 can be manufactured through an imprinting process to control the shape of the insulating dielectric layer 5, so that the insulating dielectric layer 5 and the semiconductor nanowire 2 are spaced apart to provide the semiconductor nanowire 2 with more space for free tensile deformation, thereby improving the tensile performance of the semiconductor device.

[0072] In a possible implementation, the material of the insulating dielectric layer 5 includes polydimethylsiloxane, polymethyl methacrylate, or thermoplastic polyurethane.

[0073] Specifically, the insulating dielectric layer 5 made of polydimethylsiloxane is more suitable for preparation by a spin coating process, while the insulating dielectric layer 5 made of polymethyl methacrylate or thermoplastic polyurethane is more suitable for preparation by an imprinting process. A single, uniform insulating dielectric layer 5 thin film is obtained by spin coating, and then baked at an appropriate temperature to solidify the insulating dielectric layer 5 thin film. Since the Young's modulus of the flexible substrate 1 and the semiconductor nanowires 2 is relatively large, there is no relative motion between the insulating dielectric layer 5 and the semiconductor nanowires 2, and there is no relative motion between the insulating dielectric layer 5 and the flexible substrate 1. When the insulating dielectric layer 5 is prepared by an imprinting process, the semi-cured insulating dielectric layer 5 thin film is covered on the flexible substrate 1 containing the grooves 11. The insulating dielectric layer 5 is solidified by applying pressure to the entire surface and then thermally curing. This method can reduce the obstruction of the grooves 11 on the stretching of the semiconductor nanowires 2.

[0074] In one possible implementation, Figure 1 、 Figure 6a and Figure 7 As shown, each semiconductor nanowire 2 includes two ends 21 and a middle portion 22 located between the two ends 21; the semiconductor device also includes a gate 6 covering the middle portion 22 of at least one semiconductor nanowire 2, and the insulating dielectric layer 5 is located between the middle portion 22 and the gate 6; the semiconductor device also includes a source 71 and a drain 72, the source 71 is connected to one end 21 of at least one semiconductor nanowire 2, and the drain 72 is connected to the other end 21 of at least one semiconductor nanowire 2. Figure 7The structure shown is a transistor, in which the semiconductor nanowire 2 serves as the channel of the transistor. The embodiment of the present application does not limit the specific structure of the transistor, as long as the semiconductor nanowire 2 can be used as the channel to form a transistor.

[0075] It should be noted that Figure 7 The example only illustrates the use of multiple semiconductor nanowires 2 as channels of the same transistor. In other achievable embodiments, multiple transistors can be fabricated by using multiple semiconductor nanowires 2 fabricated on the flexible substrate 1 as channels of multiple transistors, for example. Figure 8a and Figure 8b As shown, the semiconductor device includes a first source 711, a first drain 712, a second source 721, a second drain 722, a first gate 61, and a second gate 62. The semiconductor nanowire 2 includes at least one first transistor semiconductor nanowire 2 and at least one second transistor semiconductor nanowire 2. The first source 711 is connected to one end of the first transistor semiconductor nanowire 2, the first drain 712 is connected to the other end of the first transistor semiconductor nanowire 2, the second source 721 is connected to one end of the second transistor semiconductor nanowire 2, the second drain 722 is connected to the other end of the second transistor semiconductor nanowire 2, the first gate 61 covers the middle portion of the first transistor semiconductor nanowire 2, and the second gate 62 covers the middle portion of the second transistor semiconductor nanowire 2. The first transistor semiconductor nanowire 2, the first source 711, the first drain 712, and the first gate 61 constitute a transistor, and the second transistor semiconductor nanowire 2, the second source 721, the second drain 722, and the second gate 62 constitute another transistor. In addition, the embodiments of the present application only illustrate the semiconductor nanowire 2 as a transistor channel. In other feasible attempts, the role of the semiconductor nanowire may also be different depending on the semiconductor device. For other semiconductor devices besides transistors, the semiconductor nanowire 2 can be used as other structures.

[0076] If the semiconductor nanowire 2 in the embodiment of the present application is not hindered by the grooves during the stretching process, it has a larger stretching ratio, and the stretching ratio can be controlled by the shape of the semiconductor nanowire 2, such as Figure 9 As shown, Figure 9The diagram shows the shapes of two types of semiconductor nanowires 2, where the numbers marked on each segment are the relative lengths of the segments, i.e., the ratio of the absolute length to the unit length (e.g., 0.1um). The diagram includes two semiconductor nanowires, L1 and L2, where the relative length between the two ends of L1 is 8, and the relative length between the two ends of L2 is 6. Since the semiconductor nanowires do not adhere to the flexible substrate, if they are not restricted by the sidewalls of the grooves during stretching, the semiconductor nanowires have a theoretical maximum stretching length, i.e., the length of the entire nanowire when it is straightened. At this time, the maximum stretching ratio of the semiconductor nanowire L1 is The maximum stretch ratio of the semiconductor nanowire L2 is [(2+2+2+2+2)-6] / 6≈66.67%. That is, the maximum stretch ratio R of the semiconductor nanowire is equal to the ratio of the difference between the nanowire length L and the distance D between its ends, expressed as follows: R = (LD) / D. For example, for a flexible substrate 1 made of polyamide-imide material, to ensure that the flexible substrate 1 does not break, the stretch ratio r of the semiconductor nanowire 2 therein can be set to fall within the following range: 0 < r < 20%. For a flexible substrate 1 made of polyimide material, to ensure that the flexible substrate 1 does not break, the stretch ratio r of the semiconductor nanowire 2 therein can be set to fall within the following range: 0 < r < 90%. Furthermore, if the final semiconductor device product is in a bent or stretched state, since the semiconductor device only needs to be stretched once and does not need to maintain elasticity, the semiconductor nanowire can be set to have a larger maximum stretch ratio. However, if the final semiconductor device product is in a state before being bent or stretched, to maintain elasticity after multiple stretches, the semiconductor nanowire needs to have a smaller maximum stretch ratio.

[0077] It should also be noted that the above embodiments are only described using the semiconductor nanowire 2 with a "V"-shaped bend as an example. The present embodiment is not limited to the structure of the semiconductor nanowire 2. As long as it has a bend and can release tension due to the spatial arrangement of the groove 11 when stretched, it can be used. For example, Figure 10a and Figure 10b Other possible shapes of semiconductor nanowires 2 and corresponding shapes of trenches 11 are shown. Figure 10bIn the structure shown, each groove 11 includes not only the first accommodating area P1, the second accommodating area P2 and the third accommodating area P3 arranged in sequence, but also a fourth accommodating area P4 located between the second accommodating area P2 and the third accommodating area P3. The groove width of the fourth accommodating area P4 is smaller than the groove widths of the other three accommodating areas, that is, in the fourth accommodating area P4, the first side wall of the groove 11 protrudes toward the direction close to the second side wall, and the second side wall of the groove 11 protrudes toward the direction close to the first side wall. The fourth accommodating area P4 does not affect the relationship between the other accommodating areas and the semiconductor nanowire 2. The function of the fourth accommodating area P4 is to control the extension direction of the semiconductor nanowire 2 so as to control the morphology of the semiconductor nanowire 2.

[0078] The present application also provides an electronic device including the semiconductor device of the above embodiment, wherein the specific structure, principle and manufacturing method of the semiconductor device are the same as those of the above embodiment and are not described in detail here. The electronic device may be a display.

[0079] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0080] The above are merely preferred embodiments of the present application and are not intended to limit the present application. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A semiconductor device, characterized in that: include: A flexible substrate, wherein at least one groove is provided on a surface of the flexible substrate; One or two semiconductor nanowires are disposed in each of the grooves, the semiconductor nanowires are not adhered to the flexible substrate, and the semiconductor nanowires extend along the grooves; Each of the grooves includes a first accommodating area, a second accommodating area and a third accommodating area arranged in sequence in its length direction, the groove width of the second accommodating area is greater than the groove width of the first accommodating area and the groove width of the third accommodating area, and the groove width is the distance between the two side walls of the groove.

2. The semiconductor device according to claim 1, wherein Two semiconductor nanowires are arranged in each of the grooves; Each of the grooves includes a first side wall and a second side wall opposite to each other, wherein the first side wall protrudes in a direction away from the second side wall in the second accommodating area, and the second side wall protrudes in a direction away from the first side wall in the second accommodating area; In the first accommodating region and the third accommodating region of each trench, one semiconductor nanowire extends along the first sidewall, and another semiconductor nanowire extends along the second sidewall.

3. The semiconductor device according to claim 2, wherein The first side wall and the second side wall in each of the trenches are symmetrically arranged.

4. The semiconductor device according to claim 2, wherein One of the two semiconductor nanowires closer to the first sidewall is a first nanowire, a distance between the first nanowire and the first sidewall in the first accommodating region is smaller than a distance between the first nanowire and the first sidewall in the second accommodating region, and a distance between the first nanowire and the first sidewall in the third accommodating region is smaller than a distance between the first nanowire and the first sidewall in the second accommodating region; One of the two semiconductor nanowires closer to the second sidewall is a second nanowire, and the distance between the second nanowire and the second sidewall in the first accommodating region is smaller than the distance between the second nanowire and the second sidewall in the second accommodating region, and the distance between the second nanowire and the second sidewall in the third accommodating region is smaller than the distance between the second nanowire and the second sidewall in the second accommodating region.

5. The semiconductor device according to claim 2, wherein In the first accommodating region, the second accommodating region and the third accommodating region of each of the trenches, one semiconductor nanowire extends along the first sidewall, and another semiconductor nanowire extends along the second sidewall. The semiconductor device according to claim 1 , wherein: The surface of the flexible substrate is provided with a plurality of grooves arranged in parallel, and each groove has the same structure.

7. The semiconductor device according to claim 1, wherein The surface of the flexible substrate is provided with a plurality of grooves arranged in parallel, and the positions of the second accommodating areas of the plurality of grooves are staggered with each other.

8. The semiconductor device according to claim 1, wherein Also includes: an insulating dielectric layer located on a surface of the flexible substrate, wherein at least a portion of each of the semiconductor nanowires is located between the insulating dielectric layer and the flexible substrate; The Young's modulus of the insulating dielectric layer is smaller than the Young's modulus of the flexible substrate.

9. The semiconductor device according to claim 1, wherein Also includes: an insulating dielectric layer located on a surface of the flexible substrate, wherein at least a portion of each of the semiconductor nanowires is located between the insulating dielectric layer and the flexible substrate; In the second accommodating area, the insulating dielectric layer and the semiconductor nanowires are spaced apart.

10. The semiconductor device according to claim 8 or 9, characterized in that Each of the semiconductor nanowires includes two end portions and a middle portion located between the two end portions; The semiconductor device further comprises a gate covering a middle portion of at least one of the semiconductor nanowires, wherein the insulating dielectric layer is located between the middle portion and the gate; The semiconductor device further includes a source and a drain, wherein the source is connected to one end of the at least one semiconductor nanowire, and the drain is connected to the other end of the at least one semiconductor nanowire.

11. The semiconductor device according to claim 1, wherein The material of the flexible substrate includes polyimide, polyamide-imide or nitrile-based resin.

12. The semiconductor device according to claim 8, wherein The material of the insulating dielectric layer includes polydimethylsiloxane, polymethyl methacrylate or thermoplastic polyurethane.

13. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 12.

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