Power converter control circuit

Abstract

A control circuit for a power converter includes a sensing circuit, a ramp signal generating circuit, and a pulse width modulation circuit. The sensing circuit is coupled to an output circuit to provide a sensing current. The ramp signal generating circuit includes a transient circuit and a signal generating circuit. The transient circuit is coupled between the sensing circuit and the signal generating circuit to receive the sensing current and generate a variable reference voltage. The signal generating circuit provides a ramp signal based on the variable reference voltage. The pulse width modulation circuit is coupled to the ramp signal generating circuit and the output circuit and provides a pulse width modulation signal to the output circuit based on the ramp signal. When a load drop occurs, the load drop lasts for a first preset time. A transient state exists during the load drop. The transient state lasts for a second preset time, which is less than the first preset time. During the second preset time, the variable reference voltage provided by the transient circuit changes from a preset value to an adjusted value. The transient circuit then restores the variable reference voltage to the preset value after the second preset time. The present invention can increase the degree of freedom in circuit design and provide a stable output.

Description

Technical Field

[0001] The present invention relates to a power converter, and more particularly to a control circuit of the power converter. Background Art

[0002] like Figure 1 As shown, Figure 1 This power converter system utilizes output voltage VOUT for voltage feedback control and output current VOUT for current feedback control. In the voltage feedback control phase, an error amplifier EA and a compensation circuit COM generate a compensation signal COMP based on the output voltage VOUT and a reference voltage VREF. In the current feedback control phase, the system adds information about the total output current IL (the sum of the output currents IL1 and IL2 of each phase) to a ramp signal RAMP to modify the waveform of the ramp signal RAMP. Furthermore, a comparator CP compares the compensation signal COMP with the ramp signal COMP to generate a pulse-width modulation signal PWM, which controls the output circuit OS to convert the input voltage VIN into the output voltage VOUT.

[0003] like Figure 1 and Figure 2 As shown, the power converter adds information about the total output current (inductor current) IL to the ramp signal RAMP in the form of a DC offset (OFF). At time t1, a transient occurs due to an external load. The total output current IL increases to supply the current required by the external load, while the output voltage VOUT also drops due to the external load. At this point, the compensation signal COMP, which is related to the output voltage VOUT, increases due to the drop in output voltage VOU. The DC offset provided by the total output current IL also causes the ramp signal RAMP to increase. Because the amplitude of the ramp signal RAMP is fixed, the intersection of the compensation signal COMP and the ramp signal RAMP is also increased. This feedback control causes the output voltage VOUT to droop. In other words, the system does not need to forcefully increase the output voltage VOUT during transients, thus eliminating ringing in the output voltage VOUT and quickly stabilizing the output voltage VOUT, effectively shortening the transient response.

[0004] However, due to the system's headroom (the voltage difference between the operating voltage VCC and ground), the aforementioned technical disadvantage is that the ramp signal RAMP increases with the degree of unloading of the output current IL and remains elevated during the unloading period from time t1 to time t5. Once the unloading is excessive, the position of the ramp signal RAMP is limited by the operating voltage VCC and reaches its upper limit, resulting in the load being limited and unable to increase further. Specifically, because the amplitude of the ramp signal RAMP remains constant and is limited by the operating voltage VCC, when the unloading is heavier, the information of the output current IOUT cannot be fully superimposed on the ramp signal RAMP due to insufficient headroom, causing the aforementioned current feedback control mechanism to become abnormal and unable to eliminate the ringing phenomenon. Even if it enters a steady state at time t4, the output voltage VOUT still cannot return to the level before the unloading. It is not until time t5 that the feedback control and output return to normal operation. From the above, it can be seen that the circuit design of the prior art is limited by the headroom, resulting in the system's output capability to cope with unloading being limited. Summary of the Invention

[0005] In view of this, the present invention proposes a control circuit for a power converter to effectively solve the above-mentioned problems encountered in the prior art.

[0006] According to a specific embodiment of the present invention, a control circuit for a power converter is provided. In this embodiment, the control circuit is coupled to an output circuit. The control circuit includes a sensing circuit, a ramp signal generating circuit, and a pulse width modulation circuit. The sensing circuit is coupled to the output circuit to provide a current sensing signal. The ramp signal generating circuit includes a transient circuit and a signal generating circuit. The transient circuit is coupled between the sensing circuit and the signal generating circuit. The transient circuit receives the current sensing signal and generates a variable reference voltage. The signal generating circuit provides a ramp signal based on the variable reference voltage. The pulse width modulation circuit is coupled to the ramp signal generating circuit and the output circuit and provides a pulse width modulation signal to the output circuit based on the ramp signal. When a load drop occurs, the load drop lasts for a first predetermined time. A transient state occurs during the load drop. The transient state lasts for a second predetermined time, which is less than the first predetermined time. During the second predetermined time, the variable reference voltage provided by the transient circuit changes from a predetermined value to an adjusted value. After the second predetermined time, the transient circuit restores the variable reference voltage to the predetermined value.

[0007] In one embodiment of the present invention, the transient circuit includes a filter, and the variable reference voltage is a peak voltage of the ramp signal.

[0008] In one embodiment of the present invention, the transient circuit includes a filter. The filter is coupled to the sensing circuit and receives a reference voltage and a current sensing signal to generate a variable reference voltage.

[0009] In one embodiment of the present invention, the filter includes a resistor and a capacitor, and the second predetermined time is related to a resistor-capacitor delay generated by the resistor and the capacitor.

[0010] In one embodiment of the present invention, a transient circuit includes a filter and a signal conversion circuit. The filter includes a resistor and a capacitor. The resistor and capacitor are connected in series between a ground terminal and a sense voltage. The sense voltage is related to a current sense signal. The signal conversion circuit is coupled to a first node and a second node at both ends of the resistor, respectively, to provide a variable reference voltage based on a voltage difference between the first node and the second node.

[0011] In one embodiment of the present invention, the second predetermined time is related to a resistor-capacitor delay generated by the resistor and the capacitor.

[0012] Compared to the prior art, the peak voltage of the ramp signal in the control circuit of the power converter of the present invention returns to a preset voltage as the transient state ends and the device enters a steady state. This prevents the ramp signal from causing control loop failure due to load reduction. This overcomes the drawback of conventional ramp signals, which are limited by the operating voltage (VCC) margin, significantly increasing circuit design flexibility. Furthermore, the control circuit of the power converter of the present invention maintains output current feedback control during heavy load reduction, thereby providing stable output.

[0013] The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. 1 is a functional block diagram of a power converter in the prior art.

[0015] Figure 2 FIG. 1 is a transient response waveform diagram of a power converter in the prior art.

[0016] Figure 3 and Figure 4 These are different embodiments of the control circuit of the present invention applied to single-phase and two-phase power converters.

[0017] Figure 5 FIG. 4 is a transient response waveform diagram of the power converter in the present invention.

[0018] Figure 6 This is another embodiment of the transient circuit of the present invention.

[0019] Figure 7 for Figure 6 Embodiments of a signal conversion circuit in a transient circuit.

[0020] Description of main component symbols:

[0021] VCC: operating voltage

[0022] t1~t6: time

[0023] 2, 3: Control circuit of power converter

[0024] 20, 30: Sensing circuit

[0025] 21, 31: Pulse width modulation circuit

[0026] 22, 32: Ramp signal generation circuit

[0027] 23, 33: Error amplifier

[0028] 24, 34: Comparator

[0029] 25, 35: Pulse width modulation logic circuit

[0030] 200, 300, 302: Amplifier

[0031] 202, 304, 306: Current mirror

[0032] 220, 320: Transient circuit

[0033] 222, 322: Signal generating circuit

[0034] CSP, CSP1, CSP2: Current indication signal

[0035] CSN, CSN1, CSN2: current indication signal

[0036] IL, IL1, IL2: sensing current

[0037] VL: sensing voltage

[0038] R: resistance

[0039] GND: Ground

[0040] 221, 321, 60, 70: Filter

[0041] C, C2: capacitors

[0042] VREF: preset voltage

[0043] N1, N2: nodes

[0044] ACV: variable reference voltage

[0045] VB: voltage source

[0046] SW: switch

[0047] TRIG: trigger signal

[0048] INO: Current Source

[0049] VEAP: reference voltage

[0050] VFB: output feedback voltage

[0051] ERR: Error amplification signal

[0052] 26, 36: Compensation circuit

[0053] COMP: compensation signal

[0054] RAMP: Ramp signal

[0055] PWM: Pulse Width Modulation signal

[0056] OS, OS1, OS2: output circuit

[0057] D1: Driver

[0058] D2: Driver

[0059] M1: switch

[0060] M2: switch

[0061] VIN: input voltage

[0062] L: output inductance

[0063] IOUT: output current

[0064] VOUT: output voltage

[0065] R1: voltage divider resistor

[0066] R2: voltage divider resistor

[0067] RESR: output resistance

[0068] COUT: output capacitor

[0069] SCC: Signal Conversion Circuit

[0070] 6: Transient Circuit

[0071] VN1: node voltage

[0072] BF1: Voltage Follower

[0073] BF2: Voltage Follower

[0074] M: switch

[0075] CM: Current Mirror

[0076] R3: resistor

[0077] R4: resistor DETAILED DESCRIPTION

[0078] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Elements / components using the same or similar reference numerals in the drawings and embodiments are intended to represent the same or similar parts.

[0079] A specific embodiment of the present invention is a control circuit for a power converter. In this embodiment, the control circuit can be applied to a single-phase or multi-phase power converter, depending on actual needs.

[0080] Please refer to Figure 3 , Figure 3 The schematic diagram of the control circuit of the power converter is applied to a single-phase power converter. Figure 3 As shown, the power converter's control circuit 2 is coupled to the output circuit OS. Voltage divider resistors R1 and R2 are connected in series between the output circuit OS and the ground terminal GND. An output capacitor COUT and an output resistor RESR, equivalent to its parasitic resistance, are also connected in series between the output circuit OS and the ground terminal GND.

[0081] The output circuit OS includes drivers D1-D2, switches M1-M2, and an output inductor L. Driver D1 is coupled between control circuit 2 and the control terminal of switch M1. Driver D2 is coupled between control circuit 2 and the control terminal of switch M2. Switches M1 and M2 are connected in series between input voltage VIN and ground GND. One end of the output inductor L is coupled between switches M1 and M2, and the other end of the output inductor L is coupled to the output resistor RESR and the voltage divider resistor R1.

[0082] The control circuit 2 includes a sensing circuit 20, a pulse-width modulation circuit 21, and a ramp signal generating circuit 22. The pulse-width modulation circuit 21 includes an error amplifier 23, a comparator 24, a pulse-width modulation logic circuit 25, and a compensation circuit 26. The sensing circuit 20 is coupled to the output circuit OS and the ramp signal generating circuit 22. The ramp signal generating circuit 22 is coupled to the sensing circuit 20 and one input of the comparator 24. One input of the error amplifier 23 is coupled between resistors R1 and R2, and the other input receives a reference voltage VEAP. The output of the error amplifier 23 is coupled to the compensation circuit 26. The compensation circuit 26 is coupled to the other input of the comparator 24. The output of the comparator 24 is coupled to the pulse-width modulation logic circuit 25. The pulse-width modulation logic circuit 25 is coupled to the output circuit OS.

[0083] The error amplifier 23 receives a reference voltage VEAP and a power converter output feedback voltage VFB at its two input terminals to provide an error amplified signal ERR. The compensation circuit 26 is coupled to the error amplifier 23 and the comparator 24 to compensate the error amplified signal ERR to generate a compensation signal COMP.

[0084] The output feedback voltage VFB received at an input terminal of the error amplifier 23 is the divided voltage generated by the voltage-dividing resistors R1 and R2 according to the output voltage VOUT of the power converter, but the present invention is not limited thereto. The error amplifier 23 is a trans-impedance amplifier and provides an error amplified signal ERR in the form of a current, but the present invention is not limited thereto.

[0085] The sensing circuit 20 is configured to receive current indication signals CSP / CSN related to the output current IOUT of the output circuit OS and provide a current sensing signal. In this embodiment, the current indication signals CSP / CSN are voltage-type current indication signals. The sensing circuit 20 includes an amplifier 200 and a current mirror 202. Amplifier 200 receives the current indication signals CSP / CSN at its two input terminals and outputs a comparison result to control a current mirror 351 with a 1:1 ratio to generate a current sensing signal (i.e., sensed current IL) in the form of a current.

[0086] In practical applications, the resistor R is coupled between the current mirror 202 and the ground terminal GND. When the sensing current IL output by the current mirror 202 flows through the resistor R, a current sensing signal (ie, sensing voltage VL) in the form of a voltage is generated at the terminal where the resistor R is coupled to the current mirror 202.

[0087] The ramp signal generating circuit 22 includes a transient circuit 220 and a signal generating circuit 222. The transient circuit 220 is coupled between the sensing circuit 20 and the signal generating circuit 222 to receive the sensing current IL provided by the sensing circuit 20 and provide a variable reference voltage ACV to the signal generating circuit 222 when a transient caused by a load drop occurs. The signal generating circuit 222 provides a ramp signal RAMP to an input terminal of the comparator 24 based on the variable reference voltage ACV.

[0088] When a transient occurs due to a load drop, the variable reference voltage ACV provided by the transient circuit 220 changes from a preset value to an adjusted value during the transient, and then gradually returns to the preset value. In other words, the variable reference voltage ACV, originally at the preset value, changes to the adjusted value during a transient to cope with the load drop, but then immediately and gradually returns from the adjusted value to the original preset value. This avoids the drawback of the ramp signal RAMP being limited by its margin, significantly increasing the degree of freedom in circuit design.

[0089] In this embodiment, the transient circuit 220 includes a filter 221 and a voltage source VB. The filter 221 is coupled to the sensing circuit 20 and the signal generating circuit 222. When the filter 221 receives the sensing voltage VL and the preset voltage VREF provided by the voltage source VB, the filter 221 filters the sensing voltage VL and superimposes the filtered sensing voltage VL on the preset voltage VREF to generate a variable reference voltage ACV for the signal generating circuit 222. In other words, a transient state occurs during a load removal operation for a first preset time. The transient state lasts for a second preset time, which is less than the first preset time. During the second preset time, the reference voltage ACV changes from the preset value to the adjusted value and then returns to the preset value after the second preset time.

[0090] The filter 221 can be a high-pass filter (HPF) formed by a resistor R and a capacitor C2. The resistor R is coupled between the voltage source VB and the node N1. One end of the capacitor C is coupled to the node N1, and the other end of the capacitor C is coupled between the current mirror 202 and the resistor R. It is worth noting that the resistor-capacitor delay generated by the selection of the resistor R and the capacitor C can be used to set a second predetermined time for the reference voltage ACV to gradually change from the adjusted value to the predetermined value.

[0091] In this embodiment, the signal generating circuit 222 includes a switch SW, a capacitor C, and a current source INO. The switch SW is coupled between the transient circuit 220 and an input terminal of the comparator 24. It receives a reference voltage ACV and is controlled by a trigger signal TRIG provided by the comparator 24. When the trigger signal TRIG turns on the switch SW, the ramp signal RAMP is reset to the voltage level of the reference voltage ACV. In other words, the reference voltage ACV is used as the peak voltage of the ramp signal RAMP. One end of the capacitor C is coupled between the switch SW and the comparator 24, and the other end is coupled to the ground terminal GND. The capacitance of the capacitor C determines the amplitude of the ramp signal RAMP. One end of the current source INO is coupled between the switch SW and the comparator 24, and the other end is coupled to the ground terminal GND. This discharges the capacitor C, thereby generating the ramp signal RAMP with a decreasing slope.

[0092] Two input terminals of the comparator 24 receive the ramp signal RAMP and the compensation signal COMP respectively, and generate a trigger signal TRIG to the PWM logic circuit 25 and the signal generating circuit 222 in the signal generating circuit 222 .

[0093] Next, the PWM logic circuit 25 provides a PWM signal PWM to the output circuit OS based on the trigger signal TRIG to control the operation of the output circuit OS. Specifically, when drivers D1 and D2 in the output circuit OS receive the PWM signal PWM, drivers D1 and D2 control the on and off states of switches M1 and M2, respectively, based on the PWM signal PWM. This controls the inductor current IL in the output inductor L and generates the output voltage VOUT.

[0094] Next, please refer to Figure 4 , Figure 4 FIG. 1 is a schematic diagram of a power converter control circuit applied to a dual-phase power converter. Figure 4 As shown, the control circuit 3 is coupled to the output circuits OS1-OS2. Voltage divider resistors R1 and R2 are connected in series between the output circuits OS1-OS2 and the ground terminal GND. The output capacitor COUT and the output resistor RESR, which is equivalent to its parasitic resistance, are also connected in series between the output circuits OS1-OS2 and the ground terminal GND.

[0095] The control circuit 3 includes a sensing circuit 30 , a ramp signal generating circuit 32 , an error amplifier 33 , a compensation circuit 36 ​​, a comparator 34 and a pulse width modulation logic circuit 35 , which are the same as the corresponding components of the control circuit 2 described above and are not described in detail herein.

[0096] In this embodiment, the PWM logic circuit 35 generates PWM signals PWM1 - PWM2 to the output circuits OS1 - OS2 according to the trigger signal TRIG to control the operation of the output circuits OS1 - OS2 . The sensing circuit 30 includes amplifiers 300 , 302 and current mirrors 304 , 306 .

[0097] Amplifier 300 receives two input terminals of current indication signals CSP1 / CSN1 related to the output current of output circuit OS1 and outputs a comparison result to control a 1:1 current mirror 304 to generate a sense current IL1 for output circuit OS1. Similarly, amplifier 302 receives two input terminals of current indication signals CSP2 / CSN2 related to the output current of output circuit OS2 and outputs a comparison result to control a 1:1 current mirror 306 to generate a sense current IL2 for output circuit OS2. Sense circuit 30 outputs sense current IL, the sum of sense currents IL1 and IL2, to ramp signal generator 32.

[0098] In practical applications, one end of the resistor R is coupled to the current mirror 304 and the current mirror 306, respectively, and the other end thereof is coupled to the ground GND. The sense current IL, which is the sum of the sense current IL1 and the sense current IL2, flows through the resistor R and forms a sense voltage VL at one end of the resistor R. In addition to the aforementioned single-phase and dual-phase power converters, the control circuit of the present invention can also be applied to multi-phase power converters by analogy without specific limitation.

[0099] Please refer to Figure 5 , Figure 5 This is a transient response waveform diagram of the dual-phase power converter of the present invention. It should be noted that, Figure 5 Compared with existing technology Figure 2 The two-phase power converters in this example are all dual-channel devices, operating under the same load conditions (assuming each channel supplies 35 amps of inductor current IL1-IL2, resulting in a total inductor current IL of 70 amps (not shown). The amplitude of the ramp signal RAMP is 0.75 volts, and the operating voltage VCC is 4 volts.

[0100] like Figure 5 As shown, before time t1, since the load has not yet started, the inductor currents IL1-IL2 of the two channels have not increased, so that the output voltage VOUT, the compensation signal COMP and the ramp signal RAMP all maintain a stable state, and the peak voltage of the ramp signal RAMP (i.e., the reference voltage ACV) is lower than the operating voltage VCC (4V).

[0101] At time t1, load removal begins, and the inductor currents IL1-IL2 of both channels increase (i.e., the sum of the inductor current IL also increases). This causes the output voltage VOUT to decrease due to the load removal. The compensation signal COMP then increases as the output voltage VOUT decreases. After increasing, the reference voltage ACV gradually returns to its preset value.

[0102] During the period from t2 to t3, the feedback information from the inductor current IL causes the reference voltage ACV to be greater than the operating voltage VCC (4V), resulting in a limited waveform of the ramp signal RAMP. Therefore, during this period, the ramp signal RAMP can only be controlled by the feedback information from the output voltage VOUT. It should be noted that during the period from t2 to t3, the feedback information from the inductor current IL has no effect on the ramp signal RAMP. Therefore, the performance of the power converter during this period is the same as that of the prior art. However, because the transient circuit 220 in the ramp signal generating circuit 22 causes the reference voltage ACV to gradually return to the preset voltage of 3.75V immediately after the transient occurs, the period from t2 to t3 is very short.

[0103] At time t3 , the reference voltage ACV is lower than the operating voltage VCC (4V). At this time, the feedback information of the inductor current IL is added to the feedback control, so that the output voltage VOUT does not have a ringing phenomenon.

[0104] At time t4, the output voltage VOUT has climbed to the same level as Figure 2 The output voltage level (1.09 V) of the prior art is shown as the same as when it enters the steady state. At time t5, the transient state ends, the output voltage VOUT has recovered to the steady-state output voltage level (1.1 V) before the load is removed, and the ramp signal RAMP and the compensation signal COMP both tend to be stable.

[0105] As can be seen from the above description, during the unloaded period of the first predetermined time (time t1 to time t6), the control circuit of the power converter of the present invention adjusts the peak voltage of the ramp signal RAMP after the transient state, so that the intersection point of the ramp signal RAMP and the compensation signal COMP gradually recovers to a stable value over time during the transient state of the second predetermined time (time t1 to time t5). As a result, the peak voltage of the ramp signal RAMP is not limited by the operating voltage VCC, thereby enhancing the flexibility of circuit design. In other words, the control circuit of the power converter of the present invention can effectively eliminate ringing of the output voltage VOUT during heavy load withdrawal, thereby providing a stable output.

[0106] Please refer to Figure 6 In another embodiment, the transient circuit 6 includes a filter 60 and a signal conversion circuit SCC. The filter 60 includes a resistor R and a capacitor C, which are connected in series between the ground terminal GND and the sensing voltage VL. The resistor R is located between nodes N1 and N2. The capacitor C is coupled between node N1 and the ground terminal GND. The signal conversion circuit SCC is coupled to nodes N1 and N2 and a preset voltage VREF, respectively. Node N2 is coupled to the sensing voltage VL. The signal conversion circuit SCC converts the sensing voltage VL into a variable reference voltage ACV based on the voltage variation between nodes N1 and N2 across the resistor R, which is used as the peak voltage of the ramp signal RAMP. When the power converter is in a steady state, the voltage across the resistor R is zero, so the variable reference voltage ACV is the preset voltage VREF.

[0107] Please refer to Figure 7In another embodiment, the transient circuit 7 includes a filter 70 and a signal conversion circuit SCC. The filter 70 includes a resistor R and a capacitor C. The resistor R is located between nodes N1 and N2. The capacitor C is coupled between node N1 and ground GND. The signal conversion circuit SCC includes voltage followers BF1-BF2, resistors R3-R4, a switch M, and a current mirror CM. An input terminal of the voltage follower BF1 is coupled to node N2, and an input terminal of the voltage follower BF2 is coupled to node N1. The other input terminal and the output terminal of the voltage follower BF2 are both coupled to one terminal of the resistor R3. The other terminal of the resistor R3 is coupled to the other input terminal of the voltage follower BF1 and one terminal of the switch M. The output terminal of the voltage follower BF1 is coupled to the control terminal of the switch M. The other terminal of the switch M is coupled to the input terminal of the current mirror CM. The resistor R4 is coupled between the output terminal of the current mirror CM and a preset voltage VREF. A node N3 between the resistor R4 and the current mirror CM outputs a variable reference voltage ACV.

[0108] When the power converter is in a steady state, the voltages at the nodes N1 and N2 are equal, so that the voltages across the resistors R, R3, and R4 are all zero. Therefore, the variable reference voltage ACV output by the signal conversion circuit SCC is the preset voltage VREF.

[0109] When a load drop transient occurs, sense current IL increases, and the sense voltage VL at node N2 also increases. However, since voltage VN1 at node N1 needs to charge capacitor C, its rise is slower. Voltage followers BF1 and BF2 create a voltage difference (VL - VN1) across resistor R3, generating a current of (VL - VN1) / R3 in resistor R3. This current is transferred to node N3 via current mirror CM and converted to the adjusted value of reference voltage ACV by resistor R4. This current in resistor R3 decreases as voltage VN1 increases, gradually returning reference voltage ACV to the preset voltage VREF.

[0110] Compared to the prior art, the peak voltage of the ramp signal in the control circuit of the power converter of the present invention gradually recovers to a preset voltage after a transient occurs. This eliminates the headroom constraints of the ramp signal during load shedding, which can cause control loop failure. This overcomes the drawback of conventional ramp signals being limited by the operating voltage (VCC), significantly increasing circuit design flexibility. Furthermore, because the control loop can quickly resume normal operation, it can provide stable output.

Claims

1. A control circuit of a power converter, coupled to an output circuit, characterized in that: The control circuit includes: a sensing circuit coupled to the output circuit to provide a current sensing signal; a ramp signal generating circuit comprising a transient circuit and a signal generating circuit, wherein the transient circuit is coupled between the sensing circuit and the signal generating circuit, the transient circuit receives the current sensing signal and generates a variable reference voltage, and the signal generating circuit provides a ramp signal according to the variable reference voltage; and a pulse width modulation circuit coupled to the ramp signal generating circuit and the output circuit, and providing a pulse width modulation signal to the output circuit according to the ramp signal; When a load shedding occurs, the load shedding lasts for a first predetermined time. During the load shedding, a transient state occurs, and the transient state lasts for a second predetermined time, which is shorter than the first predetermined time. During the second predetermined time, the variable reference voltage provided by the transient circuit changes from a predetermined value to an adjusted value. The transient circuit then restores the variable reference voltage to the predetermined value after the second predetermined time.

2. The control circuit according to claim 1, wherein: The variable reference voltage is the peak voltage of the ramp signal.

3. The control circuit according to claim 1, wherein: The above-mentioned transient circuit includes: A filter is coupled to the sensing circuit and receives a reference voltage and the current sensing signal to generate the variable reference voltage.

4. The control circuit according to claim 3, wherein: The filter includes a resistor and a capacitor, and the second preset time is related to a resistor-capacitor delay generated by the resistor and the capacitor.

5. The control circuit according to claim 1, wherein: The above-mentioned transient circuit includes: a filter comprising a resistor and a capacitor, wherein the resistor and the capacitor are connected in series between a ground terminal and a sensing voltage, wherein the sensing voltage is related to the current sensing signal; and A signal conversion circuit is coupled to a first node and a second node at both ends of the resistor respectively to provide the variable reference voltage according to a voltage difference between the first node and the second node.

6. The control circuit according to claim 5, wherein: The second predetermined time is related to a resistance-capacitance delay generated by the resistor and the capacitor.

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