Structure and method for controlling electrostatic discharge (ESD) events in a resistor-capacitor circuit

Abstract

Embodiments of the present disclosure provide a circuit structure and method of controlling electrostatic discharge (ESD) events in a resistance-capacitance (RC) circuit. The circuit structure according to the present disclosure can include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to a portion of the RC circuit. A mirror transistor coupled in parallel with the RC circuit passes a current less than the current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode / cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device derived from the current in the mirror transistor controls anode / cathode current flow in the snapback device.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to electronic circuits. More specifically, various embodiments of this disclosure provide circuit structures and methods for controlling electrostatic discharge (ESD) events in resistor-capacitor circuits. Background Technology

[0002] Circuitry including integrated circuits (ICs) may include components for protecting device hardware from electrostatic discharge (ESD) voltages, which can cause short circuits, dielectric breakdown, and / or other failure modes. In an ideal setup, ESD components have no effect on device operation until an ESD event is seen on a pin of the IC, where the ESD event acts as a trigger voltage that turns the ESD device on and releases current to the power or ground rail through the ESD component. The ESD component is not used for any operational purpose until a trigger voltage is applied to activate it. With increasing demands for low leakage and longer battery life, typical power clamps using large FETs as discharge components often leak too much. Other problems often arise when replacing large FETs with "snapback devices" to address leakage issues. A snapback device is a specific type of device in which current remains on once enabled, even after a signal is applied to the snapback device's gate terminal (i.e., "latch-up"). The conventional configuration of ESD components and / or other structures cannot provide a stable trigger voltage while preventing latch-up and ensuring that the ESD component is active only during ESD events. Summary of the Invention

[0003] Some aspects of this disclosure provide a circuit structure including: a resistor-capacitor (RC) circuit having a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node located between the resistive element and the capacitive element; a trigger transistor having a source / drain (S / D) terminal pair coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the third node of the RC circuit; a mirror transistor having an S / D terminal pair coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the gate terminal of the trigger transistor, wherein the S / D terminal pair of the mirror transistor is configured to carry a current less than the current through the S / D terminal pair of the trigger transistor; and a quick-return device having a gate terminal coupled to a selected terminal of the S / D terminal pair of the mirror transistor, and an anode / cathode terminal pair coupled between the first node and the second node and in parallel with the RC circuit, wherein the current at the gate terminal of the quick-return device controls the flow of the anode / cathode current in the quick-return device.

[0004] Other aspects of this disclosure provide a circuit structure including: a resistor-capacitor (RC) circuit having a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node located between the resistive element and the capacitive element; a trigger transistor having a source / drain (S / D) terminal pair coupled between the first node and the second node and connected in parallel with the RC circuit, and a gate terminal coupled to the third node of the RC circuit; a mirror transistor having an S / D terminal pair coupled between the first node and the second node and connected in parallel with the RC circuit, and a gate terminal coupled to the gate terminal of the trigger transistor, wherein the S / D terminal pair of the mirror transistor is connected in parallel with the third node of the RC circuit. The current is less than the current through the S / D terminal pair of the trigger transistor; and a quick-return device having a gate terminal for controlling the current flow in the quick-return device, the quick-return device comprising: a P-well having a first N-doped region coupled to the first node; an N-well adjacent to the P-well and having a first P-doped region coupled to the second node, wherein the current path from the first node to the second node through the quick-return device is in parallel with the RC circuit; and at least one doped region within the P-well or the N-well, coupled to a selected terminal of the S / D terminal pair of the mirror transistor and defining the gate terminal of the quick-return device, wherein the at least one doped region has the same doping type relative to the P-well or the N-well.

[0005] Other aspects of this disclosure provide a method for controlling electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit, the method comprising: transmitting an ESD current through a trigger transistor connected in parallel with the RC circuit, the RC circuit including a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node coupled to the gate of the trigger transistor between the resistive element and the capacitive element; transmitting a mirror current through a mirror transistor connected in parallel with the trigger transistor, wherein the mirror transistor is configured to transmit a current less than the transmitted ESD current; and transmitting the mirror current to the gate terminal of a quick-return device electrically coupled between the first node and the second node and connected in parallel with the RC circuit, such that current flows through the quick-return device from the first node to the second node during the transmission of the mirror current to the gate terminal. Attached Figure Description

[0006] These and other features of the present disclosure will be more readily understood through a detailed description of various aspects of the present disclosure in conjunction with the accompanying drawings, which depict various embodiments thereof, in which:

[0007] Figure 1 A schematic diagram of a circuit structure for controlling electrostatic discharge (ESD) events according to embodiments of the present disclosure is provided.

[0008] Figure 2 An illustrative graph showing the relationship between the current of the shunt device and the gate voltage during operation according to an embodiment of this disclosure is provided.

[0009] Figure 3 A cross-sectional view of a quick-return device within a circuit structure according to an embodiment of the present disclosure is shown.

[0010] Figure 4 A cross-sectional view of a quick-return device within a circuit structure according to another embodiment of the present disclosure is shown.

[0011] It should be noted that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended to depict typical aspects of this disclosure and should therefore not be considered as limiting the scope of this disclosure. In the drawings, the same reference numerals denote the same elements between the figures. Detailed Implementation

[0012] In this description, reference is made to the accompanying drawings, which form a part thereof, illustrating specific exemplary embodiments in which the present teachings may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and changes may be made within the scope of the present teachings. Therefore, the description herein is merely illustrative.

[0013] Embodiments of this disclosure provide a circuit structure and related method for controlling electrostatic discharge (ESD) events, which reliably triggers in response to an ESD event without posing a significant risk of latch-up in a quick-return device for routing ESD current in parallel with a resistor-capacitor (RC) circuit. The RC circuit may include a first node, a second node separated from the first node by resistive and capacitive elements, and a third node located between the resistive and capacitive elements. A trigger transistor having a source / drain (S / D) terminal pair may be coupled between the first and second nodes and connected in parallel with the RC circuit, and the gate terminal of the trigger transistor is coupled to the third node of the RC circuit.

[0014] When an ESD event occurs, the voltage generated in the RC circuit causes current to flow through the trigger transistor connected in parallel with the RC circuit. This circuit includes a mirror transistor whose gate terminal has terminals coupled to the gate terminal of the trigger transistor and source / drain terminals coupled in parallel with the RC circuit. However, the mirror transistor can be configured to carry a much smaller current than the trigger transistor (e.g., by making the mirror transistor much smaller), so that only a portion of the current flowing through the trigger transistor can be replicated. A quick-return device (i.e., where current only flows through its gate terminal (“T”)...) Gate The component that allows current to flow between the anode and cathode terminals only during the application of voltage is coupled to an S / D terminal of the mirror transistor. The anode / cathode terminals of the quick-return device are coupled in parallel with an RC circuit. By adjusting the ratio of the trigger device current to the mirror device current, the total current required for trigger clamping (“I”) can be modulated. trigger Therefore, the circuit can be electrically configured to have high I0. trigger Values ​​are set to avoid accidental triggering of clamps.

[0015] refer to Figure 1 This illustration shows a schematic diagram of a circuit structure (hereinafter referred to as "structure") 100 according to an embodiment of the present disclosure. Structure 100 can be embodied as any type of electronic circuit and, in various embodiments, can be provided as an integrated circuit (IC) structure or included as part of an integrated circuit (IC) structure. Structure 100 may include or otherwise couple to opposite terminals of a resistor-capacitor (RC) circuit 110, which is alternatively referred to in various configurations as an "RC filter" or "RC network". RC circuit 110 may include a number of electrically active elements, including several resistors, capacitors, diodes, and / or other devices. Regardless of its structure or function, RC circuit 110 can be schematically depicted using two electrical components: a resistive element 112 and a capacitor element 114, which are connected in series at the input terminal ("V"). DD", indicating, for example, the connection to the power supply) and output terminals ("V") SS The first node A can represent the "high voltage" terminal of RC circuit 110, while the second node B can represent the opposite "low voltage" or "ground" terminal of RC circuit 110. As discussed herein, multiple features of structure 100 can be coupled between nodes A and B and in parallel with RC circuit 110. The third node C can specify the junction between resistive element 112 and capacitive element 114 within RC circuit 110. As discussed herein, the third node C can be used to control the operation of structure 100, for example, to respond to current spikes during ESD events. Structure 100 is configured to respond to excess charge and current originating from ESD events by preventing current from flowing into the active component (e.g., RC circuit 110). Input terminal V DD The input voltage and / or signal can be electrically coupled to the RC circuit 110 via any form of wiring. Excess charge generated by an ESD event can be transmitted via the input terminal V. DD Transmitted to structure 100.

[0016] Structure 100 can be in the form of a clamp, which is configured to be connected via output terminal V. SS This excess charge is shorted to ground from the power supply. It should be understood that the V00 at the input and output terminals of structure 100 and RC circuit 110... DD and V SS The specification can be switched in other implementations. Structure 100 is designed not to operate under non-ESD conditions with voltage variations. Specifically, in cases where voltage fluctuations are possible, structure 100 remains inactive during power-on and power-off operations when such voltage fluctuations are insufficient to trigger the transistor gate of its components. Therefore, structure 100 is designed to selectively allow current flow only when an ESD event is detected.

[0017] A set of ESD elements 120 can be coupled between a first node A and a second node B and connected in parallel with an RC circuit 110, with some portions of the ESD elements 120 coupled to a third node C. The ESD elements 120 can be selectively activated during an ESD event in response to a voltage or current higher than the expected voltage or current of the RC circuit 110. The ESD elements 120 can prevent current from flowing from the input terminal V. DD Flow to output terminal V SS Unless or until a trigger voltage is applied to the trigger transistor 122 of the ESD element 120. In various other examples, additional circuitry and / or current paths may be located between the RC circuit 110 and the ESD element 120 to further control the situation in which the ESD element 120 becomes electrically active.

[0018] The ESD element 120 of structure 100 may include multiple transistors, each configured to react during an ESD event to control the flow of current through the ESD element 120. A transistor is an electrical component in which the flow of current between an input node and an output node (e.g., a source terminal and a drain terminal) is controlled by a voltage applied to a third “gate” terminal. A trigger transistor 122 may be coupled to the third node C of RC circuit 110 at its gate, such that the operating current or voltage of RC circuit 110 controls whether trigger transistor 122 is turned on or off. Trigger transistor 122 may be coupled to RC circuit 110 via a first inverter 124 connected in series between the third node C and the gate of trigger transistor 122. Inverter 124 may convert the voltage at the third node C to its opposite polarity (e.g., from negative to positive, or from positive to negative). The first inverter 124 may also be coupled to nodes A and B and connected in parallel with RC circuit 110 to power its inverting function in structure 100. The first inverter 124 may operate in tandem with other inverters of the ESD element 120 to achieve electrical stability and / or intentionally delay the time required for structure 100 to respond to an ESD event. In another embodiment, the first inverter 124 may be omitted and / or replaced by multiple inverters. In any case, the electrical coupling from the third node C to the gate of the trigger transistor 122 may cause a voltage spike to activate the trigger transistor 122.

[0019] The gate of trigger transistor 122 can be coupled to the gate terminal of mirror transistor 126. Mirror transistor 126 may include source and drain terminals coupled between the first node A and the second node B of structure 100 and connected in parallel with trigger transistor 122. Mirror transistor 126, by coupling its gate to the gate of trigger transistor 126, can act as a "current mirror," wherein the source-drain current within mirror transistor 126 is proportional to the source / drain current within trigger transistor 122 by a fixed factor. A current mirror is any circuit structure configured to precisely replicate the current passing through one device (e.g., the current passing through trigger transistor 122) to another device, or to replicate it to another device by a factor between 0 and 1. Resistor 128 can be coupled between the first node A and the source or drain terminal of mirror transistor 126, for example, to a voltage level V. DDCompared to further reducing the voltage at the source or drain of mirror transistor 126, mirror transistor 126 can have a significantly lower current than the current allowed through trigger transistor 122, for example, to reduce leakage current in the active components (e.g., the quick-return device 130 discussed herein) of structure 100 coupled to mirror transistor 126. The source-to-drain width of mirror transistor 126 can be significantly smaller than that of trigger transistor 122. In such an example, mirror transistor 126 can carry up to 1 / 10 of the current in trigger transistor 122. In another example, trigger transistor 122 can carry up to about 200 mA of current, while mirror transistor 126 can carry up to about 20 mA of current. In yet another example, the source-to-drain width of trigger transistor 122 can be about 200 μm, while the source-to-drain width of mirror transistor 126 can be about 10 μm (i.e., about one-twentieth).

[0020] The source or drain of mirror transistor 126 can be coupled to the second node B, thereby providing another parallel current path relative to RC circuit 110 and trigger transistor 122. The other source or drain terminal of mirror transistor 126 can be coupled to the gate terminal T of quick-return device 130. Gate Similar to the trigger transistor 122, the ESD element 120 may include a gate terminal T coupled to the return device 130. Gate At least one second inverter 132 between the mirror transistor 126 and the mirror transistor 124. The second inverter 132 may include an inverter of the same type and / or a similar structure as the first inverter 124, and may connect the gate of the mirror transistor 126 and the T-band of the step-back device 130. Gate The voltage polarity is reversed between them, for example, to achieve further stability and / or prevent false positive ESD voltages. The electrical coupling between trigger transistor 122 and mirror transistor 126 can itself operate as a third inverter between the first inverter 124 and the second inverter 132, thereby returning the voltage to the gate terminal T of the step-back device 130. Gate This causes a voltage of opposite polarity but smaller amplitude. As described elsewhere in this document, the second inverter 132 may include multiple additional inverters in alternative configurations and / or may be omitted entirely.

[0021] In addition, the quick-return device 130 may include a cathode terminal T connected in parallel with the RC circuit 110 and coupled to the first node A. Cat and coupled to the anode terminal T of the second node B AnThe term "quick-back device" refers to a three-terminal electrical component that defines an electrical path from the cathode terminal to the anode terminal, wherein the gate terminal is electrically connected to both the cathode and anode terminals. Applying a relatively small input current to the gate terminal allows current to flow from the cathode to the anode. A silicon controlled rectifier (SCR) is a commonly used type of quick-back device because an SCR can include multiple doped semiconductor regions of different polarities and concentrations. An SCR is particularly effective for use as a quick-back device 130 in structure 100 because it is easily integrated into the semiconductor material in which other structures / devices are formed. Other types of components suitable for forming the quick-back device 130 may include, for example, a bidirectional thyristor or other thyristor-based protection device (TSPD), a gas discharge tube (GDT), a bipolar transistor with an avalanche junction, and / or other electrical components with similar characteristics.

[0022] Brief reference Figure 2 The diagram illustrates the cathode-anode current (variable I, measured in mA) and supply voltage (variable V) of the quick-return device 130 according to an exemplary embodiment. DD A graph showing the relationship between the voltage (measured in volts (V)) and the voltage (measured in volts (V)) is provided to better illustrate the behavior of structure 100. During non-ESD operation of the RC circuit 110, the non-ESD voltage (“V”) can be measured. Stable An RC circuit 110 is applied without triggering the ESD element 120. In this state, virtually no current can reach the gate terminal T. Gate And therefore, virtually no current flows from the cathode to the anode in the quick-return device 130 (i.e., the quick-return device 130 presents a current I). off With the power supply voltage V DD Increased due to ESD events, the quick-return device is able to divert current from the cathode to the anode when the overflow current from the first node A is diverted (e.g., the quick-return device 130 presents a non-zero current I). on Trigger voltage V trigger The ESD voltage that can be indicated to trigger ESD element 120 (i.e., enable cathode-to-anode current) is I. trigger This indicates the ESD voltage that the ESD element 120 will trigger. If the ESD current reaches or exceeds V... trigger If the current is not engaged, the return device 130 will return to the state where the cathode-to-anode current is currently enabled (i.e., latched). In this state, the return device 130 will permanently exhibit a higher current I, even during non-ESD operation. latchup Embodiments of this disclosure include a mirror transistor 126 ( Figure 1 This problem can be avoided or prevented. To allow the mirror transistor 126 to drive sufficient current through the gate terminal (T... GateBy biasing the circuit 100 to trigger the quick-return device 130, a significantly larger current can be supplied to the trigger transistor 122. Therefore, by configuring the circuit 100 for a specific current mirror ratio, the trigger current I can be modulated. trigger Value. As an example, where triggering the return device 130 requires 5mA of current from the mirror device 126, the trigger device 122 can drive 200mA, which may cause I... trigger The increase exceeded 205mA.

[0023] Turn Figure 1 and Figure 3 This section discusses other example sub-components of the quick-return device 130. Here, the quick-return device 130 may take the form of an SCR. The quick-return device 130 may be formed from a substrate 140 comprising, for example, one or more semiconductor materials. The substrate 140 may comprise any currently known or hereafter developed semiconductor material, which may include, but is not limited to, silicon, germanium, silicon-germanium, silicon carbide, and materials substantially composed of one or more semiconductor materials having the chemical formula Al. X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 Materials composed of group III-V compound semiconductors with defined compositions, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero, and X1 + X2 + X3 + Y1 + Y2 + Y3 + Y4 = 1 (where 1 is the total relative molar amount). Other suitable substrates include those with the composition Zn. A1 Cd A2 Se B1 Te B2 The substrate 140 is a group II-VI compound semiconductor, wherein A1, A2, B1, and B2 are relative proportions, each greater than or equal to zero, and A1 + A2 + B1 + B2 = 1 (where 1 is the total molar amount). Furthermore, the substrate 140 as a whole, or a portion thereof, may be strained.

[0024] Various portions of substrate 140 may be doped based on the desired polarity and / or desired characteristics of the turnaround device 130 and / or other device structures formed thereon to form P-well 142 and N-well 144 adjacent to P-well 142. In the example, the P-well is shown to the right of N-well 142 and has approximately equal dimensions, but this is not required. Various active elements may be formed on or within P-well 142 and / or N-well 144 to form electrical paths through turnaround device 130, electrically bias and / or affect current through wells 142, 144, etc., without substantially altering the function of the active elements and / or affecting other structures formed on or within substrate 140. In some embodiments (e.g., semiconductor-on-insulator (SOI) structures), one or more dielectric layers or other insulating material layers may be vertically positioned between one or both of wells 142, 144 and substrate 140.

[0025] A "dopant" is an element introduced into a semiconductor to establish p-type (acceptor) or n-type (donor) conductivity. In the case of a silicon substrate, common dopant elements may include, for example, boron (B) and / or indium (In) for p-type doping. For n-type doping, doping elements may include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb). Doping is the process of introducing impurities (dopants) into or forming elements on a semiconductor substrate, typically performed using masks (e.g., photoresist films and / or other components that block dopant) at appropriate locations, thereby doping only certain areas of the substrate. In examples of doping by implantation, an ion implanter may be used. In other examples, in-situ doping or other doping techniques may be used.

[0026] Typically, in doping, the dopant, dose, and energy level are specified, and / or the resulting doping level can be specified. The dose can be expressed in centimeters per square centimeter (cm²). 2 The number of atoms and energy levels (specified in keV) are specified, thus producing per cubic centimeter (cm²) 3 The doping level (concentration in the substrate) refers to the number of atoms. The number of atoms is usually specified in exponential notation, where a number like "3E15" represents 3 multiplied by 10 to the power of 15, or "3" followed by 15 zeros (3,000,000,000,000,000). An example of doping is approximately 1E12 to 1E13 atoms / cm³. 2 Boron (B) was implanted at doses between 1E17 and 1E18 atoms / cm² at energies of approximately 40 to 80 keV to produce a yield of 1E17 to 1E18 atoms / cm². 3The doping levels are as follows. The doped portion of the substrate may be referred to in the art as a “well.” A well typically refers to an implanted / diffused region in a semiconductor wafer required to realize a complementary metal-oxide-semiconductor (CMOS) element. A “deep well” refers to doped semiconductor material located beneath active device components and / or other wells. Depending on the properties of the device to be fabricated, the semiconductor material portion on or above substrate 140 may be N-type or P-type doped, as discussed herein.

[0027] Wells 142 and 144 can be doped with additional material to a greater concentration than those 142 and 144, and with different doping types, to produce the functionality of the blip-back device 130 during operation. For example, P-well 142 may have a first N-doped region 146 coupled to a first node A, which may be coupled to the cathode terminal T. Cat The same node and / or may include cathode terminal T Cat The N-doped region 146 can therefore have the opposite doping type to the P-well 142. Similarly, the N-well 144 has a first P-doped region 148 coupled to a second node B, which can be connected to the anode terminal T. An The same node and / or may include anode terminal T An Each portion of wells 142, 144 can physically separate the first N-doped region 146 from the first P-doped region 148. The alternating arrangement of doped regions within the quick-return device 130 provides access from the cathode terminal T through the quick-return device 130. Cat to anode terminal T An The current path L.

[0028] The quick-return device 130 may include a first doped region 150 and / or a second doped region 152 located within the P-well 142 and N-well 144, respectively, to provide gate contacts for controlling current flow along the current path L. Each doped region 150, 152 may be of the same doping type as its corresponding well 142, 144, and may include or otherwise be coupled to the gate terminal T. Gate Here, the first doped region 150 may be P-type doped and located within the P-well 142, while the second doped region 152 may be N-type doped and located within the N-well 142. Where applicable, doped regions 150 and 152 may be coupled to the output of the second inverter 132. The electrical coupling to the second doped region 152 is shown in dashed lines to indicate that it may be an additional or alternative coupling relative to the first doped region 150. The doped regions 150 and 152 that transmit current to the quick-return device may electrically bias the wells 142 and 144, while simultaneously allowing current to flow through the current path L.

[0029] Brief reference Figure 4Another embodiment of the quick-return device 130 may include multiple doped regions coupled to voltages of opposite polarity to more effectively control the current flowing through the current path L. In this case, the quick-return device 130 may have two gates T that can be coupled to the first doped region 150 and the second doped region 152. Gate1 and T Gate2 In this configuration, doped regions 150 and 152 can be electrically coupled to the input and output terminals of the second inverter 132, respectively. In some configurations, each gate terminal T... Gate1 and T Gate2 The polarity relative to the second inverter 132 can be opposite. Through such a connection, the polarity to the gate terminal T... Gate1 and T Gate2 Applying a single voltage can generate current reaching each doped region 150, 152 to simultaneously electrically bias N-well 142 and P-well 144 with opposite voltage polarities. This can further control leakage and conduction of the quick-return device 130.

[0030] Refer again Figure 1 and Figure 3 The method according to this disclosure may include using structure 100 during device operation to control ESD events to protect RC circuit 110 from excessive current. The method according to this disclosure may, for example, include transferring ESD current through trigger transistor 122 of ESD element 120 connected in parallel with RC circuit 110. ESD current may be caused by ESD events in one or more devices interconnected with structure 100. Allowing such current transfer through trigger transistor 122 will cause mirror transistor 126 to also receive a mirror current in parallel with trigger transistor 122, but this current is less than the current in trigger transistor 122. The reduced current in mirror transistor 126 may be attributed, for example, to the significantly smaller size of mirror transistor 126 (e.g., having a smaller source-to-drain width discussed herein) and / or to the presence of resistor 128 (where applicable). In an example embodiment, the mirror current in mirror transistor 126 may be at most about 1 / 10 of the current in trigger transistor 122. The mirror current in mirror transistor 126 may be routed to the gate terminal T of quick-return device 130. Gate This allows the cathode-to-anode current to flow along the current path J. Figure 2 When activated, the quick-return device 130 electrically short-circuits the ESD current to bypass the RC circuit 110. The time lag between the activation of the trigger transistor 122 and the enable of the quick-return device 130 can be negligible (e.g., approximately several hundred picoseconds) to prevent the ESD current from having any effect on the RC circuit 110 and the integrated circuit.

[0031] Various embodiments of this disclosure have been described for illustrative purposes, but these descriptions are not intended to be exhaustive and / or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art within the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, and / or technical improvements relative to technologies found in the market, and / or to enable others skilled in the art to understand the embodiments disclosed herein.

[0032] Embodiments of this disclosure can provide several technical and commercial advantages, some of which are discussed herein by way of example. Embodiments of structure 100 provide, for example, a structure capable of responding to ESD events with a conventional trigger voltage amplitude, while reducing the current or voltage required to achieve an electrical short circuit via the return device 130. Furthermore, embodiments of this disclosure prevent the gate voltage of the return device 130 from approaching any level that could cause a "latch-up" and a permanent electrical short circuit to the RC circuit 110. In some cases, the size and electrical parameters of the trigger transistor 122 and / or mirror transistor 126 can be selected to accommodate different types of RC circuit 110 and / or devices electrically coupled to structure 100. Compared to conventional structures used to respond to ESD events affecting the RC circuit 110, embodiments of structure 100 occupy a surface area similar to or reduced from other circuitry to temporarily bypass the RC circuit 110.

Claims

1. A circuit structure, comprising: A resistor-capacitor RC circuit having a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node located between the resistive element and the capacitive element; A trigger transistor having a source / drain S / D terminal pair coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the third node of the RC circuit; A mirror transistor having an S / D terminal pair coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the gate terminal of the trigger transistor, wherein the S / D terminal pair of the mirror transistor is configured to transmit a current less than the current through the S / D terminal pair of the trigger transistor; as well as A quick-return device having a gate terminal coupled to a selected terminal of the S / D terminal pair of the mirror transistor, and an anode / cathode terminal pair coupled between the first node and the second node and connected in parallel with the RC circuit, wherein the current at the gate terminal controls the flow of the anode / cathode current in the quick-return device.

2. The circuit structure according to claim 1 further includes: A first inverter has an input terminal coupled to the third node of the RC circuit and an output terminal coupled to the gate terminal of the trigger transistor. as well as The second inverter has an input terminal coupled to a selected terminal of the S / D terminal pair of the mirror transistor, and an output terminal coupled to the gate terminal of the quick-return device. The trigger transistor and the mirror transistor are configured to reverse the voltage polarity between the output of the first inverter and the input of the second inverter.

3. The circuit structure according to claim 1, wherein the current through the S / D terminal pair of the mirror transistor is at most 1 / 10 of the current through the S / D terminal pair of the trigger transistor.

4. The circuit structure according to claim 1, wherein the current through the S / D terminal pair of the mirror transistor is at most 20 mA, and the current through the S / D terminal pair of the trigger transistor is at most 200 mA.

5. The circuit structure according to claim 1, wherein the source-to-drain width of the trigger transistor is at most four thousand micrometers (μm), and the source-to-drain width of the mirror transistor is at most two hundred micrometers (μm).

6. The circuit structure of claim 1 further includes a resistor coupled between a selected terminal of the S / D terminal pair of the mirror transistor and the first node, wherein the resistor is configured to transmit current through the mirror transistor.

7. The circuit structure according to claim 1, wherein the quick-return device comprises a silicon controlled rectifier (SCR).

8. A circuit structure, comprising: A resistor-capacitor RC circuit having a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node located between the resistive element and the capacitive element; A trigger transistor having a source / drain S / D terminal pair coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the third node of the RC circuit; A mirror transistor having an S / D terminal pair coupled between the first node and the second node and in parallel with the RC circuit, and a gate terminal coupled to the gate terminal of the trigger transistor, wherein the current through the S / D terminal pair of the mirror transistor is less than the current through the S / D terminal pair of the trigger transistor; as well as A quick-return device having a gate terminal for controlling current flow in the quick-return device, the quick-return device comprising: A P-well having a first N-doped region coupled to one of the first nodes; An N-well, adjacent to the P-well, and having a first P-doped region coupled to the second node, wherein the current path from the first node to the second node via the quick-return device is in parallel with the RC circuit; and At least one doped region within the P-well or the N-well is coupled to a selected terminal of the S / D terminal pair of the mirror transistor and defines the gate terminal of the turnaround device, wherein the at least one doped region has the same doping type relative to the P-well or the N-well.

9. The circuit structure according to claim 8 further includes: A first inverter has an input terminal coupled to the third node of the RC circuit and an output terminal coupled to the gate terminal of the trigger transistor. as well as The second inverter has an input terminal coupled to a selected terminal of the S / D terminal pair of the mirror transistor, and an output terminal coupled to the gate terminal of the quick-return device. The trigger transistor and the mirror transistor are configured to reverse the voltage polarity between the output of the first inverter and the input of the second inverter.

10. The circuit structure of claim 8, wherein the current through the S / D terminal pair of the mirror transistor is at most 1 / 10 of the current through the S / D terminal pair of the trigger transistor.

11. The circuit structure according to claim 8, wherein the current through the S / D terminal pair of the mirror transistor is at most 20 mA, and the current through the S / D terminal pair of the trigger transistor is at most 200 mA.

12. The circuit structure according to claim 8, wherein the source-to-drain width of the trigger transistor is at most four thousand micrometers (μm), and the source-to-drain width of the mirror transistor is at most two hundred micrometers (μm).

13. The circuit structure of claim 8 further includes a resistor coupled between a selected terminal of the S / D terminal pair of the mirror transistor and the first node, wherein the resistor is configured to transmit current through the mirror transistor.

14. The circuit structure according to claim 8, wherein the quick-return device comprises a silicon controlled rectifier (SCR).

15. The circuit structure according to claim 14, wherein at least one doped region within the P-well or the N-well comprises a second P-doped region within the P-well and a second N-doped region within the N-well.

16. A method for controlling electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit, the method comprising: Electrostatic discharge (ESD) current is transmitted through a trigger transistor connected in parallel with a resistor-capacitor (RC) circuit, the RC circuit including a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node coupled to the gate of the trigger transistor between the resistive element and the capacitive element. The mirror current is transmitted through a mirror transistor connected in parallel with the trigger transistor, wherein the mirror transistor is configured to transmit a current less than the transmitted ESD current. as well as The mirrored current is transmitted to the gate terminal of a quick-return device electrically coupled between the first node and the second node and connected in parallel with the RC circuit, so that current flows through the quick-return device from the first node to the second node during the transmission of the mirrored current to the gate terminal.

17. The method of claim 16, wherein transmitting the mirror current includes preventing the mirror current from exceeding at most 1 / 10 of the transmitted ESD current.

18. The method of claim 16, wherein transmitting the ESD current includes preventing the ESD current from exceeding 200 mA, and transmitting the mirror current includes preventing the mirror current from exceeding 20 mA.

19. The method of claim 16, further comprising applying a reverse node voltage within the RC circuit to the gate terminal of the trigger transistor to allow the ESD current to flow through the trigger transistor, wherein flowing the mirror current to the gate terminal of the quick-return device comprises applying a reverse voltage of the source / drain voltage of the mirror transistor to the gate terminal of the quick-return device.

20. The method of claim 16, wherein the quick-return device comprises a silicon controlled rectifier (SCR).

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