A method for generating zero-point pulses in an absolute encoder

Abstract

This invention relates to the field of encoder application technology in servo control systems, and in particular to a method for generating zero-point pulses for absolute encoders. Based on the desired number of pulses per revolution, the method can flexibly generate corresponding zero-point pulse widths according to the real-time speed of the absolute encoder, significantly reducing usage errors compared to traditional fixed zero-point widths. Furthermore, this invention is applicable to various types of absolute encoders; simply changing the absolute encoder resolution r and communication period t to the information of the current absolute encoder allows for its application, resulting in strong compatibility and reduced usage costs.

Description

Technical Field

[0001] This invention relates to the field of encoder application technology in servo control systems, and in particular to a method for generating zero-point pulses for an absolute encoder. Background Technology

[0002] Absolute encoders are increasingly widely used in servo control due to their extremely high resolution and position memory capabilities.

[0003] In servo applications, the host controller sometimes needs to receive encoder zero-point pulses from the servo output to achieve system logic control. Since the position of the absolute encoder is acquired via data communication and does not generate actual pulses, it is generally achieved by calculating and generating encoder zero-point pulses. Currently, the common method is to compare two acquired absolute encoder positions; once the position crosses zero, the edge of the zero-point pulse is generated, and then a custom pulse width is defined to complete the zero-point pulse generation.

[0004] However, the above method has the following problems: since the width of the generated zero-point pulse is customized, it cannot output a zero-point pulse with a width that matches the real-time speed of the motor, resulting in a large error in its use. Summary of the Invention

[0005] This invention addresses the problems of existing technologies by providing a method for generating zero-point pulses for absolute encoders. The method changes the width of the generated zero-point pulses according to the real-time speed of the actual absolute encoder, which means that zero-point pulses can be flexibly generated to match the number of output pulses per revolution set by the customer, greatly reducing usage errors.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: a method for generating zero-point pulses of an absolute encoder, comprising the following steps:

[0007] A. Set the resolution of the absolute encoder per revolution to r, the number of pulses generated per revolution to m, and the communication period of the absolute encoder to t;

[0008] B. Let the position of the absolute encoder during the last communication be P(n-1), and the position of the absolute encoder during the current communication be P(n);

[0009] C. Determine the real-time speed of the absolute encoder based on the position difference (P(n)-P(n-1)) between two communications and the change in the number of pulses; obtain the width of the generated zero-point pulse based on the change in the real-time speed of the absolute encoder.

[0010] D. Determine if the position of the absolute encoder has passed zero. If so, generate the edge of the zero-point pulse and continue for the width to complete the generation of the zero-point pulse.

[0011] Preferably, obtaining the position difference of the absolute encoder and the change in the number of pulses between the two communications in step C includes the following steps:

[0012] C1. Let mull, mull = (P(n) - P(n-1)) * m;

[0013] C2. Let divide_sub and remainder be, where remainder = remainder of divide_sub / r, and remainder is initialized to 0; divide_sub = mull + remainder;

[0014] C3. Let quotient be the quotient of divide_sub / r;

[0015] C4. The zero-point pulse width is width = t / quotient.

[0016] Preferably, in step C, a first dividend register, a second dividend register, a remainder register, a pulse count register, and a zero-point pulse width register are set, wherein the value of mull is stored in the first dividend register, the value of divide_sub is stored in the second dividend register, the value of remainder is stored in the remainder register, the value of quotient is stored in the pulse count register, and the value of pulse width is stored in the zero-point pulse width register.

[0017] Preferably, all of the aforementioned registers are 32-bit registers.

[0018] Preferably, step D, determining whether the absolute encoder position has crossed zero, includes the following steps:

[0019] D1. If P(n-1) is greater than 0.8*r and Pn is less than 0.2*r, then the encoder is determined to have crossed zero in the positive direction.

[0020] D2. If P(n-1) is less than 0.2*r and Pn is greater than 0.8*r, then the encoder is determined to have crossed zero in the reverse direction.

[0021] Preferably, steps A through D are all executed in the FPGA.

[0022] The present invention also provides a computer storage medium storing computer instructions, which, when invoked, are used to execute the above-described method for generating zero-point pulses of an absolute encoder.

[0023] The present invention also provides an electronic device comprising:

[0024] The processor and the memory arranged to store computer-executable instructions, which, when executed, cause the processor to perform the above-described method for generating zero-point pulses of an absolute encoder.

[0025] The beneficial effects of this invention are:

[0026] This invention provides a method for generating zero-point pulses for an absolute encoder. Based on the desired number of pulses per revolution, the method can flexibly generate the corresponding zero-point pulse width according to the real-time speed of the absolute encoder. Compared with the traditional fixed zero-point width, this greatly reduces the usage error. Furthermore, this invention is applicable to various types of absolute encoders. It can be applied simply by changing the corresponding absolute encoder resolution r and communication period t to the information of the current absolute encoder. It has strong compatibility and reduces the cost of use. Attached Figure Description

[0027] Figure 1 This is a flowchart of the method of the present invention; Detailed Implementation

[0028] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to embodiments and accompanying drawings. The content mentioned in the embodiments is not intended to limit the present invention. The present invention will be described in detail below with reference to the accompanying drawings.

[0029] Example 1:

[0030] This embodiment provides a method for generating zero-point pulses in an absolute encoder, such as... Figure 1 This includes the following steps:

[0031] A. Set the resolution of the absolute encoder per revolution to r, the number of pulses generated per revolution to m, and the communication period of the absolute encoder to t;

[0032] B. Let the position of the absolute encoder during the last communication be P(n-1), and the position of the absolute encoder during the current communication be P(n);

[0033] C. Determine the real-time speed of the absolute encoder based on the position difference (P(n)-P(n-1)) and the change in the number of pulses between two communications; obtain the width of the generated zero-point pulse based on the change in the real-time speed of the absolute encoder.

[0034] D. Determine if the position of the absolute encoder has passed zero. If so, generate the edge of the zero-point pulse and continue for the width to complete the generation of the zero-point pulse.

[0035] Specifically, this embodiment aims to generate zero-point pulses with variable zero-point pulse widths. First, based on the position of the absolute encoder and the number of pulses between two communications, it is determined that within the same communication period t, if the number of pulses changes between two communications, it indicates a change in the real-time speed of the absolute encoder, meaning the width of the generated zero-point pulse needs adjustment. The specific calculation method is as follows:

[0036] C1. Let mull, mull = (P(n) - P(n-1)) * m;

[0037] C2. Let divide_sub and remainder be, where remainder = remainder of divide_sub / r, and remainder is initialized to 0; divide_sub = mull + remainder;

[0038] C3. Let quotient be the quotient of divide_sub / r;

[0039] C4. Zero-point pulse width = t / quotient.

[0040] The system includes a first dividend register, a second dividend register, a remainder register, a pulse count register, and a zero-point pulse width register. The value of `mull` is stored in the first dividend register, the value of `dividend_sub` is stored in the second dividend register, the value of `remainer` is stored in the remainder register, the value of `quotient` is stored in the pulse count register, and the value of the pulse width is stored in the zero-point pulse width register. All registers are 32-bit registers. By using multiple different registers, different calculation results are stored separately, and data is retrieved from the corresponding registers when needed, thus preventing data corruption.

[0041] By combining the pulse count, real-time speed, and communication cycle of the absolute encoder in the above manner, the zero-point pulse width of the absolute encoder at different speeds can be obtained. This avoids the error problem caused by a fixed zero-point pulse width. Furthermore, this embodiment can be used for different absolute encoders; it can be applied simply by modifying the data of the absolute encoder itself, such as the resolution r and the communication cycle t, which are different. It has strong compatibility and reduces the cost of use. In this embodiment, steps A to D are all executed in the FPGA.

[0042] Example 2:

[0043] This invention discloses a computer-readable storage medium storing a computer program for electronic data interchange, wherein the computer program causes a computer to perform some or all of the steps in the method for generating zero-point pulses of an absolute encoder as described in Embodiment 1.

[0044] Example 3:

[0045] This invention discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to perform some or all of the steps in the method for generating zero-point pulses of an absolute encoder as described in Embodiment 1.

[0046] Example 4:

[0047] An electronic device disclosed in an embodiment of the present invention includes:

[0048] Processor; and,

[0049] A memory arranged to store computer-executable instructions (program code) may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. The memory has storage space for storing program code used to perform any method steps in the embodiments. For example, the storage space for program code may include various program codes respectively for implementing the various steps in the methods described above. This program code can be read from or written to one or more computer program products. These computer program products include program code carriers such as hard disks, compact discs (CDs), memory cards, or floppy disks. Such computer program products are typically the computer-readable storage medium of Embodiment 4. This computer-readable storage medium may have storage units such as storage segments, storage spaces, etc., arranged similarly to the memory in an electronic device. The program code may be compressed, for example, in a suitable form. Typically, the storage units store program code for performing the method steps according to the invention, i.e., program code that can be read by a processor such as a processor, which, when run by the electronic device, causes the electronic device to perform the various steps in the method for generating zero-point pulses of an absolute encoder described above.

[0050] The algorithms and displays provided herein are not inherently related to any particular computer, virtual device, or other equipment. Various general-purpose devices can also be used in conjunction with the teachings herein. The required structure for constructing such devices is apparent from the above description. Furthermore, this invention is not directed to any particular programming language. It should be understood that the contents of the invention described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of the invention.

[0051] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the present invention without departing from the scope of the present invention are within the scope of the present invention.

Claims

1. A method for generating zero-point pulses in an absolute encoder, characterized in that, Includes the following steps: A. Set the resolution of the absolute encoder per revolution to r, the number of pulses generated per revolution to m, and the communication period of the absolute encoder to t; B. Let the position of the absolute encoder be P(n-1) during the last communication, and the position of the absolute encoder be P(n) during the current communication. C. Determine the real-time speed of the absolute encoder based on the position difference (P(n) - P(n-1)) and the change in the number of pulses between two communications; obtain the width of the generated zero-point pulse based on the change in the real-time speed of the absolute encoder. D. Determine if the position of the absolute encoder has crossed the zero point. If so, generate the edge of the zero point pulse and continue for the width to complete the generation of the zero point pulse. The acquisition of the absolute encoder position difference and pulse count change between the two communications in step C includes the following steps: C1. Let mull, and mull = (P(n) - P(n-1)) * m; C2. Let divide_sub and remainder be, where remainder = remainder of divide_sub / r, remainder is initialized to 0, and divide_sub = mull + remainder; C3. Let the number of pulses be quotient, then quotient = the quotient of divide_sub / r; C4. The zero-point pulse width is width = t / quotient; In step C, a first dividend register, a second dividend register, a remainder register, a pulse count register, and a zero-point pulse width register are set. The value of mull is stored in the first dividend register, the value of divide_sub is stored in the second dividend register, the value of remainder is stored in the remainder register, the value of quotient is stored in the pulse count register, and the value of pulse width is stored in the zero-point pulse width register.

2. The method for generating zero-point pulses of an absolute encoder according to claim 1, characterized in that: The first dividend register, the second dividend register, the remainder register, the pulse count register, and the zero-point pulse width register are all 32-bit registers.

3. The method for generating zero-point pulses of an absolute encoder according to claim 1, characterized in that, Step D, determining whether the absolute encoder position has crossed zero, includes the following steps: D1. If P(n-1) is greater than 0.8*r and Pn is less than 0.2*r, then the encoder is determined to have crossed zero in the positive direction; D2. If P(n-1) is less than 0.2*r and Pn is greater than 0.8*r, then the encoder is determined to have crossed zero in the reverse direction.

4. The method for generating zero-point pulses of an absolute encoder according to claim 1, characterized in that: Steps A through D are all executed in the FPGA.

5. A computer storage medium storing computer instructions, which, when invoked, are used to execute the method for generating a zero-point pulse for an absolute encoder as described in any one of claims 1-3.

6. An electronic device, characterized in that, The electronic device includes: A processor and a memory arranged to store computer-executable instructions, which, when executed, cause the processor to perform the method of generating a zero-point pulse for an absolute encoder as described in any one of claims 1-3.

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