Crystal oscillator frequency calibration circuit, method, chip and electronic device

Abstract

The embodiment of the application discloses a crystal frequency calibration circuit, method, chip and electronic equipment, and relates to the calibration field. According to a preset load capacitance value, the target value of two capacitor groups of a crystal oscillator is determined, the processor controls the opening or closing of each switch to realize the charging of the capacitor groups and the measurement of the charging time, the processor calculates the capacitance value of the capacitor groups according to the charging time measured by the counter and the charging current of the constant current source, adjusts the capacitance value of the adjustable capacitor in the capacitor group according to the difference between the calculated capacitance value and the target value, and until the capacitance values of the two capacitor groups are equal to the target value. The application realizes automatic matching of the capacitance value according to the actual requirement of the crystal oscillator, so that the precision of the resonant frequency of the crystal oscillator meets the requirement, the whole calibration process does not need manual participation, the time consumed in the crystal calibration link can be saved, and the calibration cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of calibration, in particular to a crystal frequency calibration circuit, method, chip and electronic device. BACKGROUND

[0002] The chip of communication chip, timing chip or USB chip type, all need a precise clock for timing or communication handshake, in order to reduce the cost, generally use passive crystal oscillator as the clock source of chip; due to the inherent characteristics of crystal oscillator, the oscillation frequency is related to the parameters of itself, and is inversely proportional to the capacitance of crystal oscillator circuit, which includes matching capacitance, PCB parasitic capacitance, chip bonding line capacitance and PAD parasitic capacitance, and these relationships are not linear, in the production of equipment containing crystal oscillator, in order to ensure the frequency accuracy, it is necessary to calibrate the crystal frequency of each device, which needs to use frequency meter or test bench to complete, which has the problems of time-consuming and high cost. SUMMARY

[0003] The present application provides a crystal frequency calibration circuit, method, chip and electronic device, which can solve the problem of long time and high cost caused by the dependence of crystal frequency calibration on special equipment in the prior art. The technical solution is as follows:

[0004] In a first aspect, the present application provides a crystal frequency calibration circuit, which is connected with a clock circuit and a crystal oscillator; the crystal frequency calibration circuit comprises:

[0005] a crystal oscillator driving circuit, a first capacitor group, a second capacitor group, a constant current source, a comparator, a counter, a processor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch and a ninth switch; the first capacitor group is composed of a first matching capacitor and a first adjustable capacitor in parallel, and the second capacitor group is composed of a second matching capacitor and a second adjustable capacitor in parallel;

[0006] The first end of the crystal oscillator is connected with the first end of the first switch, and the second end of the crystal oscillator is connected with the clock circuit.

[0007] The second end of the first switch is connected with the first end of the third switch, the first end of the second matching capacitor and the first end of the second adjustable capacitor respectively, and the second end of the second matching capacitor and the second end of the second adjustable capacitor are grounded; the second end of the third switch is connected with the crystal oscillator driving circuit, and the crystal oscillator driving circuit is connected with the first end of the fourth switch.

[0008] The clock circuit is connected with the first end of the fifth switch and the first end of the second switch respectively; the second end of the second switch is connected with the second end of the fourth switch, the first end of the first matching capacitor and the first end of the first adjustable capacitor respectively; the second end of the first matching capacitor and the second end of the first adjustable capacitor are grounded;

[0009] The second end of the fifth switch is connected with the clock input end of the counter and the clock input end of the processor respectively;

[0010] The first end of the eighth switch is connected with the first end of the second matching capacitor, and the first end of the ninth switch is connected with the first end of the first matching capacitor; the second end of the eighth switch and the second end of the ninth switch are both connected with the first end of the sixth switch, the first end of the sixth switch is connected with the first end of the seventh switch, and the second end of the seventh switch is grounded;

[0011] The first input end of the comparator is used for inputting a reference voltage signal, and the second end of the sixth switch is connected with the constant current source and the second input end of the comparator respectively;

[0012] The output end of the comparator is connected with the enable end of the counter, and the output end of the counter is connected with the processor;

[0013] The processor is connected with the control end of each switch and the control end of the first adjustable capacitor and the second adjustable capacitor.

[0014] In a second aspect, an oscillator frequency calibration method is provided, and the method comprises a calibration process of a first capacitor group and a calibration process of a second capacitor group;

[0015] The calibration process of the first capacitor group comprises:

[0016] The processor determines a target value of the first capacitor group according to a preset load capacitance value;

[0017] The processor controls the first switch, the second switch, the third switch, the fourth switch and the ninth switch to be in an open state, and controls the fifth switch and the eighth switch to be in a closed state;

[0018] The clock circuit provides a clock signal for the counter and the processor;

[0019] The processor controls the sixth switch to be in a closed state and controls the seventh switch to be in an open state;

[0020] The constant current source charges the first capacitor group;

[0021] The counter monitors the charging time;

[0022] The comparator compares whether the voltage value of the reference voltage signal and the voltage value of the first capacitor group are equal, if yes, instructs the counter to stop counting, if no, continues to compare;

[0023] The counter sends a first counting result to the processor after stopping counting;

[0024] The processor calculates the capacitance value of the first capacitor group according to the first counting result and the charging current of the constant current source, controls the sixth switch to be in an open state and the seventh switch to be in a closed state, judges whether the capacitance value of the first capacitor group is equal to the target value, if no, adjusts the capacitance value of the first adjustable capacitor according to the difference between the capacitance value of the first capacitor group and the target value, and then continues to calibrate, if yes, controls the sixth switch and the seventh switch to be in an open state, and ends the calibration process of the first capacitor group;

[0025] The calibration process of the second capacitor group comprises:

[0026] The processor determines the target value of the second capacitor group according to a preset load capacitance value;

[0027] The processor controls the first switch, the second switch, the third switch, the fourth switch and the eighth switch to be in an open state, and controls the fifth switch and the ninth switch to be in a closed state;

[0028] The clock circuit provides a clock signal for the counter and the processor;

[0029] The processor controls the sixth switch to be in a closed state, and controls the seventh switch to be in an open state;

[0030] The constant current source charges the second capacitor group;

[0031] The counter monitors the charging time;

[0032] The comparator compares whether the voltage value of the reference voltage signal and the voltage value of the second capacitor group are equal, if yes, instructs the counter to stop counting, if no, continues to compare;

[0033] The counter sends a second counting result to the processor after stopping counting;

[0034] The processor calculates the capacitance value of the second capacitor group according to the second counting result and the charging current of the constant current source, controls the sixth switch to be in an open state, and controls the seventh switch to be in a closed state; determines whether the capacitance value of the second capacitor group is equal to the target value, if not, adjusts the capacitance value of the second adjustable capacitor according to the difference between the capacitance value of the second capacitor group and the target value, and then continues to calibrate; if yes, controls the sixth switch and the seventh switch to be in an open state, and ends the calibration process of the second capacitor group.

[0035] In a third aspect, an embodiment of the present application provides a computer storage medium, which stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and performing the method steps described above.

[0036] In a fourth aspect, an embodiment of the present application provides an electronic device, which can include a processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the processor and performing the method steps described above.

[0037] The technical solutions provided by some embodiments of the present application have at least the following beneficial effects:

[0038] According to the target value of the two capacitor groups of the crystal oscillator determined according to the preset load capacitance value, the processor controls the opening or closing of each switch to realize the charging of the capacitor group and the measurement of the charging time, the processor calculates the capacitance value of the capacitor group according to the charging time measured by the counter and the charging current of the constant current source, adjusts the capacitance value of the adjustable capacitor in the capacitor group according to the difference between the calculated capacitance value and the target value, until the capacitance values of the two capacitor groups are equal to the target value, the present application realizes automatic matching of the capacitance value according to the actual demand of the crystal oscillator, so that the precision of the resonant frequency of the crystal oscillator meets the requirements, the whole calibration process does not need manual participation, and the time consumed in the calibration link of the crystal oscillator can be saved and the calibration cost can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0040] Figure 1 is a structural schematic diagram of a chip provided by an embodiment of the present application;

[0041] Figure 2 is a calibration process schematic diagram of a first capacitor group provided by an embodiment of the present application;

[0042] Figure 3is a calibration process schematic diagram of the second capacitor group provided by the embodiment of the application. DETAILED DESCRIPTION

[0043] For the purpose, technical solutions and advantages of the present application to be more clear, the following will be further described in detail with the embodiments of the present application in conjunction with the drawings.

[0044] Referring to Figure 1 As shown in the structure schematic diagram of the chip provided by the embodiment of the application, the chip is built-in with a crystal frequency calibration circuit, which comprises: a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8 and a ninth switch K9, a first capacitor group, a second capacitor group, a crystal oscillator driving circuit 1, a constant current source 2, a comparator 4, a counter 5 and a processor 6. The first capacitor group is composed of a first matching capacitor C1 and a first adjustable capacitor C1x in parallel, and the second capacitor group is composed of a second matching capacitor C2 and a second adjustable capacitor C2x. The chip is provided with two pins, which are connected with an external crystal oscillator 7 and a clock circuit 3 respectively. The clock circuit 3 and the crystal oscillator 4 share a pin of the crystal frequency calibration circuit, so as to save the number of occupied pins and improve the compactness of the circuit result. The chip of the present application can be a communication chip, an audio chip, a digital processing chip and various types of chips which need to generate a clock signal by using a passive crystal oscillator.

[0045] It should be noted that, Figure 1 In the circuit of the first capacitor group and the second capacitor group, in addition to the capacitors with known capacitance values, various parasitic capacitances are also included, such as: PAD capacitor, bonding wire capacitor, PIN capacitor and PCB trace capacitor, etc. Due to these parasitic capacitances, the real capacitance of the crystal oscillator has an error, which leads to an error in the resonant frequency of the crystal oscillator.

[0046] The processor 6 of the present application can be realized in at least one of the following hardware forms: Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), Programmable Logic Array (PLA).

[0047] In the embodiment, the connection relationship of the above-mentioned components included in the crystal frequency calibration circuit is as follows:

[0048] The first end of the crystal oscillator 7 is connected with the first end of the first switch K1, and the second end of the crystal oscillator 7 is connected with the clock output end of the clock circuit 3, which is used for outputting a clock signal.

[0049] The second end of the first switch K1 is connected with the first end of the third switch K3, the first end of the second matching capacitor C2 and the first end of the second adjustable capacitor C2x respectively, and the second end of the second matching capacitor C2 and the second end of the second adjustable capacitor C2x are grounded; the second end of the third switch K3 is connected with the crystal oscillator driving circuit 1, and the crystal oscillator driving circuit 1 is connected with the first end of the fourth switch K4; the crystal oscillator starting circuit 1 is used for providing driving voltage for the crystal oscillator 7 to drive the crystal oscillator 7 to start oscillation.

[0050] The clock output end of the clock circuit 3 is connected with the first end of the fifth switch K5 and the first end of the second switch K2 respectively; the second end of the second switch K2 is connected with the second end of the fourth switch K4, the first end of the first matching capacitor C1 and the first end of the first adjustable capacitor C1x respectively; the second end of the first matching capacitor C1 and the second end of the first adjustable capacitor C1x are grounded.

[0051] The second end of the fifth switch K5 is connected with the clock input end of the counter 5 and the clock input end of the processor 6 respectively.

[0052] The first end A of the eighth switch K8 is connected with the first end of the second matching capacitor C2, and the first end B of the ninth switch K9 is connected with the first end of the first matching capacitor C1; the second end C of the eighth switch K8 and the second end C of the ninth switch K9 are both connected with the first end of the sixth switch K6, the first end of the sixth switch K6 is connected with the first end of the seventh switch K7, and the second end of the seventh switch K7 is grounded GND.

[0053] The first input end of the comparator 4 is used for inputting a reference voltage signal, the second end of the sixth switch K6 is connected with the constant current source 2 and the second input end of the comparator 4 respectively; the output end of the comparator 4 is connected with the enable end EN of the counter 5, and the output end of the counter 5 is connected with the processor 6; the processor 6 is connected with the control ends of the switches K1-K9 and the control ends of the first adjustable capacitor C1x and the second adjustable capacitor C2x (not shown in the figure). Figure 1 The processor 6 can input control signals to the control ends of the switches K1-K9 to control the switches K1-K9 to be in the open state or the closed state; for example, a high-level signal controls the switch to be in the closed state, and a low-level signal controls the switch to be in the open state. In addition, the processor 6 can also input control instructions to the control ends of the first adjustable capacitor and the second adjustable capacitor to adjust the capacitance values thereof.

[0054] In this application, a crystal oscillator frequency calibration circuit is used to calibrate the crystal oscillator. The purpose of the calibration is to ensure that the capacitance values ​​of the first capacitor bank and the second capacitor bank are equal to twice the load capacitance value. The load capacitance value is set by the user according to actual needs and is related to the output frequency of the crystal oscillator. The calibration process of this application includes calibration procedures for the first capacitor bank and the second capacitor bank. The order of calibration is not limited in this application. The following explanation uses the calibration of the first capacitor bank as an example.

[0055] See Figure 2 As shown, the calibration procedure for the first capacitor bank includes:

[0056] S201. The processor determines the target value of the first capacitor bank according to the preset load capacitance value.

[0057] The first capacitance value is composed of a first matching capacitor and a first adjustable capacitor connected in parallel. The first matching capacitor is a fixed capacitor, meaning its capacitance value is fixed and cannot be adjusted. The first adjustable capacitor has an adjustable capacitance value and can be a capacitor array containing multiple capacitor branches. One or more capacitor branches are selected for conduction according to actual needs to adjust its capacitance value. Assume the load capacitance value can be determined according to actual needs. For example, if the user configures the load capacitance value based on the crystal oscillator's resonant frequency, and the load capacitance is CL, the capacitance value of the first matching capacitor in the first capacitor group is C1, and the capacitance value of the first adjustable capacitor is C1x, then the capacitance value of the first capacitor group is C1 + C1x. Correspondingly, the capacitance value of the first capacitor group needs to satisfy C1 + C1x = 2 × CL.

[0058] S202, the processor controls the first switch, the second switch, the third switch, the fourth switch and the ninth switch to be in the open state, and controls the fifth switch and the eighth switch to be in the closed state.

[0059] In the initial state, switches K1 through K9 may be in the open state. Processor 6 sends low-level signals to the control terminals of switches K1, K2, K3, K4, and K9 to control these four switches to be in the open state, and sends high-level signals to the control terminals of switches K5 and K8 to control these two switches to be in the closed state.

[0060] S203, the clock circuit provides clock signals for the counter and processor.

[0061] Since the fifth switch K5 in S202 is in the closed state, the clock circuit can provide clock signals to the counter 5 and the processor 6 through the second switch K5 so that the counter 5 and the processor 6 can work normally.

[0062] S204, the processor controls the sixth switch to be in a closed state and controls the seventh switch to be in an open state.

[0063] In the S204, the processor sends a high-level signal to the control end of the sixth switch K6 to control the sixth switch K6 to be in a closed state, so that a charging path is formed between the constant current source 2 and the first capacitor group. And sends a low-level signal to the control end of the seventh switch K7 to control the seventh switch K7 to be in an open state.

[0064] S205, the constant current source charges the first capacitor group.

[0065] In the S204, the sixth switch K6 is in a closed state, a charging path is formed between the constant current source 2 and the first capacitor group, the energizing path is from the sixth switch K6 and the first capacitor group to the ground, and the constant current source 2 charges the first capacitor group in a constant current mode.

[0066] S206, the counter monitors the charging time.

[0067] In the S204, the processor 6 sends a high-level signal to the sixth switch K6 to control the sixth switch K6 to be in a closed state, and instructs the counter to count to monitor the charging time. The charging time is equal to the counting frequency divided by the counting result.

[0068] S207, the comparator compares whether the voltage value of the reference voltage signal is equal to the voltage value of the first capacitor group.

[0069] The comparator is provided with a first input end, a second input end and an output end. The first input end is used to input a reference voltage signal, and the reference voltage signal is generated by a reference voltage circuit. The reference voltage circuit can be arranged in the internal or external of the chip. The second input end is used to detect the voltage value of the first capacitor group, and the voltage value is dynamically increased in the charging process. The voltage value of the reference voltage signal can be determined according to the actual demand, and the voltage value of the reference voltage signal should not be greater than the voltage value of the power supply. When the voltage value of the reference voltage signal is set to be large, the charging speed will be slow, but the calibration accuracy will be higher. On the contrary, when the voltage value of the reference voltage signal is set to be small, the charging speed will be fast, but the calibration accuracy will be lower. When the judgment result of S207 is yes, S208 is executed, and when the judgment result is no, S207 is continuously executed.

[0070] S208, the comparator instructs the counter to stop counting.

[0071] When the judgment result of S207 is no, the comparator 4 outputs a high-level signal on the output end. When the judgment result is no, the comparator 4 outputs a low-level signal on the output end. When the counter 5 detects that the comparator 4 outputs a high-level signal on the output end, the counting is stopped.

[0072] S209, the counter sends the first counting result to the processor after counting.

[0073] S210, the processor calculates the capacitance value of the first capacitor group according to the first counting result and the charging current of the constant current source, and controls the sixth switch to be in an open state and the seventh switch to be in a closed state.

[0074] The processor determines the charging time according to the first counting result and the counting frequency of the counter, and then calculates the current capacitance value of the first capacitor group according to the charging time, the charging current and the voltage value of the preset reference voltage signal. For example, the calculation is performed according to the following formula:

[0075] Wherein, n is the first counting result, f is the counting frequency, i c is the charging current, V th is the voltage value of the reference voltage signal. The processor 6 sends a low-level signal to the sixth switch K6 to control the sixth switch K6 to be in an open state, at which time the constant current source 2 stops charging the first capacitor group. The processor 6 sends a high-level signal to the seventh switch K7 to control the seventh switch to be in a closed state, at which time the first capacitor group forms a discharge path through the seventh switch K7 and discharges the first capacitor group.

[0076] S211, the processor determines whether the capacitance value of the first capacitor group is equal to the target value.

[0077] If the determination result is yes, S212 is executed, and if the determination result is no, S213 is executed.

[0078] S212, the processor controls the sixth switch and the seventh switch to be in an open state, and ends the calibration process of the first capacitor group.

[0079] S213, the processor adjusts the capacitance value of the first adjustable capacitor according to the difference between the capacitance value of the first capacitor group and the target value.

[0080] The processor sends a control command to the first adjustable capacitor according to the calculated difference value. For example, when the difference between the capacitance value of the first capacitor group and the target value is +△C, the processor instructs the first adjustable capacitor to reduce the current capacitance value by△C; when the difference between the capacitance value of the first capacitor group and the target value is -△C, the processor instructs the first adjustable capacitor to increase the current capacitance value by△C. After the adjustment is completed, the switches K1-K9 are reset to an open state, and then S202 is continued.

[0081] Referring to Figure 3 The calibration process of the second capacitor group provided by the embodiment of the application comprises:

[0082] S301, the processor determines the target value of the second capacitor group according to the preset load capacitance value.

[0083] Wherein, the first capacitance value is composed of a second matching capacitance and a second adjustable capacitance in parallel, the second matching capacitance is a fixed capacitance, i.e. the capacitance value is fixed and not adjustable. The capacitance value of the second adjustable capacitance is adjustable, and the second adjustable capacitance can be a capacitor array, which includes a plurality of capacitor branches. According to actual needs, one or more capacitor branches are selected to be turned on to adjust the capacitance value. The size of the load capacitance value can be determined according to actual needs, for example: the user configures the size of the load capacitance value according to the resonant frequency of the crystal oscillator. Assuming that the load capacitance value is CL, the capacitance value of the second matching capacitance in the second capacitor group is C2, and the capacitance value of the second adjustable capacitance is C2x, then the capacitance value of the second capacitor group is C2+C2x, and the capacitance value of the second capacitor group needs to satisfy C2+C2x=2×CL.

[0084] S302, the processor controls the first switch, the second switch, the third switch, the fourth switch and the eighth switch to be in an open state, and controls the fifth switch and the ninth switch to be in a closed state.

[0085] Wherein, in the initial state, the first switch K1 to the ninth switch K9 can be in an open state. The processor 6 sends a low-level signal to the control end of the first switch K1, the second switch K2, the third switch K3, the fourth switch K4 and the eighth switch K8 to control the above-mentioned four switches to be in an open state, and the processor 6 sends a high-level signal to the control end of the fifth switch K5 and the ninth switch K9 to control the above-mentioned two switches to be in a closed state.

[0086] S303, the clock circuit provides a clock signal for the counter and the processor.

[0087] Wherein, since the fifth switch K5 in S302 is in a closed state, the clock circuit can provide a clock signal for the counter 5 and the processor 6 through the second switch K5, so that the counter 5 and the processor 6 work normally.

[0088] S304, the processor controls the sixth switch to be in a closed state and controls the seventh switch to be in an open state.

[0089] Wherein, the processor sends a high-level signal to the control end of the sixth switch K6 to control the sixth switch K6 to be in a closed state, so that a charging path is formed between the constant current source 2 and the second capacitor group. And a low-level signal is sent to the control end of the seventh switch K7 to control the seventh switch K7 to be in an open state.

[0090] S305, the constant current source charges the second capacitor group.

[0091] In S304, the sixth switch K6 is in the closed state, the charging path is formed between the constant current source 2 and the second capacitor group, and the current path is from the sixth switch K6 and the second capacitor group to the ground. The constant current source 2 charges the second capacitor group in a constant current mode.

[0092] In S306, the counter monitors the charging time.

[0093] In S306, the processor 6 sends a high-level signal to the sixth switch K6 to control the sixth switch K6 to be in the closed state, and instructs the counter to count to monitor the charging time. The charging time is equal to the counting frequency divided by the counting result.

[0094] In S307, the comparator compares whether the voltage value of the reference voltage signal is equal to the voltage value of the second capacitor group.

[0095] In S307, the comparator is provided with a first input end, a second input end and an output end. The first input end is used to input the reference voltage signal, and the reference voltage signal is generated by a reference voltage circuit. The reference voltage circuit can be arranged inside or outside the chip. The second input end is used to detect the voltage value of the second capacitor group, and the voltage value is dynamically increased during the charging process. The voltage value of the reference voltage signal can be determined according to actual needs, and the voltage value of the reference voltage signal should not be greater than the voltage value of the power supply. When the voltage value of the reference voltage signal is set to be large, the charging speed will be slow, but the calibration accuracy will be higher. Conversely, when the voltage value of the reference voltage signal is set to be small, the charging speed will be fast, but the calibration accuracy will be lower. When the judgment result of S307 is yes, S308 is executed, and when the judgment result is no, S307 is continuously executed.

[0096] In S308, the comparator instructs the counter to stop counting.

[0097] In S307, when the judgment result is no, the comparator 4 outputs a high-level signal on the output end. When the judgment result is no, the comparator 4 outputs a low-level signal on the output end. When the counter 5 detects that the comparator 4 outputs a high-level signal on the output end, the counting is stopped.

[0098] In S309, the counter notifies the processor of the second counting result after counting.

[0099] In S310, the processor calculates the capacitance value of the second capacitor group according to the second counting result and the charging current of the constant current source, and controls the sixth switch to be in the open state and the seventh switch to be in the closed state.

[0100] In S310, the processor calculates the capacitance value of the second capacitor group according to the second counting result and the counting frequency of the counter, and then calculates the current capacitance value of the second capacitor group according to the charging time, the charging current and the preset voltage value of the reference voltage signal. For example, the calculation is performed according to the following formula:

[0101] wherein n is the second counting result, f is the counting frequency, i c is the charging current, V th is the voltage value of the reference voltage signal. The processor 6 sends a low-level signal to the sixth switch K6 to control the sixth switch K6 to be in an open state, at which time the constant current source 2 stops charging the second capacitor group. The processor 6 sends a high-level signal to the seventh switch K7 to control the seventh switch to be in a closed state, at which time the second capacitor group forms a discharging path through the seventh switch K7 to discharge the second capacitor group.

[0102] S311, the processor determines whether the capacitance value of the second capacitor group is equal to the target value.

[0103] wherein if the determination result is yes, S312 is executed, and if the determination result is no, S313 is executed.

[0104] S312, the processor controls the sixth switch and the seventh switch to be in an open state, and ends the calibration process of the second capacitor group.

[0105] S313, the processor adjusts the capacitance value of the second adjustable capacitor according to the difference between the capacitance value of the second capacitor group and the target value.

[0106] wherein the processor sends a control command to the second adjustable capacitor according to the calculated difference, for example: when the difference between the capacitance value of the second capacitor group and the target value is +△C, the processor instructs the second adjustable capacitor to reduce the current capacitance value by△C; when the difference between the capacitance value of the second capacitor group and the target value is -△C, the processor instructs the second adjustable capacitor to increase the current capacitance value by△C, after the adjustment, the switches K1-K9 are reset to an open state, and then S302 is continued to be executed.

[0107] In the embodiment, the method further comprises:

[0108] After the calibration of the first capacitor group and the second capacitor group is completed, the processor controls the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 to be in a closed state, and controls the fifth switch K5, the sixth switch K6, the seventh switch K7, the eighth switch K8, and the ninth switch K9 to be in an open state, the clock circuit is in an open state and no longer outputs a clock signal, and the crystal oscillator driving circuit drives the crystal oscillator and the first capacitor group and the second capacitor group to start oscillation.

[0109] In the embodiment, the target values of the two capacitor groups of the crystal oscillator are determined according to the preset load capacitance, the processor controls the opening or closing of each switch to realize the charging of the capacitor groups and the measurement of the charging time, the processor calculates the capacitance of the capacitor groups according to the charging time measured by the counter and the charging current of the constant current source, and adjusts the capacitance of the adjustable capacitor in the capacitor group according to the difference between the calculated capacitance and the target value until the capacitances of the two capacitor groups are equal to the target values. The application realizes automatic matching of the capacitance according to the actual requirements of the crystal oscillator, so that the precision of the resonant frequency of the crystal oscillator meets the requirements, the entire calibration process does not need manual participation, and the time consumed in the calibration link of the crystal oscillator can be saved and the calibration cost can be reduced.

[0110] In the application, an electronic device is also provided, which comprises a shell, the shell containing the chip, the clock circuit and the crystal oscillator, the clock circuit and the crystal oscillator being located outside the chip, and the chip can be a communication chip, an audio chip or a digital processing chip, etc., which is not limited in the application. In addition to the above components, the electronic device can also comprise a keyboard, a touch screen or a loudspeaker, etc.

[0111] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware, and the program can be stored in a computer readable storage medium, and when the program is executed, the processes of the above-mentioned embodiments can be included. The storage medium can be a magnetic disc, an optical disc, a read-only memory or a random access memory, etc.

[0112] The above disclosure is only the preferred embodiment of the application, and of course cannot limit the scope of the application, so equivalent changes made according to the claims of the application are still within the scope of the application.

Claims

1. A crystal frequency calibration circuit, characterized by, The crystal frequency calibration circuit is connected with a clock circuit and a crystal oscillator; The crystal frequency calibration circuit comprises: a crystal oscillator driving circuit, a first capacitor group, a second capacitor group, a constant current source, a comparator, a counter, a processor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch and a ninth switch; the first capacitor group is composed of a first matching capacitor and a first adjustable capacitor connected in parallel, and the second capacitor group is composed of a second matching capacitor and a second adjustable capacitor connected in parallel; The first end of the crystal oscillator is connected with the first end of the first switch, and the second end of the crystal oscillator is connected with the clock circuit; the capacitance of the first capacitor group is equal to the capacitance of the second capacitor group, and is equal to twice the load capacitance of the crystal oscillator; the load capacitance is set according to actual user requirements, and the load capacitance is related to the output frequency of the crystal oscillator; The second end of the first switch is connected with the first end of the third switch, the first end of the second matching capacitor and the first end of the second adjustable capacitor respectively, and the second end of the second matching capacitor and the second end of the second adjustable capacitor are grounded; the second end of the third switch is connected with the crystal oscillator driving circuit, and the crystal oscillator driving circuit is connected with the first end of the fourth switch; The clock circuit is connected with the first end of the fifth switch and the first end of the second switch respectively; the second end of the second switch is connected with the second end of the fourth switch, the first end of the first matching capacitor and the first end of the first adjustable capacitor respectively; the second end of the first matching capacitor and the second end of the first adjustable capacitor are grounded; The second end of the fifth switch is connected with the clock input end of the counter and the clock input end of the processor respectively; The first end of the eighth switch is connected with the first end of the second matching capacitor, and the first end of the ninth switch is connected with the first end of the first matching capacitor; the second end of the eighth switch and the second end of the ninth switch are both connected with the first end of the sixth switch, the first end of the sixth switch is connected with the first end of the seventh switch, and the second end of the seventh switch is grounded; The first input end of the comparator is used for inputting a reference voltage signal, and the second end of the sixth switch is connected with the constant current source and the second input end of the comparator respectively; The output end of the comparator is connected with the enable end of the counter, and the output end of the counter is connected with the processor; The processor is connected with the control ends of the switches and the control ends of the first adjustable capacitor and the second adjustable capacitor; further comprising: a reference voltage circuit connected with the first input end of the comparator, which is used for inputting a reference voltage signal; The first adjustable capacitor and the second adjustable capacitor comprise a capacitor matrix; In addition to the capacitors with known capacitances included in the first capacitor group and the second capacitor group, various parasitic capacitors are also included in the circuit; The clock circuit and the crystal oscillator share one pin of the crystal frequency calibration circuit, so as to save the number of occupied pins and improve the compactness of the circuit result.

2. A chip, characterized by The chip is connected with an external crystal oscillator and a clock circuit.

3. An electronic device, comprising: The chip is connected with an external crystal oscillator and a clock circuit.

4. A crystal oscillator frequency calibration method, characterized by, The method is applied to the crystal oscillator frequency calibration circuit in claim 1, and the method comprises a calibration process of a first capacitor group and a calibration process of a second capacitor group. The calibration process of the first capacitor group comprises: The processor determines a target value of the first capacitor group according to a preset load capacitance value; The processor controls the first switch, the second switch, the third switch, the fourth switch and the ninth switch to be in an open state, and controls the fifth switch and the eighth switch to be in a closed state; The clock circuit provides a clock signal for the counter and the processor; The processor controls the sixth switch to be in a closed state and controls the seventh switch to be in an open state; The constant current source charges the first capacitor group; The counter monitors a charging time; The comparator compares whether the voltage value of the reference voltage signal and the voltage value of the first capacitor group are equal, and if yes, instructs the counter to stop counting; if no, continues to compare; The counter sends a first counting result to the processor after stopping counting; The processor calculates the capacitance value of the first capacitor group according to the first counting result and the charging current of the constant current source, controls the sixth switch to be in an open state and controls the seventh switch to be in a closed state, and judges whether the capacitance value of the first capacitor group is equal to the target value; if no, adjusts the capacitance value of the first adjustable capacitor according to the difference between the capacitance value of the first capacitor group and the target value, and then continues to calibrate; if yes, controls the sixth switch and the seventh switch to be in an open state, and ends the calibration process of the first capacitor group; The calibration process of the second capacitor group comprises: The processor determines a target value of the second capacitor group according to a preset load capacitance value; The processor controls the first switch, the second switch, the third switch, the fourth switch and the eighth switch to be in an open state, and controls the fifth switch and the ninth switch to be in a closed state; The clock circuit provides a clock signal for the counter and the processor; The processor controls the sixth switch to be in a closed state and controls the seventh switch to be in an open state; The constant current source charges the second capacitor group; The counter monitors a charging time; The comparator compares whether the voltage value of the reference voltage signal and the voltage value of the second capacitor group are equal, and if yes, instructs the counter to stop counting; if no, continues to compare; The counter sends a second counting result to the processor after stopping counting; The processor calculates the capacitance of the second capacitor group according to the second counting result and the charging current of the constant current source, controls the sixth switch to be in an open state, and controls the seventh switch to be in a closed state; determines whether the capacitance of the second capacitor group is equal to the target value, if not, adjusts the capacitance of the second adjustable capacitor according to the difference between the capacitance of the second capacitor group and the target value, and then continues to calibrate; if yes, controls the sixth switch and the seventh switch to be in an open state, and ends the calibration process of the second capacitor group.

5. The method of claim 4, wherein, Also includes: After completing the calibration process of the first capacitor group and the calibration process of the second capacitor group, the processor controls the first switch, the second switch, the third switch and the fourth switch to be in a closed state, and controls the fifth switch, the sixth switch, the seventh switch, the eighth switch and the ninth switch to be in an open state.

6. The method according to claim 4 or 5, characterized in that, The capacitance of the first capacitor group is calculated according to the following formula: ; where n is the first count result, f is a count frequency, is a charging current, is a voltage value of the reference voltage signal.

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