Hierarchical coding method and apparatus, terminal device, and medium

Abstract

The application discloses a layered decoding method and device, a terminal equipment and a medium, wherein the method comprises the following steps: performing column reordering on a low-density parity-check code (LDPC) check base matrix to obtain a reordered check base matrix; performing layered reordering on the reordered check base matrix to obtain an optimal check base matrix; and decoding soft information to be decoded according to the optimal check base matrix to obtain corresponding decoding information. By using the application, the technical problems in the prior art, such as high QC-DPLC decoding implementation complexity, difficulty in meeting the requirements of link transmission delay and throughput, and the like, can be solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, and in particular to a layered decoding method and device, a terminal device and a medium. BACKGROUND

[0002] Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) is widely used in wireless communication protocols such as Wi-Max, Wi-Fi and DVB-S2 due to its excellent error correction performance. However, in practice, it is found that the decoding implementation complexity of QC-DPLC is high, which is difficult to meet the requirements of link transmission delay and throughput. SUMMARY

[0003] The embodiment of the present application provides a layered decoding method, which solves the technical problems of high decoding implementation complexity of QC-DPLC in the prior art, which is difficult to meet the requirements of link transmission delay and throughput.

[0004] In one aspect, the embodiment of the present application provides a layered decoding method, which comprises the following steps:

[0005] reordering columns of a Low-Density Parity-Check (LDPC) check matrix to obtain a reordered check matrix;

[0006] reordering layers of the reordered check matrix to obtain an optimal check matrix;

[0007] decoding soft information to be decoded according to the optimal check matrix to obtain corresponding decoding information.

[0008] Optionally, the reordering columns of the LDPC check matrix to obtain the reordered check matrix comprises the following steps:

[0009] reordering column orders of the LDPC check matrix to obtain the reordered check matrix;

[0010] wherein a difference between the number of non-zero elements in the first i columns and the number of non-zero elements in the last j columns in the reordered check matrix does not exceed a first threshold, i and j are positive integers, and a sum of i and j is equal to a total sum of column numbers of all columns in the LDPC check matrix.

[0011] Optionally, i and j are equal.

[0012] Optionally, the reordering column orders of the LDPC check matrix to obtain the reordered check matrix comprises the following steps:

[0013] S41: according to the element distribution of each column in the LDPC check matrix, reordering each column in the LDPC check matrix with non-zero elements exceeding a second threshold and being lower than a third threshold, to obtain a rearranged check matrix;

[0014] S42, calculating the difference between the number of non-zero elements in the first i columns and the last j columns in the rearranged check matrix;

[0015] S43, reordering the column order of each column in the rearranged check matrix, and repeating step S42 until the repetition number reaches a preset number;

[0016] S44, determining the rearranged check matrix with the smallest difference as the ordered check matrix.

[0017] Optionally, the hierarchical rearrangement of the ordered check matrix to obtain the optimal check matrix comprises the following steps:

[0018] S51, rearranging the ordered check matrix to obtain a hierarchical check matrix;

[0019] S52, determining the first base matrix and the second base matrix corresponding to the matrix in the first i columns and the last j columns of the hierarchical check matrix, respectively;

[0020] S53, using a preset read-write hierarchical algorithm to perform hierarchical iteration calculation on the first base matrix and the second base matrix, to obtain calculation information of the hierarchical check matrix, the calculation information comprising a clock cycle required for single iteration, a number of clock cycles, a read data order and a write data order, the read data order being used to indicate a read order of reading each element data in the hierarchical check matrix, and the write data order being used to indicate a write order of writing each element data in the hierarchical check matrix;

[0021] S54, reordering the layer order of each layer in the ordered check matrix, and repeating steps S52-S53 until the repetition number reaches a preset number;

[0022] S55, determining the hierarchical check matrix with the smallest number of clock cycles required for single iteration as the optimal check matrix.

[0023] Optionally, the decoding of the soft information to be decoded according to the optimal check matrix to obtain corresponding decoding information comprises the following steps:

[0024] S61, reordering the soft information to be decoded according to the column number of each column in the optimal check matrix, to obtain ordered soft information;

[0025] S62, performing double-sided low-delay layered iterative decoding on the sorted soft information according to the read data order and the write data order by using a layered iterative decoding algorithm to obtain corresponding decoding codewords;

[0026] S63, outputting the decoding codewords according to column orders of columns in the sorted check matrix to obtain the decoding information.

[0027] Optionally, the method is applied to a layered decoder, the LDPC decoder comprising a first buffer Q_buffer_wrap, a first shifter, a calculator, an updater PU_wrap, a second buffer R_buffer_wrap, a third buffer T_buffer_wrap, a second shifter and a hard decision decoder, and the method further comprises the following implementation steps:

[0028] S71, writing the soft information to be decoded into the first buffer according to column numbers of columns in the optimal check matrix;

[0029] S72, shifting the soft information to be decoded in the first buffer by the first shifter in a preset first direction;

[0030] S73, calculating the soft information to be decoded after shifting and check node update information stored in the second buffer in a previous iteration decoding by the calculator to obtain variable node update information, and storing the variable node update information to the updater and the third buffer;

[0031] S73, calculating the check node update information corresponding to the variable node and the update information of the soft information to be decoded by the updater according to the read data order, the write data order and the variable node update information by using a layered iterative decoding algorithm;

[0032] S74, shifting the update information of the soft information to be decoded by the second shifter in a preset second direction, the preset first direction being opposite to the preset second direction;

[0033] S75, performing hard decision decoding on the update information of the soft information to be decoded by the hard decision decoder to obtain corresponding decoding codewords.

[0034] In another aspect, an embodiment of the present application provides a layered decoding device, which comprises a column sorting module, a layer sorting module and a decoding module, wherein:

[0035] The column sorting module is configured to perform column reordering on a low-density parity-check code (LDPC) check matrix to obtain a sorted check matrix.

[0036] The layer ordering module is configured to reorder the sorted check matrix in layers to obtain an optimal check matrix.

[0037] The decoding module is configured to decode the soft information to be decoded according to the optimal check matrix to obtain corresponding decoding information.

[0038] In another aspect, an embodiment of the present application provides a terminal device, which comprises a processor, a memory, a communication interface and a bus; the processor, the memory and the communication interface are connected through the bus and complete communication with each other; the memory stores executable program codes; the processor runs programs corresponding to the executable program codes by reading the executable program codes stored in the memory, so as to execute the layered decoding method as described above.

[0039] In another aspect, an embodiment of the present application provides a computer readable storage medium, which stores programs, and when the programs run in a terminal device, the layered decoding method as described above is executed.

[0040] The one or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages: the present application reorders a low-density parity-check code (LDPC) check matrix in columns to obtain a sorted check matrix; the sorted check matrix is reordered in layers to obtain an optimal check matrix; finally, soft information to be decoded is decoded according to the optimal check matrix to obtain corresponding decoding information. In the above solution, the LDPC check matrix is reordered in columns and layers to obtain an optimal check matrix supported by a communication protocol, and then information decoding is performed based on the optimal check matrix, which can reduce decoding complexity, improve decoding efficiency, and solve the technical problems such as high QC-DPLC decoding implementation complexity, difficulty in meeting link transmission delay and throughput requirements and the like in the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0042] Figure 1 is a flowchart of a layered decoding method provided by an embodiment of the present application.

[0043] Figure 2 is a flowchart of a layered decoding method provided by an embodiment of the present application.

[0044] Figure 3 is a structural schematic diagram of a layered decoder provided by an embodiment of the present application.

[0045] Figure 4 is a structural schematic diagram of a layered decoding device provided by an embodiment of the present application.

[0046] Figure 5 is a structural schematic diagram of a terminal device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0047] The applicant has also found in the process of filing the present application that the QC-LDPC decoding implementation complexity is high, and in order to reduce the decoding complexity, an offset min-sum algorithm (OMS) or a normalized min-sum algorithm (NMS) can be usually used for approximate decoding at the algorithm level. A full-parallel and block-parallel framework is usually used at the implementation framework, but the full-parallel framework can achieve a higher throughput but has a higher hardware complexity and area, and the block-parallel is difficult to meet the requirements of link transmission delay and throughput.

[0048] The embodiment of the present application provides a layered decoding method, which solves the technical problems of high QC-DPLC decoding implementation complexity and difficulty to meet the requirements of link transmission delay and throughput in the prior art.

[0049] The technical scheme of the embodiment of the present application is to solve the above technical problems, and the general idea is as follows: performing column-wise reordering on a low-density parity-check code (LDPC) check matrix to obtain a reordered check matrix; performing layered reordering on the reordered check matrix to obtain an optimal check matrix; and decoding soft information to be decoded according to the optimal check matrix to obtain corresponding decoding information.

[0050] In order to better understand the above technical scheme, the above technical scheme will be described in detail in combination with the drawings of the specification and specific embodiments.

[0051] Firstly, it should be noted that the term "and / or" appearing in the present document only describes the association relationship of the associated objects, and can represent three kinds of relationships, for example, A and / or B can represent three cases of existence of A alone, existence of A and B together, and existence of B alone. In addition, the character " / " in the present document generally represents an "or" relationship between the front and rear associated objects.

[0052] Please refer to Figure 1 is a flowchart of a layered decoding method provided by an embodiment of the present application. As shown in Figure 1The method shown is applied to a layered decoder based on a communication device, including but not limited to a WLAN device, a mobile phone, a computer, or other communication-enabled devices, etc. The method includes the following implementation steps:

[0053] S101, reordering the columns of the low-density parity check code (LDPC) check base matrix to obtain a sorted check base matrix C best .

[0054] The low-density parity check code (LDPC) described in this application is the original check matrix base matrix (referred to as check base matrix) supported in the communication protocol. This application can reorder the column order of the LDPC check base matrix to obtain the corresponding sorted check base matrix. Among them, the difference between the number of non-zero elements in the first i columns and the last j columns in the sorted check base matrix is as equal as possible, for example, not more than a first threshold, etc. Wherein, i and j are positive integers. Optionally, the sum of i and j is equal to the total sum of the column numbers of all columns in the LDPC check base matrix, that is, i+j is equal to the total column number of the LDPC check base matrix.

[0055] For example, please refer to Figure 2 A possible layered decoding method is shown in the decoding process diagram. As Figure 2 In the LDPC check base matrix, for example, the LDPC check base matrix is a 4x24 matrix, in other words, the LDPC check base matrix is divided into 4 layers (i.e. 4 rows) and 24 columns. In the diagram, the white box is the zero element data.

[0056] In a specific embodiment, step S101 specifically includes the following implementation steps:

[0057] S41: According to the element distribution of each column in the LDPC check base matrix, reorder each column in the LDPC check base matrix that has more than a second threshold and less than a third threshold of non-zero elements to obtain a reordered check base matrix.

[0058] This application can reorder the columns corresponding to more and less non-zero elements (for example, the number of non-zero elements exceeds a second threshold and is less than a third threshold) in the LDPC check base matrix according to the element (data) distribution of each column in the LDPC check base matrix. To obtain a reordered check base matrix.

[0059] The first threshold, the second threshold and the third threshold involved in this application are all system-defined settings, which can be the same or different, and this application does not limit them.

[0060] S42, calculate the difference between the number of non-zero elements in the first i columns and the last j columns in the reordered check base matrix.

[0061] This application can count the number of non-zero elements in the first i columns and the number of non-zero elements in the last j columns of the rearranged check matrix, and then calculate the difference between them to obtain the difference in the number of non-zero elements in the first i columns and the last j columns of the rearranged check matrix.

[0062] S43. Reorder the column order of each column in the rearranged verification base matrix, and repeat step S42 until the number of repetitions reaches the preset number.

[0063] This application can readjust and update the column order of each column in the rearranged check matrix, and repeat step S42 until the number of repetitions reaches a preset number. Optionally, the difference in the number of non-zero elements in the first i columns and the last j columns of the rearranged check matrix calculated each time can be recorded.

[0064] S44. The rearranged verification base matrix with the smallest difference in quantity is determined as the sorting verification base matrix.

[0065] This application determines the rearranged check matrix with the smallest value among the differences in the quantities calculated each time as the sorting check matrix.

[0066] For example, citation Figure 2 As shown in the example, by observing the construction of the LDPC parity-check matrix, this application can see that the first 5 columns of the LDPC parity-check matrix have more non-zero elements, while the last 5 columns have fewer. This application can first perform a full permutation of the column element sets formed by the first 5 and last 5 columns of the LDPC parity-check matrix to obtain the corresponding rearranged parity-check matrix. The total difference in the number of non-zero elements in the first 12 columns and the last 12 columns of each layer under the rearranged parity-check matrix (i.e., under the current permutation) is calculated as the difference in the number of non-zero elements in the first 12 columns and the last 12 columns of the current rearranged parity-check matrix. The column order of each column in the rearranged parity-check matrix is ​​updated, and the corresponding difference in number is repeatedly calculated. The permutation C with the smallest difference in number is recorded. best , which serves as the sorting verification base matrix.

[0067] S102. Perform hierarchical reordering on the sorted verification base matrix to obtain the optimal verification base matrix.

[0068] In one specific embodiment, step S102 specifically includes the following implementation steps:

[0069] S51, the sorting verification base matrix C best The hierarchical rearrangement is performed to obtain the hierarchical parity matrix.

[0070] This application can verify the sorting and checking base matrix C obtained in step S101. best Perform a full permutation of the layers according to their hierarchical structure to obtain the corresponding layered parity-check basis matrix H.perm .

[0071] S52. Determine the matrices corresponding to the first i columns and the last j columns of the hierarchical verification basis matrix as the first basis matrix H. p1 Second basis matrix H p2 .

[0072] S53. Using a preset read-write layered algorithm, perform layered iterative calculations on the first base matrix and the second base matrix to obtain the calculation information of the layered parity base matrix. The calculation information includes the clock cycles required for a single iteration, the number of clock cycles, the read data order, and the write data order. The read data order indicates the order in which data is read from each element of the layered parity base matrix, and the write data order indicates the order in which data is written to each element of the layered parity base matrix.

[0073] This application first refers to C best Rearranged H perm The first i columns are re-recorded as H in column order, incrementing by column number. p1 The following columns are re-recorded as H in ascending order. p2 For example, this application Figure 2 Lieutenant General H perm The first 12 columns and the last 12 columns are all re-recorded in ascending order as H. p1 and H p2 This application employs a pre-defined read-write layered algorithm (also known as the first algorithm or Algorithm 1) to calculate the clock cycle for the first base matrix and the second base matrix respectively, obtaining the corresponding first clock cycle TL1 and second clock cycle TL2. The total clock cycle required for a single iteration is TL3 = max(TL1, TL2).

[0074] And in Algorithm 1, the data pipeline is first divided into two stages: reading phase (RP) and writing phase (WP). Among them, the reading phase mainly completes the information change of the variable node passing to the check node (hereinafter also referred to as check node change information), and the writing phase mainly completes the information change of the check node passing to the variable node (hereinafter also referred to as variable node change information). Algorithm 1 can also calculate the read data sequence read_seq and the write data sequence write_seq, which respectively indicate the access sequence of the column data block, that is, the sequence of reading / writing each element data (block) in the base matrix. It is worth noting that due to the data dependency of the layered iterative decoding algorithm, the read / write sequence (read_seq and write_seq) in Algorithm 1 defines three priorities to try to clear the pipeline bubbles as much as possible, so that the pipeline bubble filling is as small as possible, that is, the number of clock cycles required for a single iteration is minimized, and the priority is as shown in Figure 1 R0, R1, R2, W0, W1 and W2, and the number of clock cycles consumed by each layer of the base matrix is also calculated len_layer. The code of Algorithm 1 is as follows:

[0075]

[0076]

[0077] S54, re-adjust the layer order of each layer in the layered check base matrix, and repeat steps S52-S53 until the number of repetitions reaches a preset number of times.

[0078] S55, the layered check base matrix with the smallest number of clock cycles required for a single iteration is determined as the optimal check base matrix.

[0079] The application can update the layer order of each layer in the layered check base matrix (that is, update the row arrangement order), and repeat the above steps S52 and S53 until the number of repetitions reaches a preset number of times, such as after performing layered full permutation on the layered check base matrix. Further, the application can record the layered check base matrix with the smallest number of clock cycles required for a single iteration / total number, and determine it as the optimal check base matrix R best and R best The corresponding read data sequence read_seq and write data sequence write_seq.

[0080] S103, decoding the soft information to be decoded according to the optimal check base matrix to obtain the corresponding decoding information.

[0081] In a specific embodiment, step S103 specifically includes the following implementation steps:

[0082] S61, reordering the soft information to be decoded according to the column degrees of each column in the optimal check matrix, to obtain ordered soft information.

[0083] The present application is based on C best The received soft information to be decoded is reordered according to the column order of each column (i.e. R best The corresponding ordered soft information L 1×N is obtained.

[0084] S62, using a hierarchical iterative decoding algorithm to perform double-sided low-delay hierarchical iterative decoding on the ordered soft information according to the read data order and the write data order, to obtain the corresponding decoded codeword.

[0085] The hierarchical iterative decoding algorithm described in the present application includes but is not limited to NMS algorithm, OMS algorithm, or other hierarchical decoding algorithms, etc. The following text of the present application takes NMS algorithm (also known as algorithm 2) as an example to explain the relevant content, but does not constitute a limitation. The present application uses NMS algorithm to perform double-sided low-delay hierarchical iterative decoding on the reordered ordered soft information, wherein the coefficient coef involved in algorithm 2 is set to 0.75.

[0086] In a specific implementation, the present application first needs to perform initialization operation in the first stage, specifically, the present application initializes the check node update information to 0, and initializes the iterative ordered soft information to the channel estimated log-likelihood ratio information L 1×N . The second stage starts to perform iterative decoding, specifically, for each layer of data, the minimum value m1 and the second minimum value m2 of the absolute value of the variable node update information are both initialized to the maximum value. For implementation, it is the corresponding maximum value of the quantization bit width. The cumulative symbol s is initialized to the maximum value, indicating that the message is positive. After the initialization is completed, the present application needs to change the variable node (change) information according to the element data order (read_seq) specified for each layer, and record the m1, m2 and the index index1 of the variable node corresponding to m1 and s of the variable node update information of the layer.

[0087] Similarly, when the check node change information is changed, the variable node indicated by the current order is determined according to the element data order (write_seq) specified by each layer, whether it is the position corresponding to the minimum value m1 of the variable node update message of the layer (that is, whether the position of the variable node of the current order is consistent with index1), if consistent, the minimum value of the other variable node update information adjacent to the check node is m2, otherwise it is m1. After obtaining the minimum value, the check node (update) information is updated according to the NMS algorithm, and the update of the iterative soft information is completed at the same time. It is worth noting that the obtained update information of the iterative soft information needs to be inversely rotated to avoid destroying the order of the iterative soft information, and then affecting the corresponding rotation of the next time. The code of algorithm 2 is as follows:

[0088]

[0089] S63、According to the sorting check base matrix C best The column order of each column in the column order outputs the decoding code word, and obtains the decoding information.

[0090] When the number of iterations reaches the preset maximum number of iterations, the decoded decoding code word is output. Specifically, the present application can output the corresponding decoding code word according to the column order of C best , so as to obtain the decoding information.

[0091] In an optional embodiment, the present application can use hardware to generate a corresponding LDPC decoder according to the decoding information. Please refer to Figure 3 shows a structure schematic diagram of a layered decoder (LDPC decoder). As Figure 3The hierarchical decoder includes: a first buffer Q_buffer_wrap, a first shifter Cyclic_shifter_wrap1, a calculator T_caculator_wrap, an updater PU_wrap, a second buffer R_buffer_wrap, a third buffer T_buffer_wrap, a second shifter Cyclic_shifter_warp2, and a hard decision decoder Hard_decision. Optionally, the first buffer Q_buffer_wrap, the first shifter Cyclic_shifter_wrap1, the calculator T_caculator_wrap, the updater PU_wrap, the second buffer R_buffer_wrap, the third buffer T_buffer_wrap, and the second shifter Cyclic_shifter_warp2 each includes two sub-components to implement the operation of a corresponding data stream (or data pipeline). Optionally, the hierarchical decoder further includes a lookup table (H-LUT) for querying the specific shift value required by the first shifter or the second shifter, so that each shifter performs a specific shift value of the corresponding direction, such as left shift 48 bits, etc. The specific implementation includes the following implementation steps:

[0092] S71, write the soft information to be decoded into the first buffer according to the column degree of each column in the optimal check matrix.

[0093] S72, shift the soft information to be decoded in the first buffer by the first shifter in a preset first direction.

[0094] S73, calculate the variable node update information by the calculator from the soft information to be decoded after the shift and the check node update information stored in the second buffer in the previous iteration decoding, and store it to the updater and the third buffer.

[0095] S73, calculate the check node update information corresponding to the variable node and the update information of the soft information to be decoded by the updater according to the read data order, the write data order, and the variable node update information using the hierarchical iterative decoding algorithm.

[0096] S74, shift the update information of the soft information to be decoded by the second shifter in a preset second direction, and the preset first direction is opposite to the preset second direction.

[0097] S75, perform hard decision decoding on the update information of the soft information to be decoded by the hard decision decoder to obtain the corresponding decoded codeword.

[0098] The following describes the specific implementation of steps S71-S75.

[0099] First, the present application is based on C best the column order of each column (i.e., the column number of each column in R best The soft information L 1×N to be decoded is written into the first buffer Q_buffer_wrap (specifically, Q_buffer_wrap1 and Q_buffer_wrap2).

[0100] Next, the present application performs iterative decoding according to the layered decoder shown in Algorithm 2 and Figure 3 Specifically, the input LLR information (i.e., the soft information L 1×N to be decoded) is first stored in Q_buffer_wrap, which simultaneously serves as an LLR message update memory. R_buffer_wrap is initialized to 0. In consideration of the pipelining processing of consecutive frames and consecutive codewords, Q_buffer_x (x is 1 or 2) and R_buffer_x each have two groups of the same size inside. Each group of Q_buffer_x has a depth of 16 and a bit width of 567, which is in consideration of code length compatibility. The H matrix divides the codeword into 24 data blocks block, and the largest expansion factor z = 81 corresponds to a code length of 1944, so the bit width is (81*7 bits (quantization bit width)). In order to reduce the pipeline depth, Q_buffer_x can use a bypass strategy. R_buffer_x has a depth of 64 and a bit width of 405, which is in consideration of the largest number of non-zero elements in the H matrix being 88. In order to save storage space, only the check node update information of the non-zero elements in the H matrix is stored. Since the quantization bit width of the check node is 5, the bit width is (81*6 bits).

[0101] When a complete codeword is stored in Q_buffer_wrap, the iterative decoding process is started. The first stage is to calculate the variable node update information. According to the layered decoding NMS algorithm, the LLR information stored in Q_buffer_wrap (i.e. the soft information to be decoded after shifting) is taken out and subtracted by the check node update message value (also known as check node update information) stored in R_buffer_wrap in the last iteration, which is completed by the T_calculator_wrap module, to obtain the corresponding variable node update information t. The obtained t value is sent to the T_buffer_wrap and PU_wrap modules for processing in the second stage. The depth and bit width of T_buffer_x are consistent with Q_buffer_x. It is worth noting that the LLR in Q_buffer_x needs to be right-circularly shifted to restore the connection relationship between the real variable nodes and check nodes in the check matrix H. The parameter value of the right-circular shift (i.e. the specific shift value, such as right-circularly shifting c bits, where c is obtained by looking up the table) is stored in the H-LUT module, and the right-circular shift is completed by the Cyclic_shifter_wrap1 module.

[0102] The second stage is to calculate the check node update information and the LLR update information, which is mainly processed by the PU_wrap module. The Writing Phase works at layer k, and the Reading Phase works at layer k+1. The Reading Phase obtains the minimum value, minimum value index, and second minimum value of the variable nodes connected to each check node in the layer through the feedforward structure and passes them to the Writing Phase. The Writing Phase completes the corresponding check node information update and LLR information update according to the order of write_seq. In order to be consistent with the order stored in Q_buffer_x, the updated LLR information needs to be left-circularly shifted (specifically, it can be shifted by Z-c bits, where Z is a pre-defined configuration), which is completed by the Cyclic_shifter_wrap2 module.

[0103] The third stage is to output the LLR hard decision result and initialize the value of R_buffer_x (the processed buffer in Q_buffer_x will be overwritten by a new codeword). When the number of iterations reaches the preset number, the Hard_decision module completes the hard decision of the LLR information in Q_buffer_x (specifically, when the LLR information is between -128 and 0, the hard decision output is 1; otherwise, the hard decision output is 0), and the current group in R_buffer_x is cleared. At this time, if the current frame has not ended, another buffer in Q_buffer_x and R_buffer_x can continue the decoding of the new codeword, and the two buffers form a ping-pong operation.

[0104] Experiments show that the application can reduce the delay of a single iteration by 1 / 3 to 1 / 2 and increase the throughput by 0.3 times to 1 times without increasing the storage resource overhead. A lower processing delay is achieved under a relatively small resource area, and the number of clock cycles for a single iteration is 45-63. A larger throughput is achieved under a relatively small resource area. Under the SIMC55 process, the number of logic gates is 400K, and the maximum throughput of 1.36Gbps can be achieved at a clock of 320MHz.

[0105] By implementing the application, the application obtains an ordered check base matrix by column reordering a low-density parity-check code (LDPC) check base matrix; obtains an optimal check base matrix by layer reordering the ordered check base matrix; and finally decodes soft information to be decoded based on the optimal check base matrix to obtain corresponding decoding information. In the above scheme, the application obtains an optimal check base matrix supported by a communication protocol by column and layer reordering the LDPC check base matrix, and then performs information decoding based on the optimal check base matrix, which can reduce decoding complexity and improve decoding efficiency, and also solves the technical problems in the prior art, such as high QC-DPLC decoding implementation complexity and difficulty in meeting link transmission delay and throughput requirements.

[0106] Based on the same inventive concept, another embodiment of the application provides a device and a terminal equipment corresponding to the layer decoding method described in the embodiments of the application.

[0107] Please refer to Figure 4 , which is a structural schematic diagram of a layer decoding device provided by the embodiments of the application. As shown in the device includes a column ordering module 401, a layer ordering module 402, and a decoding module 403, wherein: Figure 4

[0108] The column ordering module 401 is configured to reorder columns of an LDPC check base matrix to obtain an ordered check base matrix.

[0109] The layer ordering module 402 is configured to reorder layers of the ordered check base matrix to obtain an optimal check base matrix.

[0110] The decoding module 403 is configured to decode soft information to be decoded based on the optimal check base matrix to obtain corresponding decoding information.

[0111] Optionally, the column ordering module 401 is specifically configured to:

[0112] reorder column orders of the LDPC check base matrix to obtain the ordered check base matrix. ​

[0113] wherein a difference between the number of non-zero elements in the first i columns and the last j columns of the reordered parity check matrix does not exceed a first threshold, i and j are both positive integers, and a sum of i and j is equal to a total number of columns of all columns in the LDPC parity check matrix.

[0114] Optionally, i and j are equal.

[0115] Optionally, the column reordering module 401 is specifically configured to perform the following steps:

[0116] S41: Reordering each column with non-zero elements exceeding a second threshold and being lower than a third threshold in the LDPC parity check matrix according to an element distribution of each column in the LDPC parity check matrix, to obtain a reordered parity check matrix;

[0117] S42: Calculating a difference between the number of non-zero elements in the first i columns and the last j columns of the reordered parity check matrix;

[0118] S43: Re-adjusting a column order of each column in the reordered parity check matrix, and repeatedly performing step S42 until a preset number of repetitions is reached;

[0119] S44: Determining the reordered parity check matrix with the smallest difference as the reordered parity check matrix.

[0120] Optionally, the layer reordering module 402 is specifically configured to perform the following steps:

[0121] S51: Performing a hierarchical rearrangement on the reordered parity check matrix to obtain a hierarchical parity check matrix;

[0122] S52: Determining a first base matrix and a second base matrix from the respective matrices of the first i columns and the last j columns in the hierarchical parity check matrix;

[0123] S53: Performing hierarchical iterative calculation on the first base matrix and the second base matrix by using a preset read-write hierarchical algorithm to obtain calculation information of the hierarchical parity check matrix, the calculation information including a clock period required for a single iteration, a number of clock periods, a read data order, and a write data order, the read data order being used to indicate a read order of reading each element data in the hierarchical parity check matrix, and the write data order being used to indicate a write order of writing each element data in the hierarchical parity check matrix;

[0124] S54: Re-adjusting a layer order of each layer in the hierarchical parity check matrix, and repeatedly performing steps S52-S53 until a preset number of repetitions is reached;

[0125] S55, determining the layered check matrix with the least number of clock cycles required for a single iteration as the optimal check matrix.

[0126] Optionally, the decoding module 403 is specifically configured to perform the following steps:

[0127] S61, reordering the soft information to be decoded according to the column numbers of the columns in the optimal check matrix to obtain ordered soft information;

[0128] S62, performing double-sided low-delay layered iterative decoding on the ordered soft information according to the read data order and the write data order to obtain corresponding decoded codewords;

[0129] S63, outputting the decoded codewords according to the column order of the columns in the ordered check matrix to obtain the decoded information.

[0130] Optionally, the apparatus is applied to a layered decoder, and the LDPC decoder comprises a first buffer Q_buffer_wrap, a first shifter, a calculator, an updater PU_wrap, a second buffer R_buffer_wrap, a third buffer T_buffer_wrap, a second shifter, and a hard decision decoder. The decoding module 403 is further specifically configured to perform the following steps:

[0131] S71, writing the soft information to be decoded into the first buffer according to the column numbers of the columns in the optimal check matrix;

[0132] S72, shifting the soft information to be decoded in the first buffer by a preset first direction through the first shifter;

[0133] S73, calculating the soft information to be decoded after shifting and the check node update information stored in the second buffer in the previous iteration decoding through the calculator to obtain variable node update information, and storing the variable node update information into the updater and the third buffer;

[0134] S73, calculating the check node update information corresponding to the variable node and the update information of the soft information to be decoded by the updater according to the read data order, the write data order, and the variable node update information through a layered iterative decoding algorithm;

[0135] S74, shifting the update information of the soft information to be decoded by a preset second direction through the second shifter, the preset first direction being opposite to the preset second direction;

[0136] S75, hard-decode the updated information of the soft information to be decoded by the hard-decoder to obtain a corresponding decoding code word.

[0137] Please see Figure 5, which is a structural schematic diagram of a terminal device provided by an embodiment of the present application. As shown in Figure 5, the terminal device 50 comprises at least one processor 501, a communication interface 502, a user interface 503 and a memory 504, which are connected through a bus or other means. In the embodiment of the present application, the connection through the bus 505 is taken as an example. Among them, Figure 5

[0138] The processor 501 can be a general-purpose processor, such as a central processing unit (CPU).

[0139] The communication interface 502 can be a wired interface (such as an Ethernet interface) or a wireless interface (such as a cellular network interface or a wireless local area network interface), which is used for communication with other terminals or websites. In the embodiment of the present application, the communication interface 502 is specifically used for obtaining a check matrix.

[0140] The user interface 503 can be a touch panel, including a touch screen and a touch screen, which is used for detecting operation instructions on the touch panel. The user interface 503 can also be a physical key or a mouse. The user interface 503 can also be a display screen, which is used for outputting and displaying images or data.

[0141] The memory 504 can include a volatile memory (Volatile Memory), such as a random access memory (Random Access Memory, RAM); the memory can also include a non-volatile memory (Non-Volatile Memory), such as a read-only memory (Read-Only Memory, ROM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, HDD) or a solid-state disk (Solid-State Drive, SSD); the memory 504 can also include a combination of the above kinds of memories. The memory 504 is used to store a set of program codes, and the processor 501 is used to call the program codes stored in the memory 504 to perform the following operations:

[0142] The low-density parity-check code (LDPC) check matrix is column-division reordered to obtain a reordered check matrix;

[0143] The reordered check matrix is layer-division reordered to obtain an optimal check matrix;

[0144] ​According to the optimal check matrix, soft information to be decoded is decoded to obtain corresponding decoded information.

[0145] Optionally, the column-wise reordering of the LDPC check matrix to obtain the reordered check matrix comprises:

[0146] The column order of the LDPC check matrix is reordered to obtain the reordered check matrix.

[0147] The difference between the number of non-zero elements in the first i columns and the last j columns in the reordered check matrix does not exceed a first threshold, i and j are positive integers, and the sum of i and j is equal to the total number of columns in the LDPC check matrix.

[0148] Optionally, i and j are equal.

[0149] Optionally, the column order of the LDPC check matrix is reordered to obtain the reordered check matrix, comprising the following steps:

[0150] S41: According to the element distribution of each column in the LDPC check matrix, reorder each column in the LDPC check matrix that has more than a second threshold and less than a third threshold of non-zero elements to obtain a reordered check matrix.

[0151] S42, calculate the difference between the number of non-zero elements in the first i columns and the last j columns in the reordered check matrix.

[0152] S43, adjust the column order of each column in the reordered check matrix, and repeat step S42 until the number of repetitions reaches a preset number of times.

[0153] S44, the reordered check matrix with the smallest difference is determined as the reordered check matrix.

[0154] Optionally, the hierarchical reordering of the reordered check matrix to obtain the optimal check matrix comprises the following steps:

[0155] S51, the reordered check matrix is hierarchically rearranged to obtain a hierarchical check matrix.

[0156] S52, the first base matrix and the second base matrix are determined as the respective matrices corresponding to the first i columns and the last j columns in the hierarchical check matrix.

[0157] S53, performing layered iteration calculation on the first base matrix and the second base matrix by using a preset read-write layered algorithm to obtain calculation information of the layered check base matrix, the calculation information including a clock cycle required for single iteration, a number of clock cycles, a read data order, and a write data order, the read data order being used to indicate a read order of element data in the layered check base matrix, and the write data order being used to indicate a write order of the element data in the layered check base matrix;

[0158] S54, re-adjusting a layer order of each layer in the layered check base matrix, and repeatedly performing steps S52-S53 until a preset number of repetitions is reached;

[0159] S55, determining the layered check base matrix with the smallest number of clock cycles required for single iteration as the optimal check base matrix.

[0160] Optionally, the decoding of the soft information to be decoded according to the optimal check base matrix to obtain corresponding decoding information includes the following steps:

[0161] S61, reordering the soft information to be decoded according to a column number of each column in the optimal check base matrix to obtain ordered soft information;

[0162] S62, performing double-sided low-delay layered iteration decoding on the ordered soft information according to the read data order and the write data order by using a layered iteration decoding algorithm to obtain corresponding decoding code words;

[0163] S63, outputting the decoding code words according to a column order of each column in the ordered check base matrix to obtain the decoding information.

[0164] Optionally, the application is applied to a layered decoder, and the LDPC decoder includes a first buffer Q_buffer_wrap, a first shifter, a calculator, an updater PU_wrap, a second buffer R_buffer_wrap, a third buffer T_buffer_wrap, a second shifter, and a hard decision decoder, and the processor 501 is further configured to perform the following implementation steps:

[0165] S71, writing the soft information to be decoded into the first buffer according to a column number of each column in the optimal check base matrix;

[0166] S72, shifting the soft information to be decoded in the first buffer by a preset first direction through the first shifter;

[0167] S73, calculating, by the calculator, the shifted soft information to be decoded and the check node update information stored in the second buffer in the previous iteration decoding, to obtain variable node update information, and storing to the updater and the third buffer;

[0168] S73, calculating, by the updater, the check node update information corresponding to the variable node and the update information of the soft information to be decoded according to the read data order, the write data order and the variable node update information by using the layered iterative decoding algorithm;

[0169] S74, shifting, by the second shifter, the change information of the soft information to be decoded in a preset second direction, the preset first direction being opposite to the preset second direction;

[0170] S75, performing hard decision decoding on the update information of the soft information to be decoded by a hard decision decoder, to obtain the corresponding decoding codeword.

[0171] Since the terminal device introduced in the embodiment is the terminal device used to implement the layered decoding method in the embodiment, the specific implementation of the terminal device and its various changes can be understood by those skilled in the art based on the layered decoding method introduced in the embodiment, so the implementation of the method in the embodiment by the terminal device will not be described in detail. As long as the terminal device used to implement the layered decoding method in the embodiment is implemented by those skilled in the art, it belongs to the scope of the application.

[0172] The technical solution in the embodiment has at least the following technical effects or advantages: The LDPC check matrix is reordered by column and layer, to obtain a reordered check matrix; the reordered check matrix is reordered by layer, to obtain an optimal check matrix; and finally, the soft information to be decoded is decoded based on the optimal check matrix, to obtain corresponding decoding information. In the above solution, the optimal check matrix supported by the communication protocol is obtained by reordering the LDPC check matrix by column and layer, and then the information is decoded based on the optimal check matrix, which can reduce the decoding complexity, improve the decoding efficiency, and solve the technical problems such as high QC-DPLC decoding implementation complexity, difficulty in meeting the requirements of link transmission delay and throughput, etc.

[0173] Those skilled in the art will appreciate that embodiments of the present application can be devised for a variety of applications. It is therefore intended that the present application cover all such modifications and variations of the application disclosed herein provided they come within the scope of the appended claims and their equivalents. It is intended to

[0174] The present application is described in reference to the drawings using a flowchart and / or a block diagram of the method, apparatus (system) and computer program product according to embodiments of the application. It will be understood that each block of the flowchart and / or block diagram, and combinations of blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processing device or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified by one or more blocks Figure 1 one or more functions specified by one or more blocks

[0175] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified by one or more blocks Figure 1 one or more functions specified by one or more blocks

[0176] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified by one or more blocks Figure 1 one or more functions specified by one or more blocks

[0177] While the preferred embodiments of the application have been described, additional variations and modifications can be employed by those skilled in the art. Therefore, the claimed application is intended to cover all such modifications and variations as fall within the scope of the appended claims and their equivalents.

[0178] Obviously, many modifications and variations of the present application are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A layered decoding method, characterized by, The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: S51, the sorting check matrix is rearranged in layers to obtain a layered check matrix; S52, the first base matrix and the second base matrix are determined by the corresponding matrices of the first i columns and the last j columns in the layered check matrix; S53, the first base matrix and the second base matrix are calculated by using a preset read-write layered algorithm, and calculation information of the layered check matrix is obtained, wherein the calculation information comprises a clock period required for single iteration, a number of clock periods, a read data order and a write data order, the read data order is used to indicate a read order of element data in the layered check matrix, and the write data order is used to indicate a write order of the element data in the layered check matrix; S54, the layer order of each layer in the layered check matrix is adjusted, and steps S52-S53 are repeatedly executed until the number of repetitions reaches a preset number of times; S55, the layered check matrix with the minimum number of clock periods required for single iteration is determined as the optimal check matrix; The method comprises: S61, the soft information to be decoded is reordered according to the column number of each column in the optimal check matrix to obtain sorted soft information; S62, the sorted soft information is double-sided low-delay layered iterative decoded according to the read data order and the write data order by using a layered iterative decoding algorithm to obtain a corresponding decoding code word; S63, the decoding code word is output according to the column order of each column in the sorting check matrix to obtain the decoding information; The method is applied to an LDPC decoder, and the LDPC decoder comprises a first buffer Q_buffer_wrap, a first shifter, a calculator, an updater PU_wrap, a second buffer R_buffer_wrap, a third buffer T_buffer_wrap, a second shifter and a hard decision decoder, and the method further comprises the following implementation steps: S71, the soft information to be decoded is written into the first buffer according to the column number of each column in the optimal check matrix; S72, the soft information to be decoded in the first buffer is shifted in a preset first direction by the first shifter; S73, the variable node update information is obtained by calculating the soft information to be decoded after shifting and the check node update information stored in the second buffer in the last iteration decoding by the calculator, and the variable node update information is stored in the updater and the third buffer; S73, calculating, by the updater, check node update information corresponding to the variable node and update information of the soft information to be decoded according to the read data order, the write data order and the variable node update information by using a layered iterative decoding algorithm; S74, performing, by the second shifter, a preset second direction shift on the change information of the soft information to be decoded, the preset first direction being opposite to the preset second direction; S75, performing, by the hard decision decoder, hard decision decoding on the update information of the soft information to be decoded to obtain a corresponding decoding code word.

2. The method of claim 1, wherein, The column reordering of the low-density parity-check code (LDPC) check matrix to obtain the reordered check matrix comprises: reordering the column order of the LDPC check matrix to obtain the reordered check matrix; wherein the difference between the number of non-zero elements in the first i columns and the last j columns in the reordered check matrix does not exceed a first threshold, i and j are positive integers, and the sum of i and j is equal to the total number of columns in the LDPC check matrix.

3. The method of claim 2, wherein, i and j are equal.

4. The method of claim 2, wherein, The column reordering of the LDPC check matrix to obtain the reordered check matrix comprises the following steps: S41: reordering, according to the element distribution of each column in the LDPC check matrix, each column in the LDPC check matrix having more than a second threshold and less than a third threshold of non-zero elements to obtain a rearranged check matrix; S42, calculating the difference between the number of non-zero elements in the first i columns and the last j columns in the rearranged check matrix; S43, reordering the column order of each column in the rearranged check matrix, and repeatedly performing step S42 until the number of repetitions reaches a preset number of times; S44, determining the rearranged check matrix with the smallest difference as the reordered check matrix.

5. A layered decoding apparatus, characterized by, The device comprises a column reordering module, a layer reordering module and a decoding module, wherein: the column reordering module is configured to reorder columns of a low-density parity-check code (LDPC) check matrix to obtain a reordered check matrix; the layer reordering module is configured to reorder layers of the reordered check matrix to obtain an optimal check matrix; the decoding module is configured to decode soft information to be decoded according to the optimal check matrix to obtain corresponding decoding information.

6. A terminal device, characterized by comprising: The terminal device comprises a processor, a memory, a communication interface and a bus; the processor, the memory and the communication interface are connected through the bus and complete communication with each other; the memory stores executable program codes; the processor runs programs corresponding to the executable program codes by reading the executable program codes stored in the memory, to execute the layered decoding method according to any one of claims 1-4.

7. A computer readable storage medium characterized by, The computer readable storage medium stores a program, which, when running on a terminal device, executes the layered decoding method according to any one of claims 1-4.

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