Concurrent hash map updates

Abstract

Methods according to various embodiments can perform spatial hash map updates while ensuring atomicity of updates for arbitrary data structures. A hash map can be generated for a dataset, where entries in the hash map can correspond to a plurality of independent values, such as pixels of an image to be rendered. Update requests to the independent values can be received on a plurality of concurrent threads, but change requests to the independent values corresponding to a hash map entry can be aggregated from the buffers and iteratively processed in a single thread for a given hash map entry. In a multi-resolution spatial hash algorithm, data can be stored in various discrete levels, which can be repeatedly executed to propagate changes from one level to another.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. non-provisional patent application No. 16930633, filed July 16, 2020, entitled “Concurrent Hash Map Updates,” the entire contents of which are incorporated herein by reference and for all purposes. Background Technology

[0003] Computational tasks are becoming increasingly complex, presenting new challenges in determining how best to perform those tasks. For example, for tasks related to graphics and animation, there may be many different light sources (including reflections) that could affect the performance of all pixels in an image or video frame. Performing a task on all these pixels (such as ray tracing on all these sources), especially in parallel, could require a certain amount of resource capacity, which is impractical for many different applications at best. Simply reducing the number of rays or pixels processed may result in performance that is less accurate or realistic than desired. Attached Figure Description

[0004] Various embodiments according to this disclosure will be described with reference to the accompanying drawings, in which:

[0005] Figure 1A and Figure 1B The use of shadows to generate an image is illustrated according to at least one embodiment.

[0006] Figure 2 A system for generating and presenting content according to at least one embodiment is shown;

[0007] Figure 3 Components of an image processing pipeline according to at least one embodiment are shown;

[0008] Figure 4 An algorithm for concurrent hash map updates according to at least one embodiment is shown;

[0009] Figure 5 The process for updating a hash map according to at least one embodiment is illustrated;

[0010] Figure 6 A process for performing concurrent updates according to at least one embodiment is illustrated;

[0011] Figure 7 An example data center system according to at least one embodiment is shown;

[0012] Figure 8 A computer system according to at least one embodiment is shown;

[0013] Figure 9 A computer system according to at least one embodiment is shown;

[0014] Figure 10 At least a portion of a graphics processor according to one or more embodiments is shown; and

[0015] Figure 11 At least a portion of a graphics processor according to one or more embodiments is shown. Specific Implementation

[0016] Methods according to various embodiments can efficiently store and retrieve sparse spatial data in large-scale parallel environments. Examples of sparse spatial data are shown in... Figure 1A The diagram illustrates the generation of a 2D image 100 from the perspective of a 3D world. In such an environment, the 3D world can be modeled using points representing the surfaces of various objects visible in that world. These points can represent a sparse dataset because many voxels (or volumetric pixels) in the 3D world will not correspond to the surface of at least one object and therefore may not contain data representing the object. When the 2D image is generated, these voxels are analyzed to determine which voxels are visible from the perspective of the virtual camera that generated the image, and the data from these voxels can be used to determine the pixel values ​​of the 2D image.

[0017] To enhance the realism of the generated images, shading can be used to calculate the light reflected from these various objects toward the camera. In many cases, there may be multiple light sources, such as the sun 102 or the moon, streetlights 104, vehicle headlights and turn signals 106, and other such light sources. Each object in the environment may potentially reflect light from these light sources toward the virtual camera and toward each other, and then reflect it back toward the virtual camera. Figure 1B Figure 150 illustrates a method for shading these objects using ray tracing. Ray tracing typically involves a set of rays 170 from one or more light sources 160, 162, 164, reflected by one or more objects 156, 158 (e.g., game objects in a video game) towards a virtual camera 152 corresponding to the viewpoint of the image 154 to be generated or a video frame (e.g., a frame of video game content to be rendered). To determine the pixel value of each pixel in the image 154, the pixel positions through which the rays will pass for the virtual position of that frame relative to the 3D world are determined.

[0018] Figure 2Components of an example system 200 are shown, which can be used to generate and render such content. In this example, a client device 202 receives content via at least one network 240; however, it should be understood that in some embodiments, all content generation can be performed on the client device 202 or another such source. In this example, the client device 202 can receive images, videos, or other media data across at least one network 240 for rendering using at least one display 206 and an audio component 208. For game content, a game application 204 or other media application can be used to receive and process the content, which may include a content manager for managing the content and a rendering engine 210 for rendering at least a portion of the content to a degree that the content may not yet have been rendered for display. In this example arrangement, the client device 202 can include any suitable computing device, such as, but not limited to, a desktop computer, laptop computer, set-top box, streaming device, game console, smartphone, tablet computer, virtual reality (VR) headset, augmented reality (AR) goggles, wearable computer, or smart TV. The client device 202 can submit requests for content across at least one wired or wireless network 240, which may include the Internet, Ethernet, a local area network (LAN) or a cellular network, and other such options.

[0019] In at least one embodiment, the content may be provided by a content server 220. The content server 220 may execute a game application 224, which may include components such as a session manager 226, a rendering engine 228, a content manager 230, and a game generator 232 to generate or provide content for games or other media applications. This application may utilize game content from a content repository 234 and may generate content suitable for the user of the client device 202 based at least in part on user data stored in a user data repository 236, which may relate to the player's current state data in the current game session. In at least one embodiment, the transmission manager 222 may then transmit the content to the client device via at least one network 240, for example, by streaming the content or providing the content for download. In at least one embodiment, the content may originate from a third-party content source 250, which may also include one or more game content generation modules 252, and the content may also be sent to one or more other client devices 260, for example, for online multiplayer games. Although game content is used as the primary example, it should be understood that many other types of content or information may exist within the scope of various embodiments, which can be updated and can benefit from the methods presented herein.

[0020] Performing tasks such as updating image or video data can involve processing large amounts of data. The amount of data can increase based on many different factors, such as the number of light sources or objects, the number of pixels in the image to be generated, and the resolution or reflectivity of objects in the environment. Furthermore, these light sources are often not point sources reflecting off objects, but rather have shapes and potential differences in shape and potential variation depending on location within the illumination, which may differ depending on the location of reflections from different parts of each object. Thus, for each image or video frame, there may be a large amount of data to process, and in at least some implementations, for applications such as video games, this content must be generated or refreshed at a rate of approximately 60Hz or 90Hz. Processing such large amounts of data in such a short time can require significant resources, which may be impractically expensive for various applications.

[0021] To reduce the resource requirements of such applications, spatial hashing can be used to efficiently store and retrieve sparse spatial data in a massively parallel environment. As used herein, a massively parallel environment can include any environment where a large number of processors or computing devices can concurrently execute one or more sets of coordinated computations. A hash map, including the value of each relevant location or coordinate, can be generated, which can include a direct representation of the environment's world spatial data. Entries in the hash map correspond to pixels, and in embodiments where world spatial data points are visible through pixels, multiple inputs can influence the value of that pixel, where each input can be provided by a separate execution thread. When multiple threads need to update the contents of a given hash map entry, each update is performed automatically to ensure correct results. For example, when simulating the behavior of light in a 3D environment, a large number of simulations are required to provide accurate or realistic results. For applications such as video games, there may not be sufficient resources in various implementations to perform these simulations, especially at the required frame rate and without dropped frames. Therefore, it may be desirable to reduce the amount of computation required while keeping the simulation as close to reality as possible. One approach is to reduce the number of rays to be simulated, but this negatively impacts the accuracy of the simulation. Another approach is to try intelligent sampling of light from the world or environment, but in many cases, a large number of samples are still needed to provide the required accuracy.

[0022] Methods such as spatial hashing can be used to distribute computations performed on one pixel across another, so that subsequent computations do not have to start from scratch. There is often a significant correlation between one pixel and another; for example, two pixels representing the surface of a table in an environment typically receive similar amounts and types of lighting. Sampling subsets of these rays and sharing them among related pixels can help provide the required accuracy while reducing computational requirements. In at least some embodiments, spatial hashing can involve generating hashes to represent a set of data, such as hashing the locations of points in a scene. This hashing can involve using any suitable hashing algorithm, such as any number of secure hashing algorithms (e.g., MD5, SHA-2, or SHA-3). Each hash can provide an index in a hash map, where data such as that possibly relates to lighting information can be stored. The same hash value can then be assigned to points in the same neighborhood or nearby to reduce computational requirements. For example, the surface of an object can be divided into cells, each containing a set of pixel locations, and the same hash value can be assigned to each pixel location to apply the same lighting information. Spatial hashing allows objects in an n-dimensional domain space to be projected onto a one-dimensional (1D) hash table, enabling fast lookups of those objects in the domain space. Such a method can be advantageous, at least when the data structure is relatively simple. Furthermore, even if the corresponding data may be highly discrete, the hash map can fill this one-dimensional array very evenly. In various embodiments, the hash function used can be customized to improve performance. For example, the level of detail can be customized, allowing the relevant hash function to be modulated so that the surface is relatively small for objects close to the virtual camera, but relatively large for objects further away.

[0023] When the hash map content is simple, such as an integer per entry, this approach may be relatively straightforward. However, as the entries become more complex, this update becomes less straightforward. In one case, each component of an entry can be updated independently, in which case an atomic function can be called for each component. In this case, larger entries may experience strong atomic pressure, potentially leading to performance degradation. In another instance, components may be interdependent, and updating the entire entry may require explicit locking of that entry. For this case, using locks in a massively parallel environment can result in significant performance penalties. Another possibility involves logging all necessary changes in a buffer, sorting the buffer to group modifications for a given entry together, logging the start position of each segment, and finally running a thread to update each list. While effective, this sorting can be very expensive, especially when there are millions of updates per frame.

[0024] Methods according to various embodiments can perform updates to spatial hash maps or other such constructs in a way that avoids sorting and at least most of this atomic pressure while ensuring atomic updates to arbitrary data structures. In at least one embodiment, the hash map can be divided into two parts: a set of keys and hash map entries. Each key can contain at least two fields: an unsigned integer checksum value C and an unsigned integer L representing the last attempt to modify the associated entry. The hash map can also contain a Boolean value (e.g., "was Touched") indicating whether the cell has been targeted by a change request, which can be initially set to "false" by default. In at least one embodiment, all L values ​​can be initially set to any known value, such as the largest 32-bit unsigned integer value. During information generation, each thread can generate change requests for the hash map. These requests can be stored in a buffer B upon generation. Each time a request is generated, this request automatically stores the value L of the target entry and updates L in buffer B with the index of the request. In this approach, each change request can be aware of previously generated change requests, and thus can determine all changes related to a given cell.

[0025] Once B is complete, a list T of change requests can be created, for which L is equal to the index of the change request, thus identifying the last change request for each considered hash map entry. This can be done in parallel on all entries in B. In some embodiments, the value of wasTouched can be atomically flipped, and T can be generated simultaneously with B, adding a cell identifier to T if wasTouched is false. In at least one embodiment, the list T will contain the index of the corresponding element in B. Using the contents of T, each element of T can be processed in parallel. For each entry in T, the corresponding change request in B can be retrieved. Using the index L of other change requests, all changes related to the corresponding hash entry in the same thread can be processed iteratively according to the method of at least one embodiment.

[0026] In the case of multi-resolution spatial hashing, where data can be stored at various levels of discretization, the operation can be repeated to propagate changes from one level to one or more coarser levels. For example, ambient occlusion values ​​can be computed at a fine discretization level, and these values ​​can be used to improve the ambient occlusion values ​​at a coarser level of detail.

[0027] As mentioned above, this approach neither uses atoms on simple data types to update the spatial hash map as traditional systems do, nor does it require any form of sorting. The methods presented in the various embodiments herein are inherently general, thus attaching to a specific type or data structure, and atomicity can be guaranteed because all changes to a given hash entry are processed in a single thread. In particular, this allows for more complex data structures, as well as types that might not be available due to atomic operations, as they could relate to a single 16-bit floating-point value in some implementations. Hash map updates typically involve many hash entries, thus guaranteeing high processor (e.g., GPU) utilization even if only one thread is used per hash entry during the update. This approach can be used in conjunction with spatial hashing to efficiently store data in world space, which can be beneficial for products such as RTXGI and Omniverse to improve the fidelity of global illumination computations.

[0028] In at least one embodiment, it can be such as regarding Figure 1B This approach is used within the context of the massively parallel optical transport simulation discussed, and applied to the real-time computation of ambient occlusion and ambient lighting on one or more graphics processing units (GPUs). For each pixel of an image, information can be generated for points visible through that pixel. The generated information can include at least the world spatial location or coordinates and the normals of the visible points. This information can be used as input to compute hash entries corresponding to each visible point at several levels of detail (LoD). In at least one embodiment, an incident radiance value can be generated for each pixel. In some implementations, this value can be restricted to an ambient occlusion value and can be directly added to the hash map via atomic addition. The process of performing ambient occlusion estimation obtains ambient occlusion data from the hash map, and a filtering step can eliminate unwanted blocky artifacts due to spatial discretization.

[0029] In at least one embodiment, the method can be extended to store more complex data in the hash map. This can lead to higher atomicity pressure and may involve limitations regarding data type (e.g., 32-bit values ​​only) and structure, such as the requirement that all members of the hash map must be able to be updated individually. In some implementations, it is not possible or permissible to atomically store and update 16-bit floating-point RGB values ​​on certain processors.

[0030] In at least one embodiment, all change requests related to a given hash map entry can be aggregated, and each change entry is processed sequentially to avoid concurrent access. Such a hash map update scheme can be divided into at least two parts, and an optional part that can be used for level-of-detail (LoD) propagation. One part may involve calculating lighting information and generating a list of linked change requests, one request for each modified hash map entry. Another step may involve processing the list of links and committing the changes to the hash map. This optional step may involve potentially propagating changes to a coarser level of detail (LOD) within the hash map. In at least one spatial hashing mechanism, each entry stores a checksum value to identify conflicting, unrelated points to be mapped to the same entry. Generating the list of links may require additional data to generate the links.

[0031] In at least one embodiment, a hash map can be used as a mechanism for linking each change request to other previously published change requests. This may involve considering all change requests stored in a buffer, for example, in an unspecified order. In addition to the checksum, an additional value, lastChange, can be stored for each entry. For example, this value could be a 32-bit unsigned integer representing the index of the last change request issued for that entry. A boolean value, wasTouched, can also be stored, indicating whether the entry is currently referenced in the change list. In at least one embodiment, these values ​​can be bundled together into a single value, such as a 32-bit unsigned integer, where multiple bits (e.g., 31 bits) are used to represent lastChange, and at least one bit is used for wasTouched.

[0032] In at least one embodiment, the hash map can be divided into at least two parts. The first part can be a hash key buffer containing checksums and the index of the last change. A hash data buffer can be used to store the actual lighting information. Modifications in the hash map can be performed through a buffer containing change requests (called a change list). Each entry in this change list buffer can contain the index of a previously issued change request and the requested lighting information change. The index of the unique hash entry referenced in the change list can be stored in a buffer called TouchedList.

[0033] When a hash entry is first assigned, its value `lastChange` can be set to any reserved value. In at least one embodiment, this reserved value `NO_PRECEDENT` can be, for example, the 32-bit hexadecimal value 0xFFFFFFFF. The entry's `wasTouched` value can be set to `false`.

[0034] In at least one embodiment, each pixel of the image can be processed in a separate thread. For each pixel, a self-organizing algorithm can be used to estimate lighting information, such as by using Monte Carlo integration, to estimate lighting information, such as incoming radiance values. Slots, such as change slots, can be maintained in a ChangeList, and change requests containing this information can be generated. In at least one embodiment, the value lastChange of the hash map entry corresponding to the tinted pixel can be atomically retrieved and swapped. The previous value of lastChange can be stored in the change request, and the index of changeSlot can be written to lastChange. When multiple threads issue change requests for a given hash map entry, each request can include the index of previously issued changes in changeList. This approach helps ensure the link between all changes given to a given hash map entry. When generating a change request, the wasTouched value of the corresponding hash entry can also be atomically set to true. If its previous value was false, the index of the hash entry can be added to the TouchedList.

[0035] In at least one embodiment, all entries of the TouchedList can be processed in parallel. In each thread, the lastChange index of an entry can be used to retrieve the last change request for that hashmap entry. Since each change request contains the index of its predecessor, the previous changed list item for that entry can be accessed. Those changes can then be combined according to a light-transmission algorithm, which may include algorithms such as simple addition or weighted averaging. This process can be repeated until the list is complete. In at least one embodiment, a termination condition can be reached when the lastChange value of a change request equals NO_PRECEDENT, meaning that the first change request for that hashmap entry has been reached.

[0036] In an example spatial hashing technique, the contribution gained at LoD n is propagated to three coarser LoDs by performing atomic operations at each level. However, if the entry at LoD n receives N change requests, the hash entry at the same position at LoD n+1 will receive up to 8N change requests, up to 64N changes at LoD n+2, and so on. This creates high atomic pressure, potentially leading to poor performance. Instead, methods according to various embodiments can be used to reduce the number of updates in the coarser LoDs. After the change list is committed to the hash unit, a new change request can be created for that unit at LoD n+1, in a second change list called ChangeListPropagate. The same process described above can then be reapplied by finding the tail of the linked lists in ChangeListPropagate, committing those lists, and repeating this process for each coarser level. In this way, many change requests at each level can remain largely unchanged. For efficiency, each repetition can alternate between ChangeList and ChangeListPropagate to reuse memory.

[0037] In at least one embodiment, this functionality can be implemented using graphics hardware, such as GPU-based hardware using GLSL shaders and the Vulkan API. Such applications demonstrate the use of update schemes for ambient occlusion and ambient lighting. In the case of ambient occlusion, the hash map data can consist of two 16-bit counters: one for the total number of rays tracked, and the other for the number of unoccluded rays. In the case of ambient lighting, the hash map can contain an RGB value (where each component is stored as a 16-bit floating-point value) and a 16-bit integer counter representing the total number of rays tracked. Such use cases demonstrate important aspects of various approaches because the GLSL language does not allow 16-bit floating-point atomic operations; therefore, such implementations would be impossible, for example, without implementing expensive methods based on mutexes.

[0038] Figure 3An example processing pipeline 300 that can be utilized according to various embodiments is shown. This pipeline can be used with ambient occlusion after hashing of ray-traced data; for example, the ray-tracing module 310 can directly update the data 322 in the spatial hash map via atomic operations. In this example, the hash value includes a checksum 320 and the corresponding data 322. Data received for a single request can be stored in one or more buffers, as discussed herein, which may include a position buffer 302 and a general buffer 304. This can be used with shaders where points in the 3D environment visible from a viewpoint are determined, and their positions, along with normal and surface data, are stored as input to this algorithm. Such an algorithm may not care how the data was generated (e.g., via ray tracing or sampling), but may want to obtain information about the position and normals of that data.

[0039] In at least one embodiment, the unit allocation module 306 can assign groups of pixels to individual units, where the size of those units can vary as discussed herein, for example, having a smaller unit size for objects closer to a virtual camera. As shown, there can be different unit sizes 308, which include different groups of image pixels, for example, to generate images of different resolutions. Several pixels can then provide updates for a given unit for any frame to be rendered. However, such updates are not necessarily direct, as processors such as GPUs can handle everything in parallel threads, while conventional methods might attempt to generate parallel threads for each individual pixel to be processed in parallel, making it difficult to aggregate or combine pixel values ​​during processing. To write the change data for these pixels, methods according to various embodiments can block a portion of memory. In this example, once units are allocated and pixels are assigned to specific units, the ray tracing module 310 can perform ray tracing, for example, by performing ray sampling on the individual units, which can then be applied to the pixels contained within those units. After ray tracing, the estimation module 312 can estimate the ambient occlusion 314 of the ray tracing. Ambient occlusion is a shading technique used to calculate the exposure of each point in a scene to illumination from one or more light sources. In at least one embodiment, ambient occlusion can be calculated for each surface point, but it can also be calculated for a given cell and then applied to the points or pixels of that cell. The filtering module 316 can then filter the ambient occlusion to produce the final output 318. As described above, the filtering step can remove unwanted blocky artifacts caused by factors such as spatial discretization. Even if multiple threads of multiple pixels could update a given cell, this approach can use a single thread to update a single hash cell. Instead of having multiple pixels communicate for a single cell, the computation can be performed for a single cell involving the analysis of contributions from all its related pixels.

[0040] In at least one embodiment, this can involve building a list or other grouping of all modifications that have occurred or will be applied to a given unit. This can be done on the fly, without any sorting. Once all changes have been generated for a unit, a pass can be used to traverse all modified units and iteratively access the list of these changes. These changes can be aggregated in a non-parallel manner so that multiple data structures can be supported without breaking those data structures.

[0041] In at least one embodiment, the rendering process may utilize a central hash map accessible to multiple modules or components, which may be modified. As described above, the hash map may include data from many different units, each with an index value stored in the hash map. This index value may represent the index of the last change requested for that unit. During the rendering process, a change request may be generated for any of these pixels, and this change request data may be stored in a local buffer. Previously modified content can be determined, and the index can be replaced with an index from the current change list. The next step may then be to directly browse a list of all modified units, with indices pointing to the last value change made in the hash map. The data of that change can then be aggregated with other related change data. The result of this process is a dynamically generated linked list where only atomic operations reserve space in the change list and appropriately modify the indices. Therefore, regardless of the data structure, the final result is atomic integer mathematics.

[0042] Figure 4 An example algorithm 400 that can be utilized according to at least one embodiment is shown. This example shows pseudocode for multiple steps in the hash map update process. The first step is to perform timed initialization. After initialization, requests are generated for specific changes, which may be related to ray tracing in a graphics application. These changes are then submitted to the hash map in the next step, including propagation to different levels of detail if necessary. In this example, the hash map includes a flag called “wasTouched”, which is set to false by default. When a change request is generated, this flag can be toggled to “true” and the cell is added to the touch list. Entries in this touch list are used to begin aggregating the results. The system can start as many threads as there are items in this touch list and then start from retrieving the last change, as described herein. The hash algorithm function used can be independent of other choices of spatial hashing algorithms.

[0043] As mentioned, such a method can also help manage different levels of detail. Image data can be generated for different levels of detail (LoD) that may be applicable to different displays or devices and at different distances from the viewpoint. When ray tracing is performed on a pixel, the data can be added to the cell corresponding to that pixel. In at least one embodiment, the process can start from a fine level of detail and then propagate that information up the levels of detail. In this approach, there might be an atomic operation to update to the finest level of detail, which could translate into many atomic operations for the higher levels of detail, and then into even more atomic operations for the higher levels of detail, and so on, potentially causing a significant performance impact in many atomic calls. However, the method according to various embodiments can aggregate all changes to the cell at the current level and then propagate these changes as a single change request to the parent to the relevant parent cell. After processing the parent cell, a change request can be created for the cell above it, and so on. Therefore, the result is linear, rather than top-level exponential modification, thus greatly improving performance.

[0044] This functionality can be implemented using any suitable type of processor (e.g., CPU, GPU, or a combination thereof). In a GPU-based implementation, this data can primarily be stored in GPU memory. The processes of allocating cells and updating the hash map can both be performed in GPU memory until the output for display is generated. Therefore, as regarding Figure 2 The discussed functionality can be performed on a client device or a game server, among other options. In at least some embodiments, data input into the hash map can be retained for at least a period of time, so that if the point returns to the view, relevant information about that point can be retrieved from the hash map.

[0045] Figure 5An example process 500 for performing an update hash map according to various embodiments is illustrated. It should be understood that, for this and other processes presented herein, unless otherwise specifically stated, additional, fewer, or alternative steps may exist within the scope of various embodiments, performed in a similar or alternative order or at least partially in parallel. In this example, a hash map comprising a set of keys and hash map entries is generated 502. This may correspond to pixels of an image or video frame to be rendered for display. Hash map entries may include information about the pixel shading of the associated unit, such as position and normal data. The generation process may be initiated, for example, by a game or animation application that needs to generate the next frame of image or video data for rendering for display. This may include updating data for multiple pixels and images of different resolutions. As part of this information generation process, a change request 506 may be received for each of a set of parallel threads, as they may correspond to individual pixels of the image to be generated. This change request information may be stored 508 in a buffer, where the information may include an index of the request and an integer representing the last attempt to modify the associated entry in the hash map. A list of all change requests (510) can be generated for a given hash map entry, containing indices of all corresponding elements in the buffer. This process can iterate over these changes for each hash entry in a single thread (512), and can generate updated values ​​for the current information generation process. In this way, each hash entry is processed using a single thread, where all related changes are atomically aggregated and processed, regardless of how many pixels are contained in the cell associated with that hash entry.

[0046] Figure 6 Another example process 600, according to at least one embodiment, is illustrated for handling multiple concurrent change requests. In this example, multiple change requests 602 are received on a set of parallel threads. These change requests may correspond to pixel positions of an image, for example, where data for these positions may be represented by entries in a hash map. Information about these change requests may be stored 604 in a buffer or other local repository or queue. For a given entry in the hash map to be updated, all relevant change requests currently in the buffer can be identified 606. These change requests can be retrieved from the buffer for a given entry 608, as it may correspond to a unit comprising a set of pixels. This process can then iterate over the changes to that unit in a single execution thread. Once processed, an updated value 610 resulting from this set of change requests can be provided. As mentioned, this may correspond to the next frame of an animation or video, and other such options discussed or suggested herein.

[0047] Data Center

[0048] Figure 7An example data center 700 is shown, in which at least one embodiment can be used. In at least one embodiment, the data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0049] In at least one embodiment, such as Figure 7 As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources (“nodes CRs”) 716(1)-716(N), where “N” represents any complete positive integer. In at least one embodiment, nodes CR 716(1)-716(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), storage devices (e.g., dynamic read-only memory), memory devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 716(1)-716(N) may be servers having one or more of the aforementioned computing resources.

[0050] In at least one embodiment, the grouped computing resources 714 may include individual groups of node CRs housed within one or more racks (not shown), or individual groups of racks (also not shown) housed in data centers in various geographic locations. The individual groups of node CRs within the grouped computing resources 714 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0051] In at least one embodiment, resource coordinator 712 may configure or control one or more nodes CR716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may include a Software Design Infrastructure (“SDI”) management entity for data center 700. In at least one embodiment, resource coordinator may include hardware, software, or some combination thereof.

[0052] In at least one embodiment, such as Figure 7As shown, framework layer 720 includes a job scheduler 722, a configuration manager 724, a resource manager 726, and a distributed file system 728. In at least one embodiment, framework layer 720 may include a framework for software 732 supporting software layer 730, and / or one or more applications 742 of application layer 740. In at least one embodiment, software 732 or application 742 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 720 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 728 for large-scale data processing (e.g., "big data"). TM (Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 722 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of the data center 700. In at least one embodiment, the configuration manager 724 may be able to configure different layers, such as the software layer 730 and the framework layer 720, which includes Spark and a distributed file system 728 for supporting large-scale data processing. In at least one embodiment, the resource manager 726 is able to manage cluster or group computing resources mapped to or allocated to support the distributed file system 728 and the job scheduler 722. In at least one embodiment, the cluster or group computing resources may include group computing resources 714 at the data center infrastructure layer 710. In at least one embodiment, the resource manager 726 may coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0053] In at least one embodiment, the software 732 included in the software layer 730 may include software used by at least a portion of the distributed file system 728 of the nodes CR 716(1)-716(N), the grouped computing resources 714, and / or the framework layer 720. One or more types of software may include, but are not limited to, internet web search software, email virus scanning software, database software, and streaming video content software.

[0054] In at least one embodiment, the application 742 included in the application layer 740 may include one or more types of applications used by at least a portion of nodes CR 716(1)-716(N), grouped computing resources 714, and / or the distributed file system 728 of the framework layer 720. One or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0055] In at least one embodiment, any of the configuration manager 724, resource manager 726, and resource coordinator 712 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can alleviate the trouble of data center operators of data center 700 making potentially poor configuration decisions and potentially avoiding underutilized and / or poorly performing parts of the data center.

[0056] In at least one embodiment, data center 700 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 700. In at least one embodiment, a trained machine learning model corresponding to one or more neural networks can be used to infer or predict information using weight parameters calculated through one or more training techniques described herein, using the resources described above with respect to data center 700.

[0057] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured to allow users to train or execute information inference services, such as image recognition, speech recognition, or other artificial intelligence services.

[0058] Such components can be used to update hash maps or other such constructs. This could involve updating individual entries of a hash table from a single thread to a single execution thread.

[0059] Computer System

[0060] Figure 8 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SOC), or some combination thereof with a processor 800, which may include an execution unit for executing instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, the computer system 800 may include, but is not limited to, components such as processor 802, to employ an execution unit including logic for executing algorithms for process data. In at least one embodiment, the computer system 800 may include a processor, such as those available from Intertron Corporation in Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM The microprocessor may also be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used, the computer system 800 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington.

[0061] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0062] In at least one embodiment, the computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808 performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 800 is a single-processor desktop or server system, but in another embodiment, the computer system 800 may be a multiprocessor system. In at least one embodiment, the processor 802 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, which may transmit data signals between the processor 802 and other components in the computer system 800.

[0063] In at least one embodiment, processor 802 may include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 804. In at least one embodiment, processor 802 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside externally to processor 802. Other embodiments may also include a combination of both internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 806 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0064] In at least one embodiment, an execution unit 808, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 802. In at least one embodiment, the processor 802 may further include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 808 may include logic for processing a packaged instruction set 809. In at least one embodiment, by including the packaged instruction set 809 in the instruction set of the general-purpose processor 802 and the associated circuitry for executing the instructions, packaged data in the general-purpose processor 802 can be used to perform operations used by numerous multimedia applications. In one or more embodiments, the execution of numerous multimedia applications can be accelerated and more efficiently performed by using the full width of the processor's data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0065] In at least one embodiment, execution unit 808 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, memory 820 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other storage device. In at least one embodiment, memory 820 may store instructions 819 and / or data 821 represented by data signals executable by processor 802.

[0066] In at least one embodiment, the system logic chip may be coupled to a processor bus 810 and a memory 820. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 816, and the processor 802 may communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 may provide a high-bandwidth memory path 818 to the memory 820 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 816 may direct data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge data signals between the processor bus 810, the memory 820, and the system I / O 822. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 may be coupled to the memory 820 via the high-bandwidth memory path 818, and the graphics / video card 812 may be coupled to the MCH 816 via an Accelerated Graphics Port (“AGP”) interconnect 814.

[0067] In at least one embodiment, computer system 800 may use system I / O 822, which serves as a proprietary hub interface bus, to couple MCH 816 to I / O controller hub (“ICH”) 830. In at least one embodiment, ICH 830 may provide direct connectivity to some I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 820, chipset, and processor 802. Examples may include, but are not limited to, an audio controller 829, a firmware hub (“Flash BIOS”) 828, a wireless transceiver 826, a data storage 824, a legacy I / O controller 823 including a user input and keyboard interface 825, a serial expansion port 827 (e.g., Universal Serial Bus (“USB”)), and a network controller 834. Data storage device 824 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0068] In at least one embodiment, Figure 8 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 8 An exemplary system-on-a-chip (“SoC”) may be illustrated. In at least one embodiment, the device may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 800 are interconnected using a compute fast link (CXL) interconnect.

[0069] Such components can be used to update hash maps or other such constructs. This could include updating individual entries of a hash map from a single thread to a single execution thread.

[0070] Figure 9 This is a block diagram illustrating an electronic device 900 for utilizing a processor 910 according to at least one embodiment. In at least one embodiment, the electronic device 900 may be, for example, but not limited to, a laptop, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0071] In at least one embodiment, system 900 may, but is not limited to, processor 910 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 910 is coupled using a bus or interface such as an I2C bus, system management bus (“SMBus”), low pin count (LPC) bus, serial peripheral interface (“SPI”), high-definition audio (“HDA”) bus, serial advanced technology accessory (“SATA”) bus, universal serial bus (“USB”) (versions 1, 2, and 3), or universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment, Figure 9 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 9 An exemplary system-on-a-chip (“SoC”) may be illustrated. In at least one embodiment, Figure 9 The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 9 One or more components include one or more components interconnected using computational fast link (CXL) interconnect.

[0072] In at least one embodiment, Figure 9 This may include a display 924, a touchscreen 925, a touchpad 930, a near-field communication unit (“NFC”) 945, a sensor hub 940, a thermal sensor 946, a fast chipset (“EC”) 935, a trusted platform module (“TPM”) 938, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 922, a DSP 960, a drive 920 (e.g., a solid-state drive) (“SSD”) or a hard disk drive (“HDD”), a wireless local area network unit (“WLAN”) 950, a Bluetooth unit 952, a wireless wide area network unit (“WWAN”) 956, a global positioning system (GPS) 955, a camera (“USB 3.0 camera”) 954 (e.g., a USB 3.0 camera), and / or, for example, a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 915 implemented in accordance with the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0073] In at least one embodiment, other components may be communicatively coupled to processor 910 via the components discussed above. In at least one embodiment, accelerometer 941, ambient light sensor (“ALS”) 942, compass 943, and gyroscope 944 may be communicatively coupled to sensor hub 940. In at least one embodiment, thermal sensor 939, fan 937, keyboard 946, and touchpad 930 may be communicatively coupled to EC 935. In at least one embodiment, speaker 963, earphone 964, and microphone (“mic”) 965 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 962, which may be communicatively coupled to DSP 960. In at least one embodiment, audio unit 964 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 957 may be communicatively coupled to WWAN unit 956. In at least one embodiment, components such as WLAN unit 950, Bluetooth unit 952, and WWAN unit 956 can be implemented as: next-generation form factor (“NGFF”).

[0074] Such components can be used to update hash maps or other such constructs. This could include updating individual entries of a hash map from a single thread to a single execution thread.

[0075] Figure 10 This is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 1000 includes one or more processors 1002 and one or more graphics processors 1008, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 1002 or processor cores 1007. In at least one embodiment, system 1000 is a processing platform incorporated in a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0076] In at least one embodiment, system 1000 may include or be incorporated into a server-based gaming platform, a game console including a game and media console, a mobile game console, a handheld game console, or an online game console. In at least one embodiment, system 1000 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 1000 may also include a wearable device coupled to or integrated into the wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In at least one embodiment, processing system 1000 is a television or set-top box device having one or more processors 1002 and a graphical interface generated by one or more graphics processors 1008.

[0077] In at least one embodiment, one or more processors 1002 each include one or more processor cores 1007 for processing instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 1007 is configured to process a particular instruction set 1009. In at least one embodiment, the instruction set 1009 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, the processor cores 1007 may each process a different instruction set 1009, which may include instructions that facilitate the emulation of other instruction sets. In at least one embodiment, the processor cores 1007 may also include other processing devices, such as digital signal processors (DSPs).

[0078] In at least one embodiment, processor 1002 includes cache memory 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among various components of processor 1002. In at least one embodiment, processor 1002 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which may be shared among processor cores 1007 using known cache coherence techniques. In at least one embodiment, processor 1002 further includes a register file 1006, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 1006 may include general-purpose registers or other registers.

[0079] In at least one embodiment, one or more processors 1002 are coupled to one or more interface buses 1010 to transmit communication signals, such as address, data, or control signals, between the processors 1002 and other components in the system 1000. In at least one embodiment, the interface bus 1010 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface 1010 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Fast), memory buses, or other types of interface buses. In at least one embodiment, the processor 1002 includes an integrated memory controller 1016 and a platform controller hub 1030. In at least one embodiment, the memory controller 1016 facilitates communication between memory devices and other components of the system 1000, while the platform controller hub (PCH) 1030 provides connectivity to I / O devices via a local I / O bus.

[0080] In at least one embodiment, storage device 1020 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or other memory device with suitable performance for use as process memory. In at least one embodiment, storage device 1020 may be used as system memory of system 1000 to store data 1022 and instructions 1021 for use when one or more processors 1002 execute an application or process. In at least one embodiment, memory controller 1016 is also coupled to an optional external graphics processor 1012, which may communicate with one or more graphics processors 1008 of processor 1002 to perform graphics and media operations. In at least one embodiment, display device 1011 may be connected to processor 1002. In at least one embodiment, display device 1011 may include one or more internal display devices, such as those in mobile electronic devices or portable computer devices, or external display devices attached via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 1011 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) or augmented reality (AR) applications.

[0081] In at least one embodiment, the platform controller hub 1030 enables peripheral devices to connect to the memory device 1020 and the processor 1002 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 1046, a network controller 1034, a firmware interface 1028, a wireless transceiver 1026, a touch sensor 1025, and a data storage device 1024 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 1024 may be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, the touch sensor 1025 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1026 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 1028 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 1034 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 1010. In at least one embodiment, audio controller 1046 is a multi-channel high-definition audio controller. In at least one embodiment, system 1000 includes an optional legacy I / O controller 1040 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. In at least one embodiment, platform controller hub 1030 may also be connected to one or more Universal Serial Bus (USB) controllers 1042 that connect input devices, such as a keyboard and mouse combination 1043, a camera 1044, or other USB input devices.

[0082] In at least one embodiment, instances of the memory controller 1016 and platform controller hub 1030 may be integrated into a discrete external graphics processor, such as external graphics processor 1012. In at least one embodiment, the platform controller hub 1030 and / or the memory controller 1016 may be external to one or more processors 1002. For example, in at least one embodiment, system 1000 may include external memory controller 1016 and platform controller hub 1030, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset communicating with processor 1002.

[0083] Such components can be used to update hash maps or other such constructs. This could include updating individual entries of a hash map from a single thread to a single execution thread.

[0084] Figure 11 This is a block diagram of a processor 1100 having one or more processor cores 1102A-1102N, an integrated memory controller 1114, and an integrated graphics processor 1108 according to at least one embodiment. In at least one embodiment, the processor 1100 may include additional cores up to and including additional cores 1102N, indicated by dashed boxes. In at least one embodiment, each processor core 1102A-1102N includes one or more internal cache units 1104A-1104N. In at least one embodiment, each processor core may also access one or more units 1106 of a shared cache.

[0085] In at least one embodiment, internal cache units 1104A-1104N and shared cache unit 1106 represent a cache memory hierarchy within processor 1100. In at least one embodiment, cache memory units 1104A-1104N may include at least one level of instruction cache and data cache in one or more shared intermediate cache levels per processor core, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, wherein the highest level cache preceding external memory is classified prior to the LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 1106 and 1104A-1104N.

[0086] In at least one embodiment, the processor 1100 may further include a set of one or more bus controller units 1116 and a system agent core 1110. In at least one embodiment, one or more bus controller units 1116 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 1110 provides management functions for various processor components. In at least one embodiment, the system agent core 1110 includes one or more integrated memory controllers 1114 to manage access to various external memory devices (not shown).

[0087] In at least one embodiment, one or more processor cores 1102A-1102N include support for simultaneous multithreading. In at least one embodiment, system agent core 1110 includes components for coordinating and operating cores 1102A-1102N during multithreaded processing. In at least one embodiment, system agent core 1110 may additionally include a power control unit (PCU) including logic and components to regulate one or more power states of processor cores 1102A-1102N and graphics processor 1108.

[0088] In at least one embodiment, processor 1100 further includes a graphics processor 1108 to perform graphics processing operations. In at least one embodiment, graphics processor 1108 is coupled to a shared cache unit 1106 and a system proxy core 1110 including one or more integrated memory controllers 1114. In at least one embodiment, system proxy core 1110 further includes a display controller 1111 for driving graphics processor outputs to one or more coupled displays. In at least one embodiment, display controller 1111 may also be a separate module coupled to graphics processor 1108 via at least one interconnect, or it may be integrated within graphics processor 1108.

[0089] In at least one embodiment, ring-based interconnect unit 1112 is used to couple internal components of processor 1100. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, graphics processor 1108 is coupled to ring interconnect 1112 via I / O link 1113.

[0090] In at least one embodiment, I / O link 1113 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 1118 (e.g., eDRAM module). In at least one embodiment, each of processor cores 1102A-1102N and graphics processor 1108 uses embedded memory module 1118 as a shared last-level cache.

[0091] In at least one embodiment, processor cores 1102A-1102N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 1102A-1102N are heterogeneous in terms of instruction set architecture (ISA), with one or more processor cores 1102A-1102N executing a common instruction set, while one or more other processor cores 1102A-1102N execute a common instruction set or a subset of a different instruction set. In at least one embodiment, processor cores 1102A-1102N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 1100 may be implemented on one or more chips or as a SoC integrated circuit.

[0092] Such components can be used to update hash maps or other such constructs. This could involve updating individual entries of a hash table from a single thread to a single execution thread.

[0093] Other variations are within the spirit of this disclosure. Therefore, although the disclosed technology is readily adaptable to various modifications and alternative constructions, certain illustrated embodiments are shown in the accompanying drawings and have been described in detail above. However, it should be understood that the disclosure is not intended to be limited to the one or more specific forms disclosed, but rather, it is intended to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of this disclosure as defined in the appended claims.

[0094] In the context of describing the disclosed embodiments (particularly in the context of the appended claims), the terms “a,” “an,” and “the,” and similar references, should be interpreted as encompassing both singular and plural forms rather than as definitions of terms, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise stated, the terms “comprising,” “having,” “including,” and “containing” should be interpreted as open-ended terms (meaning “including, but not limited to”). The term “connection,” when unmodified, refers to a physical connection and should be understood as being partially or wholly contained in, attached to, or connected together, even with any intervention. Unless otherwise indicated herein, references to numerical ranges herein are intended only as a way of abbreviating each individual value falling within that range, and each individual value is incorporated into the specification as if it were separately described herein. Unless otherwise indicated by the context or contradicted, the use of the terms “group” (e.g., “a set of items”) or “subset” should be interpreted as a non-empty set comprising one or more members. Furthermore, unless the context otherwise indicates or contradicts it, the term "subset" for a corresponding set does not necessarily mean an appropriate subset of the corresponding set, but rather that a subset and the corresponding set can be equal.

[0095] Unless explicitly stated otherwise or clearly contradicted by the context, the closing phrases such as “at least one of A, B, and C” or “at least one of A, B, and C” are understood in the context to generally refer to items, terms, etc., which can be A or B or C, or any non-empty subset of the set A and B with C. For example, the connecting phrases “at least one of A, B, and C” and “at least one of A, B, and C” with three members refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Therefore, such a conjunction is generally not intended to imply that some embodiments require the presence of at least one of A, at least one of B, and at least one of C. Additionally, unless otherwise stated or contradicted by the context, the term “multiple” indicates a plural state (e.g., “multiple items” means multiple items). A plural is at least two items, but can be multiple when explicitly indicated or by the context. Furthermore, unless otherwise stated or clearly understood from the context, the phrase “based on” means “at least partially based on” rather than “based on only”.

[0096] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations thereof and / or combinations thereof) are executed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more application programs) that execute jointly on one or more processors via hardware or a combination thereof. In at least one embodiment, the code is stored, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that does not include transient signals (e.g., propagating transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuitry (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on one or more non-transitory computer-readable storage media on which executable instructions (or other memory for storing executable instructions) are stored, which, when executed by one or more processors of a computer system (i.e., due to execution), cause the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media includes one or more separate non-transitory storage media comprising multiple non-transitory computer-readable storage media and multiple non-transitory computer-readable storage media lacking all the code, while the multiple non-transitory computer-readable storage media collectively store all the code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors; for example, the non-transitory computer-readable storage media stores the instructions, and the main central processing unit (“CPU”) executes some instructions while the graphics processing unit (“GPU”) executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and the different processors execute different subsets of the instructions.

[0097] Therefore, in at least one embodiment, the computer system is configured to implement one or more services that perform the processes described herein individually or collectively, and such a computer system is configured with suitable hardware and / or software capable of performing the operations. Furthermore, the computer system implementing at least one embodiment of this disclosure is a single device, and in another embodiment, it is a distributed computer system comprising multiple devices operating in different ways, such that the distributed computer system performs the operations described herein, and that a single device does not perform all the operations.

[0098] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate embodiments of this disclosure and does not constitute a limitation on the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating that any unclaimed element is essential to the implementation of the disclosure.

[0099] All references cited in this article, including publications, patent applications and patents, are incorporated herein by reference to the extent that each reference is individually and specifically indicated as incorporated herein by reference and set forth in its entirety.

[0100] The terms “coupled” and “connected” and their derivatives may be used in the specification and claims. It should be understood that these terms may not be intended to be synonyms with each other. Rather, in certain examples, “connected” or “coupled” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0101] Unless otherwise specified, it will be understood that throughout this specification, terms such as “processing,” “computational processing,” “computation,” “determine,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that processes and / or converts data represented as physical quantities (e.g., electrons) in the registers and / or memory of the computing system into other data represented as physical quantities in the memory, registers, or other such information storage, transmission, or display devices of the computing system.

[0102] In a similar manner, the term "processor" can refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. As a non-limiting example, a "processor" can be a CPU or a GPU. A "computing platform" can include one or more processors. As used herein, a "software" process can include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Moreover, each process can refer to multiple processes that execute instructions sequentially or intermittently, sequentially, or in parallel. The terms "system" and "method" are used interchangeably herein, provided that a system can embody one or more methods, and a method can be considered a system.

[0103] In this document, reference may be made to a subsystem, computer system, or computer-implemented machine that acquires, obtains, receives, or inputs analog or digital data. Acquiring, obtaining, receiving, or inputting analog and digital data can be accomplished in various ways, such as by receiving data as a parameter to a function call or a call to an application programming interface (API). In some embodiments, the process of acquiring, obtaining, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another embodiment, the process of acquiring, obtaining, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be implemented by transmitting data as an input or output parameter to a function call, an application programming interface, or an inter-process communication mechanism.

[0104] While the discussion above illustrates example implementations of the described technologies, other architectures can be used to implement the described functionality and are intended to be within the scope of this disclosure. Furthermore, although specific assignments of responsibility have been defined above for discussion purposes, various functions and responsibilities can be allocated and divided in different ways depending on the circumstances.

[0105] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or actions described. Instead, specific features and actions are disclosed as exemplary forms for implementing the claims.

Claims

1. A hash map update method comprising: receiving a set of change requests for data in a data set, the change requests being received by executing a set of parallel threads; storing information of the change requests into a buffer; for each entry in a hash map representing the data set, determining the change requests corresponding to the each entry, wherein a plurality of change requests are enabled to correspond to one of the each entry; retrieving the information of the change requests determined to correspond to the each entry in the hash map from the buffer; and iterating the change requests corresponding to the each entry in the hash map using a single thread of execution of the each entry in order to update at least a subset of the each entry.

2. The method of claim 1, further comprising: providing an updated version of the data set according to the set of change requests.

3. The method of claim 1, wherein, the data set represents world space data.

4. The method of claim 3, wherein, each entry in the hash map corresponds to a cell consisting of the world space data visible by one or more pixel locations.

5. The method of claim 4, further comprising: determining the pixel locations corresponding to the cell, wherein different cells are enabled to correspond to different numbers of pixel locations, and wherein different cells are enabled to correspond to different levels of detail corresponding to different numbers of pixel locations between levels.

6. The method of claim 5, wherein, aggregating updates for each entry of a first level such that a corresponding entry of a second level is enabled to process change requests for the each entry in a single thread of execution for the entry of the second level.

7. The method of claim 3, further comprising: determining the set of change requests based at least in part on ray tracing for a specified viewpoint of a virtual camera.

8. The method of claim 3, further comprising: aggregating the change requests for the each entry in the hash map, wherein the change requests include a last change requested by the each entry as represented by an index in a change list.

9. The method of claim 1, wherein, performing updates to at least a subset of the each entry using at least one of a graphics processing unit (GPU) or a central processing unit (CPU).

10. The method of claim 1, wherein, the data set is generated using simulation with a plurality of parallel threads.

11. A hash map update system comprising: one or more processors; and memory including instructions that, when executed by the one or more processors, cause the system to perform the following operations: receiving a set of change requests received by executing a set of parallel threads; storing information of the change requests into a buffer; for each entry in a hash map representing a data set, determining the change requests corresponding to the each entry, wherein a plurality of change requests are enabled to correspond to one of the each entry; retrieving the information of the change requests corresponding to the each entry in the hash map from the buffer; and iterating the change requests corresponding to the each entry in the hash map using a single thread of execution of the each entry in order to update at least a subset of the each entry. using an execution single thread of the individual entries, iterating through the change requests corresponding to the individual entries in the hash map in order to update at least a subset of the individual entries.

12. The system of claim 11, wherein the hash map represents dataset world space data, and wherein the individual entries in the hash map correspond to cells consisting of the world space data visible through one or more pixel locations.

13. The system of claim 12, wherein, the instructions when executed further cause the system to: determine the pixel locations corresponding to the cells, wherein different cells are enabled to correspond to different numbers of pixel locations, and wherein different cells are enabled to correspond to different levels of detail corresponding to different numbers of pixel locations between levels.

14. The system of claim 11, wherein, the instructions when executed further cause the system to: aggregate the change requests for the individual entries in the hash map, wherein the change requests include last changes requested for the individual entries as represented by indices in a change list.

15. The system of claim 11, wherein, perform the updating of at least a subset of the individual entries using at least one of a graphics processing unit (GPU) or a central processing unit (CPU).

16. A hash map updating method comprising: receiving a set of change requests for a virtual environment, the change requests being received by executing a set of parallel threads; determining, for individual entries in a hash map, the change requests corresponding to the individual entries; using an execution single thread of the individual entries, iterating through the change requests corresponding to the individual entries in the hash map in order to update at least a subset of the individual entries; and rendering an image corresponding to the virtual environment resulting from the set of change requests for display.

17. The method of claim 16, wherein, the individual entries in the hash map correspond to cells consisting of world space data visible through one or more pixel locations.

18. The method of claim 17, further comprising: determining the pixels corresponding to the cells, wherein different cells are enabled to correspond to different numbers of pixels, and wherein different cells are enabled to correspond to different levels of detail corresponding to different numbers of pixels between levels.

19. The method of claim 18, wherein, aggregating updates for individual entries of a first level such that corresponding entries of a second level are enabled to process change requests for the individual entries in a single thread of entries for the second level.

20. The method of claim 16, further comprising: determining the set of change requests based at least in part on ray tracing of a specified viewpoint of a virtual camera for a scene.

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