Memory device with 2 transistor vertical memory cell and shield structure

Abstract

Some embodiments include apparatuses and methods of forming the same. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is between and electrically separated from the first charge storage structure and the second charge storage structure. The conductive line forms a gate of each of the first transistor, the second transistor, the third transistor, and the fourth transistor.

Description

[0001] Priority Application

[0002] This application claims the priority benefit of U.S. provisional application serial number 62 / 893,023, filed August 28, 2019, which is incorporated herein by reference in its entirety. BACKGROUND

[0003] Memory devices are widely used in computers and many other electronic devices to store information. Memory devices are typically classified into two types: volatile memory devices and non-volatile memory devices. Memory devices often have a large number of memory cells in which information is stored. In volatile memory devices, the information stored in the memory cells is lost if the power is disconnected from the memory device. In non-volatile memory devices, the information stored in the memory cells remains even if the power is disconnected from the memory device.

[0004] The description herein relates to volatile memory devices. Most conventional volatile memory devices store information in the form of an electrical charge in a capacitor structure included in a memory cell. As the demand for device storage density increases, many conventional techniques provide ways to shrink the size of memory cells in order to increase the device storage density of a given device area. However, if the memory cell size is shrunk to a certain size, physical limitations and manufacturing constraints can pose challenges to such conventional techniques. Moreover, increased device storage density of a given area can cause excessive capacitive coupling between elements of adjacent memory cells. Unlike some conventional memory devices, the memory devices described herein include features that can overcome the challenges faced by conventional techniques. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 A block diagram of an apparatus in the form of a memory device including a volatile memory cell is shown in accordance with some embodiments described herein.

[0006] Figure 2 A schematic diagram of a portion of a memory device including a memory array of two-transistor (2T) memory cells is shown in accordance with some embodiments described herein.

[0007] Figure 3 A memory device including example voltages used during a read operation of the memory device is shown in accordance with some embodiments described herein. Figure 2 A memory device including example voltages used during a write operation of the memory device is shown in accordance with some embodiments described herein.

[0008] Figure 4 A memory device including example voltages used during a write operation of the memory device is shown in accordance with some embodiments described herein. Figure 2 A memory device including example voltages used during a write operation of the memory device is shown in accordance with some embodiments described herein.

[0009] Figure 5 、 Figure 6 、 Figure 7 、 Figure 8A and Figure 8B illustrate different views of structures of memory devices according to some embodiments described herein. Figure 2

[0010] Figures 9 to 22 illustrate processes of forming memory devices according to some embodiments described herein.

[0011] Figures 23A to 28 illustrate structures of additional memory devices that can be variations of memory devices according to some embodiments described herein. Figures 2 to 8B

[0012] Figure 29A 、 Figure 29B and Figure 29C illustrate different views of structures of memory devices including multiple decks of memory cells according to some embodiments described herein. DETAILED DESCRIPTION

[0013] The memory devices described herein include volatile memory cells, where each of the memory cells can include two transistors (2T). One of the two transistors has a charge storage structure that can form a memory element of the memory cell to store information. The memory devices described herein can have structures that allow the size of the memory devices to be relatively smaller than the size of similar conventional memory devices (e.g., 4F2cell footprint). The described memory devices can include a single access line (e.g., word line) to control the two transistors of the memory cells. This can result in reduced power consumption and improved processing. The described memory devices can include a shield structure between the charge storage structures of adjacent memory cells. The shield structure can reduce capacitive coupling between the adjacent charge storage structures of adjacent memory cells. The reduction in capacitive coupling between the adjacent charge storage structures can improve the operation of the described memory devices (e.g., improve read signal margin). Each of the memory cells of the described memory devices can include a cross-point gain cell structure (and cross-point operation) such that a single access line (e.g., word line) and a single data line (e.g., bit line) can be used to access the memory cells during operation of the memory devices (e.g., read or write operations). Reference is made below to Figures 1 to 29C Other improvements and benefits of the described memory devices and variations thereof are discussed.

[0014] Figure 1 ​​A block diagram of an apparatus in the form of a memory device 100 including volatile memory cells is shown in accordance with some embodiments described herein. The memory device 100 includes a memory array 101 that can contain memory cells 102. The memory device 100 can include a volatile memory device such that the memory cells 102 can be volatile memory cells. An example of the memory device 100 includes a dynamic random access memory (DRAM) device. If a power source (e.g., a supply voltage Vcc) is disconnected from the memory device 100, information stored in the memory cells 102 of the memory device 100 can be lost (e.g., invalidated). Hereinafter, the supply voltage Vcc is referred to as representing some voltage level, however, it is not limited to a supply voltage (e.g., Vcc) of a memory device (e.g., the memory device 100). For example, if the memory device (e.g., the memory device 100) has an internal voltage generator (not shown in Figure 1 ) that generates an internal voltage based on the supply voltage Vcc, this internal voltage can be used instead of the supply voltage Vcc.

[0015] In a physical structure of the memory device 100, each of the memory cells 102 can include transistors (e.g., two transistors) formed vertically (e.g., stacked on different levels) in different levels above a substrate (e.g., a semiconductor substrate) of the memory device 100. The memory device 100 can also include multiple levels (e.g., multiple decks) of memory cells, where one level (e.g., one deck) of memory cells can be formed (e.g., stacked) above another level (e.g., another deck) of memory cells. The structure of the memory array 101 including the memory cells 102 can include the structures of the memory array and the memory cells described below with reference to Figures 2 to 29C .

[0016] As shown in Figure 1 , the memory device 100 can include access lines 104 (e.g., “word lines”) and data lines (e.g., bit lines) 105. The memory device 100 can use signals (e.g., word line signals) on the access lines 104 to access the memory cells 102 and the data lines 105 to provide information (e.g., data) to be stored (e.g., written) in the memory cells 102 or read (e.g., sensed) from the memory cells 102.

[0017] Memory device 100 can include address register 106 to receive address information ADDR (e.g., row and column address signals) on lines (e.g., address lines) 107. Memory device 100 can include row access circuitry (e.g., X-decoder) 108 and column access circuitry (e.g., Y-decoder) 109 operable to decode address information ADDR from address register 106. Based on the decoded address information, memory device 100 can determine which memory cells 102 are to be accessed during a memory operation. Memory device 100 can perform write operations to store information in memory cells 102, and read operations to read (e.g., sense) information (e.g., previously stored information) in memory cells 102. Memory device 100 can also perform operations (e.g., refresh operations) to refresh values of information stored in memory cells 102 (e.g., to keep them valid). Each of memory cells 102 can be configured to store information that can represent at most one bit (e.g., a single bit having a binary 0 (“0”) or a binary 1 (“1”)) or more than one bit (e.g., multiple bits having a combination of at least two binary bits).

[0018] Memory device 100 can receive supply voltages, including supply voltages Vcc and Vss, on lines 130 and 132, respectively. Supply voltage Vss can operate at a ground potential (e.g., having a value of approximately zero volts). Supply voltage Vcc can include an external voltage supplied to memory device 100 from an external power source, such as a battery, or alternating current to direct current (AC-DC) converter circuitry.

[0019] As shown in Figure 1 Memory device 100 can include memory control unit 118 including circuitry (e.g., hardware components) to control memory operations (e.g., read and write operations) of memory device 100 based on control signals on lines (e.g., control lines) 120. Examples of signals on lines 120 include row access strobe signal RAS*, column access strobe signal CAS*, write enable signal WE*, chip select signal CS*, clock signal CK, and clock enable signal CKE. These signals can be part of the signals provided to a DRAM device.

[0020] As shown in Figure 1As shown in the middle, memory device 100 can include lines (e.g., global data lines) 112 that can carry signals DQ0 through DQN. In a read operation, the value (e.g., “0” or “1”) of the information (read from memory cells 102) provided to lines 112 (in the form of signals DQ0 through DQN) can be based on the value of the signal on data lines 105. In a write operation, the value (e.g., “0” or “1”) of the information provided to data lines 105 (to be stored in memory cells 102) can be based on the value of signals DQ0 through DQN on lines 112.

[0021] Memory device 100 can include sensing circuitry 103, selection circuitry 115, and input / output (I / O) circuitry 116. Column access circuitry 109 can selectively activate signals on lines (e.g., select lines) based on address signals ADDR. Selection circuitry 115 can respond to signals on lines 114 to select signals on data lines 105. The signals on data lines 105 can represent the value of information to be stored in memory cells 102 (e.g., during a write operation) or the value of information read (e.g., sensed) from memory cells 102 (e.g., during a read operation).

[0022] I / O circuitry 116 can operate to provide information read from memory cells 102 to lines 112 (e.g., during a read operation) and to provide information from lines 112 (e.g., provided by an external device) to data lines 105 for storage in memory cells 102 (e.g., during a write operation). Lines 112 can include nodes within memory device 100 or pins (or solder balls) on a package in which memory device 100 can reside. Other devices external to memory device 100 (e.g., a hardware memory controller or a hardware processor) can communicate with memory device 100 via lines 107, 112, and 120.

[0023] Memory device 100 can include other components that are not shown in Figure 1 the middle so as not to obscure the example embodiments described herein. At least a portion of memory device 100 (e.g., a portion of memory array 101) can include structures and operations similar to or the same as any of the memory devices described below with reference to Figures 2 to 29C .

[0024] Figure 2 A diagram showing a portion of a memory device 200 including a memory array 201 is shown in accordance with some embodiments described herein. Memory device 200 can correspond to Figure 1 memory device 100. For example, memory array 201 can form a portion of Figure 1 memory array 101. As Figure 2As shown in the middle, the memory device 200 can include memory cells 210-215 that are volatile memory cells (e.g., DRAM cells). For simplicity, like or identical elements among the memory cells 210-215 are given the same label.

[0025] Each of the memory cells 210-215 can include two transistors Tl and T2. Thus, each of the memory cells 210-215 can be referred to as a 2T memory cell (e.g., a 2T gain cell). Each of the transistors Tl and T2 can include a field effect transistor (FET). As an example, the transistor Tl can be a p-channel FET (PFET), and the transistor T2 can be an n-channel FET (NFET). Portions of the transistor Tl can include structures of a p-channel metal-oxide-semiconductor (PMOS) transistor FET (PFET). Thus, the transistor Tl can include operations similar to operations of a PMOS transistor. Portions of the transistor T2 can include an n-channel metal-oxide-semiconductor (NMOS). Thus, the transistor T2 can include operations similar to operations of an NMOS transistor.

[0026] The transistor Tl of the memory device 200 can include a charge storage based structure (e.g., based on a floating gate). As shown in the middle, the transistor Tl can include a floating gate 204. The floating gate 204 can be electrically coupled to (e.g., directly coupled to) the transistor Tl of a particular memory cell among the memory cells 210-215. Thus, a circuit path (e.g., a current path) can be formed directly between the transistor Tl of a particular memory cell and the floating gate 204 of the particular memory cell during an operation (e.g., a write operation) of the memory device 200. Figure 2 As shown in the middle, each of the memory cells 210-215 can include a charge storage structure 202 that can include a floating gate of the transistor Tl. The charge storage structure 202 can form a memory element of a respective memory cell among the memory cells 210-215. The charge storage structure 202 can store a charge. A value (e.g., a “0” or a “1”) of information stored in a particular memory cell among the memory cells 210-215 can be based on an amount of charge in the charge storage structure 202 of the particular memory cell.

[0027] As shown in the middle, the transistor T2 (e.g., a channel region of the transistor T2) of a particular memory cell among the memory cells 210-215 can be electrically coupled to (e.g., directly coupled to) the charge storage structure 202 of the particular memory cell. Thus, a circuit path (e.g., a current path) can be formed directly between the transistor T2 of a particular memory cell and the charge storage structure 202 of the particular memory cell during an operation (e.g., a write operation) of the memory device 200. Figure 2 As shown in the middle, the transistor T2 (e.g., a channel region of the transistor T2) of a particular memory cell among the memory cells 210-215 can be electrically coupled to (e.g., directly coupled to) the charge storage structure 202 of the particular memory cell. Thus, a circuit path (e.g., a current path) can be formed directly between the transistor T2 of a particular memory cell and the charge storage structure 202 of the particular memory cell during an operation (e.g., a write operation) of the memory device 200.

[0028] The memory cells 210-215 can be arranged in memory cell groups 2010 and 2011. Figure 2Two memory cell groups (e.g., 2010 and 2011) are shown as an example. However, memory device 200 may include more than two memory cell groups. Memory cell groups 2010 and 2011 may include the same number of memory cells. For example, memory cell group 2010 may include memory cells 210, 212, and 214, and memory cell group 2011 may include memory cells 211, 213, and 215. Figure 2 Three memory cells from each of memory cell groups 2010 and 2011 are shown as an example. The number of memory cells in memory cell groups 2010 and 2011 may be different from three.

[0029] Memory device 200 can perform write operations to store information in memory cells 210 to 215 and read operations to read (e.g., sense) information from memory cells 210 to 215. Memory device 200 can be configured to operate as a DRAM device. However, unlike some conventional DRAM devices that store information in a container structure such as a capacitor, memory device 200 can store information in the form of charge in a charge storage structure 202 (which may be a floating gate structure). As mentioned above, charge storage structure 202 may be a floating gate of transistor T1. During operation of memory device 200 (e.g., read or write operations), access lines (e.g., a single access line) and data lines (e.g., a single data line) can be used to access selected memory cells (e.g., a target memory cell).

[0030] like Figure 2 As shown, memory device 200 may include access lines (e.g., word lines) 241, 242, and 243 capable of carrying corresponding signals (e.g., word line signals) WL1, WL2, and WLn. Access lines 241, 242, and 243 can be used to access both memory cell groups 2010 and 2011. Each of access lines 241, 242, and 243 may be configured as at least one conductive line (one or more conductive lines electrically coupled (e.g., short-circuited) to each other). Access lines 241, 242, and 243 may be selectively activated (e.g., activated one at a time) during operation of memory device 200 (e.g., read or write operations) to access one or more selected memory cells (or multiple selected memory cells) among memory cells 210 to 215. The selected cell may be referred to as the target cell. In a read operation, information may be read from one or more selected memory cells. In a write operation, information may be stored in one or more selected memory cells.

[0031] In memory device 200, a single access line (e.g., a single word line) can be used to control (e.g., turn on or off) the transistors Tl and T2 of a respective memory cell during a read or write operation of memory device 200. Some conventional memory devices can use multiple (e.g., two separate) access lines to control access to a respective memory cell during read and write operations. In contrast to such conventional memory devices (which use multiple access lines to a same memory cell), memory device 200 uses a single access line (e.g., a shared access line) in memory device 200 to control both transistors Tl and T2 of a respective memory cell to access the respective memory cell. This technique can save space and simplify the operation of memory device 200. In addition, some conventional memory devices can use multiple data lines to access a selected memory cell (e.g., during a read operation) to read information from the selected memory cell. In memory device 200, a single data line (e.g., data line 221 or 222) can be used to access a selected memory cell (e.g., during a read operation) to read information from the selected memory cell. This can also simplify the structure, operation, or both, of memory device 200 compared to conventional memory devices that use multiple data lines to access a selected memory cell.

[0032] In memory device 200, the gate of each of transistors Tl and T2 can be part of a respective access line (e.g., a respective word line). As shown in FIG. 2, the gate of each of transistors Tl and T2 of memory cell 210 can be part of access line 241. The gate of each of transistors Tl and T2 of memory cell 211 can be part of access line 241. For example, in the structure of memory device 200, four different portions of one conductive material (or multiple materials) that form access line 241 can form the gates (e.g., four gates) of transistors Tl and T2 of memory cell 210 and the gates of transistors Tl and T2 of memory cell 211, respectively. Figure 2 In memory device 200, the gate of each of transistors Tl and T2 can be part of a respective access line (e.g., a respective word line). As shown in FIG. 2, the gate of each of transistors Tl and T2 of memory cell 210 can be part of access line 241. The gate of each of transistors Tl and T2 of memory cell 211 can be part of access line 241. For example, in the structure of memory device 200, four different portions of one conductive material (or multiple materials) that form access line 241 can form the gates (e.g., four gates) of transistors Tl and T2 of memory cell 210 and the gates of transistors Tl and T2 of memory cell 211, respectively.

[0033] In memory device 200, the gate of each of transistors Tl and T2 can be part of a respective access line (e.g., a respective word line). As shown in FIG. 2, the gate of each of transistors Tl and T2 of memory cell 210 can be part of access line 241. The gate of each of transistors Tl and T2 of memory cell 211 can be part of access line 241. For example, in the structure of memory device 200, four different portions of one conductive material (or multiple materials) that form access line 241 can form the gates (e.g., four gates) of transistors Tl and T2 of memory cell 210 and the gates of transistors Tl and T2 of memory cell 211, respectively.

[0034] The gate of each of transistors T1 and T2 in memory cell 214 may be a portion of access line 243. The gate of each of transistors T1 and T2 in memory cell 215 may be a portion of access line 243. For example, in the structure of memory device 200, four different portions of a conductive material (or multiple materials) forming access line 243 may respectively form the gates of transistors T1 and T2 in memory cell 214 (e.g., four gates) and the gates of transistors T1 and T2 in memory cell 215.

[0035] Memory device 200 may include data lines (e.g., bit lines) 221 and 222, which may carry corresponding signals (e.g., bit line signals) BL1 and BL2. During a read operation, memory device 200 may use data line 221 to obtain information read (e.g., sensed) from selected memory cells in memory cell group 2010, and use data line 222 to read information from selected memory cells in memory cell group 2011. During a write operation, memory device 200 may use data line 221 to provide information to be stored in selected memory cells in memory cell group 2010, and use data line 222 to provide information to be stored in selected memory cells in memory cell group 2011.

[0036] The memory device 200 may include a ground connection (e.g., a ground plane) 297 coupled to each of the memory cells 210 to 215. The ground connection 297 may be constructed from a conductive plate (e.g., a layer of conductive material) that can be coupled to a ground terminal of the memory device 200. As an example, the ground connection 297 may be a common plate of the memory device 200 (e.g., formed below the memory cells (e.g., memory cells 210 to 215)). In this example, elements (e.g., transistors T1 and T2) of each of the memory cells (e.g., memory cells 210 to 215) of the memory device 200 may be formed above the common plate (e.g., vertically).

[0037] like Figure 2 As shown, the transistor T1 (e.g., the channel region of transistor T1) of a specific memory cell among memory cells 210 to 215 can be electrically coupled (e.g., directly coupled to) ground connection 297 and electrically coupled (e.g., directly coupled to) the corresponding data line (e.g., data line 221 or 222). Therefore, a circuit path (e.g., a current path) can be formed between the corresponding data line (e.g., data line 221 or 222) and ground connection 297 via the transistor T1 of the selected memory cell during an operation (e.g., a read operation) performed on the selected memory cell.

[0038] Memory device 200 can include read paths (e.g., circuit paths). Information read from a selected memory cell during a read operation can be obtained through a read path coupled to the selected memory cell. In memory cell group 2010, a read path for a particular memory cell (e.g., memory cell 210, 212, or 214) can include a current path (e.g., a read current path) through a channel region of transistor Tl of the particular memory cell, data line 221, and ground connection 297. In memory cell group 2011, a read path for a particular memory cell (e.g., memory cell 211, 213, or 215) can include a current path (e.g., a read current path) through a channel region of transistor Tl of the particular memory cell, data line 222, and ground connection 297. In examples where transistor Tl is a PFET (e.g., a PMOS), current in the read path (e.g., during a read operation) can include hole conduction (e.g., hole conduction through the channel region of transistor Tl in a direction from data line 221 to ground connection 297). Since transistor Tl can be used in a read path to read information from a respective memory cell during a read operation, transistor Tl can be referred to as a read transistor, and the channel region of transistor Tl can be referred to as a read channel region.

[0039] Memory device 200 can include write paths (e.g., circuit paths). Information to be stored in a selected memory cell during a write operation can be provided to the selected memory cell through a write path coupled to the selected memory cell. In memory cell group 2010, a write path for a particular memory cell can include transistor T2 (e.g., can include a write current path through a channel region of transistor T2) of the particular memory cell and data line 221. In memory cell group 2011, a write path for a particular memory cell (e.g., memory cell 211, 213, or 215) can include transistor T2 (e.g., can include a write current path through a channel region of transistor T2) of the particular memory cell and data line 222. In examples where transistor T2 is a NFET (e.g., an NMOS), current in the write path (e.g., during a write operation) can include electron conduction through the channel region of transistor T2 (e.g., electron conduction in a direction from data line 221 to charge storage structure 202). Since transistor T2 can be used in a write path to store information in a respective memory cell during a write operation, transistor T2 can be referred to as a write transistor, and the channel region of transistor Tl can be referred to as a write channel region.

[0040] Each of transistors Tl and T2 can have a threshold voltage (Vt). Transistor Tl has a threshold voltage Vtl. Transistor T2 has a threshold voltage Vt2. The values of threshold voltages Vtl and Vt2 can be different (not equal values). For example, the value of threshold voltage Vt2 can be greater than the value of threshold voltage Vtl. The difference in the values of threshold voltages Vtl and Vt2 allows for the reading (e.g., sensing) of information stored in charge storage structure 202 in transistor Tl on the read path without affecting (e.g., without turning on) transistor T2 on the write path (e.g., the path through transistor T2). This can prevent leakage of charge (e.g., during a read operation) from charge storage structure 202 through transistor T2 on the write path.

[0041] In the structure of memory device 200, transistors Tl and T2 can be formed (e.g., engineered) such that threshold voltage Vtl of transistor Tl can be less than zero volts (e.g., Vtl < 0 V) regardless of the value (e.g., "0" or "1") of information stored in charge storage structure 202 of transistor Tl, and Vtl < Vt2. When information having a value of "0" is stored in charge storage structure 202, charge storage structure 202 can be in state "0". When information having a value of "1" is stored in charge storage structure 202, charge storage structure 202 can be in state "1". Thus, in this structure, the relationship between the values of threshold voltages Vtl and Vt2 can be expressed as follows: Vtl for state "0" < Vtl for state "1" < 0 V, and Vt2 = 0 V (or alternatively Vt2 > 0 V).

[0042] In an alternative structure of memory device 200, transistors Tl and T2 can be formed (e.g., engineered) such that Vtl for state "0" < Vtl for state "1", where Vtl for state "0" < 0 V (or alternatively, Vtl for state "0" = 0 V), Vtl for state "1" > 0 V, and Vtl < Vt2.

[0043] In another alternative structure, transistors Tl and T2 can be formed (e.g., engineered) such that Vtl for state "0" < Vtl for state "1", where Vtl for state "0" = 0 V (or alternatively, Vtl for state "0" > 0 V, and Vtl < Vt2.

[0044] During a read operation of the memory device 200, only one memory cell of the same group of memory cells can be selected at a time to read information from the selected memory cell. For example, the memory cells 210, 212, and 214 of the group of memory cells 2010 can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of the memory cells 210, 212, and 214 in this example). In another example, the memory cells 211, 213, and 215 of the group of memory cells 2011 can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of the memory cells 211, 213, and 215 in this example).

[0045] During a read operation, memory cells of different groups of memory cells (e.g., the groups of memory cells 2010 and 2011) that share the same access line (e.g., the access lines 241, 242, or 243) can be selected in parallel (or alternatively, can be selected sequentially). For example, the memory cells 210 and 211 can be selected in parallel during a read operation to read (e.g., read in parallel) information from the memory cells 210 and 211. The memory cells 212 and 213 can be selected in parallel during a read operation to read (e.g., read in parallel) information from the memory cells 212 and 213. The memory cells 214 and 215 can be selected in parallel during a read operation to read (e.g., read in parallel) information from the memory cells 214 and 215.

[0046] The value of the information read from the selected memory cell of the group of memory cells 2010 during a read operation can be determined based on the value of the current detected (e.g., sensed) from the read path including the data line 221, the transistor Tl of the selected memory cell (e.g., the memory cell 210, 212, or 214), and the ground connection 297 (described above). The value of the information read from the selected memory cell of the group of memory cells 2011 during a read operation can be determined based on the value of the current detected (e.g., sensed) from the read path including the data line 222, the transistor Tl of the selected memory cell (e.g., the memory cell 211, 213, or 215), and the ground connection 297.

[0047] Memory device 200 can include detection circuitry (not shown) that can operate during a read operation to detect (e.g., sense) a current (e.g., current II, not shown) on a read path including data line 221 and to detect a current (e.g., current I2, not shown) on a read path including data line 222. The value of the detected current can be based on the value of the information stored in the selected memory cell. For example, depending on the value of the information stored in the selected memory cell of memory cell group 2010, the value of the detected current on data line 221 (e.g., the value of current II) can be zero or greater than zero. Similarly, depending on the value of the information stored in the selected memory cell of memory cell group 2011, the value of the detected current between data line 222 (e.g., the value of current I2) can be zero or greater than zero. Memory device 200 can include circuitry (not shown) that converts the value of the detected current to the value of the information (e.g., a “0,” a “1,” or a combination of multi-bit values) stored in the selected memory cell.

[0048] During a write operation of memory device 200, only one memory cell of the same memory cell group can be selected at a time to store information in the selected memory cell. For example, memory cells 210, 212, and 214 of memory cell group 2010 can be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of memory cells 210, 212, and 214 in this example). In another example, memory cells 211, 213, and 215 of memory cell group 2011 can be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of memory cells 211, 213, and 215 in this example).

[0049] During a write operation, memory cells of different memory cell groups (e.g., memory cell groups 2010 and 2011) that share the same access line (e.g., access lines 241, 242, or 243) can be selected in parallel. For example, memory cells 210 and 211 can be selected in parallel during a write operation to store (e.g., store in parallel) information in memory cells 210 and 211. Memory cells 212 and 213 can be selected in parallel during a write operation to store (e.g., store in parallel) information in memory cells 212 and 213. Memory cells 214 and 215 can be selected in parallel during a write operation to store (e.g., store in parallel) information in memory cells 214 and 215.

[0050] Information stored in selected memory cells of memory cell group 2010 during a write operation can be provided via a write path including data line 221 and transistor T2 (e.g., memory cells 210, 212, or 214). Information stored in selected memory cells of memory cell group 2011 during a write operation can be provided via a write path including data line 222 and transistor T2 (e.g., memory cells 211, 213, or 215). As described above, the value (e.g., binary value) of information stored in a particular memory cell among memory cells 210 to 215 can be based on the amount of charge in the charge storage structure 202 of that particular memory cell.

[0051] During a write operation, the amount of charge in the charge storage structure 202 of the selected memory cell can be changed (to reflect the value of the information stored in the selected memory cell) by applying a voltage to the write path including the transistor T2 of the specific memory cell and the data line coupled to the specific memory cell (e.g., data line 221 or 222). For example, if the information in the selected memory cell to be stored in memory cells 210, 212, and 214 has a value (e.g., "0"), then a voltage with a value (e.g., 0V) can be applied to data line 221 (e.g., providing 0V to signal BL1). In another example, if the information in the selected memory cell to be stored in memory cells 210, 212, and 214 has another value (e.g., "1"), then a voltage with another value (e.g., a positive voltage) can be applied to data line 221 (e.g., providing a positive voltage to signal BL1). Therefore, information can be stored (e.g., directly stored) in the charge storage structure 202 of the particular memory cell by providing the information to be stored (e.g., in the form of voltage) on the write path (which includes transistor T2) of the particular memory cell.

[0052] Figure 3 The example voltages V1, V2, and V3 used during read operations of the memory device 200, according to some embodiments described herein, are illustrated. Figure 2 Memory device 200. Figure 3 The example assumes that memory cells 210 and 211 are selected memory cells (e.g., target memory cells) used during a read operation to read (e.g., sense) information stored (e.g., previously stored) in memory cells 210 and 211. It is assumed that memory cells 212 to 215 are unselected memory cells. This means that in the process of reading from... Figure 3 In the example, when memory cells 210 and 211 read information, they do not access memory cells 212 to 215, nor do they read the information stored in memory cells 212 to 215.

[0053] In Figure 3 , voltages VI, V2, and V3 can represent different voltages applied to respective access lines 241, 242, and 243 and data lines 221 and 222 during a read operation of memory device 200. As an example, voltages VI, V2, and V3 can have values of -1 V, 0 V, and 0.5 V, respectively. The particular values of voltages used in this description are example values only. Different values can be used. For example, voltage VI can have a range of negative values (e.g., voltage VI can have a value of -3 V to -1 V).

[0054] In Figure 3 the read operation shown in, voltage VI can have a value (voltage value) to turn on transistor Tl of memory cells 210 and 211 (selected memory cells in this example) and turn off (or remain off) transistor T2 of each of memory cells 210 and 211. This allows information to be read from memory cells 210 and 211. Voltage V2 can have a value such that transistors Tl and T2 of each of memory cells 212 to 215 (unselected memory cells in this example) are turned off (e.g., remain off). Voltage V3 can have a value such that a current (e.g., a read current) can be formed on a read path that includes data line 221 and transistor Tl of memory cell 210 and a read path that includes data line 222 and transistor Tl of memory cell 212 (separate read paths). This allows the current on the read paths respectively coupled to memory cells 210 and 211 to be detected. Detection circuitry (not shown) of memory device 200 can be operable to convert the value of the detected current (during reading of information from the selected memory cells) to the value of the information read from the selected memory cells (e.g., a “0,” a “1,” or a combination of multi-bit values). In Figure 3 the example of, the value of the detected current on data lines 221 and 222 can be converted to the value of the information read from memory cells 210 and 211, respectively.

[0055] In Figure 3In the read operation illustrated, the voltages applied to the corresponding access lines 241, 242, and 243 can turn off (or remain off) transistors T1 and T2 of each of memory cells 212 to 215, except for transistor T1 of each of memory cells 210 and 211 (selected memory cells). Depending on the value of the threshold voltage Vt1 of transistor T1 in memory cell 210, transistor T1 in memory cell 210 (selected memory cell) may or may not be turned on. Depending on the value of the threshold voltage Vt1 of transistor T1 in memory cell 211, transistor T1 in memory cell 211 (selected memory cell) may or may not be turned on. For example, if the transistor T1 of each of the memory cells (e.g., 210 to 215) of the memory device 200 is configured (e.g., constructed) such that the threshold voltage of the transistor T1 is less than zero (e.g., Vt1 < -1V) regardless of the value (e.g., state) of the information stored in the corresponding memory cell 210, then in this example, the transistor T1 of memory cell 210 can be turned on and conduct current on data line 221 (through the transistor T1 of memory cell 210). In this example, the transistor T1 of memory cell 211 can also be turned on and conduct current on data line 222 (through the transistor T1 of memory cell 211). The memory device 200 can determine the value of the information stored in memory cells 210 and 211 based on the value of the current on data lines 221 and 222, respectively. As described above, the memory device 200 may include a detection circuitry system to measure the value of the current on data lines 221 and 222 during a read operation.

[0056] Figure 4 The examples shown herein include instance voltages V4, V5, V6, and V7 used during write operations of the memory device 200, according to some embodiments described herein. Figure 2 Memory device 200. Figure 4 The example assumes that memory cells 210 and 211 are selected memory cells (e.g., target memory cells) used to store information in memory cells 210 and 211 during a write operation. It is assumed that memory cells 212 to 215 are unselected memory cells. This means that when information is stored... Figure 4 In the example of memory cells 210 and 211, memory cells 212 to 215 are not accessed, and information is not stored in memory cells 212 to 215.

[0057] exist Figure 4In particular, voltages V4, V5, V6, and V7 can represent different voltages applied to respective access lines 241, 242, and 243 and data lines 221 and 222 during a write operation of memory device 200. As an example, voltages V4 and V5 can have values of 3 V and 0 V, respectively. These values are example values. Different values can be used.

[0058] The values of voltages V6 and V7 can be the same or different depending on the values (e.g., "0" or "1") of information stored in memory cells 210 and 211. For example, if memory cells 210 and 211 are to store information having the same value, the values of voltages V6 and V7 can be the same (e.g., V6 = V7). As an example, if the information to be stored in each memory cell 210 and 211 is "0", then V6 = V7 = 0 V, and if the information to be stored in each memory cell 210 and 211 is "1", then V6 = V7 = 1 V to 3 V.

[0059] In another example, if memory cells 210 and 211 are to store information having different values, the values of voltages V6 and V7 can be different (e.g., V6 ≠ V7). As an example, if "0" is to be stored in memory cell 210 and "1" is to be stored in memory cell 211, then V6 = 0 V and V7 = 1 V to 3 V. As another example, if "1" is to be stored in memory cell 210 and "0" is to be stored in memory cell 211, then V6 = 1 V to 3 V and V7 = 0 V.

[0060] The voltage range of 1 V to 3 V is used here as an example. Different voltage ranges can be used. Also, instead of applying 0 V (e.g., V6 = 0 V or V7 = 0 V) to a particular write data line (e.g., data line 221 or 222) for storing information having a value of "0" to a memory cell (e.g., memory cell 210 or 211) coupled to the particular write data line, a positive voltage (e.g., V6 > 0 V or V7 > 0 V) can be applied to the particular data line.

[0061] In Figure 4During a write operation of the memory device 200, voltage V5 may have a value such that transistors T1 and T2 of each of memory cells 212 to 215 (unselected memory cells in this example) are turned off (e.g., kept off). Voltage V4 may have a value such that transistors T2 of each of memory cells 210 and 211 (selected memory cells in this example) are turned on, forming a write path between the charge storage structure 202 of memory cell 210 and the data line 221, and a write path between the charge storage structure 202 of memory cell 211 and the data line 222. A current (e.g., write current) may be formed between the charge storage structure 202 of memory cell 210 (selected memory cell) and the data line 221. This current may affect (e.g., change) the amount of charge on the charge storage structure 202 of memory cell 210 to reflect the value of the information to be stored in memory cell 210. A current (e.g., another write current) may be formed between the charge storage structure 202 of the memory cell 211 (the selected memory cell) and the data line 222. This current may affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory cell 211 to reflect the value of the information to be stored in the memory cell 211.

[0062] exist Figure 4 In the instance write operation, the value of voltage V6 can cause the charge storage structure 202 of memory cell 210 to discharge or charge, such that the resulting charge on the charge storage structure 202 of memory cell 210 (e.g., the charge remaining after the discharge or charge operation) reflects the value of the information stored in memory cell 210. Similarly, in this example, the value of voltage V7 can cause the charge storage structure 202 of memory cell 211 to discharge or charge, such that the resulting charge on the charge storage structure 202 of memory cell 211 (e.g., the charge remaining after the discharge or charge operation) reflects the value of the information stored in memory cell 211.

[0063] Figure 5 , Figure 6 , Figure 7 , Figure 8A and Figure 8B Demonstrating some embodiments according to the description herein Figure 2 The structure of the memory device 200 is shown in different views relative to the X, Y, and Z directions. For simplicity, from... Figures 5 to 8B And other diagrams in the schemata described herein (e.g., Figures 9 to 29CMost of the elements shown in FIG. 1 are omitted from the cross-sectional view (e.g., the cross-sectional line). Some elements of the memory device 200 (and other memory devices described herein) can be omitted from a particular figure of the drawings in order not to obscure the descriptions of one (or more) element(s) being described in that particular figure. The dimensions (e.g., physical structures) of the elements shown in the figures described herein are not to scale.

[0064] Figure 5 and Figure 6 Different 3-dimensional views (e.g., isometric views) of the memory device 200 relative to the X-Y and Z directions are shown. Figure 7 A side view (e.g., cross-sectional view) of the memory device 200 relative to the X-Z direction is shown. Figure 8A A view (e.g., cross-sectional view) taken along line 8A-8A of FIG. 8A is shown. Figure 7 A top view (e.g., plan view) of a portion of the memory device 200 of FIG. 8B is shown. Figure 8B The structures of the memory cells 214 and 215 and the associated access lines 243 of FIG. 8B are omitted. However, Figure 7 The structures of the memory cells 210', 211', 212', and 213' and the associated data lines 223 and 224 of FIG. 8C are shown. Figure 8B The memory cells 210', 211', 212', and 213' and the associated data lines 223 and 224 are not shown schematically in FIG. 8C. Figure 2 For simplicity, Figure 8B and Figure 2 The structure of the memory cell 210 is shown. The structures of other memory cells (e.g., memory cells 211-215) of the memory device 200 of FIG. 8A can be similar to or the same as the structure of the memory cell 210 shown in FIG. 8A. In

[0065] and Figure 5 The structures of the memory cells 210, 211, 212, and 213 of FIG. 8B can be similar to or the same as the structure of the memory cell 210 shown in FIG. 8A. In Figure 6 and Figure 2 Some portions of the memory device 200 (e.g., gate oxide and cell isolation structures) are omitted in FIG. 8C in order not to obscure the structures of the elements shown in FIG. 8C. Figure 5 and Figure 6 The structures of the memory cells 210, 211, 212, and 213 of FIG. 8B can be similar to or the same as the structure of the memory cell 210 shown in FIG. 8A. In Figure 2 and Figures 5 to 8B The same elements are given the same reference numbers in FIGS. 8A-8C. Some portions of the memory device 200 are omitted in FIGS. 8A-8C in order not to obscure the structures of the elements shown in FIGS. 8A-8C. Figure 5 and Figure 6 The structures of the memory cells 210, 211, 212, and 213 of FIG. 8B can be similar to or the same as the structure of the memory cell 210 shown in FIG. 8A. In Figure 5 and Figure 6 The structures of the memory cells 210, 211, 212, and 213 of FIG. 8B can be similar to or the same as the structure of the memory cell 210 shown in FIG. 8A. In

[0066] The following description refers to FIG. 8A. For simplicity, detailed descriptions of identical elements are not repeated in the description of FIG. 8A. Figures 5 to 8B Figures 5 to 8B As

[0067] As Figure 5As shown, memory device 200 may include a substrate 599, and memory cells 210 (and other memory cells of memory device 200 (not shown)) may be formed above said substrate 599. Transistors T1 and T2 of memory cells 210 may be formed vertically relative to said substrate 599. Substrate 599 may be a semiconductor substrate (e.g., a silicon-based substrate) or other types of substrate. The Z direction (e.g., a vertical direction) is a direction perpendicular to said substrate 599 (e.g., extending outward from said substrate 599). The Z direction is also perpendicular to the X and Y directions (e.g., extending vertically from the X and Y directions). The X and Y directions are perpendicular to each other.

[0068] like Figures 5 to 8A As shown, ground connection 297 may include a structure (e.g., a sheet (e.g., a layer) of conductive material (e.g., a conductive region) located above substrate 599. Examples of materials for ground connection 297 include sheets of metal, conductive doped polysilicon, or other conductive materials. Ground connection 297 may be coupled to a ground terminal (not shown) of memory device 200.

[0069] Figures 5 to 8B A ground connection 297 that contacts (e.g., is directly coupled to) substrate 599 is shown as an example. In an alternative configuration, memory device 200 may include a dielectric (e.g., a dielectric material layer, not shown) between ground connection 297 and substrate 599.

[0070] like Figures 5 to 8B As shown, the memory device 200 may include semiconductor material 596 formed above the ground connection 297. Figure 8B In the middle, grounding connector 297 and substrate 599 (unmarked) are beneath semiconductor material 596 (and from...) Figure 8B (Hidden in the view). Semiconductor material 596 may include a structure of silicon, polysilicon or other semiconductor materials (e.g., a wafer (e.g., a layer)) and may include doped regions (e.g., p-type doped regions) or other conductive materials.

[0071] like Figures 5 to 8B As shown, each of data lines 221, 222, 223, and 224 (associated with signals BL1, BL2, BL3, and BL4, respectively) may have a length in the Y direction, a width in the X direction, and a thickness in the Z direction. Each of data lines 221, 222, 223, and 224 may include a conductive material (or combination of materials) that can be configured as a conductive line (e.g., a conductive region). Example materials for data lines 221 and 222 include metals, conductive doped polysilicon, or other conductive materials.

[0072] Access line 241 (associated with signal WL1) can be constructed from (may include) a combination of portions 541F and 541B (e.g., leading and trailing conductive portions with respect to the Y direction). Each of portions 541F and 541B can include a conductive material (or combination of materials) that can be constructed as a conductive line (e.g., a conductive region) having a length that extends continuously in the X direction. Thus, portions 541F and 541B can be portions of a conductive line that are opposite each other (e.g., opposite each other in the Y direction).

[0073] Each of portions 541F and 541B can include a structure (e.g., a piece (e.g., a layer)) of a conductive material (e.g., a metal, a conductively-doped polysilicon, or other conductive material). Each of portions 541F and 541B can have a length in the X direction (shown in Figure 5 Figure 5 a width in the Z direction (shown in Figure 5 Figure 5 and a thickness in the Y direction (shown in Figure 8A Figure 8A

[0074] Portions 541F and 541B can be electrically coupled to each other. For example, memory device 200 can include a conductive material (e.g., not shown) that can contact (e.g., be electrically coupled to) portions 541F and 541B such that portions 541F and 541B (which are portions of a single access line 241) can be applied by the same signal (e.g., signal WL1) in parallel.

[0075] Figure 8B Access line 242 (associated with signal WL2) is also shown that can include structures (and materials) similar to (or the same as) those of access line 241. For example, access line 242 can be constructed from (may include) a combination of portions 542F and 542B (e.g., leading and trailing conductive portions with respect to the Y direction). Portions 542F and 542B can be electrically coupled to each other (e.g., coupled to each other by a conductive material (e.g., not shown)) such that portions 542F and 542B can be applied by the same signal (e.g., signal WL2) at the same time.

[0076] In alternative structures of memory device 200, one of the two portions of each of the access lines of memory device 200 can be omitted. For example, either portions 541F and 542F or portions 541B and 542B can be omitted such that access line 241 can include only portion 541F or portion 541B, and access line 242 can include only portion 542F or portion 542B. In Figures 5 to 8B In the structures shown in Figures 5 to 8B Figures 5 to 8B in each access line, and can help better control the memory cells of memory device 200 (e.g.,Figure 8B The transistor T1 in each of the memory cells 210, 211, 212, 213, 210', 211', 212', and 213' in the memory is (e.g., Figure 2 (The transistor T1 is shown schematically in the diagram).

[0077] Charge storage structure 202 ( Figures 5 to 8B The charge storage structure 202 may include a charge storage material (or combination of materials), which may include a wafer (e.g., a layer) of a semiconductor material (e.g., polycrystalline silicon), a wafer (e.g., a layer) of a metal, or a wafer of one or more materials capable of trapping charge. The materials of portions (e.g., portions 541F and 541B and portions 542F and 542B) of the charge storage structure 202 and the access lines (e.g., access lines 241 and 242) may be the same or different. Figure 5 As shown, the charge storage structure 202 may include a portion (e.g., a bottom portion) that is closer to the substrate 599 (e.g., extends closer to the substrate 599 in the Z direction) than each of the portions 541F and 541B of the access line 241.

[0078] Figures 5 to 8A The top edge of the charge storage structure 202 is at a specific distance from the edges (e.g., the bottom edge) of each of portions 541F and 541B of the access line 241. Figure 5 Examples of distances shown in the diagram. However, the distance between the top edge of the charge storage structure 202 and the edges (e.g., the bottom edges) of each of portions 541F and 541B can vary.

[0079] Figures 5 to 8A Examples are shown where portions 541F and 541B overlap with charge storage structure 202 (in the Z direction). However, portions 541F and 541B may not overlap with charge storage structure 202.

[0080] The memory device 200 may include material 520 located between the data line 221 and the charge storage structure 202. For example... Figure 5 As shown, material 520 can be electrically coupled to data lines 221 and charge storage structure 202 of memory cell 210. As described above, charge storage structure 202 of memory cell 210 can form a memory element of memory cell 210. Therefore, memory cell 210 can include a memory element (which is charge storage structure 202) located between substrate 599 and material 520 relative to the Z direction, and the memory element is in contact with (e.g., directly coupled to) material 520.

[0081] Material 520 can form a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel region (e.g., a write channel region) between the source and the drain, of transistor T2 of memory cell 210. Thus, as shown in Figure 5 Material 520 can form a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel region (e.g., a write channel region) between the source and the drain, of transistor T2 of memory cell 210. Thus, as shown in

[0082] Material 520 can form a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel region (e.g., a write channel region) between the source and the drain, of transistor T2 of memory cell 210. Thus, as shown in Figure 7 Material 520 can form a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel region (e.g., a write channel region) between the source and the drain, of transistor T2 of memory cell 210. Thus, as shown in Figure 5 Material 520 can form a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel region (e.g., a write channel region) between the source and the drain, of transistor T2 of memory cell 210. Thus, as shown in

[0083] Material 520 and 521 can be the same. For example, each of material 520 and 521 can include a structure (e.g., a piece (e.g., a layer)) of a semiconductor material. In examples where transistor T2 is an NFET (as described above), material 520 and 521 can include an n-type semiconductor material (e.g., n-type silicon).

[0084] In another example, the semiconductor material forming material 520 or material 521 can include a piece of an oxide material. Examples of oxide materials for material 520 and 521 include semiconductive oxide materials, transparent conductive oxide materials, and other oxide materials.

[0085] As an example, each of material 520 and 521 can include at least one of: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O zIndium gallium zinc oxide (In) x Ga y Zn z O a Zirconia indium zinc (Zr) x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc (Al x Sn y In z Zn a O d ), silicon indium zinc (Si) x In y Zn z O a ), Zinc tin oxide (Zn) x Sn y O z ), aluminum oxide zinc tin (Al x Zn y Sn z O a Gallium zinc tin oxide (Ga) x Zn y Sn z O a Zirconia zinc tin (Zr) x Zn y Sn z O a Indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

[0086] The use of the materials listed above in memory device 200 provides improvements and benefits to memory device 200. For example, during a read operation to read information from a selected memory cell (e.g., memory cell 210 or 211), charge from the charge storage structure 202 of the selected memory cell may leak into the transistor T2 of the selected memory cell. Using the materials listed above (e.g., materials 520 or 521) in the channel region of transistor T2 can reduce or prevent this leakage. This improves the accuracy of information read from the selected memory cell and improves the retention of information stored in the memory cells of the memory device (e.g., memory device 200) described herein.

[0087] The materials listed above are examples of materials 520 and 521. However, other materials (e.g., relatively high bandgap materials) different from those listed above can be used.

[0088] In Figure 5 , material 520 and charge storage structure 202 of memory cell 210 can be electrically coupled to one another (e.g., directly coupled) such that material 520 can contact charge storage structure 202 of memory cell 210 without an intervening material (e.g., without a conductive material) between charge storage structure 202 of memory cell 210 and material 520. In another example, material 520 can be electrically coupled to charge storage structure 202 of memory cell 210 such that material 520 does not directly couple to (contact) charge storage structure 202 of memory cell 210, but material 520 is coupled to (e.g., indirectly contacts) charge storage structure 202 of memory cell 210 through an intervening material (e.g., a conductive material, Figure 5 not shown in

[0089] As shown in Figure 5 , memory cell 210 can include portions 510A and 510B that are electrically coupled to one another. Each of portions 510A and 510B can include a structure (e.g., a piece (e.g., a layer)) of a semiconductor material. Example materials for each of portions 510A and 510B include silicon, polysilicon (e.g., undoped or doped polysilicon), germanium, silicon germanium, or other semiconductor materials, as well as semiconductor oxide materials (oxide semiconductors, e.g., SnO or other oxide semiconductors).

[0090] As described above with reference to Figure 2 , transistor T1 of memory cell 210 includes a channel region (e.g., a read channel region). In Figure 5 , the channel region of transistor T1 of memory cell 210 can include (e.g., can be formed from a combination of) portions 510A and 510B. Portions 510A and 510B can be electrically coupled to data line 221. As described above with reference to Figure 2 , memory cell 210 can include a read path. In Figure 5In some examples, portions 510A and 510B (e.g., the read channel region of transistor Tl of memory cell 210) can be part of a read path of memory cell 210, which can carry current (e.g., a read current) during a read operation to read information from memory cell 210. For example, during a read operation to read information from memory cell 210, portions 510A and 510B can conduct current (e.g., a read current) between data line 221 and ground connection 297 (through portions of semiconductor material 596). The direction of the read current can be from data line 221 to ground connection 297 (through portions 510A, portions 510B, and portions of semiconductor material 596). In examples where transistor Tl is a PFET and transistor T2 is a NFET, the material forming portions 510A and 510B can have a different conductivity type than materials 520 or 521. For example, portions 510A and 510B can include regions of p-type semiconductor material (e.g., p-type silicon), and materials 520 and 521 can include regions of n-type semiconductor material (e.g., n-type gallium phosphide (GaP)).

[0091] As shown in Figure 5 , Figure 6 and Figure 7 , memory cell 210 can include dielectric 515A and 515B. Dielectric 515A and 515B can be gate oxide regions that electrically separate charge storage structure 202 from portions 510A and 510B, and separate material 520 from portion 510A. Example materials for dielectric 515A and 515B include silicon dioxide, hafnium oxide (e.g., Hf02), aluminum oxide (e.g., AI2O3), or other dielectric materials. In example structures of memory device 200, dielectric 515A and 515B include a high-k dielectric material (e.g., a dielectric material having a dielectric constant greater than that of silicon dioxide). Using such a high-k dielectric material (rather than silicon dioxide) can improve the performance of memory device 200 (e.g., reduce current leakage, increase the drive capability of transistor Tl, or both).

[0092] As shown in Figure 8B , the memory cells of memory device 200 (e.g., memory cells 210, 211, 212, 213, 210', 211', 212', and 213' in Figure 8B may share (e.g., can be electrically coupled to) semiconductor material 596. For example, the read channel regions of the memory cells of memory device 200 (e.g., portions 510A and 510B of memory cell 210 and portions 511A and 511B of memory cell 211 in Figure 7 may contact (e.g., can be electrically coupled to) semiconductor material 596.

[0093] As shown inFigures 5 to 8B As shown in Figure 8B The conductive region 597 (e.g., a common conductive plate) can include at least one of a material of the semiconductor material 596 (e.g., doped polysilicon) and a material of the ground connection 297 (e.g., metal or doped polysilicon). For example, the conductive region 597 can include the material of the semiconductor material 596, the material of the ground connection 297, or a combination of the semiconductor material 596 and the material of the ground connection 297. Thus, as shown in Figure 8B As shown in Figure 8B The memory cells (e.g., memory cells 210, 211, 212, 213, 210', 211', 212', and 213') of the memory device 200 can share the conductive region 597 (which can include any combination of the semiconductor material 596 and the ground connection 297).

[0094] As shown in Figure 7 The memory device 200 can include a conductive structure 503 between the charge storage structure 202 of the memory cell 210 and the charge storage structure 202 of the memory cell 210. The memory device 200 can include dielectric (e.g., silicon dioxide) 545A and 545B to electrically separate (e.g., isolate) the conductive structure 503 from the charge storage structure 202 of the memory cell 210 and the charge storage structure 202 of the memory cell 210.

[0095] The conductive structure 503 can be a shield (e.g., a capacitive coupling isolation structure) between adjacent charge storage structures of adjacent memory cells. For example, the conductive structure 503 between the memory cells 210 and 211 (adjacent memory cells) can be a shield between the charge storage structures 202 of the memory cells 210 and 211. The conductive structure 503 between the memory cells 212 and 213 (adjacent memory cells) can be a shield between the charge storage structures 202 of the memory cells 212 and 213. The conductive structure 503 between the memory cells 210' and 211' (adjacent memory cells) can be a shield between the charge storage structures 202 of the memory cells 210' and 211'. The conductive structure 503 between the memory cells 212' and 213' (adjacent memory cells) can be a shield between the charge storage structures 202 of the memory cells 212' and 213'.

[0096] Including a conductive structure 503 (e.g., a capacitively coupled isolation structure) between adjacent charge storage structures (e.g., charge storage structure 202) of adjacent memory cells in memory device 200 can reduce capacitive coupling between adjacent charge storage structures of adjacent memory cells. This reduction in capacitive coupling between adjacent charge storage structures can improve the operation of memory device 200 (e.g., improve read signal tolerance).

[0097] The conductive structure 503 may include metal, polysilicon (e.g., conductive doped polysilicon), or other conductive materials (or combinations of conductive materials). The conductive doped polysilicon used in the conductive structure 503 may be n-type conductive polysilicon (e.g., heavily doped n-type polysilicon (N+ polysilicon)) or p-type conductive polysilicon (e.g., heavily doped p-type polysilicon (P+ polysilicon)).

[0098] like Figure 7 As shown, conductive structure 503 can contact (e.g., be electrically coupled to) semiconductor material 596. As described above, the material of semiconductor material 596 (e.g., doped polysilicon), the material of ground connection 297 (e.g., metal or doped polysilicon), or a combination of the materials of semiconductor material 596 and ground connection 297 can be a portion of conductive region 597 of memory device 200. Therefore, conductive structure 503 can contact (e.g., be electrically coupled to) conductive region 597 (which may include any combination of semiconductor material 596 and ground connection 297 as described above).

[0099] like Figure 7 As shown, a portion of 541F may be adjacent to a portion of 510A and a portion of material 520, and may span (e.g., overlap in the X direction) a portion of 510A and a portion of material 520. As described above, portion 510A may form a portion of the read channel region of transistor T1, and material 520 may form a portion of the write channel region of transistor T2. Therefore, as Figure 7 As shown, portions of 541F may respectively span (e.g., overlap) portions of the read and write channels of transistors T1 and T2 (e.g., on one side (e.g., the front side) in the Y direction). Although from Figure 7 The view shown in the image is hidden (but as shown in the image) Figure 5 (As can be seen in the image), but part 541B may be adjacent to part 510A and part of material 520, and may span (e.g., overlap in the X direction) part of part 510A (e.g., on the other side in the Y direction (e.g., the rear side opposite the front side)) and part of material 520. Figure 7As shown, access line 241 can also span (e.g., overlap in the X-direction) a portion of 511A (e.g., a portion of the read channel region of transistor Tl of memory cell 211) and a portion of material 521 (e.g., a portion of the write channel region of transistor T2 of memory cell 211).

[0100] Access line 241 spanning (e.g., overlapping) portion 510A and material 520 allows access line 241 (a single access line) to control (e.g., turn on or off) transistors Tl and T2 of memory cell 210 and both transistors of memory cell 211. Similarly, access line 241 spanning (e.g., overlapping) portion 511A and material 521 allows access line 241 (a single access line) to control (e.g., turn on or off) both transistors Tl and T2 of memory cell 211.

[0101] As shown in Figure 7 Memory device 200 can include a dielectric material (e.g., silicon dioxide) 526 that can form a structure (e.g., a dielectric) to electrically separate (e.g., isolate) portions of two adjacent (in the X-direction) memory cells of memory device 200, as shown in

[0102] As shown in Figure 7 Memory device 200 can include a dielectric portion 531 and a dielectric portion 532, where memory cells 210 and 211 can be located between dielectric portions 531 and 532. Dielectric portion 531 can electrically isolate memory cell 210 from another memory cell (e.g., a left memory cell (not shown)) of memory cell 210. Dielectric portion 532 can electrically isolate memory cell 211 from another memory cell (e.g., a right memory cell (not shown)) of memory cell 211. The area bounded by dielectric portions 531 and 532 and semiconductor material 596 can be a portion of a trench (not labeled) formed during a process of forming memory device 200. Thus, memory cells 210 and 211 can be formed in portions of the trench.

[0103] Some of the portions (e.g., materials) of memory cells 210 and 211 can be formed adjacent to (e.g., on) respective sidewalls (e.g., vertical portions with respect to the Z-direction) of dielectric portions 531 and 532. For example, as shown in Figure 7As shown in the middle, a portion 510A (e.g., a semiconductor material portion) of the memory cell 210 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 531. In another example, as shown in the middle, a portion 511A (e.g., a semiconductor material portion) of the memory cell 211 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 532. Figure 7 As shown in the middle, a portion 510A (e.g., a semiconductor material portion) of the memory cell 210 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 531. In another example, as shown in the middle, a portion 511A (e.g., a semiconductor material portion) of the memory cell 211 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 532.

[0104] As shown in the middle, a portion 510A (e.g., a semiconductor material portion) of the memory cell 210 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 531. In another example, as shown in the middle, a portion 511A (e.g., a semiconductor material portion) of the memory cell 211 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 532. Figure 8A As shown in the middle, a portion 510A (e.g., a semiconductor material portion) of the memory cell 210 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 531. In another example, as shown in the middle, a portion 511A (e.g., a semiconductor material portion) of the memory cell 211 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 532.

[0105] As shown in the middle, a portion 510A (e.g., a semiconductor material portion) of the memory cell 210 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 531. In another example, as shown in the middle, a portion 511A (e.g., a semiconductor material portion) of the memory cell 211 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 532. Figure 8A As shown in the middle, a portion 510A (e.g., a semiconductor material portion) of the memory cell 210 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 531. In another example, as shown in the middle, a portion 511A (e.g., a semiconductor material portion) of the memory cell 211 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 532. Figure 8A As shown in the middle, a portion 510A (e.g., a semiconductor material portion) of the memory cell 210 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 531. In another example, as shown in the middle, a portion 511A (e.g., a semiconductor material portion) of the memory cell 211 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 532. Figure 8A As shown in the middle, a portion 510A (e.g., a semiconductor material portion) of the memory cell 210 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 531. In another example, as shown in the middle, a portion 511A (e.g., a semiconductor material portion) of the memory cell 211 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 532.

[0106] The above description focuses on the structure of the memory cell 210. The memory cell 211 can include elements configured in a similar or same manner as the elements of the memory cell 210 described above. For example, as shown in the middle, the memory cell 211 can include the charge storage structure 202, a channel region (e.g., a write channel region) 521, portions 511A and 511B (e.g., read channel regions), and dielectrics 525A and 525B. A material (or materials) of the dielectrics 525A and 525B can be the same as a material (or materials) of the dielectrics 515A and 515B. Figure 7 As shown in the middle, a portion 510A (e.g., a semiconductor material portion) of the memory cell 210 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 531. In another example, as shown in the middle, a portion 511A (e.g., a semiconductor material portion) of the memory cell 211 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 532.

[0107] As shown in the middle, a portion 510A (e.g., a semiconductor material portion) of the memory cell 210 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 531. In another example, as shown in the middle, a portion 511A (e.g., a semiconductor material portion) of the memory cell 211 can be formed adjacent to (e.g., on) a sidewall (not labeled) of the dielectric portion 532. Figures 2 to 8BThe connections and structure of the memory device 200 described can allow for cross-point operation, as a memory cell (e.g., memory cell 210) of the memory device 200 can be accessed using a single access line (e.g., access line 241) and a single data line (e.g., data line 221) during an operation (e.g., a read or write operation) of the memory device 200. This cross-point operation can be achieved, in part, due to a terminal (e.g., a source terminal) of transistor Tl of each of the memory cells (e.g., memory cells 210-215) being coupled to a ground connection (e.g., ground connection 297). This ground connection allows the voltage level at the terminal (e.g., the source terminal) of transistor Tl of the selected memory cell to remain constant (e.g., remain unswitched at 0 V), thereby allowing for cross-point operation. The cross-point operation and structure of the memory device 200 can provide better memory performance compared to some conventional volatile memory devices (e.g., DRAM devices).

[0108] Figures 9 to 22 Different views of elements during a process of forming the memory device 900 are shown in accordance with some embodiments described herein. Some or all of the process for forming the memory device 900 can be used to form the memory device 200 described above with reference to FIGS. 1-8. Figures 2 to 8B The memory device 200 described.

[0109] Figure 9 The memory device 900 is shown after different material levels (e.g., layers) are formed in respective levels (e.g., layers) of the memory device 900 in the Z-direction over the substrate 999. The different material levels include a dielectric material 930, a semiconductor material 996, and a conductive material 997. The dielectric material 930, the conductive material 996, and the conductive material 997 can be formed in a sequential manner one material after another over the substrate 999. For example, the conductive material 997 can be formed (e.g., deposited) over the substrate 999, the semiconductor material 996 can be formed (e.g., deposited) over the conductive material 997, and the dielectric material 930 can be formed (e.g., deposited) over the semiconductor material 996. Figure 9 The process used in the memory device 900 can include forming (e.g., depositing) the conductive material 997 over the substrate 999, forming (e.g., depositing) the semiconductor material 996 over the conductive material 997, and forming (e.g., depositing) the dielectric material 930 over the semiconductor material 996.

[0110] The substrate 999 can be similar to or the same as the substrate 599 of the memory device 200 Figure 5 The conductive material 997 can include a material (or materials) similar to or the same as the material of the ground connection 297 of the memory device 200 Figures 5 to 8B For example, the conductive material 997 can include a metal, a conductively doped polysilicon, or other conductive material.

[0111] The semiconductor material 996 includes a material (or materials) similar to or the same as the material of the semiconductor material 996 of the memory device 200 Figures 5 to 8BA material (or materials) similar or identical to the material of the semiconductor material 596 of the memory device 600. For example, the semiconductor material 996 can include silicon, polysilicon, or other semiconductor material, and can include doped regions (e.g., p-type doped regions). As described below in subsequent processes of forming the memory device 900, the semiconductor material 996 can be configured to form portions of channel regions (e.g., read channel regions) of respective memory cells of the memory device 900.

[0112] Figure 9 The dielectric material 930 of the memory device 600 can include a nitride material (e.g., silicon nitride (e.g., Si3N4)), an oxide material (e.g., SiO2), or other dielectric material. As described below in subsequent processes of forming the memory device 900, the dielectric material 930 can be processed into dielectric portions to form portions of cell isolation structures to electrically isolate one memory cell of the memory device 900 from another memory cell.

[0113] Figure 10 The memory device 900 is shown after formation of trenches (e.g., openings) 1001 and 1002. Formation of the trenches 1001 and 1002 can include removing (e.g., by patterning) portions of the dielectric material 930 at locations of the trenches 1001 and 1002 Figure 9 ) and leaving portions (e.g., dielectric portions) 1031, 1032, and 1033 (which are remaining portions of the dielectric material 930) as shown in Figure 10 .

[0114] Each of the trenches 1001 and 1002 can have a length in the Y-direction, a width (shorter than the length) in the X-direction, and a bottom (not labeled) resting on (e.g., bounded by) a respective portion of the semiconductor material 996. Each of the trenches 1001 and 1002 can include opposing sidewalls (e.g., vertical sidewalls) formed by the respective portions 1031, 1032, and 1033. For example, the trench 1001 can include sidewall 1011 (formed by the portion 1031) and sidewall 1012 (formed by the portion 1032). The trench 1002 can include sidewall 1013 (formed by the portion 1032) and sidewall 1014 (formed by the portion 1033).

[0115] Figure 11 The memory device 900 is shown after formation (e.g., deposition) of the material 1110' and the material 1110" in the trenches 1001 and 1002, respectively. As Figure 11As shown in the middle, material 1110' can be formed on the sidewalls 1011 and 1012 and the bottom of trench 1001 (e.g., on a portion of semiconductor material 996). Material 1110" can be formed on the sidewalls 1013 and 1014 and the bottom of trench 1002 (e.g., on another portion of semiconductor material 996).

[0116] Materials 1110' and 1110" can be the same material. Examples of material 1110' and material 1110" include semiconductor materials. Materials 1110' and 1110" can have the same properties as the materials of portions 510A, 510B, 511A, and 511B (e.g., read channel regions) of transistors Tl of respective memory cells of memory device 200 formed Figures 5 to 8B as described below in subsequent processes (e.g., processes 1200 and 1300) to form memory device 900. As described below in processes 1200 and 1300, material 1110' and material 1110" can be configured to form channel regions (e.g., read channel regions) of transistors (e.g., transistors Tl) of respective memory cells of memory device 900. Thus, each of material 1110' and 1110" can conduct current (e.g., conduct holes) during operations (e.g., read operations) of memory device 900. Figure 19

[0117] Processes to form material 1110' and 1110" can include a doping process. This doping process can include introducing dopants into material 1110' and 1110" to allow transistors (e.g., transistors Tl) of respective memory cells of memory device 900 to include a particular structure. For example, Figure 9 The doping process used in process 1100 can include introducing dopants with different dopant concentrations for different portions of material 1110' and 1110" (e.g., using a laser anneal process) such that a transistor including material 1110' (or material 1110") can have a PFET structure. In this PFET structure, portions of material 1110' (or material 1110") can form channel regions (e.g., read channel regions) to conduct current (e.g., holes) during operations (e.g., read operations) of memory device 900.

[0118] Figure 12 Memory device 900 is shown after dielectric materials (e.g., oxide materials) 1215' and 1215" are formed (e.g., deposited) on material 1110' and 1110", respectively. Dielectric materials 1215' and 1215" can be deposited such that dielectric materials 1215' and 1215" can conform to material 1110' and 1110", respectively. Materials 1215' and 1215" can have the same properties as the materials of portions 510A, 510B, 511A, and 511B (e.g., read channel regions) of transistors Tl of respective memory cells of memory device 200 formed Figures 5 to 8B ​The dielectric materials (e.g., oxide materials) of the memory device 200 515A, 515B, 525A and 525B have the same properties.

[0119] Figure 13 A memory device 900 is shown after materials (e.g., charge storage materials) 1302', 1302”, 1302”', and 1302”” are formed on the respective sidewalls of materials 1215' and 1215”. Materials 1302', 1302”, 1302”', and 1302”” are electrically isolated from each other. This is explained below in the subsequent processes of forming the memory device 900 (…). Figure 19 As described in [the original text], each of materials 1302', 1302”, 1302”', and 1302”” can be constructed to form a charge storage structure for a corresponding memory cell of memory device 900. Materials 1302', 1302”, 1302”', and 1302”” may be incorporated into memory device 200 (…). Figures 5 to 8B The material of the charge storage structure 202 of the memory cell (e.g., memory cell 210 or 211) is similar to or the same as that of the material (e.g., polycrystalline silicon).

[0120] Figure 14 The dielectric materials 1445', 1445”, 1445”' and 1445”” are formed on materials 1302', 1302”, and 1302”'.

[0121] The memory device 900 is located on the corresponding sidewall of 1302”'. The dielectric materials 1445’, 1445”, 1445”' and 1445”” may include oxide materials (e.g., silicon dioxide). The dielectric materials 1445’, 1445”, 1445”' and 1445”” may have the same characteristics as those formed by... Figures 5 to 8B The dielectric materials (e.g., oxide materials) of the memory device 200 545A and 545B have the same properties.

[0122] like Figure 14 As shown, dielectric materials 1445', 1445”, 1445”', and 1445”” can be formed such that portions of the semiconductor material 996 at trenches 1001 and 1002 are not covered by dielectric materials 1445', 1445”, 1445”', and 1445”” (e.g., excluding the dielectric materials). Therefore, after forming dielectric materials 1445', 1445”, 1445”', and 1445””, portions of the semiconductor material 996 can be exposed at trenches 1001 and 1002.

[0123] Figure 15The memory device 900 is shown after the conductive materials 1503' and 1503" are formed (e.g., fill) in the open spaces in the trenches 1001 and 1002, respectively. Forming the conductive materials 1503' and 1503" can include depositing the conductive materials 1503' and 1503" in the trenches 1001 and 1002, respectively, such that the conductive materials 1503' and 1503" can contact (e.g., can be electrically coupled to) the respective portions of the semiconductor material 596 that are exposed to the open spaces in the trenches 1001 and 1002, respectively, and the conductive materials 1503' and 1503" can be formed to have the same properties as the materials of the conductive structures 503 of the memory device 200. Figure 14 The conductive materials 1503' and 1503" can be formed to have the same properties as the materials of the conductive structures 503 of the memory device 200.

[0124] The conductive materials 1503' and 1503" can be formed to have the same properties as the materials of the conductive structures 503 of the memory device 200. Figures 5 to 8B The conductive materials 1503' and 1503" can include a metal, polysilicon (e.g., conductively doped polysilicon), or other conductive material (or combination of conductive materials). As described below in subsequent processes of forming the memory device 900, the conductive materials 1503' and 1503" can form portions of conductive structures (e.g., capacitive coupling isolation structures) that can electrically isolate charge storage structures of adjacent memory cells of the memory device 900.

[0125] Figure 16 The memory device 900 is shown after the materials 1602', 1602", 1602"' and 1602"", the dielectric materials 1645', 1645", 1645"' and 1645"", and the conductive materials 1603' and 1603" are formed. Forming the materials 1602', 1602", 1602"' and 1602" can include removing (e.g., by using an etching process) portions (e.g., top portions) of each of the dielectric materials 1302', 1302", 1302"' and 1302"" ( Figure 15 ), such that the remaining portions of the materials 1302', 1302", 1302"' and 1302"" are the materials 1602', 1602", 1602"' and 1602"" ( Figure 16 ), respectively. Forming the dielectric materials 1645', 1645", 1645"' and 1645"" can include removing (e.g., by using an etching process) portions (e.g., top portions) of each of the dielectric materials 1445', 1445", 1445"' and 1445"" ( Figure 15 ), such that the remaining portions of the dielectric materials 1445', 1445", 1445"' and 1445"" are the dielectric materials 1645', 1645", 1645"' and 1645"" ( Figure 16 ), respectively. Forming the conductive materials 1603' and 1603" can include removing (e.g., by using an etching process) the conductive materials 1503' and 1503" ( Figure 15of conductive material 1503' and 1503" are conductive material 1603' and 1603", respectively Figure 16

[0126] In Figure 16 , portions (e.g., top portions) of material 1302', 1302", 1302"', 1302"" can be removed in a single process (e.g., a single step) or in separate processes (e.g., multiple steps), portions (e.g., top portions) of dielectric material 1445', 1445", 1445"', and 1445"" and conductive material 1503' and 1503". For example, portions of material 1302', 1302", 1302"', 1302"" can be removed in a process (or processes) different from the process(es) that remove portions of dielectric material 1445', 1445", 1445"', and 1445"" and / or in a process different from the process that removes conductive material 1503' and 1503". Figure 15 Figure 15 Figure 15

[0127] Figure 17 The memory device 900 after formation of material 1720', 1721', 1720", and 1721" is shown. Formation of material 1720', 1721', 1720", and 1721" can include depositing an initial material (or materials) on material 1602', 1602", 1602"', and 1602"", dielectric material 1645', 1645", 1645"', and 1645"" and conductive material 1603' and 1603". Then, Figure 17 The process used in Figure 17 The material 1720', 1721', 1720", and 1721" are electrically separated from each other as shown in

[0128] The material 1720', 1721', 1720", and 1721" can include materials similar to or the same as the materials (e.g., write channel regions) 520 or 521 Figures 5 to 8B of transistor T2 of memory device 200 Figure 5 of transistor T2 of memory device 200 Figure 19 ​​​​As described in [the original text], each of materials 1720', 1721', 1720”, and 1721” can form the channel region (e.g., write channel region) of the transistor (e.g., transistor T2) of the corresponding memory cell of the memory device 900. Therefore, each of materials 1720', 1721', 1720”, and 1721” can conduct current (e.g., conduct electrons) during operation (e.g., write operation) of the memory device 900.

[0129] Figure 18 The dielectric materials 1826' and 1826" are formed at positions 1701 and 1702. Figure 17 The memory device 900 following the location (e.g., filled in the location). Dielectric materials 1826' and 1826" may include those with... Figure 7 The dielectric material 526 is the same material (e.g., silicon dioxide). As described below in the subsequent process of forming the memory device 900, the dielectric materials 1826' and 1826" may form part of an isolation structure that electrically isolates portions (e.g., write channel regions) of two adjacent (in the X direction) memory cells of the memory device 900.

[0130] Figure 19 The memory device 900 is shown after trenches 1911, 1912, and 1913 (in the X direction) are formed across the material of the memory device 900. Each of trenches 1911, 1912, and 1913 may have a length in the X direction, a width in the Y direction (shorter than the length), and a bottom (not labeled) resting on a corresponding portion of semiconductor material 996 (e.g., defined by said corresponding portion). Alternatively, each of trenches 1911, 1912, and 1913 may have a bottom (not labeled) resting on a corresponding portion of conductive material 997 (rather than semiconductor material 996) (e.g., defined by said corresponding portion). Forming trenches 1911, 1912, and 1913 may include removing (e.g., by cutting (e.g., etching)) a ​​portion of the material of the memory device 900 at the locations of trenches 1911, 1912, and 1913, leaving Figure 19 A portion (e.g., a slice) of the structure of the memory device 900 shown in the figure.

[0131] After removal (e.g., cutting) of portions of the memory device 900 at the locations of the trenches 1911, 1912, and 1913, the remaining portions can form portions of shields (e.g., capacitive coupling isolation structures) between memory cells and adjacent charge storage structures of adjacent memory cells of the memory device 900. For example, the memory device 900 can include memory cells 210', 211', 210", and 211" in one row along the X direction and cells 212', 213', 212", and 213" in another row along the X direction. The memory cells 210' and 211' can correspond to the memory cells 210 and 211, respectively, of the memory device 200 Figure 2 and Figure 7 ) of FIG. 1A. Figure 19 The memory cells 212' and 213' in Figure 2 may correspond to the memory cells 212 and 213, respectively, of the memory device 200

[0132] For simplicity, only some of the similar elements (portions) of the memory device 900 in Figure 19 are labeled. For example, the memory device 900 can include dielectric portions (e.g., cell isolation structures) 1931, 1932, 1933, 1934, 1935, and 1936 and a dielectric material 1926. The dielectric portions 1931 and 1932 can correspond to the dielectric portions 531 and 532, respectively, of the memory device 200 of FIG. 1A. Figure 7

[0133] As shown in Figure 19 , the memory cell 210' can include portions 1910A and 1910B (which can be portions of a read channel region of the memory cell 210'), dielectrics 1915A and 1915B, a material (e.g., a write channel region) 1920, and a charge storage structure 1902 (directly below the material 1920). The memory cell 211' can include portions 1911A and 1911B (which can be portions of a read channel region of the memory cell 211'), dielectrics 1925A and 1925B, a material (e.g., a write channel region) 1921, and a charge storage structure 1902 (directly below the material 1921).

[0134] The memory device 900 can include conductive structures 1903 that are portions of respective remaining portions of the conductive materials 1603' and 1603" ( Figure 19 ) after formation of the trenches 1911, 1912, and 1913( Figure 18 ). Each of the conductive structures 1903 can correspond to the conductive structure 503 ( Figure 7 ) of the memory device 200 of FIG. 1A. In Figure 19 ​In particular embodiments, each of the conductive structures 1903 can be a shield (e.g., a capacitive coupling isolation structure) between adjacent charge storage structures 1902 of adjacent memory cells of the memory device 900. For example, the conductive structure 1903 between the memory cells 210' and 211' can be a shield (e.g., a capacitive coupling isolation structure) between the memory cells 210' and 211'.

[0135] As described above with reference to Figures 9 to 19 As described above with reference to Figures 29A to 29C Examples of multi-stack memory devices are described below.

[0136] Figure 20 The memory device 900 is shown after formation of the dielectric 2018F, 2018B, 2018F', and 2018B' (e.g., oxide regions). One material (or multiple materials) of the dielectric 2018F, 2018B, 2018F', and 2018B' can be the same as (or alternatively, different from) one material (or multiple materials) of the dielectric 515A, 515B, 525A, and 525B. Example materials of the dielectric 2018F, 2018B, 2018F', and 2018B' can include silicon dioxide, hafnium oxide (e.g., Hf02), aluminum oxide (e.g., AI2O3), or other dielectric materials.

[0137] Figure 21 The memory device 900 is shown after formation of the conductive lines (e.g., conductive regions) 2141F, 2141B, 2142F, and 2142B. Each of the conductive lines 2141F, 2141B, 2142F, and 2142B can include a metal, a conductively-doped polysilicon, or other conductive material. As described above with reference to Figure 21 As shown in particular embodiments, the conductive lines 2141F, 2141B, 2142F, and 2142B are electrically isolated from other elements of the memory device 900 by the dielectrics 2018F, 2018B, 2018F', and 2018B', respectively.

[0138] Conductive lines 2141F and 2141B can form portions of access lines (e.g., word lines) 2141 to control read and write transistors (e.g., transistors T1 and T2, respectively) of respective memory cells 210', 211', 210", and 211" of memory device 900. For example, conductive lines 2141F and 2141B can form front and back conductive portions, respectively, of access lines 2141. Conductive lines 2142F and 2142B can form portions of access lines (e.g., word lines) 2142 to access memory cells 212', 213', 212", and 213" of memory device 900. For example, conductive lines 2142F and 2142B can form front and back conductive portions, respectively, of access lines 2142. Access lines 2141 and 2412 can correspond to access lines 241 and 242, respectively, of memory device 200 (e.g., Figure 2 and Figure 8B ).

[0139] The process of forming memory device 900 in Figure 21 may include forming conductive connections 2141' that electrically couple conductive lines 2141F and 2141B to each other (which can include a conductive material, e.g., a metal). This allows conductive lines 2141F and 2141B to form portions of or a single access line (e.g., access line 2141). Similarly, the process of forming memory device 900 can include forming conductive connections 2142' that electrically couple conductive lines 2142F and 2142B to each other. This allows conductive lines 2142F and 2142B to form portions of or a single access line (e.g., access line 2142).

[0140] Figure 22 Memory device 900 is shown after formation of data lines 2221, 2222, 2223, and 2224. Each of data lines 2221, 2222, 2223, and 2224 can have a length in the Y direction, a width in the X direction, and a thickness in the Z direction. Data lines 2221, 2222, 2223, and 2224 can correspond to data lines 221, 222, 223, and 224, respectively, of memory device 200 (e.g., Figure 8B ).

[0141] In Figure 22In particular embodiments, data lines 2221, 2222, 2223, and 2224 can be electrically coupled to (e.g., contact) a respective portion of each of the memory cells in the Y direction of memory device 900. For example, data line 2221 can be electrically coupled to portion 1910A (a portion of the read channel region of memory cell 210') and material 1920 (a portion of the write channel region of memory cell 210'). Data line 2221 can also be electrically coupled to the read channel region (not labeled) of memory cell 212' and the write channel region (not labeled) of memory cell 212'.

[0142] Reference is made to Figures 9 to 22 The description of forming memory device 900 can include other processes to form a complete memory device. Such processes are omitted from the above description to avoid obscuring the subject matter described herein.

[0143] The processes of forming memory device 900 as described above can have a relatively reduced number of masks (e.g., a reduced number of critical masks) compared to some conventional processes. For example, by forming trenches 1001 and 1002 in the process associated with Figure 10 and forming trenches 1911, 1912, and 1913 in the process associated with Figure 19 of memory device 900 can be reduced. Reducing the number of masks can simplify the processes of forming memory device 900, reduce the cost thereof, or both.

[0144] Figures 23A to 28 Portions of structures of memory devices 2300A, 2400A, 2500A, and 2700A, which can be variants of memory device 200, in accordance with some embodiments described herein, are shown. Like or identical elements among memory devices 200, 2300A, 2400A, 2500A, and 2700A are given the same labels for simplicity.

[0145] Figure 23A A top-down view of memory device 2300A, which can be a variant of memory device 200 in Figure 8B is shown. As shown in Figure 23A Memory device 2300A can include conductive structures 2303 between respective charge storage structures 202, as shown in Figures 5 to 5 Memory device 2300A can include conductive structures 2303 between respective charge storage structures 202, as shown in Figure 23A Each of conductive structures 2303 in can be a shield (e.g., a capacitance coupling isolation structure) between adjacent charge storage structures of adjacent memory cells of memory device 2300A to reduce capacitance coupling between charge storage structures 202 of adjacent memory cells of memory device 2300A.

[0146] Similar to conductive structure 503 ( Figure 7 and Figure 8B ), Figure 23A Each of the contactable (e.g., electrically coupled to) conductive regions 597 in the conductive structure 2303. (See above reference.) Figures 5 to 8B As described, the conductive region 597 may include any combination of semiconductor material 596 and grounding connection 297.

[0147] Memory device 200 ( Figure 8B ) and memory device 2300A ( Figure 23A The differences between them include the conductive structure 503 ( Figure 8B ) and conductive structure 2303 ( Figure 23A The structural differences. For example... Figure 23A As shown, each of the conductive structures 2303 in the memory device 2300A may extend continuously in the Y direction (e.g., may have a length) between the charge storage structures 202 of corresponding pairs of memory cells located in the Y direction (e.g., in the same column). For example, the conductive structure 2303 (between memory cells 210 and 211) may extend continuously in the Y direction between the charge storage structures 202 of memory cells 210 and 211 and between the charge storage structures 202 of memory cells 212 and 213. In another example, the conductive structure 2303 (between memory cells 210' and 211') may extend continuously in the Y direction between the charge storage structures 202 of memory cells 210' and 211' and between the charge storage structures 202 of memory cells 212' and 213'. The conductive structure 2303 can provide an improvement to the memory device 2300A, which may be similar to the connection provided by the conductive structure 503 as referenced above. Figures 5 to 8B Improvements to the memory device 200 as described.

[0148] Figure 23B Demonstrates what can be a memory device 2300A Figure 23A A top view of a variant of the memory device 2300B, as shown in the top view. Figure 23BAs shown, memory device 2300B may include a conductive structure 2303' that may extend continuously in the X direction (e.g., may have a length). The conductive structure 2303' may contact (e.g., may be electrically coupled to) the conductive structure 2303. The conductive structure 2303' may be located between the charge storage structures 202 of memory cells 212, 213, 212', and 213' and the charge storage structures 202 of memory cells 210, 211, 210', and 211'. The conductive structure 2303' may serve as a shield (e.g., a capacitively coupled isolation structure) between the charge storage structures 202 of at least one of memory cells 212, 213, 212', and 213' and the charge storage structures 202 of at least one of memory cells 210, 211, 210', and 211'.

[0149] Figure 23B The display can be seen from Figure 23B The top view shows an example of conductive structure 2303' (e.g., the entire top portion of conductive structure 2303') (e.g., a portion of the top portion of conductive structure 2303' is not hidden below portions 541B and 542F of access lines 241 and 242, respectively). In an alternative structure of memory device 2300B, at least a portion of conductive structure 2303' (e.g., a portion or the entire conductive structure 2303') may be formed below at least one of portions 541B and 542F (e.g., in the Z direction) (e.g., directly formed below at least one of portions 541B and 542F in the Z direction). Therefore, in an alternative structure of memory device 2300B, at least a portion of conductive structure 2303' (e.g., a portion or the entire top portion of conductive structure 2303') may be hidden below at least one of portions 541B and 542F.

[0150] Figure 24A The demonstration can be a memory device 200 Figure 8B A top view of a variant of the memory device 2400A, as shown in the diagram. Figure 24A As shown, memory device 2400A may include conductive structure 503 that can be connected to memory device 200. Figure 8B The same conductive structure 503.

[0151] Memory device 200 ( Figure 8B ) and memory device 2400A ( Figure 24A The differences between them include conductive region 597 ( Figure 8B The structure of ) and the conductive regions 597' and 597" Figure 24A The differences between the structures of ) are as shown in the reference above. Figures 5 to 8B As described, the conductive region 597 may be a memory cell of the memory device 200 (e.g.,Figure 8B The memory cells 210, 211, 212, 213, 210', 211', 212', and 213' in the memory array 2400A share (e.g., can be electrically coupled to) a common conductive plate. However, Figure 8B The conductive region 597 can be divided (e.g., as shown in Figure 24A The conductive region 597 can be divided (e.g., as shown in Figure 8B The conductive region 597 can be divided (e.g., as shown in Figure 24A The conductive region 597 can be divided (e.g., as shown in

[0152] Figure 24A A portion of the substrate 599 at a spacing (e.g., gap) between the conductive regions 597' and 597" that indicates that the conductive regions 597' and 597" are separate from each other is shown. As shown in Figure 24A The spacing between the conductive regions 597' and 597" can have a length in the X-direction (e.g., a direction parallel to a length of each of the data lines 221, 222, 223, and 224) such that the conductive regions 597' and 597" can be positioned side-by-side with respect to the Y-direction, as shown in

[0153] The conductive region 597' can include the semiconductor material 596' and the ground connection 297' (under the semiconductor material 596'). The conductive region 597" can include the semiconductor material 596" and the ground connection 297" (under the semiconductor material 596"). The conductive regions 597' and 597" can be coupled to a ground connection (e.g., a ground plate, not shown) of the memory device 2400A. The semiconductor materials 596' and 596" can be separate portions of the semiconductor material 596. Figure 8B The ground connections 297' and 297" in the memory device 2400A can be separate portions of the ground connection 297. Figure 24A The ground connections 297' and 297" in the memory device 2400A can be separate portions of the ground connection 297. Figure 8B The ground connections 297' and 297" in the memory device 2400A can be separate portions of the ground connection 297.

[0154] Each of the memory cells (memory cells 210, 211, 212, 213, 210', 211', 212', and 213') of the memory device 2400A can include transistors T1 and T2 (e.g., similar to the transistors T1 and T2 shown in Figure 2 The memory cells (memory cells 210, 211, 212, 213, 210', 211', 212', and 213') of the memory device 2400A can be electrically coupled to the conductive region 597.Figure 24A In the example, the conductive region 597' can be coupled (e.g., directly coupled) to the transistor Tl of the memory cells 210, 211, 210', and 211'. The conductive region 597" (which is separate from the conductive region 597') can be coupled (e.g., directly coupled) to the transistor Tl of the memory cells 212, 213, 212', and 213'.

[0155] In Figure 24A In the example, each of the conductive structures 503 located above the conductive region 597' can contact (e.g., can be electrically coupled to) the conductive region 597'. Each of the conductive structures 503 located above the conductive region 597" can contact (e.g., can be electrically coupled to) the conductive region 597".

[0156] Figure 24A A memory device 2400A is shown that includes two conductive regions 597' and 597" (e.g., two conductive plates (e.g., sub-plates)) as an example. However, the memory device 2400A can include more than two conductive regions (e.g., more than two sub-plates) similar to the conductive regions 597' and 597".

[0157] The conductive structures 503 of the memory device 2400A can provide improvements to the memory device 2400A that can be similar to improvements provided by the conductive structures 503 to the memory device 200 as described above with reference to Figures 5 to 8B .

[0158] Figure 24B A top view of a memory device 2400B is shown that can be a variation of the top view in Figure 24A the memory device 2400A. As Figure 24B shown in the example, the memory device 2400B can include a conductive structure 2403 that can extend continuously (e.g., can have a length) in the X-direction. The conductive structure 2403 can not contact the conductive regions 597' and 597". Alternatively, the conductive structure 2403 can contact at least one of the conductive regions 597' and 597". As Figure 24B shown in the example, the conductive structure 2403 can be located between the charge storage structure 202 of the memory cells 212, 213, 212', and 213' and the charge storage structure 202 of the memory cells 210, 211, 210', and 211'. The conductive structure 2403 can be a shield (e.g., a capacitance coupling isolation structure) between the charge storage structure 202 of at least one of the memory cells 212, 213, 212', and 213' and the charge storage structure 202 of at least one of the memory cells 210, 211, 210', and 211'.

[0159] Figure 24B A top view of a memory device 2400C is shown that can be a variation of the top view in Figure 24BAn example of a top-down view of the conductive structure 2403 (e.g., an entire top portion of the conductive structure 2403) (e.g., portions of the top portion of the conductive structure 2403' that are not respectively hidden under portions 541B and 542F of access lines 241 and 242) is seen in FIG. 24B. In an alternative structure of the memory device 2400B, at least a portion of the conductive structure 2403 (e.g., a portion of the conductive structure 2403 or the entire conductive structure 2403) can be formed under (e.g., in the Z-direction) at least one of portions 541B and 542F (e.g., directly under at least one of portions 541B and 542F in the Z-direction). Thus, in the alternative structure of the memory device 2400B, at least a portion of the conductive structure 2403 (e.g., a portion of the top portion of the conductive structure 2403 or the entire top portion of the conductive structure 2403) can be hidden under at least one of portions 541B and 542F.

[0160] As shown in Figure 24B , the memory device 2400B can include a conductive segment (e.g., a conductive region) 2405 that can contact (can be electrically coupled to) the conductive structure 2403. The conductive segment 2405 can be coupled to a ground connection (e.g., a ground plate, not shown) of the memory device 2400B.

[0161] Figure 25A A top-down view of the memory device 2500A that can be a variation of the top-down view of the memory device 200 of Figure 8B and can include a combination of elements from the memory device 2300A Figure 23A and the memory device 2400A Figure 25A is shown. As shown in Figure 23A , the memory device 2500A can include a conductive structure 2303 that can be similar to (or the same as) the conductive structure 2303 of Figure 24A . The memory device 2500A can include a conductive segment (e.g., a conductive region) 2503 that can contact (can be electrically coupled to) the conductive structure 2303. The conductive segment 2503 can be coupled to a ground connection (e.g., a ground plate, not shown) of the memory device 2500A. The memory device 2500A can also include conductive regions 597' and 597" that can be respectively similar to (or the same as) the conductive regions 597' and 597" of Figure 25A . Figure 26 A line 26-26 in Figure 25B shows the location of a portion of the memory device 2500A shown in

[0162] Figure 25A A top-down view of the memory device 2500B that can be a variation of the top-down view of the memory device 2500A of Figure 25B is shown. As shown in Figure 25BAs shown, the memory device 2500B may include a conductive structure 2303" that can extend continuously in the X direction (e.g., may have a length). The conductive structure 2303" may be contactable (e.g., electrically coupled to) the conductive structure 2303. The conductive structure 2303" may be located between the charge storage structures 202 of memory cells 212, 213, 212', and 213' and the charge storage structures 202 of memory cells 210, 211, 210', and 211'. The conductive structure 2303" may serve as a shield (e.g., a capacitively coupled isolation structure) between the charge storage structures 202 of at least one of memory cells 212, 213, 212', and 213' and the charge storage structures 202 of at least one of memory cells 210, 211, 210', and 211'.

[0163] Figure 23B The display can be seen from Figure 26 The top view shows an example of conductive structure 2303" (e.g., the entire top portion of conductive structure 2303"). (e.g., a portion of the top portion of conductive structure 2303" is not hidden below portions 541B and 542F of access lines 241 and 242, respectively.) In an alternative structure of memory device 2500B, at least a portion of conductive structure 2303" (e.g., a portion or the entire conductive structure 2303") may be formed below at least one of portions 541B and 542F (e.g., in the Z direction) (e.g., directly formed below at least one of portions 541B and 542F in the Z direction). Therefore, in an alternative structure of memory device 2500B, at least a portion of conductive structure 2303" (e.g., a portion or the entire top portion of conductive structure 2303") may be hidden below at least one of portions 541B and 542F.

[0164] Figure 25A Exhibition along Figure 26 A partial side view (e.g., cross-sectional view) of the memory device 2500A with lines 26-26. Figure 7 Some of the elements (e.g., charge storage structure 202 and substrate 599) in the memory device 2500A can be connected to Figure 26 Some of the elements in the memory device 200 are similar (or identical).

[0165] like Figure 25AAs shown in Figure 25A , the conductive structures 2303 (located between memory cells 210 and 211 and between memory cells 212 and 213) can be electrically separated from the semiconductor material 596' and 596" by a dielectric (e.g., dielectric 2545). Similarly, the conductive structures 2303 (located between memory cells 210' and 211' and between memory cells 212' and 213') can be electrically separated from the semiconductor material 596' and 596" by a dielectric (e.g., a dielectric similar to dielectric 2545). Figure 7

[0166] In Figure 25A and Figure 7 , the conductive structures 2303 are electrically separated from the conductive regions 597' and 597" by a dielectric (e.g., dielectric 2545). However, as described above, the conductive structures 2303 can contact conductive regions (e.g., conductive segments 2503) that can be coupled to a ground plate of the memory device 2500A. Figure 25A Figure 26 and Figures 5 to 8B , the conductive structures 2303 are electrically separated from the conductive regions 597' and 597" by a dielectric (e.g., dielectric 2545). However, as described above, the conductive structures 2303 can contact conductive regions (e.g., conductive segments 2503) that can be coupled to a ground plate of the memory device 2500A.

[0167] The conductive structures 2303 of the memory device 2500A can provide improvements to the memory device 2500A that can be similar to the improvements provided by the conductive structures 503 to the memory device 200 as described above with reference to Figure 27A .

[0168] Figure 25A A top-down view of a memory device 2700A that can be a variation of the top-down view in Figure 27A of the memory device 2500A is shown. As shown in Figure 25A , the memory device 2700A can include conductive structures 2303 and conductive segments (e.g., conductive regions) 2503 that can be similar to (or the same as) the conductive structures 2303 and conductive segments 2503, respectively, of Figure 27A . The memory device 2700A Figure 27A may include conductive regions (e.g., sub-plates) 597"' and 597"". Figure 8B ​​The conductive region 597"' can include the semiconductor material 596' and the ground connection 297'. The conductive region 597"" can include the semiconductor material 596" and the ground connection 297". The semiconductor materials 596' and 596" can be Figure 27A separate portions of the semiconductor material 596. Figure 8B The ground connections 297' and 297" in the memory device 2500A can be Figure 27A separate portions of the ground connection 297. The conductive regions 597"' and 597"" can be coupled to a ground connection (e.g., a ground plate, not shown) of the memory device 2700A. ​ A portion of the substrate 599 is shown at a separation (e.g., gap) between the conductive regions 597"' and 597"" that indicates that the conductive regions 597"' and 597"" are separate from each other.

[0169] Differences between the memory device 2500A Figure 25A and the memory device 2700A Figure 27A include Figure 27A differences between structures (e.g., orientations) of the conductive regions 597"' and 597"" in the memory device 2500A. As described above with reference to Figure 24A and Figure 25A , Figure 25A the conductive regions 597' and 597" in the memory device 2500A can be separated from each other by a separation (e.g., gap) having a length in the X-direction (e.g., a direction parallel to a length of each of the data lines 221, 222, 223, and 224) such that the conductive regions 597' and 597" can be positioned side-by-side with respect to the Y-direction. In Figure 27A , the conductive regions 597"' and 597"" can be separated from each other by a separation (e.g., gap) having a length in the Y-direction (e.g., a direction perpendicular to a length of each of the data lines 221, 222, 223, and 224) such that the conductive regions 597"' and 597"" can be positioned side-by-side with respect to the X-direction.

[0170] Each of the conductive regions 597"' and 597"" can be shared by a smaller number of memory cells than the number of memory cells that share the conductive region 597. As Figure 8B shown in Figure 27A , each of the conductive regions 597"' and 597"" can be shared by respective memory cells that are in the same direction (e.g., in the same column) in the Y-direction. For example, the conductive region 597' can be shared by the memory cells 210, 211, 212, and 213. In another example, the conductive region 597" can be shared by the memory cells 210', 211', 212', and 213'.

[0171] Each of the memory cells (memory cells 210, 211, 212, 213, 210', 211', 212', and 213') of the memory device 2700A can include transistors T1 and T2 (e.g., similar to transistors T1 and T2 shown in Figure 2 Figure 27A In

[0172] Figure 27A The memory device 2700A is shown including two conductive regions 597"' and 597"" (e.g., two conductive plates (e.g., sub-plates)) as an example. However, the memory device 2700A can include more than two conductive regions (e.g., more than two sub-plates) similar to the conductive regions 597"' and 597"". Figure 27A Line 28-28 in Figure 28 shows the location of a portion of the memory device 2700A shown in

[0173] Figure 27B A top view of a memory device 2700B is shown that can be a variation of the top view in Figure 27A Figure 27B As shown in

[0174] Figure 27B A top view of a memory device 2700B is shown that can be a variation of the top view in Figure 27B ​​The top view shows an example of conductive structure 2303" (e.g., the entire top portion of conductive structure 2303"). (e.g., a portion of the top portion of conductive structure 2303" is not hidden below portions 541B and 542F of access lines 241 and 242, respectively.) In an alternative structure of memory device 2700B, at least a portion of conductive structure 2303" (e.g., a portion or the entire conductive structure 2303") may be formed below at least one of portions 541B and 542F (e.g., in the Z direction) (e.g., directly formed below at least one of portions 541B and 542F in the Z direction). Therefore, in an alternative structure of memory device 2700B, at least a portion of conductive structure 2303" (e.g., a portion or the entire top portion of conductive structure 2303") may be hidden below at least one of portions 541B and 542F.

[0175] Figure 28 Exhibition along Figure 27A A partial side view (e.g., cross-sectional view) of the memory device 2700A with lines 28-28. Figure 28 Some of the elements (e.g., charge storage structure 202 and substrate 599) in the memory device 2700A can be connected to... Figure 7 Some of the elements in the memory device 200 are similar (or identical).

[0176] like Figure 28 As shown, the memory device 2700A may include a dielectric (e.g., silicon dioxide) 2745 located between the conductive structure 2303 and the semiconductor material 596'. The memory device 2700A may also include a dielectric (e.g., silicon dioxide, not shown) similar to the dielectric 2745 located between each of the conductive structures 2303 and the semiconductor material 596'. Therefore, the conductive structure 2303 (in...) Figure 27A The components located between memory cells 210 and 211 and between memory cells 212 and 213 can be electrically separated from semiconductor materials 596' and 596" by a dielectric (e.g., dielectric 2745). Similarly, conductive structure 2303 (in Figure 27A The memory cells located between memory cells 210' and 211' and between memory cells 212' and 213' can be electrically separated from semiconductor materials 596' and 596" by a dielectric (e.g., a dielectric similar to dielectric 2745).

[0177] exist Figure 7 and Figure 27A In the comparison between them, Figure 7 The conductive structure 503 is accessible (electrically coupled to) the conductive region 597. Figure 27A and Figure 28In some embodiments, the conductive structure 2303 is electrically separated from the conductive regions 597'" and 597"" by a dielectric (e.g., dielectric 2745). However, the conductive structure 2303 can contact a conductive region (e.g., conductive segment 2503) that can be coupled to a ground plate of the memory device 2700A.

[0178] The conductive structure 2303 of the memory device 2700A Figure 27A may provide improvements to the memory device 2700A that can be similar to the improvements provided by the conductive structure 503 to the memory device 200 as described above with reference to Figures 5 to 8B .

[0179] Figure 29A , Figure 29B and Figure 29C different views of a structure of a memory device 2900 including a plurality of decks of memory cells according to some embodiments described herein. Figure 29A An exploded view (e.g., in the Z-direction) of the memory device 2900 is shown. Figure 29B A side view (e.g., cross-sectional view) in the X-direction and the Z-direction of the memory device 2900 is shown. Figure 29C A side view (e.g., cross-sectional view) in the Y-direction and the Z-direction of the memory device 2900 is shown.

[0180] As shown in Figure 29A , the memory device 2900 can include decks (decks of memory cells) 29050, 29051, 29052, and 29053 that are shown exploded from one another in the exploded view to help facilitate ease of viewing the deck structure of the memory device 2900. In practice, the decks 29050, 29051, 29052, and 29053 can be attached to one another in an arrangement in which one deck can be formed (e.g., stacked) over another deck over a substrate (e.g., a semiconductor (e.g., silicon) substrate) 2999. For example, as shown in Figure 29A , the decks 29050, 29051, 29052, and 29053 can be formed in the Z-direction (e.g., vertically formed in the Z-direction relative to the substrate 2999) perpendicular to the substrate 2999.

[0181] As shown in Figure 29AAs shown in the middle, each of the decks 29050, 29051, 29052, and 29053 can have memory cells arranged in the X and Y directions (e.g., arranged in rows in the X direction and in columns in the Y direction). For example, the deck 29050 can include memory cells 29100, 29110, 29120, and 29130 (e.g., arranged in a row), memory cells 29200, 29210, 29220, and 29230 (e.g., arranged in a row), and memory cells 29300, 29310, 29320, and 29330 (e.g., arranged in a row).

[0182] The deck 29051 can include memory cells 29101, 29111, 29121, and 29131 (e.g., arranged in a row), memory cells 29201, 29211, 29221, and 29231 (e.g., arranged in a row), and memory cells 29301, 29311, 29321, and 29331 (e.g., arranged in a row).

[0183] The deck 29052 can include memory cells 29102, 29112, 29122, and 29132 (e.g., arranged in a row), memory cells 29202, 29212, 29222, and 29232 (e.g., arranged in a row), and memory cells 29302, 29312, 29322, and 29332 (e.g., arranged in a row).

[0184] The deck 29053 can include memory cells 29103, 29113, 29123, and 29133 (e.g., arranged in a row), memory cells 29203, 29213, 29223, and 29233 (e.g., arranged in a row), and memory cells 29303, 29313, 29323, and 29333 (e.g., arranged in a row).

[0185] As Figure 29A As shown in the middle, the decks 29050, 29051, 29052, and 29053 can be located (e.g., vertically formed in the Z direction) on tiers (e.g., portions) 2950, 2951, 2952, and 2953, respectively, of the memory device 2900. The arrangement of the decks 29050, 29051, 29052, and 29053 forms a 3-dimensional (3-D) structure of memory cells of the memory device 2900, where different tiers of memory cells of the memory device 2900 can be located (e.g., formed) in different tiers (e.g., different vertical portions) 2950, 2951, 2952, and 2953 of the memory device 2900.

[0186] Stacks 29050, 29051, 29052, and 29053 can be formed one stack at a time. For example, stacks 29050, 29051, 29052, and 29053 can be formed sequentially in the order of stacks 29050, 29051, 29052, and 29053 (e.g., stack 29051 is formed first and stack 29053 is formed last). In this example, memory cells of one stack (e.g., stack 29051) can be formed after memory cells of another stack (e.g., stack 29050) are formed or before memory cells of another stack (e.g., stack 29052) are formed. Alternatively, stacks 29050, 29051, 29052, and 29053 can be formed simultaneously (e.g., synchronously) such that memory cells of stacks 29050, 29051, 29052, and 29053 can be formed simultaneously. For example, memory cells in tiers 2950, 2951, 2952, and 2953 of memory device 2900 can be formed simultaneously.

[0187] The structure of the memory cells of each of stacks 29050, 29051, 29052, and 29053 can include the structure of the memory cells described above with reference to Figures 1 to 28 For example, the structure of the memory cells of stacks 29050, 29051, 29052, and 29053 can include the structure of the memory cells of memory devices 200, 900, and 2300A.

[0188] Memory device 2900 can include data lines (e.g., bit lines) and access lines (e.g., word lines) to access the memory cells of stacks 29050, 29051, 29052, and 29053. For simplicity, the data lines and access lines of the memory cells are omitted from Figure 29A However, the data lines and access lines of memory device 2900 can be similar to the data lines and access lines of memory devices described above with reference to Figures 1 to 28

[0189] Figure 29A Memory device 2900 is shown including four stacks (e.g., 29050, 29051, 29052, and 29053) as an example. However, the number of stacks can be different than four. Figure 29A Each of stacks 29050, 29051, 29052, and 29053 is shown including one tier (e.g., layer) of memory cells as an example. However, at least one of the stacks (e.g., one or more of stacks 29050, 29051, 29052, and 29053) can have two (or more) tiers of memory cells. Figure 29A ​Each of the display stacks 29050, 29051, 29052, and 29053 includes an instance of four memory cells in the X direction (e.g., in a row) and three memory cells in the Y direction (e.g., in a column). However, the number of memory cells in a row, a column, or both can vary.

[0190] The description of the apparatuses (e.g., memory devices 100, 200, 900, 2300A, 2300B, 2400A, 2400B, 2500A, 2500B, 2700A, 2700B, and 2900) and methods (e.g., operations of memory devices 100 and 200 and methods of forming memory device 900) is intended to provide a general understanding of the structure of various embodiments and is not intended to provide a complete description of all the elements and features of the apparatuses that can utilize the structures described herein. For example, the apparatuses herein refer to a device (e.g., any of memory devices 100, 200, 900, 2300A, 2300B, 2400A, 2400B, 2500A, 2500B, 2700A, 2700B, and 2900) or a system (e.g., an electronic article that can include any of memory devices 100, 200, 900, 2300A, 2300B, 2400A, 2400B, 2500A, 2500B, 2700A, 2700B, and 2900).

[0191] The above references Figures 1 to 29C Any of the described components can be implemented in a number of ways, including by software. Accordingly, the apparatuses (e.g., memory devices 100, 200, 900, 2300A, 2300B, 2400A, 2400B, 2500A, 2500B, 2700A, 2700B, and 2900) or portions of each of these memory devices described above can be characterized as a “module” (or “modules”) herein. Such modules can include hardware circuitry, single- and / or multi-processor circuitry, memory circuitry, software program modules, and objects and / or firmware and combinations thereof as needed and / or appropriate for the particular implementation of various embodiments. For example, such modules can include in a system operation simulation package, such as a software electrical signal simulation package, a power usage and range simulation package, a capacitance-inductance simulation package, a power / heat dissipation simulation package, a signal transmission-reception simulation package, and / or a combination of software and hardware for operating or simulating the operation of various potential embodiments.

[0192] The memory devices described herein (e.g., memory devices 100, 200, 900, 2300A, 2300B, 2400A, 2400B, 2500A, 2500B, 2700A, 2700B, and 2900) can be included in an apparatus (e.g., electronic circuitry) such as a high-speed computer, communications, and signal processing circuitry, a single- or multi-processor module, a single or multiple embedded processors, multi-core processors, message information switches, and specialized modules including multiple layers, multi-chip modules. Such apparatus can further include subcomponents such as, for example, a microprocessor that is used in a computer system, personal computer (e.g., laptop computer, desktop computer, handheld computer, tablet computer, etc.), workstation, radio, video player, audio player (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) player), vehicle, medical device (e.g., heart monitor, blood pressure monitor, etc.), set-top box, and others.

[0193] The above references Figures 1 to 29C The described embodiments include devices and methods of forming the devices. One of the devices includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is between and electrically separated from the first charge storage structure and the second charge storage structure. The conductive line forms a gate of each of the first, second, third, and fourth transistors. Other embodiments including additional devices and methods are described.

[0194] In the DETAILED DESCRIPTION and in the claims, the term "on," with respect to two or more elements (e.g., materials), means at least some contact between the elements (e.g., materials). The term "above" means extremely close proximity, but possibly with one or more intervening elements (e.g., materials) such that contact is possible but not required. Neither "on" nor "above" implies any directionality as used herein unless so stated.

[0195] In the DETAILED DESCRIPTION and in the claims, a list of items joined by the term "at least one of" can mean any single one of the listed items. The phrase "at least one of" can mean, for example, A; B; or A and B. In another example, if items A and B are listed, the phrase "at least one of A and B" can mean A, B, or both A and B. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0196] In the DETAILED DESCRIPTION and in the claims, a list of items joined by the term "one of' can mean any single one of the listed items. The phrase "at least one of' can mean, for example, A (and not B), or B (and not A). In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" can mean A, B, or C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0197] The above description and drawings illustrate and describe several embodiments of the inventive subject matter to enable a person skilled in the art to make and use the embodiments of the inventive subject matter. Other embodiments can be made and implemented without departing from the scope of the inventive subject matter. The examples are indicative of the possibilities of variations. Parts and features of some embodiments can be included in or substituted for those of other embodiments. Many other embodiments will be apparent to those of ordinary skill in the art having the benefit of the above description and drawings.

Claims

1. A memory device comprising: a conductive region; a first data line; a second data line; a first memory cell including a first transistor and a second transistor, the first transistor including a first channel region coupled between the first data line and the conductive region and a first charge storage structure between the first data line and the conductive region and electrically isolated from the first channel region, the second transistor including a second channel region coupled to and between the first data line and the first charge storage structure; a second memory cell including a third transistor and a fourth transistor, the third transistor including a third channel region coupled between the second data line and the conductive region and a second charge storage structure between the second data line and the conductive region and electrically isolated from the third channel region, the fourth transistor including a fourth channel region coupled to and between the second data line and the second charge storage structure; a conductive structure between and electrically isolated from the first charge storage structure and the second charge storage structure; and a conductive line forming a gate for each of the first transistor, the second transistor, the third transistor, and the fourth transistor.

2. The memory device of claim 1, wherein the conductive structure comprises one of a metal and a conductively-doped polysilicon.

3. The memory device of claim 1, wherein the second channel region comprises a same material as the fourth channel region.

4. The memory device of claim 1, wherein each of the second channel region and the fourth channel region comprises a semiconductive oxide material.

5. The memory device of claim 1, wherein the first channel region and the third channel region comprise a first material and the second channel region and the fourth channel region comprise a second material different from the first material.

6. The memory device of claim 1, wherein the conductive region is coupled to a ground connection.

7. The memory device of claim 1, wherein the conductive structure contacts the conductive region.

8. The memory device of claim 1, wherein the conductive structure is electrically isolated from the conductive region.

9. The memory device of claim 1, further comprising: a third memory cell including a first additional transistor and a second additional transistor, the first additional transistor including a first additional channel region coupled between the first data line and the conductive region and a first additional charge storage structure electrically isolated from the first additional channel region, the second additional transistor including a second additional channel region coupled between the first data line and the first additional charge storage structure. ​ a fourth additional transistor, the third additional transistor including a third additional channel region coupled between the second data line and the conductive region and a second additional charge storage structure electrically isolated from the third additional channel region, the fourth additional transistor including a fourth additional channel region coupled between the second data line and the second additional charge storage structure; and wherein the conductive structure extends between and is electrically isolated from the first additional charge storage structure and the second additional charge storage structure.

10. The memory device of claim 9, further comprising: an additional conductive structure extending in a direction perpendicular to the conductive structure, the additional conductive structure extending between and being electrically isolated from the first charge storage structure and the second charge storage structure and from the first additional charge storage structure and the second additional charge storage structure.

11. The memory device of claim 1, further comprising: a third memory cell including a first additional transistor and a second additional transistor, the first additional transistor including a first additional channel region coupled between the first data line and the conductive region and a first additional charge storage structure electrically isolated from the first additional channel region, the second additional transistor including a second additional channel region coupled between the first data line and the first additional charge storage structure; a fourth memory cell including a third additional transistor and a fourth additional transistor, the third additional transistor including a third additional channel region coupled between the second data line and the conductive region and a second additional charge storage structure electrically isolated from the third additional channel region, the fourth additional transistor including a fourth additional channel region coupled between the second data line and the second additional charge storage structure; a first additional conductive structure between and electrically isolated from the first additional charge storage structure and the second additional charge storage structure; an additional conductive line forming a gate for each of the first additional transistor, the second additional transistor, the third additional transistor, and the fourth additional transistor, the conductive line and the additional conductive line being between the first memory cell and the first additional memory cell; and a second additional conductive structure extending in a direction from the first memory cell to the second memory cell, and the second additional conductive structure being electrically isolated from the first charge storage structure and the second charge storage structure and from the first additional charge storage structure and the second additional charge storage structure.

12. The memory device of claim 1, wherein the conductive region is a first conductive region, and the memory device further comprises: a second conductive region separate from the first conductive region; ​ a third memory cell including a first additional transistor including a first additional channel region coupled between the first data line and the second conductive region and a first additional charge storage structure electrically isolated from the first additional channel region, and a second additional transistor including a second additional channel region coupled between the first data line and the first additional charge storage structure; a fourth memory cell including a third additional transistor including a third additional channel region coupled between the second data line and the second conductive region and a second additional charge storage structure electrically isolated from the third additional channel region, and a fourth additional transistor including a fourth additional channel region coupled between the second data line and the second additional charge storage structure; and wherein the conductive structure extends between and is electrically isolated from the first additional charge storage structure and the second additional charge storage structure.

13. A memory device comprising: a conductive region in a first level of the memory device; a first additional conductive region in a second level of the memory device; a second additional conductive region in the second level and electrically isolated from the first additional conductive region; a first memory cell between the first level and the second level and including a first charge storage structure, a first channel region contacting the first charge storage structure and the first additional conductive region, and a first semiconductor material contacting the first additional conductive region and the conductive region; a second memory cell between the first level and the second level and including a second charge storage structure, a second channel region contacting the second charge storage structure and the second additional conductive region, and a second semiconductor material contacting the second additional conductive region and the conductive region; a conductive structure between and electrically isolated from the first charge storage structure and the second charge storage structure; and a conductive line electrically isolated from the first and second charge storage structures, the first and second channel regions, and the first and second semiconductor materials, the conductive line spanning portions of each of the first semiconductor material, the first channel region, the second semiconductor material, and the second channel region.

14. The memory device of claim 13, wherein: the first additional conductive region is part of a first data line of the memory device; and the second additional conductive region is part of a second data line of the memory device.

15. The memory device of claim 13, wherein the conductive line is part of an access line of the memory device.

16. The memory device of claim 13, wherein the conductive line further spans portions of each of the first and second charge storage structures.

17. The memory device of claim 13, wherein the conductive structure contacts the conductive region.

18. The memory device of claim 13, wherein the conductive structure is electrically separated from the conductive region.

19. The memory device of claim 13, wherein the conductive structure comprises a metal.

20. The memory device of claim 13, wherein the conductive structure comprises p-type conductive polysilicon.

21. The memory device of claim 13, wherein the conductive structure comprises n-type conductive polysilicon.

22. The memory device of claim 13, wherein the channel region comprises at least one of: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), indium gallium zinc oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), hafnium indium zinc oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a ), zirconium zinc tin oxide (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).

23. A method of forming a memory device, the method comprising: forming a material level, the material level comprising a dielectric material; forming first trenches in the dielectric material by removing portions of the material level to provide first remaining portions of the material level, such that each of the first trenches comprises a length in a first direction, a first sidewall formed of a first portion of the dielectric material, and a second sidewall formed of a second portion of the dielectric material; forming a material in the first trenches, including forming a first charge storage material in the first trenches, forming a second charge storage material in the first trenches separate from the first charge storage material, and forming a conductive material between and separate from the first charge storage material and the second charge storage material; and forming second trenches extending in a second direction across the first remaining portions of the material level, the first and second charge storage materials, and the conductive material to form memory cells from second remaining portions of the material level and remaining portions of the first and second charge storage materials, such that a first memory cell of the memory cells is adjacent to a portion of the first sidewall of a trench of the first trenches, a second memory cell of the memory cells is adjacent to a portion of the second sidewall of the trench of the first trenches, and the remaining portions of the first and second charge storage materials form respective charge storage structures of the first and second memory cells, and a portion of the conductive material is between the charge storage structures of the first and second memory cells.

24. The method of claim 23, wherein the second remaining portions of the material level comprise conductive regions coupled to the first and second memory cells, and the portion of the conductive material contacts the conductive regions.

25. The method of claim 23, wherein forming the material in the first trenches comprises forming additional dielectric material in each of the first trenches, such that after forming the second trenches, a portion of the additional dielectric material is between the first and second memory cells.

26. The method of claim 23, wherein forming the material level comprises: forming additional conductive material over the substrate; forming semiconductor material over the additional conductive material; and forming the dielectric material over the semiconductor material.

27. The method of claim 26, wherein the additional conductive material is formed after forming the second trenches such that each of the memory cells includes a portion of the additional conductive material electrically coupled thereto.

28. The method of claim 23, wherein each of the memory cells comprises a portion formed from a portion of the material in the first trench, and the portion of each of the memory cells comprises at least one of: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), indium gallium zinc oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), hafnium indium zinc oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a ), zirconium zinc tin oxide (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).

29. The method of claim 23, further comprising: forming access lines after forming the second trenches such that each of the access lines is electrically isolated from the memory cells.

30. The method of claim 29, further comprising: forming data lines after forming the access lines such that each of the data lines extends in the first direction and each of the data lines is electrically coupled to at least a portion of the second remaining portion of the material level.

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