Detection device

Abstract

A detection device includes: a substrate; a plurality of photoelectric conversion elements disposed on the substrate and including semiconductor layers; a plurality of transistors respectively disposed corresponding to the plurality of photoelectric conversion elements; and a plurality of signal lines. One detection element is configured to include a photoelectric conversion element and a plurality of transistors disposed adjacent to the photoelectric conversion element in a second direction. A first signal line among the plurality of signal lines is disposed between the photoelectric conversion element of the first detection element and the photoelectric conversion element of a second detection element adjacent to the first detection element on one side in a first direction, and is connected to the first detection element and the second detection element. A second signal line among the plurality of signal lines is disposed between the photoelectric conversion element of the first detection element and the photoelectric conversion element of a third detection element adjacent to the first detection element on the other side in the first direction, and is connected to the first detection element and the third detection element.

Description

Technical Field

[0001] The present invention relates to a detection device. Background Art

[0002] There is known an optical detection device in which a plurality of photoelectric conversion elements such as PIN photodiodes are arranged on a substrate. Such an optical detection device is used, for example, as a biological sensor for detecting biological information such as a fingerprint sensor and a vein sensor. The plurality of photoelectric conversion elements are arranged at intervals corresponding to the detection resolution.

[0003] In Patent Document 1, there is described a solid-state imaging device having a photodiode and a plurality of transistors in units of pixels. In the solid-state imaging device described in Patent Document 1, the amplifier transistors formed in each pixel are symmetrically provided with respect to a signal line connected to the amplifier transistor. That is, in Patent Document 1, the signal line is shared between adjacent pixels.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2010-187022 Summary of the Invention

[0007] Technical Problem to be Solved by the Invention

[0008] An optical detection device is required to increase the aperture ratio. When the structure described in Patent Document 1 is applied to an optical detection device, although the aperture ratio becomes large, the photoelectric conversion element and the plurality of transistors are symmetrically arranged with respect to the signal line. Therefore, there is a case where the arrangement pitch of the photoelectric conversion elements is not constant. As a result, there is a possibility that the detection position accuracy is reduced.

[0009] An object of the present invention is to provide a detection device that can increase the aperture ratio while suppressing a decrease in detection position accuracy.

[0010] Solution to the Technical Problem

[0011] A detection device according to one embodiment of the present invention includes: a substrate; a plurality of photoelectric conversion elements provided on the substrate and including a semiconductor layer having a photovoltaic effect; a plurality of transistors provided corresponding to the plurality of photoelectric conversion elements respectively; and a plurality of signal lines provided between the plurality of photoelectric conversion elements adjacent in a first direction, extending in a second direction intersecting the first direction, and supplying signals to either the photoelectric conversion elements or any one of the plurality of transistors. One detection element is configured to include the photoelectric conversion element and the plurality of transistors arranged adjacent to the photoelectric conversion element in the second direction. A first signal line among the plurality of signal lines is arranged between the photoelectric conversion element of the first detection element and the photoelectric conversion element of the second detection element and is connected to the first detection element and the second detection element. The second detection element is adjacent to the first detection element on one side in the first direction. A second signal line among the plurality of signal lines is arranged between the photoelectric conversion element of the first detection element and the photoelectric conversion element of the third detection element and is connected to the first detection element and the third detection element. The third detection element is adjacent to the first detection element on the other side in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view showing a schematic cross-sectional structure of a detection device with an illumination device according to an embodiment.

[0013] Figure 2 is a cross-sectional view showing a schematic cross-sectional structure of a detection device with an illumination device according to a modified example.

[0014] Figure 3 is a top view showing the detection device according to the embodiment.

[0015] Figure 4 is a block diagram showing a structural example of the detection device according to the embodiment.

[0016] Figure 5 is a circuit diagram showing a plurality of detection elements.

[0017] Figure 6 is a timing waveform diagram showing an operation example of the detection element.

[0018] Figure 7 is a top view showing a plurality of detection elements.

[0019] Figure 8 is a magnified top view showing adjacent detection elements.

[0020] Figure 9 is Figure 8 a cross-sectional view taken along line IX-IX'. Detailed Embodiment

[0021] The mode (embodiment) for implementing the invention will be described in detail with reference to the accompanying drawings. The present invention is not limited by the content described in the following embodiments. In addition, among the constituent elements described below, there are elements that can be easily conceived by those skilled in the art and elements that are substantially the same. Furthermore, the constituent elements described below can be appropriately combined. In addition, the disclosure is merely an example, and for those skilled in the art, appropriate changes that can be easily conceived while maintaining the gist of the invention are of course also included in the scope of the present invention. In addition, in order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part compared with the actual mode, but this is ultimately just an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, for the figures that have appeared, sometimes the same reference numerals are assigned to the same elements as above, and the detailed description is appropriately omitted.

[0022] In this specification and the claims, when expressing the mode of disposing other structures on a certain structure, when only expressed as "on", unless otherwise specified, it includes both the case of disposing other structures directly above in contact with a certain structure and the case of disposing other structures above a certain structure with another structure in between.

[0023] (Embodiment)

[0024] Figure 1 is a cross-sectional view showing a schematic cross-sectional structure of a detection device with an illumination device having the detection device according to the embodiment. As shown Figure 1 in the figure, the detection device 120 with an illumination device has a detection device 1, an illumination device 121, and a cover glass 122. The illumination device 121, the detection device 1, and the cover glass 122 are stacked in this order in a direction perpendicular to the surface of the detection device 1.

[0025] The illumination device 121 has a light irradiation surface 121a that irradiates light, and irradiates light L1 from the light irradiation surface 121a toward the detection device 1. The illumination device 121 is a backlight. The illumination device 121 can also be, for example, a so-called side light type backlight having a light guide plate provided at a position corresponding to the detection area AA and a plurality of light sources arranged at one end or both ends of the light guide plate. As the light source, for example, a light emitting diode (LED: Light Emitting Diode) that emits light of a specified color is used. In addition, the illumination device 121 can also be a so-called direct-lit type backlight having a light source (for example, an LED) provided directly below the detection area AA. In addition, the illumination device 121 is not limited to a backlight, and can also be provided on the side or above the detection device 1, and can irradiate the light L1 from the side or above the finger Fg.

[0026] The detection device 1 is disposed opposite to the light irradiation surface 121a of the lighting device 121. The light L1 irradiated from the lighting device 121 passes through the detection device 1 and the cover glass 122. The detection device 1 is, for example, a light reflection type biological sensor, and can detect unevenness (such as fingerprints) on the surface of the finger Fg by detecting the light L2 reflected on the surface of the finger Fg. Alternatively, in addition to detecting fingerprints, the detection device 1 can also detect biological-related information by detecting the light L2 reflected inside the finger Fg. Biological-related information is, for example, blood vessel images such as veins, pulse, pulse wave, etc. The color of the light L1 from the lighting device 121 can also be different according to the detection object.

[0027] The cover glass 122 is a member for protecting the detection device 1 and the lighting device 121, and covers the detection device 1 and the lighting device 121. The cover glass 122 is, for example, a glass substrate. In addition, the cover glass 122 is not limited to a glass substrate, and may also be a resin substrate or the like. Alternatively, the cover glass 122 may not be provided. In this case, a protective layer is provided on the surface of the detection device 1, and the finger Fg is in contact with the protective layer of the detection device 1.

[0028] The detection device 120 with a lighting device may be provided with a display panel instead of the lighting device 121. The display panel may be, for example, an organic EL display panel (OLED: Organic Light Emitting Diode), an inorganic EL display (micro LED, mini LED). Alternatively, the display panel may also be a liquid crystal display panel (LCD: Liquid Crystal Display) using a liquid crystal element as a display element, or an electrophoretic display panel (EPD: Electrophoretic Display) using an electrophoretic element as a display element. In this case, it is also possible to detect fingerprint and biological-related information of the finger Fg based on the light L2 that the display light irradiated from the display panel passes through the detection device 1 and is reflected by the finger Fg.

[0029] Figure 2 is a cross-sectional view showing a schematic cross-sectional structure of the detection device with a lighting device according to the modified example. As Figure 2 shown, in the detection device 120A with a lighting device, the detection device 1, the lighting device 121, and the cover glass 122 are stacked in sequence in a direction perpendicular to the surface of the detection device 1. In this modified example, as the lighting device 121, a display panel such as an organic EL display panel can also be used.

[0030] The light L1 irradiated from the lighting device 121 passes through the cover glass 122 and is then reflected by the finger Fg. The light L2 reflected by the finger Fg passes through the cover glass 122 and then through the lighting device 121. By receiving the light L2 that has passed through the lighting device 121, the detection device 1 can detect biometric-related information such as fingerprint detection.

[0031] Figure 3 It is a top view showing the detection device according to the embodiment. As Figure 3 shown, the detection device 1 includes a substrate 21, a sensor unit 10, a first gate line drive circuit 15A, a second gate line drive circuit 15B, a signal line selection circuit 16, a detection circuit 48, a control circuit 102, and a power supply circuit 103.

[0032] The control substrate 101 is electrically connected to the substrate 21 via a wiring substrate 110. The wiring substrate 110 is, for example, a flexible printed circuit board or a rigid substrate. The detection circuit 48 is provided on the wiring substrate 110. The control circuit 102 and the power supply circuit 103 are provided on the control substrate 101. The control circuit 102 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 102 supplies control signals to the sensor unit 10, the first gate line drive circuit 15A, the second gate line drive circuit 15B, and the signal line selection circuit 16 to control the detection operation of the sensor unit 10. The power supply circuit 103 supplies voltage signals such as a power supply potential Vsf and a reference potential Vcom (refer to Figure 5 ) to the sensor unit 10, the first gate line drive circuit 15A, the second gate line drive circuit 15B, and the signal line selection circuit 16.

[0033] The substrate 21 has a detection region AA and a peripheral region GA. The detection region AA is a region that overlaps with the plurality of detection elements 3 included in the sensor unit 10. The peripheral region GA is a region outside the detection region AA and does not overlap with the detection elements 3. That is, the peripheral region GA is a region between the outer periphery of the detection region AA and the end of the substrate 21. The first gate line drive circuit 15A, the second gate line drive circuit 15B, and the signal line selection circuit 16 are provided in the peripheral region GA.

[0034] Each of the plurality of detection elements 3 of the sensor unit 10 is a photosensor having a photoelectric conversion element 30. The photoelectric conversion element 30 is a photodiode that outputs an electrical signal corresponding to the light irradiated thereon. More specifically, the photoelectric conversion element 30 is a PIN (Positive Intrinsic Negative) photodiode. The detection elements 3 are arranged in a matrix in the detection area AA. The photoelectric conversion elements 30 included in the plurality of detection elements 3 perform detection in accordance with gate drive signals (e.g., a reset control signal RST and a read control signal RD) supplied from the first gate line drive circuit 15A and the second gate line drive circuit 15B. The plurality of photoelectric conversion elements 30 output, as detection signals Vdet, electrical signals corresponding to the light irradiated thereon to the signal line selection circuit 16. The detection device 1 detects biological information based on the detection signals Vdet from the plurality of photoelectric conversion elements 30.

[0035] The first gate line drive circuit 15A, the second gate line drive circuit 15B, and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the first gate line drive circuit 15A and the second gate line drive circuit 15B are provided in the area extending along the second direction Dy in the peripheral area GA. The signal line selection circuit 16 is provided in the area extending along the first direction Dx in the peripheral area GA and is provided between the sensor unit 10 and the detection circuit 48. The first gate line drive circuit 15A and the second gate line drive circuit 15B are arranged with the detection area AA therebetween in the first direction Dx. However, it is not limited thereto, and the first gate line drive circuit 15A and the second gate line drive circuit 15B may be formed as one circuit and arranged along one side of the detection area AA.

[0036] In addition, the first direction Dx is one direction in the plane parallel to the substrate 21. The second direction Dy is one direction in the plane parallel to the substrate 21 and is a direction orthogonal to the first direction Dx. In addition, the second direction Dy may cross the first direction Dx instead of being orthogonal thereto. Further, the third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy and is the normal direction of the substrate 21.

[0037] Figure 4 is a block diagram showing a structural example of the detection device according to the embodiment. As Figure 4 shown, the detection device 1 further includes a detection control circuit 11 and a detection unit 40. A part or all of the functions of the detection control circuit 11 are included in the control circuit 102. In addition, a part or all of the functions of the detection unit 40 other than the detection circuit 48 are included in the control circuit 102.

[0038] The detection control circuit 11 is a circuit that supplies control signals to the first gate line driving circuit 15A, the second gate line driving circuit 15B, the signal line selection circuit 16, and the detection unit 40 respectively, and controls these operations. The detection control circuit 11 supplies various control signals such as a start signal STV and a clock signal CK to the first gate line driving circuit 15A and the second gate line driving circuit 15B. In addition, the detection control circuit 11 supplies various control signals such as a selection signal ASW to the signal line selection circuit 16.

[0039] The first gate line driving circuit 15A and the second gate line driving circuit 15B are circuits that drive a plurality of gate lines (read control scan line GLrd, reset control scan line GLrst (refer to Figure 5 )) based on various control signals. The first gate line driving circuit 15A and the second gate line driving circuit 15B sequentially or simultaneously select a plurality of gate lines, and supply gate drive signals (for example, a reset control signal RST, a read control signal RD) to the selected gate lines. Thereby, the first gate line driving circuit 15A and the second gate line driving circuit 15B select a plurality of photoelectric conversion elements 30 connected to the gate lines.

[0040] The signal line selection circuit 16 is a switching circuit that sequentially or simultaneously selects a plurality of output signal lines SL (refer to Figure 5 ). The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected output signal line SL to the detection circuit 48 based on the selection signal ASW supplied from the detection control circuit 11. Thereby, the signal line selection circuit 16 outputs the detection signal Vdet of the photoelectric conversion element 30 to the detection unit 40. In addition, the signal line selection circuit 16 may be omitted. In this case, the output signal line SL may also be directly connected to the detection circuit 48.

[0041] The detection unit 40 includes a detection circuit 48, a signal processing circuit 44, a coordinate extraction circuit 45, a storage circuit 46, and a detection timing control circuit 47. The detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, and the coordinate extraction circuit 45 to operate synchronously based on the control signal supplied from the detection control circuit 11.

[0042] The detection circuit 48 is, for example, an analog front end circuit (AFE: Analog Front End). The detection circuit 48 is a signal processing circuit that at least has the functions of a detection signal amplification circuit 42 and an A / D conversion circuit 43. The detection signal amplification circuit 42 amplifies the detection signal Vdet. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplification circuit 42 into a digital signal.

[0043] The signal processing circuit 44 is a logic circuit that detects a specified physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. When the finger Fg is in contact with or close to the detection surface, the signal processing circuit 44 can detect the unevenness of the surface of the finger Fg and the palm based on the signal from the detection circuit 48. In addition, the signal processing circuit 44 can also detect biological-related information based on the signal from the detection circuit 48. Biological-related information is, for example, the blood vessel pattern, pulse wave, pulse, blood oxygen saturation, etc. of the finger Fg and the palm.

[0044] The storage circuit 46 temporarily stores the signal calculated by the signal processing circuit 44. The storage circuit 46 can be, for example, a RAM (Random Access Memory), a register circuit, etc.

[0045] The coordinate extraction circuit 45 is a logic circuit that calculates the detection coordinates of the unevenness of the surface of the finger Fg, etc. when the contact or approach of the finger Fg is detected in the signal processing circuit 44. In addition, the coordinate extraction circuit 45 is a logic circuit that calculates the detection coordinates of the blood vessels of the finger Fg and the palm. The coordinate extraction circuit 45 combines the detection signals Vdet output from each detection element 3 of the sensor unit 10 to generate two-dimensional information representing the uneven shape of the surface of the finger Fg, etc. In addition, the coordinate extraction circuit 45 can output the detection signal Vdet as the sensor output Vo without calculating the detection coordinates.

[0046] Next, a circuit structure example and an operation example of the detection device 1 will be described. Figure 5 It is a circuit diagram showing a plurality of detection elements. As Figure 5 shown, the detection element 3 includes a photoelectric conversion element 30, a reset transistor Mrst, a read transistor Mrd, and a source follower transistor Msf. In addition, in the detection element 3, a reset control scan line GLrst and a read control scan line GLrd are provided as detection drive lines (gate lines), and an output signal line SL is provided as a wiring for signal reading.

[0047] The reset control scan line GLrst, the read control scan line GLrd, and the output signal line SL are respectively connected to a plurality of detection elements 3. Specifically, the reset control scan line GLrst and the read control scan line GLrd extend in the first direction Dx (see Figure 3 ) and are connected to a plurality of detection elements 3 arranged in the first direction Dx. In addition, the output signal line SL extends in the second direction Dy and is connected to a plurality of detection elements 3 arranged in the second direction Dy. The output signal line SL is a wiring for outputting signals from a plurality of transistors (the read transistor Mrd and the source follower transistor Msf).

[0048] A reset transistor Mrst, a readout transistor Mrd, and a source follower transistor Msf are provided corresponding to a photoelectric conversion element 30. The plurality of transistors included in the detection element 3 are each formed of an n-type TFT (Thin Film Transistor). However, this is not limiting, and each transistor may be formed of a p-type TFT.

[0049] A reference potential Vcom is applied to the anode of the photoelectric conversion element 30. The cathode of the photoelectric conversion element 30 is connected to a node N1. The node N1 is connected to one of the source or drain of the reset transistor Mrst and the gate of the source follower transistor Msf. When light is applied to the photoelectric conversion element 30, a signal (charge) output from the photoelectric conversion element 30 is accumulated in a capacitive element formed at the node N1.

[0050] The gate of the reset transistor Mrst is connected to a reset control scan line GLrst. A reset potential Vrst is supplied to the other of the source or drain of the reset transistor Mrst. When the reset transistor Mrst becomes ON (conductive state) in response to a reset control signal RST supplied from the first gate line drive circuit 15A, the potential of the node N1 is reset to the reset potential Vrst. The reference potential Vcom has a potential lower than the reset potential Vrst, and the photoelectric conversion element 30 is driven with a reverse bias.

[0051] The source follower transistor Msf is connected between a terminal supplied with a power supply potential Vsf and the readout transistor Mrd (node N2). The gate of the source follower transistor Msf is connected to the node N1. A signal (voltage) corresponding to the signal (charge) generated in the photoelectric conversion element 30 is supplied to the gate of the source follower transistor Msf. Thereby, the source follower transistor Msf outputs a signal voltage corresponding to the signal (charge) generated in the photoelectric conversion element 30 to the readout transistor Mrd.

[0052] The readout transistor Mrd is connected between the source (node N2) of the source follower transistor Msf and an output signal line SL. The gate of the readout transistor Mrd is connected to a readout control scan line GLrd. When the readout transistor Mrd becomes ON in response to a readout control signal RD supplied from the second gate line drive circuit 15B, the signal output from the source follower transistor Msf, that is, the signal (voltage) corresponding to the signal (charge) generated in the photoelectric conversion element 30, is output as a detection signal Vdet to the output signal line SL.

[0053] In addition, the circuit of a detection element 3 is not limited to a structure having three transistors, namely a reset transistor Mrst, a source follower transistor Msf, and a read transistor Mrd. The detection element 3 may have two transistors or may have four or more transistors.

[0054] Figure 6 is a timing waveform diagram showing an operation example of the detection element. As Figure 6 shown, the detection element 3 performs detection in the order of a reset period Prst, an accumulation period Pch, and a read period Pdet. The power supply circuit 103 supplies a reference potential Vcom to the anode of the photoelectric conversion element 30 during the reset period Prst, the accumulation period Pch, and the read period Pdet.

[0055] The control circuit 102 sets the reset control signal RST supplied to the reset control scan line GLrst to high (high-level voltage) at time t0, and the reset period Prst starts. During the reset period Prst, the reset transistor Mrst becomes on (conducting state), and the potential of the node N1 rises to the reset potential Vrst. In addition, since the read transistor Mrd is off (non-conducting state), the source of the source follower transistor Msf is charged with the power supply potential Vsf, and the potential of the node N2 rises.

[0056] The control circuit 102 sets the read control signal RD supplied to the read control scan line GLrd to high (high-level voltage) at time t1. As a result, the read transistor Mrd becomes on (conducting state), and the potential of the node N2 becomes (Vrst - Vthsf). In addition, Vthsf is the threshold voltage Vthsf of the source follower transistor Msf.

[0057] The control circuit 102 sets the reset control signal RST to low (low-level voltage) at time t2, the reset period Prst ends, and the accumulation period Pch starts. During the accumulation period Pch, the reset transistor Mrst becomes off (non-conducting state). The potential of the node N1 accumulates a signal corresponding to the light irradiated to the photoelectric conversion element 30 and decreases to (Vrst - Vphoto). In addition, Vphoto is a signal (voltage variation amount) corresponding to the light irradiated to the photoelectric conversion element 30.

[0058] The potential of the detection signal Vdet1 output from the output signal line SL at time t3 becomes (Vrst - Vthsf - Vrdon). Vrdon is the voltage drop caused by the on-resistance of the read transistor Mrd.

[0059] The control circuit 102 sets the read control signal RD to low (low-level voltage) at time t3. As a result, the read transistor Mrd becomes off (non-conductive state), and the potential of the node N2 becomes constant at (Vrst - Vthsf). In addition, a load is applied such that the potential of the detection signal Vdet output from the output signal line SL becomes low (low-level voltage).

[0060] The control circuit 102 sets the read control signal RD to high (high-level voltage) at time t4. As a result, the read transistor Mrd becomes on (conductive state), the accumulation period Pch ends, and the read period Pdet starts. The potential of the node N2 changes to (Vrst - Vthsf - Vphoto) according to the signal Vphoto. The potential of the detection signal Vdet2 output to the read period Pdet decreases by the signal Vphoto amount from the potential of the detection signal Vdet1 obtained at time t3, and becomes (Vrst - Vthsf - Vrdon - Vphoto).

[0061] The detection unit 40 can detect the light irradiated on the photoelectric conversion element 30 based on the differential signal (Vphoto) between the detection signal Vdet1 at time t3 and the detection signal Vdet2 at time t5. In Figure 6 , an operation example of one detection element 3 is shown, but the first gate line drive circuit 15A and the second gate line drive circuit 15B can perform detection using the detection elements 3 of the entire detection region AA by sequentially scanning the reset control scan line GLrst and the read control scan line GLrd in a time-division manner, respectively.

[0062] Next, the planar structure and cross-sectional structure of the detection element 3 will be described. Figure 7 is a top view showing a plurality of detection elements. As Figure 7 shown, the plurality of detection elements 3 are arranged in the first direction Dx and the second direction Dy. The plurality of detection elements 3 arranged along the first direction Dx are represented as detection elements 3(m), 3(m + 1), 3(m + 2), 3(m + 3). However, when it is not necessary to distinguish the detection elements 3(m), 3(m + 1), 3(m + 2), 3(m + 3) for explanation, they are only represented as the detection element 3. In addition, the output signal line SL, the read control scan line GLrd, and the reset control scan line GLrst are also represented in the same way.

[0063] A detection element 3 is connected to two gate lines (read control scan line GLrd, reset control scan line GLrst) and four signal lines (output signal line SL, power supply signal line SLsf, reset signal line SLrst, and reference signal line SLcom), and includes a part thereof. The read control scan line GLrd and the reset control scan line GLrst extend in a first direction Dx and are arranged in a second direction Dy. A plurality of signal lines (output signal line SL, power supply signal line SLsf, reset signal line SLrst, and reference signal line SLcom) extend in the second direction Dy and are arranged in the first direction Dx.

[0064] In Figure 7 the example shown, the detection element 3 is an area surrounded by two gate lines (reset control scan lines GLrst(N), GLrst(N + 1)) and two signal lines (power supply signal line SLsf, reference signal line SLcom).

[0065] In addition, a detection element 3 is configured to include a photoelectric conversion element 30 and a plurality of transistors (reset transistor Mrst, read transistor Mrd, and source follower transistor Msf) arranged adjacent to the photoelectric conversion element 30 in the second direction Dy.

[0066] The photoelectric conversion element 30 is disposed in an area surrounded by the read control scan line GLrd, the reset control scan line GLrst, the reset signal line SLrst, and the output signal line SL. The plurality of transistors are arranged between the read control scan line GLrd and the reset control scan line GLrst adjacent in the second direction Dy. In addition, in Figure 7 it, the area where a plurality of transistors are formed is taken as area MA and represented by a dotted line.

[0067] Here, three signal lines other than the output signal line SL (the power supply signal line SLsf, the reset signal line SLrst, and the reference signal line SLcom) are respectively provided between two adjacent photoelectric conversion elements 30 in the first direction Dx and extend in the second direction Dy intersecting the first direction Dx. They are wirings for supplying signals to either the photoelectric conversion element 30 or any one of the plurality of transistors. For example, the output signal line SL(m), the reference signal line SLcom, and the output signal line SL(m + 1) are arranged between two adjacent photoelectric conversion elements 30 in the first direction Dx. In addition, the reset signal line SLrst, the power supply signal line SLsf, and the reset signal line SLrst are arranged between two adjacent photoelectric conversion elements 30 in the first direction Dx. Specifically, the reference signal line SLcom is a wiring for supplying the reference potential Vcom to the photoelectric conversion element 30. In addition, the power supply signal line SLsf is a wiring for supplying the power supply potential Vsf to the source follower transistor Msf. The reset signal line SLrst is a wiring for supplying the reset potential Vrst to the reset transistor Mrst.

[0068] The output signal lines SL(m), SL(m + 1), SL(m + 2), SL(m + 3) are respectively provided corresponding to the detection elements 3(m), 3(m + 1), 3(m + 2), 3(m + 3). Two of the three signal lines other than the output signal line SL (for example, the power supply signal line SLsf and the reference signal line SLcom) are connected to two adjacent detection elements 3 on both sides.

[0069] For example, taking the detection element 3(m + 1) and the detection element 3(m + 2) as an example, the power supply signal line SLsf (the first signal line) among the above three signal lines is arranged between the photoelectric conversion element 30 of the detection element 3(m + 1) (the first detection element) and the photoelectric conversion element 30 of the detection element 3(m + 2) (the second detection element). The detection element 3(m + 2) is adjacent to the detection element 3(m + 1) on one side in the first direction Dx. Then, the power supply signal line SLsf is connected to the two detection elements 3(m + 1), 3(m + 2).

[0070] In addition, the reference signal line SLcom (the second signal line) among the above three signal lines is arranged between the photoelectric conversion element 30 of the detection element 3(m + 1) and the photoelectric conversion element 30 of the detection element 3(m) (the third detection element). The detection element 3(m) is adjacent to the detection element 3(m + 1) on the other side in the first direction Dx. Then, the reference signal line SLcom is connected to the two detection elements 3(m), 3(m + 1).

[0071] Two adjacent detection elements 3 are configured to be flipped with a virtual line parallel to the second direction Dy as the axis of symmetry. For example, the two detection elements 3(m) and the detection element 3(m + 1) are symmetric with respect to the reference signal line SLcom. The two detection elements 3(m + 1) and the detection element 3(m + 2) are symmetric with respect to the power supply signal line SLsf. The two detection elements 3(m + 2) and the detection element 3(m + 3) are symmetric with respect to the reference signal line SLcom.

[0072] More specifically, in the detection element 3(m), the power supply signal line SLsf, the reset signal line SLrst, the photoelectric conversion element 30 (and a plurality of transistors), the output signal line SL(m), and the reference signal line SLcom are arranged in sequence in the first direction Dx. In the detection element 3(m + 1), the reference signal line SLcom, the output signal line SL(m + 1), the photoelectric conversion element 30 (and a plurality of transistors), the reset signal line SLrst, and the power supply signal line SLsf are arranged in sequence in the first direction Dx. Similarly for the detection elements 3(m + 1) and 3(m + 2), the order of the arrangement of each signal line is flipped. The reference signal line SLcom is arranged between two adjacent output signal lines SL(m) and SL(m + 1) in the first direction Dx. In addition, the power supply signal line SLsf is provided between two adjacent reset signal lines SLrst in the first direction Dx.

[0073] In addition, in the detection elements 3 arranged along the first direction Dx, the plurality of photoelectric conversion elements 30 are arranged at equal arrangement intervals Px along the first direction Dx. The arrangement interval Px is set as the interval between the virtual lines CL passing through the midpoints in the first direction Dx of the respective photoelectric conversion elements 30 and parallel to the second direction Dy. In addition, the plurality of photoelectric conversion elements 30 each have an outer shape that is symmetric with respect to the virtual line CL as the axis of symmetry. In addition, in this specification, when expressed as "equal", it also includes substantially equal cases.

[0074] Furthermore, in each detection element 3, the photoelectric conversion element 30 is arranged between two signal lines (for example, the power supply signal line SLsf and the reset signal line SLrst) and two signal lines (for example, the output signal line SL and the reference signal line SLcom) in the first direction Dx. Thus, in each detection element 3, the regions occupied by the four signal lines are symmetric with respect to the virtual line CL as the axis of symmetry.

[0075] As described above, the detection device 1 of the present embodiment can increase the aperture ratio of the detection element 3 by sharing two signal lines among a plurality of signal lines in two adjacent detection elements 3. For example, compared with a structure in which four signal lines (output signal line SL, power supply signal line SLsf, reset signal line SLrst, and reference signal line SLcom) are provided for each detection element 3, the aperture ratio increases by about 15%. In addition, in this specification, the aperture ratio represents the ratio of the area that does not overlap with the wiring and transistors in the area surrounded by two gate lines (reset control scan lines GLrst(N), GLrst(N+1)) and two signal lines (for example, power supply signal line SLsf, reference signal line SLcom).

[0076] In addition, the arrangement pitch Px of the plurality of photoelectric conversion elements 30 is equal, and in each detection element 3, the photoelectric conversion element 30 and the plurality of signal lines are symmetrically formed with respect to the imaginary line CL as the axis of symmetry. Thus, when the arrangement pitch Px is formed to be unequal, the detection device 1 can suppress a decrease in the position accuracy of detection compared to a case where the photoelectric conversion element 30 and the plurality of transistors are arranged adjacent to each other in the first direction Dx and share signal lines, for example.

[0077] Figure 8 It is a plan view showing an enlarged adjacent detection element. Figure 8 An enlarged view shows a part of adjacent detection elements 3(m), 3(m+1), and detection element 3(m+2). As Figure 8 shown, the photoelectric conversion element 30 is configured to include a semiconductor layer having a photovoltaic effect. Specifically, the semiconductor layer of the photoelectric conversion element 30 includes an i-type semiconductor layer 31, an n-type semiconductor layer 32, and a p-type semiconductor layer 33. The i-type semiconductor layer 31, the n-type semiconductor layer 32, and the p-type semiconductor layer 33 are, for example, amorphous silicon (a-Si). In addition, the material of the semiconductor layer is not limited thereto, and may also be polycrystalline silicon, microcrystalline silicon, or the like.

[0078] The n-type semiconductor layer 32 is formed by doping impurities in a-Si to form an n+ region. The p-type semiconductor layer 33 is formed by doping impurities in polycrystalline silicon to form a p+ region. The i-type semiconductor layer 31 is, for example, an undoped intrinsic semiconductor and has a lower conductivity than the n-type semiconductor layer 32 and the p-type semiconductor layer 33.

[0079] Among adjacent detection elements 3(m) and 3(m + 1), two p-type semiconductor layers 33 are connected by a connection wiring 33s. The connection wiring 33s is disposed to cross a reference signal line SLcom and is connected to the reference signal line SLcom via a contact hole H11. Thus, two adjacent photoelectric conversion elements 30 in the first direction Dx are electrically connected to one reference signal line SLcom disposed between the two photoelectric conversion elements 30. A reference potential Vcom is supplied to the p-type semiconductor layers 33 of the two photoelectric conversion elements 30 via the common reference signal line SLcom. In addition, two adjacent photoelectric conversion elements 30 in the first direction Dx are symmetrically disposed with the reference signal line SLcom therebetween.

[0080] A lower conductive layer 35 is provided in a region overlapping with the semiconductor layer of the photoelectric conversion element 30. Among adjacent detection elements 3(m) and 3(m + 1), two lower conductive layers 35 are connected by a connection wiring 35s. The connection wiring 35s overlaps with the connection wiring 33s, is disposed to cross the reference signal line SLcom, and is connected to the reference signal line SLcom via a contact hole H11. Thus, two adjacent lower conductive layers 35 in the first direction Dx are electrically connected to one reference signal line SLcom. The lower conductive layer 35 is supplied with the same reference potential Vcom as the p-type semiconductor layer 33, and parasitic capacitance between the lower conductive layer 35 and the p-type semiconductor layer 33 can be suppressed. In addition, the p-type semiconductor layer 33 (connection wiring 33s) and the lower conductive layer 35 (connection wiring 35s) may be connected to the common reference signal line SLcom at different positions in the second direction Dy.

[0081] The outer shape of the photoelectric conversion element 30 in a plan view is symmetrically formed with an imaginary line CL as an axis of symmetry. In the detection element 3(m + 1), a recess LA is formed at the lower left corner of the photoelectric conversion element 30. The recess LA is set, for example, so that the output signal line SL(m + 1) and the photoelectric conversion element 30 do not interfere with each other according to the routing structure of the output signal line SL(m + 1). A recess RA is formed at the lower right corner of the photoelectric conversion element 30 and at a position symmetric to the recess LA. Thus, the symmetry of the photoelectric conversion element 30 is improved, and the detection position accuracy can be improved.

[0082] In addition, the upper electrode 34 provided on the photoelectric conversion element 30 is connected to the n-type semiconductor layer 32 via the contact hole H1. The connection wiring 34a is connected to the upper electrode 34 and extends in the second direction Dy. The connection wiring 34a is connected to the node N1 via the contact hole. Thus, the cathode (n-type semiconductor layer 32) of the photoelectric conversion element 30 is electrically connected to the reset transistor Mrst and the source follower transistor Msf via the connection wiring 34a and the node N1. The connection wiring 34a can, for example, adopt a stacked structure of molybdenum (Mo) and aluminum (Al). However, it is not limited to this, and the connection wiring 34a can also be other metal materials, or a light-transmitting conductive material such as ITO.

[0083] The reset transistor Mrst, the source follower transistor Msf, and the read transistor Mrd are adjacent to the photoelectric conversion element 30 in the second direction Dy via the read control scanning line GLrd. The three transistors are arranged in a row in the first direction Dx.

[0084] The reset transistor Mrst includes a semiconductor layer 61, a source electrode 62, a drain electrode 63, and a gate electrode 64. One end of the semiconductor layer 61 is connected to the reset signal line SLrst. The other end of the semiconductor layer 61 is connected to the node N1 via the contact hole H3. The portion of the reset signal line SLrst connected to the semiconductor layer 61 functions as the source electrode 62, and the portion of the node N1 connected to the semiconductor layer 61 functions as the drain electrode 63. The gate electrode 64 is formed by branching from the reset control scanning line GLrst in the second direction Dy and intersecting the semiconductor layer 61. A channel region is formed in the portion of the semiconductor layer 61 that overlaps with the gate electrode 64.

[0085] The source follower transistor Msf has a semiconductor layer 65, a source electrode 67, and a gate electrode 68. One end of the semiconductor layer 65 is connected to the connection wiring SLcn via a contact hole. The connection wiring SLcn is electrically connected to the power signal line SLsf via a bridge wiring BG and a contact hole H12. The bridge wiring BG is, for example, provided in the same layer as the gate line (readout control scanning line GLrd, etc.), and intersects with the reset signal line SLrst when viewed from above. The other end of the semiconductor layer 65 is connected to the semiconductor layer 71 of the readout transistor Mrd via a connection wiring CN (node ​​N2).

[0086] The read transistor Mrd has a semiconductor layer 71, a drain electrode 72, and a gate electrode 74. Figure 8In this case, the semiconductor layer 71 is shown separately from the connection wiring CN and the semiconductor layer 65, but the semiconductor layer 65, the semiconductor layer 71, and the connection wiring CN are formed of a continuous semiconductor layer. The other end of the semiconductor layer 71 is connected to the output signal line SL. In other words, the portion of the connection wiring CN (node N2) connected to the semiconductor layer 71 functions as a source electrode, and the portion of the output signal line SL connected to the semiconductor layer 71 functions as a drain electrode 72. The two gate electrodes 74 are portions branched from the read control scan line GLrd. The semiconductor layer 71 intersects the two gate electrodes 74 branched from the read control scan line GLrd. In such a structure, the source follower transistor Msf and the read transistor Mrd are connected to the output signal line SL.

[0087] When looking at adjacent detection elements 3(m) and 3(m + 1), the reset transistor Mrst, the source follower transistor Msf, and the read transistor Mrd are symmetrically arranged with respect to the reference signal line SLcom.

[0088] When looking at adjacent detection elements 3(m + 1) and 3(m + 2), two connection wirings SLcn adjacent in the first direction Dx are connected to a common bridge wiring BG and connected to one power supply signal line SLsf via a contact hole H12. That is, two source follower transistors Msf adjacent in the first direction Dx are connected to one power supply signal line SLsf disposed between the two source follower transistors Msf. The two source follower transistors Msf are symmetrically arranged with respect to the power supply signal line SLsf.

[0089] In addition, Figure 8 The planar structure of the photoelectric conversion element 30 and each transistor shown is only an example and can be appropriately changed. For example, it is not limited to a structure in which a plurality of transistors are arranged in the first direction Dx, and some transistors may be arranged adjacent to other transistors in the second direction Dy, etc., and are provided at different positions.

[0090] Figure 9 is Figure 8 a cross-sectional view taken along IX-IX'. In addition, in Figure 9 the cross-sectional structure of the reset transistor Mrst among the three transistors included in the detection element 3 is shown, but the cross-sectional structures of the source follower transistor Msf and the read transistor Mrd are the same as those of the reset transistor Mrst.

[0091] The substrate 21 is an insulating substrate, such as a glass substrate like quartz or alkali-free glass, or a resin substrate like polyimide. The gate electrode 64 is provided on the substrate 21. The insulating films 22 and 23 are provided on the substrate 21 to cover the gate electrode 64. The insulating films 22, 23, 24, 25, and 26 are inorganic insulating films, such as silicon oxide (SiO2), silicon nitride (SiN), etc.

[0092] The semiconductor layer 61 is provided on the insulating film 23. The semiconductor layer 61 uses, for example, polysilicon. However, the semiconductor layer 61 is not limited thereto, and may also be a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, low-temperature polycrystalline silicon (LTPS: Low Temperature Polycrystalline Silicon), etc. The reset transistor Mrst has a bottom-gate structure in which the gate electrode 64 is provided on the lower side of the semiconductor layer 61, but may also have a top-gate structure in which the gate electrode 64 is provided on the upper side of the semiconductor layer 61, and the gate electrode 64 may also have a double-gate structure provided on both the upper and lower sides of the semiconductor layer 61.

[0093] The semiconductor layer 61 includes a channel region 61a, high-concentration impurity regions 61b and 61c, and low-concentration impurity regions 61d and 61e. The channel region 61a is, for example, undoped intrinsic semiconductor or a low-impurity region, and has lower conductivity than the high-concentration impurity regions 61b and 61c and the low-concentration impurity regions 61d and 61e. The channel region 61a is provided in a region overlapping with the gate electrode 64.

[0094] The high-concentration impurity region 61b is provided in a region connected to the source electrode 62, that is, a region overlapping with the bottom surface of the contact hole H5. The high-concentration impurity region 61c is provided in a region connected to the drain electrode 63, that is, a region overlapping with the bottom surface of the contact hole H3. The low-concentration impurity regions 61d and 61e are respectively provided between the channel region 61a and the high-concentration impurity regions 61b and 61c.

[0095] The insulating films 24 and 25 are provided on the insulating film 23 to cover the semiconductor layer 61. The source electrode 62 and the drain electrode 63 are connected to the semiconductor layer 61 via the contact holes H3 and H5 penetrating the insulating films 24 and 25. The source electrode 62 and the drain electrode 63 are composed of, for example, a stacked film of TiAlTi or TiAl which is a stacked structure of titanium and aluminum.

[0096] The gate electrode 68 of the source follower transistor Msf is provided in the same layer as the gate electrode 64. The drain electrode 63 (node N1) is connected to the gate electrode 68 via a contact hole penetrating from the insulating film 22 through the insulating film 25.

[0097] In addition, the connection wiring SLcn is provided in the same layer as the source electrode 62 (reset signal line SLrst) and the drain electrode 63 (node N1).

[0098] Next, the cross-sectional structure of the photoelectric conversion element 30 will be described. The lower conductive layer 35 is provided on the substrate 21 on the same layer as the gate electrode 64. The insulating films 22 and 23 are provided on the lower conductive layer 35. The photoelectric conversion element 30 is provided on the insulating film 23. In other words, the lower conductive layer 35 is provided between the substrate 21 and the p-type semiconductor layer 33. The lower conductive layer 35 functions as a light-shielding layer by being formed of the same material as the gate electrode 64, and the lower conductive layer 35 can suppress light from invading the photoelectric conversion element 30 from the substrate 21 side.

[0099] In the direction perpendicular to the surface of the substrate 21 (the third direction Dz), the i-type semiconductor layer 31 is provided between the p-type semiconductor layer 33 and the n-type semiconductor layer 32. In the present embodiment, the p-type semiconductor layer 33, the i-type semiconductor layer 31, and the n-type semiconductor layer 32 are sequentially stacked on the insulating film 23.

[0100] Specifically, the p-type semiconductor layer 33 is provided on the insulating film 23 on the same layer as the semiconductor layer 61. The insulating films 24, 25, and 26 are provided so as to cover the p-type semiconductor layer 33. The insulating films 24 and 25 are provided with contact holes H13 at positions overlapping the p-type semiconductor layer 33. The insulating film 26 is provided on the insulating film 25 so as to cover a plurality of transistors including the reset transistor Mrst. The insulating film 26 covers the side surfaces of the insulating films 24 and 25 that constitute the inner wall of the contact hole H13. In addition, in the insulating film 26, a contact hole H14 is provided at a position overlapping the p-type semiconductor layer 33.

[0101] The connection wiring 33s connected to the p-type semiconductor layer 33 and the connection wiring 35s connected to the lower conductive layer 35 respectively extend to positions overlapping the output signal line SL and the reference signal line SLcom. The contact hole H11 is provided so as to penetrate from the insulating film 22 to the insulating film 25, and the connection wiring 33s and the connection wiring 35s are connected to the reference signal line SLcom via the contact hole H11.

[0102] The i-type semiconductor layer 31 is provided on the insulating film 26 and is connected to the p-type semiconductor layer 33 via the contact hole H14 that penetrates the insulating film 26 from the insulating film 24. The n-type semiconductor layer 32 is provided on the i-type semiconductor layer 31.

[0103] The insulating film 27 is provided on the insulating film 26 in such a manner as to cover the photoelectric conversion element 30. The insulating film 27 is provided in such a manner as to be directly in contact with the photoelectric conversion element 30 and the insulating film 26. The insulating film 27 is made of an organic material such as photosensitive acrylic. The insulating film 27 is thicker than the insulating film 26. The insulating film 27 has better step coverage than an inorganic insulating material, and is provided in such a manner as to cover the side surfaces of the i-type semiconductor layer 31 and the n-type semiconductor layer 32. In addition, the insulating film 27 may also be an inorganic insulating film.

[0104] The upper electrode 34 is provided on the insulating film 27. The upper electrode 34 is, for example, a light-transmitting conductive material such as ITO (Indium Tin Oxide). The upper electrode 34 is provided along the surface of the insulating film 27, and is connected to the n-type semiconductor layer 32 via a contact hole H1 provided in the insulating film 27. In addition, the upper electrode 34 is provided in a manner that straddles the upper side of the readout control scanning line GLrd and the connection wiring SLcn, and is electrically connected to the drain electrode 63 and the gate electrode 68 of the reset transistor Mrst via a contact hole H2 provided in the insulating film 27.

[0105] Insulating films 28 and 29 are provided on insulating film 27 so as to cover upper electrode 34. Insulating film 28 is an inorganic insulating film. Insulating film 28 is provided as a protective layer for suppressing the intrusion of moisture toward photoelectric conversion element 30. Insulating film 29 is an organic protective film. Insulating film 29 is formed to flatten the surface of detection device 1.

[0106] The detection device 1 of this embodiment shows a structure in which, among the three signal lines (power signal line SLsf, reset signal line SLrst and reference signal line SLcom) other than the output signal line SL, the power signal line SLsf and the reference signal line SLcom are shared by two adjacent detection elements 3, but is not limited to this.

[0107] For example, among the three signal lines other than the output signal line SL, the power signal line SLsf and the reset signal line SLrst may also be connected to two adjacent detection elements 3. In this case, the power signal line SLsf and the reset signal line SLrst are arranged in the first direction Dx across the photoelectric conversion element 30. In addition, the reference signal line SLcom is provided in units of the photoelectric conversion elements 30 arranged in the first direction Dx. In addition, two reset transistors Mrst adjacent to each other in the first direction Dx are electrically connected to a reset signal line SLrst arranged between the two reset transistors Mrst, and are symmetrically arranged across the reset signal line SLrst.

[0108] Alternatively, among the three signal lines other than the output signal line SL, the reference signal line SLcom and the reset signal line SLrst may also be connected to two adjacent detection elements 3. In this case, the reference signal line SLcom and the reset signal line SLrst are arranged with the photoelectric conversion element 30 therebetween in the first direction Dx. In addition, the power supply signal line SLsf is provided for each detection element 3 arranged in the first direction Dx.

[0109] Furthermore, the planar structure and the cross-sectional structure of the detection element 3 are merely examples and can be appropriately changed. For example, the photoelectric conversion element 30 is not limited to the structure having the concave portion LA, and may be rectangular, polygonal, or other shapes. In addition, the stacking order of the p-type semiconductor layer 33, the i-type semiconductor layer 31, and the n-type semiconductor layer 32 of the photoelectric conversion element 30 may be reversed. The photoelectric conversion element 30 may also be provided on a layer different from the semiconductor layer of each transistor. For example, the photoelectric conversion element 30 may be provided on the insulating film 26.

[0110] As described above, the preferred embodiments of the present invention have been described, but the present invention is not limited to such embodiments. The content disclosed in the embodiments is merely an example, and various changes can be made without departing from the gist of the present invention. Appropriate changes made without departing from the gist of the present invention also naturally belong to the technical scope of the present invention.

[0111] Description of Reference Numerals

[0112] 1: Detection device; 3: Detection element; 10: Sensor unit; 15A: First gate line drive circuit; 15B: Second gate line drive circuit; 16: Signal line selection circuit; 21: Substrate; 22, 23, 24, 25, 26, 27, 28, 29: Insulating film; 30: Photoelectric conversion element; 31: i-type semiconductor layer; 32: n-type semiconductor layer; 33: p-type semiconductor layer; 34: Upper electrode; 34a: Connection wiring; 48: Detection circuit; AA: Detection area; GA: Peripheral area; GLrst: Reset control scan line; GLrd: Read control scan line; SL: Output signal line; SLsf: Power supply signal line; SLrst: Reset signal line; SLcom: Reference signal line; Vsf: Power supply potential; Vcom: Reference potential; Vrst: Reset potential; RST: Reset control signal; RD: Read control signal; Mrst: Reset transistor; Mrd: Read transistor; Msf: Source follower transistor.

Claims

1. A detection device having: a substrate; a plurality of photoelectric conversion elements provided on the substrate and including a semiconductor layer having a photovoltaic effect; a plurality of transistors respectively provided corresponding to the plurality of photoelectric conversion elements; and a plurality of signal lines provided between the plurality of photoelectric conversion elements adjacent in a first direction, extending in a second direction intersecting the first direction, and supplying a signal to any one of the photoelectric conversion elements or the plurality of transistors; one detection element is configured to include the photoelectric conversion element and the plurality of transistors arranged adjacent to the photoelectric conversion element in the second direction; a first signal line among the plurality of signal lines is arranged between the photoelectric conversion element of the first detection element and the photoelectric conversion element of the second detection element, and is connected to the first detection element and the second detection element, and the second detection element is adjacent to the first detection element on one side in the first direction; a second signal line among the plurality of signal lines is arranged between the photoelectric conversion element of the first detection element and the photoelectric conversion element of the third detection element, and is connected to the first detection element and the third detection element, and the third detection element is adjacent to the first detection element on the other side in the first direction; the transistor includes a source follower transistor, a reset transistor, and a readout transistor; the plurality of signal lines include a reset signal line for supplying a reset signal to the reset transistor and a power supply signal line for supplying a power supply potential to the source follower transistor; two source follower transistors adjacent in the first direction are electrically connected to one power supply signal line arranged between the two source follower transistors, and are symmetrically arranged with two reset signal lines and the power supply signal line therebetween.

2. The detection device according to claim 1, wherein the plurality of signal lines include a reference signal line for supplying a reference potential to the photoelectric conversion element; two photoelectric conversion elements adjacent in the first direction are electrically connected to one reference signal line arranged between the two photoelectric conversion elements, and are symmetrically arranged with the reference signal line therebetween.

3. The detection device according to claim 2, wherein the detection device has an output signal line for outputting signals from the plurality of transistors; the reference signal line is arranged between two output signal lines adjacent in the first direction.

4. The detection device according to any one of claims 1 to 3, wherein the plurality of photoelectric conversion elements are arranged along the first direction at equal arrangement intervals.

5. The detection device according to any one of claims 1 to 3, wherein the outer shape of the photoelectric conversion element is symmetric with respect to an imaginary line passing through the midpoint of the photoelectric conversion element in the first direction and parallel to the second direction.

6. The detection device according to any one of claims 1 to 3, wherein each of the detection elements includes a plurality of gate lines extending in the first direction and adjacent in the second direction. A plurality of the transistors are disposed between a plurality of gate lines adjacent in the second direction.

7. The detection device according to any one of claims 1 to 3, wherein the detection device has an output signal line for outputting signals from a plurality of the transistors, a region occupied by the plurality of signal lines and the output signal line is symmetric with respect to an imaginary line passing through the midpoint in the first direction of the photoelectric conversion element and parallel to the second direction.

8. The detection device according to any one of claims 1 to 3, wherein the transistor includes a source follower transistor, a reset transistor, and a readout transistor, the plurality of signal lines include a reset signal line for supplying a reset signal to the reset transistor and a power supply signal line for supplying a power supply potential to the source follower transistor, two source follower transistors adjacent in the first direction are electrically connected to one power supply signal line disposed between the two source follower transistors and are symmetrically disposed with the power supply signal line therebetween.

9. The detection device according to claim 8, wherein the power supply signal line is disposed between two reset signal lines adjacent in the first direction.

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