Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device including: a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of the first conductivity type provided above the base region; a plurality of trench portions arranged in a predetermined arrangement direction on a front surface side of the semiconductor substrate; a trench contact portion provided between two adjacent trench portions of the plurality of trench portions on the front surface side of the semiconductor substrate; and a contact layer of the second conductivity type provided below the trench contact portion and having a higher doping concentration than the base region, the lower end of the trench contact portion being deeper than the lower end of the emitter region, and the emitter region being in contact with the contact layer on a side wall of the trench contact portion.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] Previously, semiconductor devices having trench contacts were known (for example, see Patent Documents 1-3).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2014-158013

[0004] Patent Document 2: Japanese Patent Application Publication No. 2013-065724

[0005] Patent Document 3: International Publication No. 2018 / 052099 Summary of the Invention

[0006] Technical issues

[0007] The aim is to improve the damage resistance of semiconductor devices with trench contacts.

[0008] Technical solution

[0009] In a first aspect of the present invention, a semiconductor device is provided, comprising: a drift region of a first conductivity type disposed on a semiconductor substrate; a base region of a second conductivity type disposed above the drift region; an emitter region of the first conductivity type disposed above the base region; a plurality of trench portions arranged in a predetermined arrangement direction on the front side of the semiconductor substrate; trench contact portions disposed between two adjacent trench portions of the plurality of trench portions on the front side of the semiconductor substrate; and a contact layer of the second conductivity type disposed below the trench contact portions, having a higher doping concentration than the base region, wherein the lower end of the trench contact portion is deeper than the lower end of the emitter region, and the emitter region contacts the contact layer on the sidewall of the trench contact portion.

[0010] In the arrangement direction, the length of the lower end of the emitter region in contact with the base region can be greater than the shortest distance between the contact layer and the adjacent trench portion of the multiple trench portions.

[0011] In the arrangement direction, the maximum distance from the bottom of the sidewall of the groove contact portion to the outer peripheral surface of the contact layer can be greater than the shortest distance between the contact layer and the adjacent groove portion among the multiple groove portions.

[0012] The shortest distance between the contact layer and the adjacent groove portion of the multiple groove portions can be 0.1 μm or more.

[0013] The contact layer may have an extension region that extends further toward the front side of the semiconductor substrate than the lower end of the emitter region.

[0014] The grooved contact portion can have a bottom surface with a generally planar shape.

[0015] The trench contact portion may have a concave bottom surface recessed toward the back side of the semiconductor substrate.

[0016] The contact layer may have: a first contact layer disposed on the sidewall of the groove contact portion; and a second contact layer disposed on the sidewall of the groove contact portion, below the first contact layer.

[0017] The shortest distance between the first contact layer and the adjacent groove of the first contact layer among the plurality of grooves can be greater than the shortest distance between the second contact layer and the adjacent groove of the second contact layer among the plurality of grooves.

[0018] The doping concentration of the first contact layer can be lower than that of the second contact layer.

[0019] The grooved contact portion can be configured to extend along the extension direction of the plurality of groove portions. A contact layer can be provided on the sidewall of the terminal portion at the end of the extension direction of the grooved contact portion.

[0020] The sidewalls of the terminal can be covered by the emission area and the contact layer.

[0021] The sidewall of the terminal can be covered by a region of the second conductivity type.

[0022] A second conductivity type contact region with a higher doping concentration than the base region can be provided on the front side of the semiconductor substrate. The sidewalls of the terminal portion can be covered by the contact region, the base region, and the contact layer.

[0023] A second conductivity type contact region with a higher doping concentration than the base region can be provided on the front side of the semiconductor substrate. The sidewalls of the terminal portion can be covered by the contact region and the contact layer.

[0024] In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: a step of forming a drift region of a first conductivity type on a semiconductor substrate; a step of forming a base region of a second conductivity type above the drift region; a step of forming an emitter region of the first conductivity type above the base region; a step of arranging a plurality of trench portions along a predetermined arrangement direction on the front side of the semiconductor substrate; a step of forming a trench contact portion on the front side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions; and a step of forming a contact layer of the second conductivity type with a doping concentration higher than that of the base region below the trench contact portion, wherein the lower end of the trench contact portion is deeper than the lower end of the emitter region, and the emitter region contacts the contact layer on the sidewall of the trench contact portion.

[0025] A method for manufacturing a semiconductor device may include, after the step of forming contact holes for trench contacts, performing ion implantation to form a contact layer.

[0026] A method for manufacturing a semiconductor device may include: forming an oxide mask over a semiconductor substrate; and using the oxide mask as a mask, performing ion implantation to form a contact layer.

[0027] A method for manufacturing a semiconductor device may include the steps of forming a first contact layer on the sidewall of a trench contact portion; and forming a second contact layer on the sidewall of the trench contact portion, below the first contact layer. The implantation width of the ion implantation used to form the first contact layer may be smaller than the implantation width of the ion implantation used to form the second contact layer.

[0028] A method for manufacturing a semiconductor device may include the steps of forming a first contact layer on the sidewall of a trench contact portion; and forming a second contact layer on the sidewall of the trench contact portion, below the first contact layer. The doping concentration of the first contact layer may be lower than the doping concentration of the second contact layer.

[0029] It should be noted that the above description of the invention does not list all the features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0030] Figure 1A An example of a top view of a semiconductor device 100 according to an embodiment is shown.

[0031] Figure 1B It is shown Figure 1A A diagram of an example of section a-a' in the figure.

[0032] Figure 1C It is shown Figure 1A A diagram of an example of section b-b' in the figure.

[0033] Figure 1D An example of an enlarged view showing the vicinity of the groove contact portion 27 is shown.

[0034] Figure 1E An example of the doping concentration distribution around the trench contact portion 27 is shown.

[0035] Figure 1F An example of a cross-sectional view obtained by magnifying the vicinity of the terminal portion 28 is shown.

[0036] Figure 2 An example of an enlarged view showing the vicinity of the groove contact portion 27 is shown.

[0037] Figure 3 An example of a cross-sectional view obtained by magnifying the vicinity of the terminal portion 28 is shown.

[0038] Figure 4A An example of a top view of a semiconductor device 100 according to an embodiment is shown.

[0039] Figure 4B Showing will Figure 4A An example of a cross-sectional view obtained by magnifying the area near the terminal portion 28.

[0040] Figure 5 An example of a method for manufacturing a single-layer contact layer 19 is shown.

[0041] Figure 6 An example of a method for manufacturing a two-layer contact layer 19 is shown.

[0042] Figure 7 The configuration of the semiconductor device 500 of the comparative example is shown.

[0043] Symbol Explanation

[0044] 10: Semiconductor substrate; 12: Emitter region; 14: Base region; 15: Contact region; 16: Accumulation region; 17: Well region; 18: Drift region; 19: Contact layer; 21: Front side; 22: Collector region; 23: Back side; 24: Collector electrode; 25: Connector portion; 27: Trench contact portion; 28: Termination portion; 29: Sidewall bottom; 30: Dummy trench portion; 31: Extension portion; 32: Dummy insulating film; 33: Connector portion; 34: Dummy conductive portion; 38: Interlayer insulating film; 40: Gate 41: Trench portion; 42: Extension portion; 43: Gate insulating film; 44: Connection portion; 50: Gate conductive portion; 50: Gate metal layer; 52: Emitter electrode; 54: Contact hole; 55: Contact hole; 56: Contact hole; 70: Transistor portion; 71: Mesa portion; 80: Diode portion; 81: Mesa portion; 82: Cathode region; 90: Boundary portion; 91: Mesa portion; 100: Semiconductor device; 500: Semiconductor device; 512: Emitter region; 519: Contact layer; 527: Trench contact portion Detailed Implementation

[0045] The present invention will now be described through embodiments thereof; however, these embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the inventive solution.

[0046] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper" and the other side as "lower". One of the two main surfaces of the substrate, layer or other component is referred to as the upper surface and the other as the lower surface. The directions of "upper", "lower", "front" and "back" are not limited to the direction of gravity or the mounting direction towards the substrate when mounting a semiconductor device.

[0047] In this specification, orthogonal coordinate axes of X, Y, and Z are sometimes used to illustrate technical matters. In this specification, the plane parallel to the upper surface of the semiconductor substrate is designated as the XY plane, and the depth direction of the semiconductor substrate is designated as the Z-axis. It should be noted that in this specification, the view of the semiconductor substrate along the Z-axis direction is referred to as a top view.

[0048] In each embodiment, an example is shown where the first conductivity type is N-type and the second conductivity type is P-type, but it is also possible to set the first conductivity type to P-type and the second conductivity type to N-type. In this case, the conductivity types of the substrate, layer, region, etc., in each embodiment become opposite polarities.

[0049] In this specification, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - markings on n or p indicate that the doping concentration is higher and lower than that of layers or regions without + or - markings, respectively; ++ indicates a higher doping concentration than +, and -- indicates a lower doping concentration than -.

[0050] In this specification, doping concentration refers to the concentration of donor- or acceptor-modified dopants. Therefore, its unit is / cm². 3 In this specification, the concentration difference between donors and acceptors (i.e., net doping concentration) is sometimes used as the doping concentration. In this case, the doping concentration can be determined by the SR method. Alternatively, the chemical concentrations of donors and acceptors can be used as the doping concentration. In this case, the doping concentration can be determined by the SIMS method. Unless otherwise specified, any of the above methods can be used as the doping concentration. Unless otherwise specified, the peak value of the doping concentration distribution in the doped region can be used as the doping concentration in that doped region.

[0051] Furthermore, in this specification, dosage refers to the number of ions implanted per unit area of ​​the wafer during ion implantation. Therefore, its unit is / cm². 2 It should be noted that the dose in the semiconductor region can be set as the integrated concentration obtained by integrating the doping concentration along the depth direction throughout the semiconductor region. The unit of this integrated concentration is / cm². 2 Therefore, the dose and integrated concentration can be treated to be the same. The integrated concentration can be set to the integral value up to the full width at half maximum (FWHM), and can be derived by removing the influence of other semiconductor regions when their spectra overlap with those of other semiconductor regions.

[0052] Therefore, in this specification, the level of doping concentration can be interpreted as the level of dose. That is, if the doping concentration in one region is higher than that in other regions, it can be understood that the dose in that region is higher than that in other regions.

[0053] Figure 1AThis illustration shows an example of a top view of a semiconductor device 100 according to an embodiment. The semiconductor device 100 in this example is a semiconductor chip including a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a reverse-conducting IGBT (RC-IGBT). It should be noted that the semiconductor device 100 can be an IGBT or a MOS transistor.

[0054] The transistor section 70 is a region obtained by projecting the collector region 22, which is disposed on the back side of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The collector region 22 has a second conductivity type. As an example, the collector region 22 in this example is P+ type. The transistor section 70 includes transistors such as IGBTs. The transistor section 70 includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80.

[0055] The diode section 80 is a region obtained by projecting the cathode region 82, which is disposed on the back side of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. As an example, the cathode region 82 in this example is of the N+ type. The diode section 80 includes a diode such as a freewheeling diode disposed adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0056] exist Figure 1A The diagram shows the region surrounding the chip end, which is the edge side of the semiconductor device 100, and other regions are omitted. For example, an edge termination structure may be provided in the region on the negative side of the semiconductor device 100 in the Y-axis direction. The edge termination structure mitigates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure has, for example, a protective ring, a field plate, a surface electric field reducing element, and a structure combining these. It should be noted that, for convenience, the edge on the negative side in the Y-axis direction is described in this example, but the same applies to the other edges of the semiconductor device 100.

[0057] The semiconductor substrate 10 can be a silicon substrate, a silicon carbide substrate, or a gallium nitride or other nitride semiconductor substrate. In this example, the semiconductor substrate 10 is a silicon substrate.

[0058] The semiconductor device 100 of this example has a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front side 21 of the semiconductor substrate 10. The front side 21 will be described later. In addition, the semiconductor device 100 of this example has an emitter electrode 52 and a gate metal layer 50 disposed on the upper part of the front side 21 of the semiconductor substrate 10.

[0059] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. Furthermore, the gate metal layer 50 is disposed above the gate trench portion 40 and the well region 17.

[0060] The emitter electrode 52 and the gate metal layer 50 are formed of a metal-containing material. For example, at least a portion of the emitter electrode 52 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium and / or titanium compounds as a lower layer beneath the regions formed of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are configured to be separated from each other.

[0061] The emitter electrode 52 and the gate metal layer 50 are disposed above the semiconductor substrate 10, separated by an interlayer insulating film 38. The interlayer insulating film 38... Figure 1A The middle part is omitted. Contact holes 54, 55 and 56 are provided in a through manner in the interlayer insulating film 38.

[0062] The contact hole 55 connects the gate metal layer 50 to the gate conductive portion within the transistor section 70. A plug made of tungsten or the like may be formed inside the contact hole 55.

[0063] The contact hole 56 connects the emitting electrode 52 to the dummy conductive part within the dummy trench portion 30. A plug made of tungsten or the like may also be formed inside the contact hole 56.

[0064] The connection portion 25 electrically connects the front-side electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is disposed between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also disposed between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. Here, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is disposed above the front side 21 of the semiconductor substrate 10, separated by an insulating film such as an oxide film.

[0065] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (X-axis direction in this example). The gate trench portions 40 in this example may have two extension portions 41 extending along an extension direction (Y-axis direction in this example) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction. The connection portion 43 connects the two extension portions 41.

[0066] Preferably, at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, the electric field concentration at the ends of the extension portions 41 can be mitigated. In the connection portion 43 of the gate trench portion 40, the gate metal layer 50 can be connected to the gate conductive portion.

[0067] The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Similar to the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). Also similar to the gate trench portion 40, the dummy trench portion 30 in this example may have a U-shape on the front side 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction, and a connecting portion 33 connecting the two extension portions 31.

[0068] The transistor section 70 in this example has a structure in which two gate trench sections 40 and three dummy trench sections 30 are arranged in a repeating pattern. That is, the transistor section 70 in this example has gate trench sections 40 and dummy trench sections 30 in a 2:3 ratio. For example, the transistor section 70 has an extension section 31 between two extension sections 41. Furthermore, the transistor section 70 has two extension sections 31 adjacent to the gate trench sections 40.

[0069] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 to the dummy trench portion 30 can be 1:1 or 2:4. In addition, it can also be configured as a so-called full-gate structure in which the transistor portion 70 is entirely composed of gate trench portions 40 and no dummy trench portions 30 are provided.

[0070] Well region 17 is a second conductivity type region located further on the front side 21 of the semiconductor substrate 10 than the drift region 18 described later. Well region 17 is an example of a well region located on the edge side of the semiconductor device 100. As an example, well region 17 is P+ type. Well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is located. The diffusion depth of well region 17 can be deeper than the depth of gate trench portion 40 and dummy trench portion 30. A portion of the gate trench portion 40 and dummy trench portion 30 on the gate metal layer 50 side is formed in well region 17. The bottom of one end of the extending direction of gate trench portion 40 and dummy trench portion 30 can be covered by well region 17.

[0071] Contact holes 54 are formed in the transistor section 70 above each region of the emitter region 12 and the contact region 15. Furthermore, contact holes 54 are provided above the contact region 15 in the diode section 80. Contact holes 54 are provided above the contact region 15 in the boundary section 90. Contact holes 54 are provided above the base region 14 in the diode section 80. No contact hole 54 is provided above the well regions 17 located at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 can be configured to extend along the extension direction.

[0072] The trench contact 27 electrically connects the emitter electrode 52 to the semiconductor substrate 10. The trench contact 27 is disposed in the contact hole 54. The trench contact 27 is configured to extend along the extension direction.

[0073] The terminal portion 28 is the end portion of the groove contact portion 27 extending in the direction of extension. The terminal portion 28 is disposed in the table surface 71 in the area where the contact area 15 is formed on the front surface 21. The terminal portion 28 may be disposed in the table surface 81 or the table surface 91 in the area where the contact area 15 is formed on the front surface 21.

[0074] The boundary portion 90 is a region disposed on the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact area 15. In this example, the boundary portion 90 does not have an emitter area 12. In one example, the trench portion of the boundary portion 90 is a dummy trench portion 30. In this example, the boundary portion 90 is configured such that both ends in the X-axis direction are dummy trench portions 30.

[0075] Mesa portions 71, 91, and 81 are mesa portions disposed adjacent to the trench portions in a plane parallel to the front surface 21 of the semiconductor substrate 10. A mesa portion can be a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and extends from the front surface 21 of the semiconductor substrate 10 to the deepest bottom of each trench portion. An extension portion of each trench portion can be defined as a single trench portion. That is, the area sandwiched between two extension portions can be defined as a mesa portion.

[0076] The mesa 71 is configured to be adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40 in the transistor portion 70. The mesa 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front side 21 of the semiconductor substrate 10. In the mesa 71, the emitter region 12 and the contact region 15 are alternately arranged in the extending direction.

[0077] A mesa 91 is provided at the boundary portion 90. The mesa 91 has a contact area 15 on the front side 21 of the semiconductor substrate 10. In this example, the mesa 91 has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0078] The mesa portion 81 is disposed in the diode portion 80 in the region sandwiched by the adjacent dummy trench portion 30. The mesa portion 81 has a contact area 15 on the front side 21 of the semiconductor substrate 10. In this example, the mesa portion 81 has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0079] The base region 14 is a region of a second conductivity type disposed on the front side 21 of the semiconductor substrate 10 in the transistor section 70 and the diode section 80. As an example, the base region 14 is P-type. The base region 14 can be disposed at both ends of the mesa 71 and mesa 91 in the Y-axis direction on the front side 21 of the semiconductor substrate 10. It should be noted that... Figure 1A Only one end of the base region 14 in the Y-axis direction is shown.

[0080] Emitter region 12 is a region of the first conductivity type with a higher doping concentration than drift region 18. As an example, emitter region 12 in this example is N+ type. An example of the dopant for emitter region 12 is arsenic (As). Emitter region 12 is configured to contact the gate trench portion 40 on the front side 21 of mesa 71. Emitter region 12 can be configured to extend along the X-axis from one of the two trench portions sandwiching mesa 71 to the other trench portion. Emitter region 12 is also located below contact hole 54.

[0081] Furthermore, the emission area 12 may or may not contact the dummy groove portion 30. In this example, the emission area 12 contacts the dummy groove portion 30. The emission area 12 may not be provided on the platform surface 81 and platform surface 91.

[0082] Contact region 15 is a region of the second conductivity type with a higher doping concentration than the base region 14. As an example, contact region 15 in this example is P+ type. In this example, contact region 15 is disposed on the front surface 21 of mesa 71, mesa 81, and mesa 91. Contact region 15 can be disposed along the X-axis from one of the two trench portions sandwiching mesa 71, mesa 81, or mesa 91 to the other trench portion. Contact region 15 may or may not contact the gate trench portion 40. Furthermore, contact region 15 may or may not contact the dummy trench portion 30. In this example, contact region 15 contacts both the dummy trench portion 30 and the gate trench portion 40. Contact region 15 is also disposed below contact hole 54.

[0083] Figure 1B It is shown Figure 1AThe figure shows an example of the a-a' section. The a-a' section is the XZ plane passing through the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' section. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0084] Drift region 18 is a region of a first conductivity type disposed on semiconductor substrate 10. As an example, drift region 18 in this example is N-type. Drift region 18 can be a region remaining in semiconductor substrate 10 where no other doped regions are formed. That is, the doping concentration of drift region 18 can be the doping concentration of semiconductor substrate 10.

[0085] Buffer 20 is a region of the first conductivity type disposed below drift region 18. As an example, buffer 20 in this example is N-type. The doping concentration of buffer 20 is higher than that of drift region 18. Buffer 20 can function as a field cutoff layer to prevent the depletion layer extending from the lower surface side of base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0086] The collector region 22 is disposed below the buffer zone 20 in the transistor section 70. The cathode region 82 is disposed below the buffer zone 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80.

[0087] The collector electrode 24 is formed on the back side 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal.

[0088] The base region 14 is a second conductivity type region disposed above the drift region 18 in the mesa 71, mesa 91, and mesa 81. The base region 14 is configured to contact the gate trench portion 40. The base region 14 may also be configured to contact the dummy trench portion 30.

[0089] The emitter region 12 is disposed between the base region 14 and the front surface 21. In this example, the emitter region 12 is disposed on the mesa 71, but not on the mesa 81 and mesa 91. The emitter region 12 is configured to contact the gate trench portion 40. The emitter region 12 may or may not contact the dummy trench portion 30.

[0090] Contact area 15 is provided above base area 14 in table surface 81 and table surface 91. Contact area 15 is configured to contact the dummy groove portion 30 in table surface 81 and table surface 91. In other cross sections, contact area 15 may be provided on the front surface 21 of table surface 71.

[0091] The trench contact 27 has a conductive material filling the contact hole 54. The trench contact 27 is disposed between two adjacent trenches in a plurality of trenches. The trench contact 27 is configured to contact the contact layer 19 on the front side 21. In this example, the trench contact 27 is configured to extend through the emitting region 12 from the front side 21. The trench contact 27 may have the same material as the emitting electrode 52.

[0092] The lower end of the trench contact portion 27 is deeper than the lower end of the emitter region 12. By providing the trench contact portion 27, the resistance of the base region 14 is reduced, making it easier to extract minority carriers (e.g., holes). As a result, it is possible to improve the resistance to damage such as latch-up caused by minority carriers.

[0093] The groove contact portion 27 has a generally planar bottom surface. The bottom surface of the groove contact portion 27 is covered by the contact layer 19. In this example, the groove contact portion 27 has a tapered shape with inclined sidewalls. However, the sidewalls of the groove contact portion 27 can also be configured to be generally perpendicular to the front surface 21.

[0094] Contact layer 19 is disposed below trench contact portion 27. Contact layer 19 is a region of the second conductivity type with a higher doping concentration than the base region 14. As an example, contact layer 19 in this example is P+ type. For example, contact layer 19 is formed by ion implantation of boron (B) or boron fluoride (BF2). The doping concentration of contact layer 19 can be the same as the doping concentration of contact region 15. Contact layer 19 suppresses latch-up by extracting minority carriers.

[0095] Contact layer 19 is disposed on the sidewalls and bottom surface of the groove contact portion 27. In this example, contact layer 19 is disposed on each of the table surface 71, table surface 81, and table surface 91. Contact layer 19 can be configured to extend along the Y-axis direction.

[0096] On the sidewall of the trench contact portion 27, the emitting region 12 contacts the contact layer 19. In this example, the sidewall of the trench contact portion 27 is covered by the emitting region 12 and the contact layer 19. That is, the trench contact portion 27 does not contact the base region 14.

[0097] In this example, by connecting the emitter region 12 to the contact layer 19, the injection of charge carriers from the emitter region 12 can be suppressed, thereby improving the damage resistance. Furthermore, even when a large current flows through the semiconductor device 100, the minority carrier extraction efficiency can be improved through the contact layer 19, and the potential of the base region 14 can be stabilized.

[0098] The accumulation region 16 is a first conductivity type region located on the front side 21 of the semiconductor substrate 10, further than the drift region 18. As an example, the accumulation region 16 in this example is N+ type. The accumulation region 16 is provided in both the transistor section 70 and the diode section 80. However, the accumulation region 16 may not be provided.

[0099] Furthermore, the accumulation region 16 is configured to contact the gate trench 40. The accumulation region 16 may or may not contact the dummy trench 30. The doping concentration of the accumulation region 16 is higher than that of the drift region 18. The ion implantation dose of the accumulation region 16 can be 1E12cm⁻¹. -2 Above and 1E13cm -2 Below. Furthermore, the ion implantation dose in accumulation region 16 can also be 3E12cm. -2 Above and 6E12cm -2 The following describes how, by setting the accumulation region 16, the carrier injection enhancement effect (IE effect) can be improved, thereby reducing the turn-on voltage of the transistor section 70. It should be noted that E refers to a power of 10, for example, 1E12cm. -2 It refers to 1×10 12 cm -2 .

[0100] One or more gate trench portions 40 and one or more dummy trench portions 30 are disposed on the front side 21. Each trench portion is configured to extend from the front side 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and accumulation region 16 is disposed, each trench portion also extends through these regions to reach the drift region 18. The trench portion extending through the doped region is not limited to the case where the trench portions are formed after the doped region is formed. The case where the doped region is formed between the trench portions after the trench portions are formed is also included in the case where the trench portion extends through the doped region.

[0101] The gate trench portion 40 has a gate trench formed on the front side 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench at a position closer to the inner side of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front side 21 by an interlayer insulating film 38.

[0102] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces the base region 14 adjacent to the mesa 71 side, separated by the gate insulating film 42. If a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in the base region 14 that contacts the gate trench.

[0103] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench formed on the front side 21, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is located further inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front side 21 by an interlayer insulating film 38.

[0104] An interlayer insulating film 38 is disposed on the front side 21. An emitter electrode 52 is disposed above the interlayer insulating film 38. One or more contact holes 54 are provided on the interlayer insulating film 38 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 can also be configured to penetrate the interlayer insulating film 38.

[0105] Figure 1C It is shown Figure 1A The figure shows an example of the b-b' section. The b-b' section is the XZ plane passing through the contact area 15 in the transistor section 70.

[0106] The platform surface 71 has a base region 14, a contact region 15, an accumulation region 16, and a contact layer 19 in the b-b' section. The platform surface 91, similar to the a-a' section, has a base region 14, a contact region 15, an accumulation region 16, and a contact layer 19. In the b-b' section, the platform surface 71 has the same structure as the platform surface 91. The platform surface 81, similar to the a-a' section, has a base region 14, a contact region 15, an accumulation region 16, and a contact layer 19.

[0107] Figure 1D An example of an enlarged view of the area near the trench contact portion 27 is shown. In this example, the mesa portion 71 between the dummy trench portion 30 and the gate trench portion 40 is used for illustration, but the mesa portion 81 or the mesa portion 91 may also have the same structure.

[0108] Tabletop width W M This refers to the width of the table surface along the X-axis. Table surfaces 71, 81, and 91 can have the same table surface width W. M In this example, the table width W M It is between 0.8μm and 1.5μm.

[0109] The length A is the length at which the lower end of the emitter region 12 contacts the base region 14 in the alignment direction. For example, the length A is greater than 0.1 μm and less than 0.3 μm.

[0110] The length B is the shortest distance between the contact layer 19 and adjacent trench portions among the plurality of trench portions. To form a channel, the contact layer 19 is configured to be separated from adjacent trench portions. For example, the length B is 0.1 μm or more. This avoids interference with the gate threshold voltage Vth and improves damage resistance.

[0111] Length A is greater than length B. That is, the width of the base region 14 through which minority carriers pass is smaller than the lower surface of the emitter region 12. As a result, minority carriers can be easily extracted using the contact layer 19 before they move to the vicinity of the emitter region 12.

[0112] The extension region E is a region in the contact layer 19 that extends further towards the front side 21 than the lower end of the emitter region 12. By providing the extension region E, reliable contact between the emitter region 12 and the contact layer 19 can be achieved. Furthermore, latch-up is more easily suppressed due to the improved minority carrier extraction efficiency.

[0113] The length C is the difference between the upper depth of the contact layer 19 and the lower depth of the emission region 12. That is, the length C refers to the amount by which the extension region E extends into the emission region 12. The larger the length C, the more the contact layer 19 extends into the emission region 12.

[0114] Length D is the maximum distance in the arrangement direction from the bottom 29 of the sidewall of the trench contact portion 27 to the outer peripheral surface of the contact layer 19. In this example, length D is greater than length B. That is, the contact layer 19 extends to a position closer to the trench portion than the bottom 29 of the sidewall of the trench contact portion 27. As a result, minority carriers can be easily guided to the contact layer 19, and the amount of minority carriers passing between the contact layer 19 and the trench portion toward the emission region 12 can be suppressed.

[0115] The trench contact portion 27 has a concave bottom surface recessed towards the back surface 23. In this example, the concave bottom surface of the trench contact portion 27 is recessed from the bottom 29 of the sidewall toward the center of the trench contact portion 27. The bottom surface of the trench contact portion 27 may be concave in an arc shape. The concave bottom surface of the trench contact portion 27 is formed by etching the contact hole 54 for forming the trench contact portion 27.

[0116] The length L1 is the difference between the lower end of the emitter region 12 and the bottom surface of the trench contact portion 27. The larger the length L1, the further the trench contact portion 27 is set to extend from the emitter region 12, making it easier to extract minority carriers. In this example, the semiconductor device 100, by contacting the contact layer 19 with the emitter region 12, can suppress the injection of carriers from the emitter region 12 even when the length L1 is large.

[0117] The length L2 is the distance from the front surface 21 to the upper end of the dummy conductive portion 34 or the upper end of the gate conductive portion 44. When the upper end of the dummy conductive portion 34 or the gate conductive portion 44 has a recess, the length L2 can be the distance from the front surface 21 to the uppermost end of the dummy conductive portion 34 or the gate conductive portion 44. For example, the length L2 is 0.1 μm or more and 0.4 μm or less.

[0118] Depth D12 is the depth from the front side 21 to the lower end of the emitter region 12. For example, depth D12 is 0.3 μm or more and 0.7 μm or less. Depth D12 can be larger than length L2. That is, emitter region 12 is set to extend from the front side 21 to a depth opposite to the dummy conductive portion 34 or the gate conductive portion 44.

[0119] Depth D27 is the depth from the front surface 21 to the bottom surface of the groove contact portion 27. In this example, depth D27 is the depth from the front surface 21 to the lower end of the sidewall of the groove contact portion 27. Depth D27 is greater than depth D12. For example, depth D27 is 0.5 μm or more and 1.0 μm or less.

[0120] Figure 1E This shows an example of the doping concentration distribution around the trench contact portion 27. The vertical axis represents the doping concentration (cm²). -2 The horizontal axis represents the distance (μm) from the top of the contact layer 19 towards the depth. The solid line represents the doping concentration distribution at the Z-Z' position. The dashed line represents the doping concentration of the emitter region 12 at the same depth as the solid line.

[0121] Contact layer 19 is formed by ion implantation across trench contact portion 27. Contact layer 19 has one peak, but may also have multiple peaks. The peak position of contact layer 19 can be formed at a depth deeper than the lower end of emitter region 12. In this example, the peak of contact layer 19 is approximately 1E20cm. -2 .

[0122] It should be noted that the doping concentration distribution in this example is merely one illustration. In order to realize the semiconductor device 100 disclosed in this application, the size and depth of the doping concentration peaks can be appropriately changed.

[0123] Figure 1F An example of a cross-sectional view obtained by magnifying the vicinity of the terminal portion 28 is shown. This figure shows the XZ plane through the terminal portion 28.

[0124] The sidewall of the terminal portion 28 of the trench contact portion 27 is covered by a region of the second conductivity type. In this example, the sidewall of the terminal portion 28 of the trench contact portion 27 is covered by the contact area 15 and the contact layer 19. Thus, the contact layer 19 can be configured to contact the transmitting area 12 or to contact the contact area 15.

[0125] The length A' is the length at which the lower end of the contact area 15 contacts the base area 14 in the alignment direction. For example, the length A' is greater than 0.1 μm and less than 0.3 μm.

[0126] Depth D15 is the depth from the front side 21 to the lower end of the contact area 15. For example, depth D15 is 0.3 μm or more and 0.7 μm or less. Depth D15 can be greater than length L2. Furthermore, depth D15 can be the same as or different from depth D12 of the emission area 12.

[0127] Figure 2 An example of an enlarged view of the area near the groove contact portion 27 is shown. In this example, the contact layer 19 includes two contact layers: contact layer 19a and contact layer 19b. Contact layer 19a is an example of a first contact layer, and contact layer 19b is an example of a second contact layer.

[0128] A contact layer 19a is provided on the sidewall of the trench contact portion 27. The contact layer 19a is configured to contact the emission region 12. The contact layer 19a has an extension region E that extends further towards the front side 21 than the lower end of the emission region 12. Even when the trench contact portion 27 is configured to protrude from the emission region 12 toward the back side 23, the contact layer 19a still contacts the emission region 12. Therefore, minority carrier extraction efficiency can be improved while latch-up can be suppressed.

[0129] Contact layer 19b is disposed on the sidewall of trench contact portion 27 below contact layer 19a. Contact layer 19b is disposed on the sidewall of trench contact portion 27 in a manner that it contacts contact layer 19a. That is, the sidewall of trench contact portion 27 is covered by emission area 12, contact layer 19a, and contact layer 19b.

[0130] The doping concentration of contact layer 19a can be the same as that of contact layer 19b. Furthermore, the doping concentrations of contact layers 19a and 19b can also be the same as the doping concentration of contact region 15. Additionally, the doping concentration of contact layer 19a can be lower than that of contact layer 19b.

[0131] Length B1 is the shortest distance between contact layer 19a and adjacent trench portions among the plurality of trench portions. Length B2 is the shortest distance between contact layer 19b and adjacent trench portions among the plurality of trench portions. Length B1 is greater than length B2. Therefore, contact layer 19b can reliably extract minority carriers.

[0132] Figure 3 This shows an example of a cross-sectional view magnified near the terminal portion 28. The view shows the XZ plane through the terminal portion 28. In this example, [the view is related to...]. Figure 1D The differences in the cross-sectional views are explained in detail.

[0133] The sidewall of the terminal portion 28 is covered by a region of the second conductivity type. In this example, a contact layer 19 is provided on the sidewall of the terminal portion 28. The sidewall of the terminal portion 28 is covered by the base region 14, the contact region 15, and the contact layer 19. Thus, when the contact region 15 is provided on the front side 21, the contact layer 19 can be configured to be separate from the contact region 15.

[0134] Figure 4A An example top view of a semiconductor device 100 according to an embodiment is shown. The semiconductor device 100 in this example is... Figure 1A The difference in the top view is that the terminal portion 28 of the front 21 is located in the transmitting area 12. In this example, for... Figure 1A The differences between the top view and the top view are explained in detail.

[0135] The base region 14 is disposed adjacent to the transmitting region 12 in the stage surface 71. The transmitting region 12 and the contact region 15 are disposed alternately along the Y-axis direction on the front surface 21. In this example, the terminal portion 28 is disposed in the area where the transmitting region 12 is formed.

[0136] Figure 4B Showing will Figure 4A An example of a cross-sectional view magnified near the terminal portion 28. This view shows the XZ plane through the terminal portion 28. In this example, the semiconductor device 100 and... Figure 1F The difference in the cross-sectional view is that a transmitting area 12 is provided on the front side 21 of the terminal 28. In this example, for... Figure 1F The differences in the cross-sectional views are explained in detail.

[0137] The sidewall of the terminal portion 28 of the groove contact portion 27 is covered by the emission area 12 and the contact layer 19. For example... Figure 4B As shown, the contact layer 19 is configured to contact the emission region 12.

[0138] Figure 5 An example of a method for manufacturing a single-layer contact layer 19 is shown.

[0139] In step S100, an emitter region 12 and a base region 14 are formed on the semiconductor substrate 10. In addition, an interlayer insulating film 38 is formed on the upper surface of the emitter region 12 on the front side 21.

[0140] In step S102, a contact hole 54 is formed by etching through the emitter region 12 to the base region 14. Here, an oxide mask is formed above the semiconductor substrate 10 by etching the interlayer insulating film 38.

[0141] In step S104, the interlayer insulating film 38 is used as a mask for ion implantation to form the contact layer 19. The dashed lines indicate the regions where dopants of the contact layer 19 have been implanted.

[0142] In step S106, a contact layer 19 is formed by heat treatment. The contact layer 19 can be configured to extend towards the emission region 12 by heat treatment. Thus, the emission region 12 contacts the contact layer 19 on the sidewall of the trench contact portion 27.

[0143] It should be noted that in this example, after the contact hole 54 of the trench contact portion 27 is provided, ion implantation is performed to form the contact layer 19. That is, the interlayer insulating film 38 is used as a mask to perform ion implantation of the dopant of the contact layer 19, thus improving the positional alignment accuracy of the contact layer 19 relative to the trench contact portion 27.

[0144] Figure 6 An example of a method for manufacturing a two-layer contact layer 19 is shown.

[0145] In step S200, dopant for forming contact layer 19a is implanted. The dashed lines indicate the regions where dopant for contact layer 19a is implanted.

[0146] In step S202, the contact layer 19a is activated by heat treatment. The heat treatment for activating the contact layer 19a can be omitted, and it can be performed together with the contact layer 19b.

[0147] In step S204, the contact hole 54 is formed by etching through the emitter region 12 to the base region 14. A portion of the contact layer 19a remains on the sidewall of the contact hole 54.

[0148] In step S206, the dopant used to form contact layer 19b is ion implanted and then heat-treated. Contact layer 19b is formed below contact layer 19a. The dashed lines indicate the regions where the dopant of contact layer 19b is implanted.

[0149] The implantation width of the ion implantation used to form contact layer 19a can be smaller than the implantation width of the ion implantation used to form contact layer 19b. Furthermore, the doping concentration of contact layer 19a can be smaller than the doping concentration of contact layer 19b. Therefore, it is possible to form contact layer 19b over a larger area than contact layer 19a.

[0150] Figure 7 The configuration of a comparative example semiconductor device 500 is shown. In this example, a configuration similar to... Figure 1A The cross-sectional diagram corresponding to section a-a'.

[0151] The contact layer 519 is separated from the emitter region 512 on the sidewall of the trench contact portion 527. Therefore, in the semiconductor device 500, it is difficult to suppress the injection of charge carriers from the emitter region 512.

[0152] In contrast, in the semiconductor device 100, since the contact layer 19 is in contact with the emitter region 12, the injection of charge carriers from the emitter region 12 can be suppressed, thereby improving the damage resistance.

[0153] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. According to the claims, such modifications or improvements can obviously also be included within the technical scope of the present invention.

[0154] It should be noted that the execution order of actions, sequences, steps, and stages in the apparatus, systems, procedures, and methods shown in the claims, description, and drawings can be implemented in any order, unless specifically stated as "before," "before," etc., and unless the results of previous processes are used in subsequent processes. Even if the flow of actions in the claims, description, and drawings is described using terms such as "firstly," "nextly," etc. for convenience, this does not imply that the actions must be performed in that order.

Claims

1. A semiconductor device, characterized in that, have: A drift region of the first conductivity type is disposed on a semiconductor substrate; The base region of the second conductivity type is disposed above the drift region; The emitter region of the first conductivity type is disposed above the base region; Multiple trench portions are arranged along a predetermined arrangement direction on the front side of the semiconductor substrate; A trench contact portion is disposed on the front side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions; as well as A second conductivity contact layer is disposed below the trench contact portion, and its doping concentration is higher than that of the base region. The lower end of the groove contact portion is deeper than the lower end of the emission region. The emission region is exposed on the front side of the semiconductor substrate on the sidewall of the trench contact portion. On the sidewall of the groove contact portion, the emission area contacts the contact layer. In the arrangement direction, the maximum distance from the bottom of the sidewall of the groove contact portion to the outer peripheral surface of the contact layer is greater than the shortest distance between the contact layer and the adjacent groove portion of the plurality of groove portions.

2. The semiconductor device according to claim 1, characterized in that, In the arrangement direction, the length of the lower end of the emission region in contact with the base region is greater than the shortest distance between the contact layer and the groove portion adjacent to the contact layer among the plurality of groove portions.

3. The semiconductor device according to claim 1, characterized in that, The shortest distance between the contact layer and the adjacent groove portion of the plurality of groove portions is 0.1 μm or more.

4. The semiconductor device according to claim 1, characterized in that, The contact layer has an extension region that extends further toward the front side of the semiconductor substrate than the lower end of the emitter region.

5. The semiconductor device according to claim 1, characterized in that, The groove contact portion has a generally planar bottom surface.

6. The semiconductor device according to claim 1, characterized in that, The trench contact portion has a concave bottom surface recessed toward the back side of the semiconductor substrate.

7. The semiconductor device according to claim 1, characterized in that, The contact layer has: A first contact layer is disposed on the sidewall of the groove contact portion; and The second contact layer is disposed on the sidewall of the groove contact portion, below the first contact layer.

8. The semiconductor device according to claim 7, characterized in that, In the arrangement direction, the shortest distance between the first contact layer and the groove portion adjacent to the first contact layer among the plurality of groove portions is greater than the shortest distance between the second contact layer and the groove portion adjacent to the second contact layer among the plurality of groove portions.

9. The semiconductor device according to claim 7, characterized in that, The doping concentration of the first contact layer is lower than that of the second contact layer.

10. The semiconductor device according to claim 1, characterized in that, The groove contact portion is configured to extend along the extension direction of the plurality of groove portions. The contact layer is provided on the sidewall of the terminal portion at the end of the extension direction of the groove contact portion.

11. The semiconductor device according to claim 10, characterized in that, The sidewall of the terminal is covered by the transmitting area and the contact layer.

12. The semiconductor device according to claim 10, characterized in that, The sidewall of the terminal is covered by a region of the second conductivity type.

13. The semiconductor device according to claim 12, characterized in that, The semiconductor device has a contact region of a second conductivity type on the front side of the semiconductor substrate, which has a higher doping concentration than the base region. The sidewall of the terminal is covered by the contact area, the base area, and the contact layer.

14. The semiconductor device according to claim 12, characterized in that, The semiconductor device has a contact region of a second conductivity type on the front side of the semiconductor substrate, which has a higher doping concentration than the base region. The sidewall of the terminal is covered by the contact area and the contact layer.

15. The semiconductor device according to claim 1, characterized in that, The semiconductor device has an accumulation region of a first conductivity type, which is disposed on the front side of the semiconductor substrate of the drift region and has a doping concentration greater than that of the drift region.

16. A semiconductor device, characterized in that, have: A drift region of the first conductivity type is disposed on a semiconductor substrate; The base region of the second conductivity type is disposed above the drift region; The emitter region of the first conductivity type is disposed above the base region; Multiple trench portions are arranged along a predetermined arrangement direction on the front side of the semiconductor substrate; A trench contact portion is disposed on the front side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions; as well as A second conductivity contact layer is disposed below the trench contact portion, and its doping concentration is higher than that of the base region. The lower end of the groove contact portion is deeper than the lower end of the emission region. The emission region is exposed on the front side of the semiconductor substrate on the sidewall of the trench contact portion. On the sidewall of the groove contact portion, the emission area contacts the contact layer. The contact layer has: A first contact layer is disposed on the sidewall of the groove contact portion; as well as The second contact layer is disposed below the first contact layer on the sidewall of the groove contact portion. In the arrangement direction, the shortest distance between the first contact layer and the groove portion adjacent to the first contact layer among the plurality of groove portions is greater than the shortest distance between the second contact layer and the groove portion adjacent to the second contact layer among the plurality of groove portions.

17. The semiconductor device according to claim 16, characterized in that, In the arrangement direction, the length of the lower end of the emission region in contact with the base region is greater than the shortest distance between the contact layer and the groove portion adjacent to the contact layer among the plurality of groove portions.

18. The semiconductor device according to claim 16, characterized in that, The shortest distance between the contact layer and the adjacent groove portion of the plurality of groove portions is 0.1 μm or more.

19. The semiconductor device according to claim 16, characterized in that, The contact layer has an extension region that extends further toward the front side of the semiconductor substrate than the lower end of the emitter region.

20. The semiconductor device according to claim 16, characterized in that, The groove contact portion has a generally planar bottom surface.

21. The semiconductor device according to claim 16, characterized in that, The trench contact portion has a concave bottom surface recessed toward the back side of the semiconductor substrate.

22. The semiconductor device according to claim 16, characterized in that, The doping concentration of the first contact layer is lower than that of the second contact layer.

23. The semiconductor device according to claim 16, characterized in that, The groove contact portion is configured to extend along the extension direction of the plurality of groove portions. The contact layer is provided on the sidewall of the terminal portion at the end of the extension direction of the groove contact portion.

24. The semiconductor device according to claim 23, characterized in that, The sidewall of the terminal is covered by the transmitting area and the contact layer.

25. The semiconductor device according to claim 23, characterized in that, The sidewall of the terminal is covered by a region of the second conductivity type.

26. The semiconductor device according to claim 25, characterized in that, The semiconductor device has a contact region of a second conductivity type on the front side of the semiconductor substrate, which has a higher doping concentration than the base region. The sidewall of the terminal is covered by the contact area, the base area, and the contact layer.

27. The semiconductor device according to claim 25, characterized in that, The semiconductor device has a contact region of a second conductivity type on the front side of the semiconductor substrate, which has a higher doping concentration than the base region. The sidewall of the terminal is covered by the contact area and the contact layer.

28. The semiconductor device according to claim 16, characterized in that, The semiconductor device has an accumulation region of a first conductivity type, which is disposed on the front side of the semiconductor substrate of the drift region and has a doping concentration greater than that of the drift region.

29. A semiconductor device, characterized in that, have: A drift region of the first conductivity type is disposed on a semiconductor substrate; The base region of the second conductivity type is disposed above the drift region; The emitter region of the first conductivity type is disposed above the base region; Multiple trench portions are arranged along a predetermined arrangement direction on the front side of the semiconductor substrate; A trench contact portion is disposed on the front side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions; as well as A second conductivity contact layer is disposed below the trench contact portion, and its doping concentration is higher than that of the base region. The lower end of the groove contact portion is deeper than the lower end of the emission region. The emission region is exposed on the front side of the semiconductor substrate on the sidewall of the trench contact portion. On the sidewall of the groove contact portion, the emission area contacts the contact layer. The contact layer has: A first contact layer is disposed on the sidewall of the groove contact portion; as well as The second contact layer is disposed below the first contact layer on the sidewall of the groove contact portion. The doping concentration of the first contact layer is lower than that of the second contact layer.

30. The semiconductor device according to claim 29, characterized in that, In the arrangement direction, the length of the lower end of the emission region in contact with the base region is greater than the shortest distance between the contact layer and the groove portion adjacent to the contact layer among the plurality of groove portions.

31. The semiconductor device according to claim 29, characterized in that, The shortest distance between the contact layer and the adjacent groove portion of the plurality of groove portions is 0.1 μm or more.

32. The semiconductor device according to claim 29, characterized in that, The contact layer has an extension region that extends further toward the front side of the semiconductor substrate than the lower end of the emitter region.

33. The semiconductor device according to claim 29, characterized in that, The groove contact portion has a generally planar bottom surface.

34. The semiconductor device according to claim 29, characterized in that, The trench contact portion has a concave bottom surface recessed toward the back side of the semiconductor substrate.

35. The semiconductor device according to claim 29, characterized in that, The groove contact portion is configured to extend along the extension direction of the plurality of groove portions. The contact layer is provided on the sidewall of the terminal portion at the end of the extension direction of the groove contact portion.

36. The semiconductor device according to claim 35, characterized in that, The sidewall of the terminal is covered by the transmitting area and the contact layer.

37. The semiconductor device according to claim 35, characterized in that, The sidewall of the terminal is covered by a region of the second conductivity type.

38. The semiconductor device according to claim 37, characterized in that, The semiconductor device has a contact region of a second conductivity type on the front side of the semiconductor substrate, which has a higher doping concentration than the base region. The sidewall of the terminal is covered by the contact area, the base area, and the contact layer.

39. The semiconductor device according to claim 37, characterized in that, The semiconductor device has a contact region of a second conductivity type on the front side of the semiconductor substrate, which has a higher doping concentration than the base region. The sidewall of the terminal is covered by the contact area and the contact layer.

40. The semiconductor device according to claim 29, characterized in that, The semiconductor device has an accumulation region of a first conductivity type, which is disposed on the front side of the semiconductor substrate of the drift region and has a doping concentration greater than that of the drift region.

41. A method for manufacturing a semiconductor device, characterized in that, include: The step of setting a drift region of a first conductivity type on a semiconductor substrate; The step of setting a base region of a second conductivity type above the drift region; The step of setting an emitter region of a first conductivity type above the base region; The step of arranging and providing a plurality of trench portions along a predetermined arrangement direction on the front side of the semiconductor substrate; The step of providing a trench contact portion on the front side of the semiconductor substrate between two adjacent trench portions in the plurality of trench portions; The step of providing a second conductivity type contact layer with a higher doping concentration than the base region below the trench contact portion; The step of forming a first contact layer on the sidewall of the groove contact portion; as well as In the step of forming a second contact layer below the first contact layer on the sidewall of the groove contact portion, The lower end of the groove contact portion is deeper than the lower end of the emission region. The emission region is exposed on the front side of the semiconductor substrate on the sidewall of the trench contact portion. On the sidewall of the groove contact portion, the emission area contacts the contact layer. The implantation width of the ion implantation used to form the first contact layer is smaller than the implantation width of the ion implantation used to form the second contact layer.

42. The method for manufacturing a semiconductor device according to claim 41, characterized in that, The method for manufacturing the semiconductor device includes, after the step of providing contact holes for the trench contact portion, performing ion implantation to form the contact layer.

43. The method for manufacturing a semiconductor device according to claim 41, characterized in that, The method for manufacturing the semiconductor device includes: The step of forming an oxide film mask over the semiconductor substrate; and The step of using the oxide film mask as a mask to perform ion implantation to form the contact layer.

44. The method for manufacturing a semiconductor device according to claim 41, characterized in that, The method for manufacturing the semiconductor device includes: The step of forming a first contact layer on the sidewall of the groove contact portion; and In the step of forming a second contact layer below the first contact layer on the sidewall of the groove contact portion, The doping concentration of the first contact layer is lower than that of the second contact layer.

45. The method for manufacturing a semiconductor device according to claim 41, characterized in that, The method for manufacturing the semiconductor device includes the step of forming an accumulation region of a first conductivity type on the front side of the semiconductor substrate in the drift region, where the doping concentration is greater than that of the drift region.

46. ​​A method for manufacturing a semiconductor device, characterized in that, include: The step of setting a drift region of a first conductivity type on a semiconductor substrate; The step of setting a base region of a second conductivity type above the drift region; The step of setting an emitter region of a first conductivity type above the base region; The step of arranging and providing a plurality of trench portions along a predetermined arrangement direction on the front side of the semiconductor substrate; The step of providing a trench contact portion on the front side of the semiconductor substrate between two adjacent trench portions in the plurality of trench portions; The step of providing a second conductivity type contact layer with a higher doping concentration than the base region below the trench contact portion; The step of forming a first contact layer on the sidewall of the groove contact portion; as well as In the step of forming a second contact layer below the first contact layer on the sidewall of the groove contact portion, The lower end of the groove contact portion is deeper than the lower end of the emission region. The emission region is exposed on the front side of the semiconductor substrate on the sidewall of the trench contact portion. On the sidewall of the groove contact portion, the emission area contacts the contact layer. The doping concentration of the first contact layer is lower than that of the second contact layer.

47. The method for manufacturing a semiconductor device according to claim 46, characterized in that, The method for manufacturing the semiconductor device includes, after the step of providing contact holes for the trench contact portion, performing ion implantation to form the contact layer.

48. The method for manufacturing a semiconductor device according to claim 46, characterized in that, The method for manufacturing the semiconductor device includes: The step of forming an oxide film mask over the semiconductor substrate; and The step of using the oxide film mask as a mask to perform ion implantation to form the contact layer.

49. The method for manufacturing a semiconductor device according to claim 46, characterized in that, The method for manufacturing the semiconductor device includes the step of forming an accumulation region of a first conductivity type on the front side of the semiconductor substrate in the drift region, where the doping concentration is greater than that of the drift region.

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