Power conversion device

Abstract

A power conversion device (40) includes: a full-bridge circuit (50) having a series connection of a first switch (Q1) and a second switch (Q2) and a series connection of a third switch (Q3) and a fourth switch (Q4), and connected to power transmission side terminals (CH1, CL1); a power conversion circuit (70, 110, 120, 130) connected to power reception side terminals (CH2, CL2); a transformer (80) having a power transmission side coil (81) connected to the full-bridge circuit and a power reception side coil (83) connected to the power conversion circuit; and a control unit (100) that alternately turns on the first switch and the second switch and alternately turns on the third switch and the fourth switch. The power reception side terminals are connected to a resistive load (30). The lower the detected voltage (V3r) of the power reception side terminals, the smaller the phase difference (λ1) set by the control unit between the timing of switching the first switch to the on operation and the timing of switching the third switch to the on operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on Japanese Patent Application No. 2019-181705 filed on Oct. 1, 2019, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to a power conversion device. BACKGROUND ART

[0004] Conventionally, as described in, for example, Patent Document 1, a power conversion device is known that includes a power transmission side terminal and a power reception side terminal, and outputs power input from the power transmission side terminal from the power reception side terminal. Specifically, the power conversion device includes a full-bridge circuit, a power conversion circuit, a transformer, and a control unit. The full-bridge circuit has a series connection body of a first switch and a second switch and a series connection body of a third switch and a fourth switch. The series connection bodies are connected to the power transmission side terminal. In addition, the power conversion circuit is connected to the power reception side terminal.

[0005] The transformer has a power transmission side coil and a power reception side coil. The power transmission side coil is connected to the full-bridge circuit, the power reception side coil is connected to the power conversion circuit, and is magnetically coupled to the power transmission side coil.

[0006] The control unit alternately turns on the first switch and the second switch, and alternately turns on the third switch and the fourth switch. Thereby, the power input from the power transmission side terminal is output from the power reception side terminal via the full-bridge circuit, the transformer, and the power conversion circuit.

[0007] PRIOR ART DOCUMENTS

[0008] PATENT DOCUMENTS

[0009] Patent Document 1: Japanese Patent No. 6140602 SUMMARY OF THE INVENTION

[0010] Here, the power reception side terminal is sometimes connected to a resistive load such as a heater. In this case, compared with the case where, for example, a battery is connected to the power reception side terminal, the voltage of the power reception side terminal becomes a low voltage (for example, 0 V). As a result, when the power input from the power transmission side terminal is output from the power reception side terminal, the difference in the effective value of the voltage of the power transmission side coil and the effective value of the voltage of the power reception side coil becomes large, and an overcurrent may flow through the transformer, the power conversion circuit, and the resistive load.

[0011] A main object of the present invention is to provide a power conversion device capable of suppressing an overcurrent from flowing through a transformer, a power conversion circuit, and a resistive load.

[0012] The present disclosure relates to a power conversion device. The power conversion device includes a power transmission side terminal and a power reception side terminal, and the power reception side terminal is connected to a resistive load. The power conversion device includes:

[0013] A full-bridge circuit having a series connection of a first switch and a second switch and a series connection of a third switch and a fourth switch, and these series connections are connected to the power transmission side terminal;

[0014] A power conversion circuit connected to the power reception side terminal;

[0015] A transformer having a power transmission side coil and a power reception side coil, the power transmission side coil is connected to the full-bridge circuit, the power reception side coil is connected to the power conversion circuit, and is magnetically coupled to the power transmission side coil;

[0016] A power reception side voltage sensor for detecting the voltage of the power reception side terminal; and

[0017] A control unit that alternately turns on the first switch and the second switch, and alternately turns on the third switch and the fourth switch.

[0018] The lower the detected voltage of the power reception side terminal, the smaller the phase difference between the time when the control unit switches the first switch to the on operation and the time when the third switch is switched to the on operation is set.

[0019] The smaller the phase difference between the time when the first switch is switched to the on operation and the time when the third switch is switched to the on operation, the smaller the difference between the effective value of the voltage of the power transmission side coil and the effective value of the voltage of the power reception side coil can be reduced. In view of this, in the present disclosure, the lower the detected voltage of the power reception side terminal, the smaller the phase difference is set. Thereby, it is possible to suppress an overcurrent from flowing through the transformer, the power conversion circuit, and the resistive load. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above object, other objects, features, and advantages of the present disclosure can be made more apparent by referring to the drawings and the following detailed description. The drawings are as follows.

[0021] Figure 1 is a diagram showing a power conversion device according to the first embodiment.

[0022] Figure 2 is a block diagram showing the processing contents of the control unit.

[0023] Figure 3 is a timing diagram showing the operation states of the switches and the transition of the transformer voltage.

[0024] Figure 4 It is a diagram of the complex plane showing the suppression effect of overcurrent.

[0025] Figure 5 It is a timing diagram showing the transitions of the transformer current, transformer voltage, etc. of the first embodiment.

[0026] Figure 6 It is a timing diagram showing the transitions of the transformer current, transformer voltage, etc. of the comparative example.

[0027] Figure 7 It is a timing diagram showing the operating states of the respective switches and the transition of the transformer voltage in a modified example of the first embodiment.

[0028] Figure 8 It is a diagram showing the power conversion device of the second embodiment.

[0029] Figure 9 It is a timing diagram showing the operating states of the respective switches and the transition of the transformer voltage.

[0030] Figure 10 It is a diagram showing the power conversion device of the third embodiment.

[0031] Figure 11 It is a diagram showing the power conversion device of the fourth embodiment.

[0032] Figure 12 It is a timing diagram showing the operating states of the respective switches and the transition of the transformer voltage.

[0033] Figure 13 It is a diagram showing the power conversion device of the fifth embodiment.

[0034] Figure 14 It is a timing diagram showing the operating states of the respective switches and the transition of the transformer voltage. Detailed Embodiments

[0035] <First Embodiment>

[0036] Hereinafter, with reference to the drawings, a first embodiment in which the power conversion device of the present disclosure is embodied will be described. The power conversion device of this embodiment is a multi-port type and is installed in an electrified vehicle such as a plug-in hybrid vehicle (PHEV) or an electric vehicle (EV), for example.

[0037] As Figure 1 shown, the power supply system includes a first battery 10, a second battery 20, a resistive load 30, and a power conversion device 40. Each of the batteries 10 and 20 is a rechargeable secondary battery, for example, a lithium-ion battery or a nickel-metal hydride battery. The rated voltage of the second battery 20 is, for example, 200V.

[0038] The power conversion device 40 includes a first full-bridge circuit 50. The first full-bridge circuit 50 includes a first switch Q1 to a fourth switch Q4 and a first capacitor 51. In the present embodiment, the first switch Q1 to the fourth switch Q4 are N-channel MOSFETs. The drains of the first switch Q1 and the third switch Q3 are connected to the first high-potential side terminal CH1 of the power conversion device 40. The source of the first switch Q1 is connected to the drain of the second switch Q2, and the source of the third switch Q3 is connected to the drain of the fourth switch Q4. The sources of the second switch Q2 and the fourth switch Q4 are connected to the first low-potential side terminal CL1 of the power conversion device 40. The first high-potential side terminal CH1 is connected to the first end of the first capacitor 51 and the positive terminal of the first storage battery 10, and the first low-potential side terminal CL1 is connected to the second end of the first capacitor 51 and the negative terminal of the first storage battery 10.

[0039] Alternatively, instead of the first storage battery 10, the first high-potential side terminal CH1 and the first low-potential side terminal CL1 may be connected to the output side of an ACDC converter that converts AC power input from an external power source into DC power and outputs it. Additionally, in the present embodiment, the first high-potential side terminal CH1 and the first low-potential side terminal CL1 correspond to the "power transmission side terminals".

[0040] The power conversion device 40 includes a second full-bridge circuit 60. The second full-bridge circuit 60 includes a fifth switch Q5 to an eighth switch Q8 and a second capacitor 61. In the present embodiment, the fifth switch Q5 to the eighth switch Q8 are N-channel MOSFETs. The drains of the fifth switch Q5 and the seventh switch Q7 are connected to the second high-potential side terminal CH2 of the power conversion device 40. The source of the fifth switch Q5 is connected to the drain of the sixth switch Q6, and the source of the seventh switch Q7 is connected to the drain of the eighth switch Q8. The sources of the sixth switch Q6 and the eighth switch Q8 are connected to the second low-potential side terminal CL2 of the power conversion device 40. The second high-potential side terminal CH2 is connected to the first end of the second capacitor 61 and the positive terminal of the second storage battery 20, and the second low-potential side terminal CL2 is connected to the second end of the second capacitor 61 and the negative terminal of the second storage battery 20.

[0041] The power conversion device 40 includes a third full-bridge circuit 70 (equivalent to the "power conversion circuit"). The third full-bridge circuit 70 includes the ninth switch Q9 to the twelfth switch Q12 and the third capacitor 71. In the present embodiment, the ninth switch Q9 to the twelfth switch Q12 are N-channel MOSFETs. The drains of the ninth switch Q9 and the eleventh switch Q11 are connected to the third high-potential side terminal CH3 of the power conversion device 40. The source of the ninth switch Q9 is connected to the drain of the tenth switch Q10, and the source of the eleventh switch Q11 is connected to the drain of the twelfth switch Q12. The sources of the tenth switch Q10 and the twelfth switch Q12 are connected to the third low-potential side terminal CL3 of the power conversion device 40. The third high-potential side terminal CH3 is connected to the first end of the third capacitor 71 and the first end of the resistive load 30, and the third low-potential side terminal CL3 is connected to the second end of the third capacitor 71 and the second end of the resistive load 30. In addition, in the present embodiment, the third high-potential side terminal CH3 and the third low-potential side terminal CL3 are equivalent to the "power receiving side terminals". In addition, the ninth switch Q9 to the twelfth switch Q12 are equivalent to the "first conversion switch to the fourth conversion switch".

[0042] The resistive load 30 has a resistor that electrically connects the third high-potential side terminal CH3 and the third low-potential side terminal CL3. In the present embodiment, the resistive load 30 is a heater that generates heat by energizing the resistor. The resistive load 30 is an electrical device that does not have a voltage higher than 0V starting from before the start of the power conversion device 40, such as a storage battery. In the present embodiment, only the resistive load 30 is connected to the third high-potential side terminal CH3 and the third low-potential side terminal CL3, and no storage battery is connected. In addition, the resistive load 30 is not limited to a heater.

[0043] The power conversion device 40 includes a transformer 80. The transformer 80 has a first coil 81 (equivalent to the "power transmission side coil"), a second coil 82, and a third coil 83 (equivalent to the "power receiving side coil"). The first end of the first coil 81 is connected to the source of the first switch Q1 and the drain of the second switch Q2, and the second end of the first coil 81 is connected to the source of the third switch Q3 and the drain of the fourth switch Q4. The first end of the second coil 82 is connected to the source of the fifth switch Q5 and the drain of the sixth switch Q6, and the second end of the second coil 82 is connected to the source of the seventh switch Q7 and the drain of the eighth switch Q8. The first end of the third coil 83 is connected to the source of the ninth switch Q9 and the drain of the tenth switch Q10, and the second end of the third coil 83 is connected to the source of the eleventh switch Q11 and the drain of the twelfth switch Q12.

[0044] The first coil 81, the second coil 82, and the third coil 83 are magnetically coupled to each other via, for example, the iron core included in the transformer 80. When the potential of the first end of the first coil 81 becomes higher than the potential of the second end, induced voltages are respectively generated in the second coil 82 and the third coil 83 such that the potential of their first ends is higher than the potential of their second ends. On the other hand, when the potential of the second end of the first coil 81 becomes higher than the potential of the first end, induced voltages are respectively generated in the second coil 82 and the third coil 83 such that the potential of their second ends is higher than the potential of their first ends.

[0045] The power conversion device 40 includes first to third voltage sensors 91 to 93 and first to third current sensors 94 to 96. The first voltage sensor 91 detects the terminal voltage of the first capacitor 51, i.e., the first voltage V1r. The second voltage sensor 92 detects the terminal voltage of the second capacitor 61, i.e., the second voltage V2r. The third voltage sensor 93 detects the terminal voltage of the third capacitor 71, i.e., the third voltage V3r. In addition, in the present embodiment, the first voltage sensor 91 corresponds to the "power transmission side voltage sensor", and the third voltage sensor 93 corresponds to the "power reception side voltage sensor".

[0046] The first current sensor 94 detects the current flowing through the first high-potential side terminal CH1, i.e., the first current I1r. The second current sensor 95 detects the current flowing between the second full-bridge circuit 60 and the second high-potential side terminal CH2, i.e., the second current I2r. The third current sensor 96 detects the current flowing between the third full-bridge circuit 70 and the third high-potential side terminal CH3, i.e., the third current I3r. In the present embodiment, the sign of the first current I1r flowing through the first high-potential side terminal CH1 in the direction from the positive terminal of the first battery 10 toward the first full-bridge circuit 50 is defined as positive. The sign of the second current I2r flowing through the second high-potential side terminal CH2 in the direction from the second full-bridge circuit 60 toward the second battery 20 is defined as positive. The sign of the third current I3r flowing through the third high-potential side terminal CH3 in the direction from the third full-bridge circuit 70 toward the resistive load 30 is defined as positive.

[0047] The detection values of the respective sensors 91 to 96 are input to the control unit 100 included in the power conversion device 40. The control unit 100 turns on / off the first switch Q1 to the twelfth switch Q12. Hereinafter, Figure 2 , the operation method will be described. Figure 2 is a block diagram of the processing executed by the control unit 100.

[0048] The control unit 100 includes a first command current calculation unit 200 and a first current control unit 210. The first command current calculation unit 200 includes a first current calculation unit 201 and a first minimum value selection unit 202. The first current calculation unit 201 calculates a command value of the charging current flowing in the second battery 20, that is, a command current I2p, by dividing the input second command power P2* by the second voltage V2r detected by the second voltage sensor 92. The command current I2p is set to supply power to the second battery 20 through constant power control (CP). When the sign of the command current I2p is positive, the current flows through the second high potential side terminal CH2 on the side where the second battery 20 is charged. In addition, when the second command power P2* input to the first command current calculation unit 200 is 0, the command current I2p is 0.

[0049] The first minimum value selection unit 202 selects the smaller one of the command current I2p calculated by the first current calculation unit 201 and the second constant current command value I2* as the second command current Iref2. The second constant current command value I2* is set to supply power to the second battery 20 through constant current control (CC). The second command current Iref2 output from the first minimum value selection unit 202 has its upper limit value or lower limit value restricted by a limiter 203.

[0050] The first current control unit 210 includes a first current deviation calculation unit 211, a first feedback control unit 212, and a first limiter 213. The first current deviation calculation unit 211 calculates a second current deviation ΔI2 by subtracting the second current I2r detected by the second current sensor 95 from the second command current Iref2 output from the limiter 203.

[0051] The first feedback control unit 212 calculates a first command phase φa as an operation amount for feedback controlling the calculated second current deviation ΔI2 to 0. In the present embodiment, proportional-integral control is used as this feedback control. The first command phase φa will be described later. In addition, the feedback control used in the first feedback control unit 212 is not limited to proportional-integral control, and for example, proportional-integral-derivative control may also be used.

[0052] The first command phase φa calculated by the first feedback control unit 212 has its upper limit value or lower limit value restricted by the first limiter 213 and is input to the PWM generation unit 320 included in the control unit 100.

[0053] The control unit 100 includes a second command current calculation unit 300 and a second current control unit 310. The second command current calculation unit 300 includes a second current calculation unit 301, an addition unit 302, a feedback control unit 303, and a second minimum value selection unit 304. The second current calculation unit 301 calculates a command current I3p flowing through the third high potential side terminal CH3 by dividing the input third command power P3* by the third voltage V3r detected by the third voltage sensor 93. The command current I3p is set to supply power to the resistive load 30 and the third capacitor 71 through constant power control (CP). When the sign of the command current I3p is positive, the current flows through the third high potential side terminal CH3 in the direction from the third high potential side terminal CH3 toward the resistive load 30.

[0054] The addition unit 302 calculates a voltage deviation ΔV by subtracting the third voltage V3r from the target value V3* of the applied voltage of the resistive load 30 and the third capacitor 71. The feedback control unit 303 calculates a command current I3v as an operation amount for feedback controlling the calculated voltage deviation ΔV to 0. In the present embodiment, proportional integral control is used as this feedback control. The command current I3v is set to supply power to the resistive load 30 and the third capacitor 71 through constant voltage control (CV). In addition, the feedback control used in the feedback control unit 303 is not limited to proportional integral control, and for example, proportional integral derivative control may also be used.

[0055] The second minimum value selection unit 304 selects the minimum value among the command current I3p calculated by the second current calculation unit 301, the command current I3v calculated by the feedback control unit 303, and the third constant current command value I3* as the third command current Iref3. The third constant current command value I3* is set to supply power to the resistive load 30 and the third capacitor 71 through constant current control. The third command current Iref3 output from the second minimum value selection unit 304 is limited in upper limit value or lower limit value by the limiter 305.

[0056] The second current control unit 310 includes a second current deviation calculation unit 311, a second feedback control unit 312, and a second limiter 313. The second current deviation calculation unit 311 calculates a third current deviation ΔI3 by subtracting the third current I3r detected by the third current sensor 96 from the third command current Iref3 output from the limiter 305.

[0057] The second feedback control unit 312 calculates a second command phase φb as an operation amount for feedback - controlling the calculated third current deviation ΔI3 to 0. In the present embodiment, proportional - integral control is used as this feedback control. The second command phase φb will be described later. In addition, the feedback control used in the second feedback control unit 312 is not limited to proportional - integral control, and for example, proportional - integral - derivative control may also be used.

[0058] The second command phase φb calculated by the second feedback control unit 312 is limited to an upper limit value or a lower limit value by the second limiter 313 and input to the PWM generation unit 320. In addition, in the present embodiment, the second command current calculation unit 300, the limiter 305, and the second current control unit 310 correspond to the "second calculation unit".

[0059] The control unit 100 includes a phase calculation unit 400. The phase calculation unit 400 calculates a first specified time δ1 to a third specified time δ3. In addition, in the present embodiment, the third specified time δ3 is 0.

[0060] The first specified time δ1 (≥0) is represented by the following formula (eq1). In the following formula (eq1), Ts represents a switching period of one of the first switch Q1 to the twelfth switch Q12, N1 represents the number of turns of the first coil 81, and N3 represents the number of turns of the third coil 83.

[0061] [Mathematical formula 1]

[0062]

[0063] In the present embodiment, since "N1 = N2", the above formula (eq1) becomes the following formula (eq2).

[0064] [Mathematical formula 2]

[0065]

[0066] The second specified time δ2 (≥0) is represented by the following formula (eq3). In the following formula (eq3), N2 represents the number of turns of the second coil 82.

[0067] [Mathematical formula 3]

[0068]

[0069] In the present embodiment, since "N2 = N3", the above formula (eq3) becomes the following formula (eq4).

[0070] [Mathematical formula 4]

[0071]

[0072] Hereinafter, the calculation methods of the first specified time δ1 and the second specified time δ2 will be described.

[0073] In the phase calculation unit 400, the first multiplication unit 401 calculates "Ts×V3r / (2×V1r)" based on the first voltage V1r, the third voltage V3r, and the switching period Ts. The first calculation unit 402 calculates the first specified time δ1 by subtracting the calculated value of the first multiplication unit 401 from Ts / 2. The calculated first specified time δ1 is input to the PWM generation unit 320. Additionally, in this embodiment, the first multiplication unit 401 and the first calculation unit 402 correspond to the "first calculation unit".

[0074] The second multiplication unit 403 calculates "Ts×V3r / (2×V2r)" based on the second voltage V2r, the third voltage V3r, and the switching period Ts. The second calculation unit 404 calculates the second specified time δ2 by subtracting the calculated value of the second multiplication unit 403 from Ts / 2. The calculated second specified time δ2 is input to the PWM generation unit 320.

[0075] The PWM generation unit 320 generates operation signals for each of the switches Q1 to Q12 based on the first command phase φa, the second command phase φb, the first specified time δ1, the second specified time δ2, and the third specified time δ3 (=0), and outputs them to the gates of the respective switches Q1 to Q12. Hereinafter, Figure 3 the operation modes of each of the switches Q1 to Q12 will be described.

[0076] Figure 3 (a) and (b) of represent the transitions of the operation states of the first switch Q1 to the fourth switch Q4, Figure 3 and (c) of represents the transition of the voltage Vt1 of the first coil 81. Figure 3 (d) and (e) of represent the transitions of the operation states of the fifth switch Q5 to the eighth switch Q8, Figure 3 and (f) of represents the transition of the voltage Vt2 of the second coil 82. Figure 3 (g) and (h) of represent the transitions of the operation states of the ninth switch Q9 to the twelfth switch Q12, Figure 3 and (i) of represents the transition of the voltage Vt3 of the third coil 83.

[0077] The first switch Q1 and the second switch Q2 are alternately turned on, and the third switch Q3 and the fourth switch Q4 are alternately turned on. Additionally, with respect to the moment when the first switch Q1 switches to on, the moment when the third switch Q3 switches to off is delayed by the first specified time δ1. That is, when "Ts / 2 - δ1" is set as the first phase difference λ1, with respect to the moment when the first switch Q1 switches to on, the moment when the third switch Q3 switches to on is advanced by the first phase difference λ1.

[0078] As represented by the above formula (eq2), the first specified time δ1 depends on the first voltage V1r and the third voltage V3r. Specifically, the lower the first voltage V1r, the shorter the first specified time δ1 becomes. In addition, the first specified time δ1 becomes 0 when "V3r / V1r" is 1, and the smaller "V3r / V1r" is relative to 1, the longer the first specified time δ1 is.

[0079] The first phase difference λ1 is "Ts / 2×(V3r / V1r)", becomes Ts / 2 when "V3r / V1r" is 1, and the smaller "V3r / V1r" is, the smaller the first phase difference λ1 is.

[0080] The fifth switch Q5 and the sixth switch Q6 are alternately turned on, and the seventh switch Q7 and the eighth switch Q8 are alternately turned on. In addition, the moment when the seventh switch Q7 switches to off is delayed by the second specified time δ2 with respect to the moment when the fifth switch Q5 switches to on. That is, when "Ts / 2-δ2" is set as the second phase difference λ2, the moment when the seventh switch Q7 switches to on is advanced by the second phase difference λ2 with respect to the moment when the fifth switch Q5 switches to on.

[0081] As represented by the above formula (eq4), the second specified time δ1 depends on the second voltage V2r and the third voltage V3r. Specifically, the lower the second voltage V2r, the shorter the second specified time δ2 becomes. In addition, the second specified time δ2 becomes 0 when "V3r / V2r" is 1, and the smaller "V3r / V2r" is relative to 1, the longer the second specified time δ2 is.

[0082] The second phase difference λ2 is "Ts / 2×(V3r / V2r)", becomes Ts / 2 when "V3r / V2r" is 1, and the smaller "V3r / V2r" is, the smaller the second phase difference λ2 is.

[0083] The moment delayed by δ1 / 2 from the moment when the first switch Q1 switches to on is set as the reference moment. When the first command phase φa is positive, the moment delayed by δ2 / 2 from the moment when the fifth switch Q5 switches to on is delayed by the first command phase φa with respect to the reference moment.

[0084] The ninth switch Q9 and the eleventh switch Q11 are alternately turned on, and the eleventh switch Q11 and the twelfth switch Q12 are alternately turned on. In addition, with respect to the moment when the ninth switch Q9 switches to on, the moment when the tenth switch Q10 switches to off is delayed by a third specified time δ3. That is, when “Ts / 2−δ3” is set as the third phase difference λ3, with respect to the moment when the ninth switch Q9 switches to on, the moment when the eleventh switch Q11 switches to on is advanced by the third phase difference λ3. In the present embodiment, since the third specified time δ3 is 0, the moment when the ninth switch Q9 switches to on is synchronized with the moment when the eleventh switch Q11 switches to off. In addition, the ninth switch Q9 and the tenth switch Q10 are alternately turned on every half of the switching period Ts / 2, and the eleventh switch Q11 and the twelfth switch Q12 are alternately turned on every half of the switching period Ts / 2.

[0085] When the second command phase φb is positive, the moment that is delayed by δ3 / 2 from the moment when the ninth switch Q9 switches to on is delayed by the second command phase φb with respect to the reference moment. In the present embodiment, since the third specified time δ3 is 0, the moment when the ninth switch Q9 switches to on is delayed by the second command phase φb with respect to the reference moment.

[0086] According to Figure 3 the operation method of the switch shown, for power transmission, the phase of the voltage Vt2 of the second coil 82 with respect to the phase of the voltage Vt1 of the first coil 81 is controlled to be the first command phase φa, and the phase of the voltage Vt3 of the third coil 83 with respect to the voltage Vt1 of the first coil 81 is controlled to be the second command phase φb.

[0087] In addition, since the first specified time δ1 is adjusted based on the first voltage V1r and the third voltage V3r, the lower the third voltage V3r is with respect to the first voltage V1r, the smaller the difference between the effective value of the voltage Vt1 of the first coil 81 and the effective value of the voltage Vt3 of the third coil 83 becomes. As a result, by supplying power from the first storage battery 10 via the first full-bridge circuit 50 and the third full-bridge circuit 70 to the resistive load 30 and the third capacitor 71, it is possible to suppress an overcurrent from flowing through the transformer 80, the third full-bridge circuit 70, the resistive load 30, and the third capacitor 71.

[0088] In addition, the second specified time δ2 is adjusted based on the second voltage V2r and the third voltage V3r. Therefore, the lower the third voltage V3r is relative to the second voltage V2r, the smaller the difference between the effective value of the voltage Vt2 of the second coil 82 and the effective value of the voltage Vt3 of the third coil 83 becomes. As a result, by supplying power from the second battery 20 to the resistive load 30 and the third capacitor 71 via the second full-bridge circuit 60 and the third full-bridge circuit 70, it is possible to suppress an overcurrent from flowing through the transformer 80, the third full-bridge circuit 70, the resistive load 30, and the third capacitor 71.

[0089] Figure 4 It is a diagram for explaining the suppression of overcurrent using a current vector in the complex plane. Figure 4 (a) thereof shows the case of the present embodiment, Figure 4 and (b) thereof shows the case of a comparative example. The comparative example is a configuration in which the first specified time δ1 and the second specified time δ2 are set to 0. In Figure 4 , I2 represents the current vector flowing through the resistive load 30 and the third capacitor 71 when power is supplied from the second battery 20 to the resistive load 30 and the third capacitor 71 via the second full-bridge circuit 60 and the third full-bridge circuit 70. I3 represents the current vector flowing through the resistive load 30 and the third capacitor 71 when power is supplied from the first battery 10 to the resistive load 30 and the third capacitor 71 via the first full-bridge circuit 50 and the third full-bridge circuit 70. As shown in the figure, in the present embodiment, compared with the comparative example, the current vectors I2 and I3 become smaller.

[0090] Figure 5 It shows the transition of each waveform of the present embodiment. Figure 5 (a) thereof shows the transition of the current of the transformer 80, Figure 5 and (b) thereof shows the transition of the voltage of the transformer 80, Figure 5 and (c) thereof shows the transition of the third voltage V3r. In addition, in Figure 5 (a), IL1 represents the current flowing through the first coil 81, IL2 represents the current flowing through the second coil 82, and IL3 represents the current flowing through the third coil 83.

[0091] According to the present embodiment, after the power conversion device 40 is started, it is possible to perform pre-charging of the third capacitor 71 without the currents IL1 to IL3 exceeding the overcurrent threshold OC.

[0092] In contrast, in Figure 6 the case of the comparative example shown, immediately after starting, the current IL3 exceeds the overcurrent threshold OC, and a shutdown due to overcurrent is performed. Therefore, the pre-charging of the third capacitor 71 cannot be completed, and the third voltage V3r cannot be controlled to the target value V3*.

[0093] According to the embodiment described in detail above, the following effects can be obtained.

[0094] The lower the third voltage V3r is, the smaller the first phase difference λ1 is set. Thus, the pre-charging of the third capacitor 71 can be completed without causing an overcurrent to flow through the transformer 80, the third full-bridge circuit 70, the resistive load 30, and the third capacitor 71.

[0095] In particular, in this embodiment, the smaller "V3r / V1r" is, the smaller the first phase difference λ1 is set. Therefore, even if the voltages of the first capacitor 51 and the third capacitor 71 change respectively, the flow of overcurrent can be reliably suppressed.

[0096] The ninth switch Q9 and the tenth switch Q10 are alternately turned on, and the eleventh switch Q11 and the twelfth switch Q12 are alternately turned on. In addition, the time when the ninth switch Q9 switches to the on state and the time when the eleventh switch Q11 switches to the on state are staggered by Ts / 2. Thereby, the power transmission efficiency from the first storage battery 10 to the resistive load 30 can be improved.

[0097] The time when the ninth switch Q9 switches to the on state is delayed compared with the time when the first switch Q1 switches to the on state. Thereby, it is possible to prevent current from flowing backward from the third high-potential side terminal CH3 and the third low-potential side terminal CL3 side through the third full-bridge circuit 70 and the transformer 80 to the first full-bridge circuit 50 side.

[0098] <Modification Example of the First Embodiment>

[0099] · As Figure 7 shown, the third specified time δ3 may also be greater than 0. However, it is desirable that the third specified time δ3 be small.

[0100] · In the calculation of the first specified time δ1, instead of using the first voltage V1r among the first voltage V1r and the third voltage V3r, a fixed value determined in advance may be used, for example. In addition, in the calculation of the second specified time δ2, instead of using the second voltage V2r among the second voltage V2r and the third voltage V3r, a fixed value determined in advance may be used, for example.

[0101] <Second Embodiment>

[0102] Hereinafter, with reference to the drawings, the second embodiment will be described centering on the differences from the first embodiment. In this embodiment, as Figure 8 shown, instead of the third full-bridge circuit 70, a half-bridge circuit 110 is used. In Figure 8 for convenience, the same reference numerals are given to the structures that are the same as the structures shown previously in Figure 1 shown. In addition, in Figure 8In the figure, illustrations of the respective current sensors 94 to 96 are omitted.

[0103] The half-bridge circuit 110 includes a ninth switch Q9, a tenth switch Q10, a first auxiliary capacitor 111, and a second auxiliary capacitor 112. The drain of the ninth switch Q9 and the first end of the first auxiliary capacitor 111 are connected to the third high-potential side terminal CH3. The source of the ninth switch Q9 is connected to the drain of the tenth switch Q10 and the first end of the third coil 83. The second end of the first auxiliary capacitor 111 is connected to the first end of the second auxiliary capacitor 112 and the second end of the third coil 83. The source of the tenth switch Q10 and the second end of the second auxiliary capacitor 112 are connected to the third low-potential side terminal CL3.

[0104] In Figure 9 the operation modes of the respective switches Q1 to Q10 are described. Figure 9 (a) to (f), (i) of Figure 3 correspond to (a) to (f), (i) of the previous Figure 9 (g), (h) of

[0105] The ninth switch Q9 and the tenth switch Q10 are alternately turned on. When the second command phase φb is positive, the timing at which the ninth switch Q9 is switched to the on state is delayed by the second command phase φb with respect to the reference timing.

[0106] According to the present embodiment described above, the number of switches of the half-bridge circuit 110 can be reduced compared to the number of switches of the third full-bridge circuit 70 of the first embodiment.

[0107] <Third Embodiment>

[0108] Hereinafter, with reference to the drawings, the third embodiment will be described centering on the differences from the second embodiment. In the present embodiment, as Figure 10 shown, an asymmetric half-bridge circuit 120 is used. In Figure 10 for convenience, the same symbols are assigned to the structures that are the same as the structures shown in the previous Figure 8 . In addition, in Figure 10 the illustrations of the respective current sensors 94 to 96 are omitted.

[0109] The half-bridge circuit 120 includes a ninth switch Q9, a tenth switch Q10, and an auxiliary capacitor 121. The drain of the ninth switch Q9 is connected to the third high-potential side terminal CH3. The source of the ninth switch Q9 is connected to the drain of the tenth switch Q10 and the first end of the third coil 83. The second end of the third coil 83 is connected to the first end of the auxiliary capacitor 121. The second end of the auxiliary capacitor 121 and the source of the tenth switch Q10 are connected to the third low-potential side terminal CL3.

[0110] In addition, the operation modes of the switches Q1 to Q10 in the present embodiment are the same as those in the previous Figure 9 shown.

[0111] According to the present embodiment described above, the same effects as those of the second embodiment can be achieved.

[0112] <Fourth Embodiment>

[0113] Hereinafter, with reference to the drawings, the fourth embodiment will be described centering on the differences from the first embodiment. In the present embodiment, as Figure 11 shown, the structure of the third full-bridge circuit 130 is changed. In Figure 11 , for convenience, the same symbols are assigned to the structures that are the same as those in the previous Figure 1 shown. In addition, in Figure 11 , the illustration of each current sensor 94 to 96 is omitted.

[0114] The third full-bridge circuit 130 includes ninth switches Q9 to twelfth switches Q12 and a flying capacitor 131. The drain of the ninth switch Q9 is connected to the third high-potential side terminal CH3. The source of the ninth switch Q9 is connected to the drain of the eleventh switch Q11 and the first end of the flying capacitor 131. The source of the eleventh switch Q11 is connected to the first end of the third coil 83 and the drain of the twelfth switch Q12. The second end of the flying capacitor 131 is connected to the second end of the third coil 83 and the drain of the tenth switch Q10. The sources of the tenth switch Q10 and the twelfth switch Q12 are connected to the third low-potential side terminal CL3.

[0115] In Figure 12 , the operation modes of the switches Q1 to Q12 will be described. Figure 12 (a) to (i) of Figure 3 correspond to (a) to (i) of the previous

[0116] According to the present embodiment described above, the voltage applied to the switches Q9 to Q12 constituting the third full-bridge circuit 130 can be reduced. Thus, for example, switches with a lower withstand voltage can be used as the switches Q9 to Q12.

[0117] <Fifth Embodiment>

[0118] Hereinafter, with reference to the drawings, the fifth embodiment will be described centering on the differences from the first embodiment. In the present embodiment, as Figure 13 shown, the power conversion device 40 includes a fourth full-bridge circuit 140. In Figure 13 , for convenience, for those that are the same as the previous Figure 1Structures with the same structure as shown are labeled with the same symbols. Additionally, in Figure 13 the illustration of each current sensor is omitted.

[0119] The fourth full-bridge circuit 140 includes the thirteenth switch Q13 to the sixteenth switch Q16 and the fourth capacitor 141. In the present embodiment, the thirteenth switch Q13 to the sixteenth switch Q16 are N-channel MOSFETs. The drains of the thirteenth switch Q13 and the fifteenth switch Q15 are connected to the fourth high-potential side terminal CH4 of the power conversion device 40. The source of the thirteenth switch Q13 is connected to the drain of the fourteenth switch Q14, and the source of the fifteenth switch Q15 is connected to the drain of the sixteenth switch Q16. The sources of the fourteenth switch Q14 and the sixteenth switch Q16 are connected to the fourth low-potential side terminal CL4 of the power conversion device 40. The fourth high-potential side terminal CH4 is connected to the first end of the fourth capacitor 141 and the positive terminal of the third battery 21, and the fourth low-potential side terminal CL4 is connected to the second end of the fourth capacitor 141 and the negative terminal of the third battery 21. In the present embodiment, the rated voltage (e.g., 48V) of the third battery 21 is lower than the rated voltage (e.g., 200V) of the second battery 20.

[0120] The transformer 80 further includes a fourth coil 84. The first end of the fourth coil 84 is connected to the source of the thirteenth switch Q13 and the drain of the fourteenth switch Q14, and the second end of the fourth coil 84 is connected to the source of the fifteenth switch Q15 and the drain of the sixteenth switch Q16. The fourth coil 84 is magnetically coupled to the first coil 81 to the third coil 83 via an iron core, for example. When the potential of the first end of the first coil 81 becomes higher than the potential of the second end, an induced voltage is generated in the fourth coil 81 such that the potential of its first end is higher than the potential of the second end.

[0121] The power conversion device 40 includes a fourth voltage sensor 97. The fourth voltage sensor 97 detects the terminal voltage of the fourth capacitor 141, i.e., the fourth voltage V4r. The detected fourth voltage V4r is input to the control unit 100. The control unit 100 turns on / off the first switch Q1 to the sixteenth switch Q16.

[0122] The phase calculation unit 400 of the present embodiment calculates a fourth specified time δ4. The fourth specified time δ4 (≥0) is represented by the following equation (eq5). In the following equation (eq5), N4 represents the number of turns of the fourth coil 84.

[0123] [Mathematical formula 5]

[0124]

[0125] In the present embodiment, since "N3 = N4", the above equation (eq5) becomes the following equation (eq6).

[0126] [Equation 6]

[0127]

[0128] Use Figure 14 , the operation modes of each of the switches Q1 to Q16 will be described. Figure 14 (a) to (i) of Figure 3 corresponds to (a) to (i) of Figure 14 (j) and (k) of represent the transitions of the operation states of the thirteenth switch Q13 to the sixteenth switch Q16, Figure 14 (m) of represents the transition of the voltage Vt4 of the fourth coil 84.

[0129] The thirteenth switch Q13 and the fourteenth switch Q14 are alternately turned on, and the fifteenth switch Q15 and the sixteenth switch Q16 are alternately turned on. In addition, with respect to the timing at which the thirteenth switch Q13 switches to the on state, the timing at which the fifteenth switch Q15 switches to the off state is delayed by a fourth specified time δ4. That is, when “Ts / 2 - δ4” is set as the fourth phase difference λ4, with respect to the timing at which the thirteenth switch Q13 switches to the on state, the timing at which the fifteenth switch Q15 switches to the on state is advanced by the fourth phase difference λ4. In addition, when the first command phase φa is positive, the timing at which the timing of switching the thirteenth switch Q13 to the on state is delayed by δ4 / 2 is delayed by a third command phase φc (>0) with respect to the reference timing. Similar to the first command phase φa, the third command phase φc is a value set for transmitting power from the first battery 10 to the third battery 21 via the transformer 80 and the fourth full-bridge circuit 140.

[0130] According to the present embodiment described above, the same effects as those of the first embodiment can be achieved.

[0131] <Other Embodiments>

[0132] The control unit and the method of the control unit described in the present disclosure can also be implemented by a dedicated computer provided by configuring a processor and a memory, and the above processor is programmed to execute one or more functions embodied by a computer program. Alternatively, the control unit and the method of the control unit described in the present disclosure can be implemented by a dedicated computer provided by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the control unit and the method of the control unit described in the present disclosure can be implemented by one or more dedicated computers provided by a combination of a processor programmed to execute one or more functions and a memory and a processor configured with one or more hardware logic circuits. In addition, the computer program can also be stored in a computer-readable non-transitory tangible storage medium as instructions to be executed by a computer.

[0133] Although the present disclosure has been described based on embodiments, it should be understood that the present disclosure is not limited to the above-described embodiments and structures. The present disclosure also includes various modifications and variations within an equivalent range. In addition, various combinations, manners, and further combinations and manners including only one element, more than one, or less than one also fall within the scope and spirit of the present disclosure.

Claims

1. A power conversion device, the power conversion device includes a power transmission side terminal and a power reception side terminal, and the power reception side terminal is connected to a resistive load. The power conversion device includes: A full-bridge circuit, the full-bridge circuit has a series connection body of a first switch and a second switch and a series connection body of a third switch and a fourth switch, and these series connection bodies are connected to the power transmission side terminal; A power conversion circuit, the power conversion circuit is connected to the power reception side terminal; A transformer, the transformer has a power transmission side coil and a power reception side coil, the power transmission side coil is connected to the full-bridge circuit, the power reception side coil is connected to the power conversion circuit, and is magnetically coupled to the power transmission side coil; A power reception side voltage sensor, the power reception side voltage sensor detects the voltage of the power reception side terminal; and A control unit, the control unit alternately turns on the first switch and the second switch, and alternately turns on the third switch and the fourth switch. The lower the detected voltage of the power reception side terminal, the smaller the phase difference set by the control unit between the time when the first switch is switched to the on operation and the time when the third switch is switched to the on operation.

2. The power conversion device according to claim 1, wherein, The power conversion device includes a power transmission side voltage sensor, the power transmission side voltage sensor detects the voltage of the power transmission side terminal, The smaller the value obtained by dividing the detected voltage of the power reception side terminal by the detected voltage of the power transmission side terminal, the smaller the phase difference set by the control unit.

3. The power conversion device according to claim 1 or 2, wherein, The power conversion circuit is a full-bridge circuit having a series connection body of a first conversion switch and a second conversion switch and a series connection body of a third conversion switch and a fourth conversion switch, and these series connection bodies are connected to the power reception side terminal and the power reception side coil. The control unit alternately turns on the first conversion switch and the second conversion switch, and alternately turns on the third conversion switch and the fourth conversion switch.

4. The power conversion device according to claim 3, wherein, The switching periods of the first conversion switch, the second conversion switch, the third conversion switch and the fourth conversion switch are the same, The control unit makes the time when the first conversion switch is switched to on and the time when the third conversion switch is switched to on stagger by 1 / 2 of the switching period.

5. The power conversion device according to claim 4, wherein, The control unit makes the time when the first conversion switch is switched to on be delayed compared with the time when the first switch is switched to on.

6. The power conversion device according to claim 4 or 5, wherein, The switching periods of the first switch, the second switch, the third switch and the fourth switch are the same as the switching periods of the first conversion switch, the second conversion switch, the third conversion switch and the fourth conversion switch. The control unit includes: a first calculation unit that calculates a specified time based on the voltage of the power transmission side terminal and the voltage of the power reception side terminal; and a second calculation unit that calculates a command phase for controlling the current flowing through the power reception side terminal to its command value, The switching-on time of the first changeover switch is delayed by the command phase with respect to a reference time which is a time delayed by 1 / 2 of the specified time from the time when the first switch changes over to the on state.

7. The power conversion device according to claim 1 or 2, characterized in that the power conversion circuit is a half-bridge circuit in which a series connection body of a first changeover switch and a second changeover switch and a series connection body of a first capacitor and a second capacitor are connected to the power reception side terminal and the power reception side coil, the control unit alternately turns on the first changeover switch and the second changeover switch.

8. The power conversion device according to claim 1 or 2, characterized in that the power conversion circuit is an asymmetric half-bridge circuit in which a series connection body of a first changeover switch and a second changeover switch and a capacitor are connected to the power reception side terminal and the power reception side coil, the control unit alternately turns on the first changeover switch and the second changeover switch.

9. The power conversion device according to claim 1 or 2, characterized in that the power conversion circuit is a circuit in which a series connection body of a first changeover switch, a capacitor, and a second changeover switch and a series connection body of a third changeover switch and a fourth changeover switch connected in parallel to the series connection body of the capacitor and the second changeover switch are connected to the power reception side terminal and the power reception side coil, the control unit alternately turns on the first changeover switch and the second changeover switch, and alternately turns on the third changeover switch and the fourth changeover switch.

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