Self-diagnosis device for electronic equipment

Abstract

The present invention relates to a self-diagnosis apparatus of an electronic device, including a vector memory configured to store a test function code for testing a device under test (DUT) equipped with a plurality of cores performing arithmetic operations, a function test expectation value corresponding to a function test according to the test function code, a design for test (DFT) test code for testing, a DFT test expectation value corresponding to a DFT test according to the DFT test code, and a non-test function code for general arithmetic operations or operations of the DUT, a test data memory configured to store test data, and a secure area test controller configured to select a test mode, control an environment variable of a test signal applied to the DUT and test the DUT, compare the function test expectation value with a test function code result value, and compare the DFT test expectation value with a DFT test code result value to output comparison result information.

Description

TECHNICAL FIELD

[0001] The present invention relates to a self-diagnosis apparatus of an electronic device. More specifically, the present invention relates to a test technology capable of improving the safety of a Device Under Test (DUT), such as a semiconductor, a circuit module, or a system, by analyzing the change in characteristics of the DUT in a safe operating area over time and allowing regular tests and periodic tests to be performed even while the DUT is operating, unlike the prior art. BACKGROUND

[0002] In general, for functional safety of a mobile system equipped with electrical and electronic circuits, ISO 26262 defines a standard for ensuring high safety on Automotive Safety Integrity Level (ASIL) 4.

[0003] In order to achieve such a high safety goal, it is necessary to have a test circuit capable of performing self-diagnosis on site.

[0004] Figure 1 FIG. 1 is a diagram showing the configuration of a device according to prior art U.S. Patent No. US 10,620,266 B2, Figure 2 and Figure 3 is a diagram for describing the operation according to the prior art.

[0005] Referring to Figures 1 to 3 , according to the prior art, a device having a plurality of cores includes a self-diagnosis control circuit, and at least one core stores a current arithmetic operation state in a memory according to an external test instruction at a place of use, and controls entry into a diagnostic sleep mode.

[0006] According to the prior art, since the arithmetic operation circuit of the core needs to be stopped in the process of entering the test mode and the arithmetic operation circuit of the core is restored after the test, and a passive method of performing the test by receiving a test mode entry instruction from the outside is adopted, there is a problem that the operation efficiency of the system is reduced.

[0007] In addition, the prior art has a problem of not being applicable to a system requiring high safety, because it is not possible to know the deterioration of the circuit function and the change in quality due to time variation.

[0008] (Prior Art Document)

[0009] (Patent Document)

[0010] (Patent Document 1) U.S. Patent No. US 10,620,266 B2 (Registration Date: April 14, 2020, Title: "System, device, and method for on-site self-check in diagnostic sleep state") SUMMARY

[0011] TECHNICAL PROBLEM

[0012] The technical purpose of the present invention is to provide a device configured to identify a safe operating region of a device under test (DUT), such as a semiconductor device, an Information and Communications Technology (ICT) module or system, and to analyze the characteristic variations of the safe operating region over time, thus improving the safety of mobile objects equipped with electrical and electronic circuits.

[0013] Another technical purpose of the present invention is to allow the execution of routine tests and periodic tests even when the DUT is in operation, thus providing a particularly effective solution for the testing of electronic devices installed on mobile objects such as autonomous vehicles or drones.

[0014] TECHNICAL SOLUTION TO THE PROBLEM

[0015] The self-diagnosis device for electronic devices according to the present invention comprises: a vector memory configured to store a test function code for testing a device under test (DUT) equipped with a plurality of cores performing arithmetic operations, a function test expected value corresponding to a function test according to the test function code, a Design For Test (DFT) test code for testing, a DFT test expected value corresponding to a DFT test according to the DFT test code, and a non-test function code for general arithmetic operations or operations of the DUT; a test data memory configured to store test data including a DFT test code result value, a test function code result value, and a non-test function code result value, the DFT test code result value being a result of a DFT test according to the DFT test code, the test function code result value being a result of a function test according to the test function code, the non-test function code result value being a result of a function test according to the non-test function code; and a safe region test controller configured to select one of the test function code, the DFT test code, and the non-test function code to select a test mode, control an environmental variable of a test signal applied to the DUT in response to the selected test mode and test the DUT, compare the function test expected value stored in the vector memory with the test function code result value stored in the test data memory, and compare the DFT test expected value stored in the vector memory with the DFT test code result value stored in the test data memory to output comparison result information.

[0016] In the self-diagnosis apparatus for electronic devices according to the present application, the safe area test controller can control to periodically allocate a partial section of an operation section, which exists between a boot section that boots the DUT and a termination section that terminates the operation of the DUT, to a section that executes a test pattern according to the test function code, thereby allowing the execution of the test pattern according to the test function code in the operation section.

[0017] In the self-diagnosis apparatus for electronic devices according to the present application, the safe area test controller can control a test function code result value, which is obtained by changing an environment variable (such as voltage, clock frequency, and temperature) constituting a test signal applied to the DUT from a minimum value to a maximum value in a test pattern according to the test function code, to be accumulated in the test data memory, compare the test function code result value accumulated in the test data memory with the function test expected value stored in the vector memory, determine a section in which the test function code normally operates and a section in which the test function code abnormally operates, and output the determination result by including it in comparison result information.

[0018] In the self-diagnosis apparatus for electronic devices according to the present application, the test function code, the DFT test code, the function test expected value, the DFT test expected value, and the non-test function code stored in the vector memory can be input through an external device.

[0019] In the self-diagnosis apparatus for electronic devices according to the present application, the safety area test controller can include: a self-test controller configured to set a test environment and a test period for the DUT, and output an early warning information according to time variation information of the test data; a test mode selector configured to select a test mode for the DUT; a voltage controller configured to control a voltage applied to the DUT according to the test mode selected by the test mode selector; a clock controller configured to control a clock applied to the DUT according to the test mode selected by the test mode selector; a data comparator configured to compare the functional test expected value stored in the vector memory with the test function code result value stored in the test data memory, and compare the DFT test expected value stored in the vector memory with the DFT test code result value stored in the test data memory; and a network interface configured to support network connection with an external device.

[0020] In the self-diagnosis apparatus for electronic devices according to the present application, the safety area test controller can further include a voltage register configured to store a voltage environment variable including a minimum value and a maximum value of a voltage applied to the DUT by the voltage controller, and a step value, that is, a unit voltage variation value in a case where the voltage is gradually increased from the minimum value to the maximum value, a case where the voltage is gradually decreased from the maximum value to the minimum value, and a case of binary search for a boundary line between a failure voltage section and an operation voltage section.

[0021] In the self-diagnosis apparatus for electronic devices according to the present application, the safe region test controller can further include a clock register configured to store a clock environment variable including a minimum value and a maximum value of a frequency of a clock applied to the DUT by a clock controller, a step value, i.e., a unit frequency change value of the clock and a minimum delay value and a maximum delay value, a step value, i.e., a unit delay change value of the clock and a minimum value and a maximum value of a duty ratio of the clock in a case where the delay value of the clock is increased from the minimum delay value to the maximum delay value, a case where the delay value of the clock is decreased from the maximum delay value to the minimum delay value, and a case where a boundary line between a malfunction delay section and an operation delay section is binary searched, and a step value, i.e., a unit duty ratio change value of the clock in a case where the duty ratio of the clock is increased from a minimum value of the duty ratio to a maximum value thereof, a case where the duty ratio of the clock is decreased from the maximum value to the minimum value, and a case where a boundary line between a malfunction duty ratio section and an operation duty ratio section is binary searched.

[0022] In the self-diagnosis apparatus for electronic devices according to the present application, the safe region test controller can further include a temperature controller configured to control a temperature of the DUT according to a test mode selected by the test mode selector, and a temperature register configured to store a temperature environment variable including a temperature value and a cooling fan driving value for controlling or suspending a process of testing the DUT in response to heat generated in the DUT in the process of testing the DUT.

[0023] In the self-diagnosis apparatus for electronic devices according to the present application, the safe region test controller can further include a temperature detector configured to detect a temperature of the DUT to transmit the detected temperature to the self-test controller in the process of testing the DUT.

[0024] In the self-diagnosis apparatus for electronic devices according to the present application, the safe region test controller can further include a current-voltage detector configured to measure a leakage current of an input / output terminal or a power terminal of the DUT to transmit the leakage current to the self-test controller before and after the process of testing the DUT.

[0025] In the self-diagnosis apparatus for electronic devices according to the present application, the DUT can include an electronic device mounted on a mobile object including an autonomous vehicle or a drone, an electronic circuit formed of an information and communication technology (ICT) element including a semiconductor or a display, or an electronic device mounted on a test device.

[0026] Advantageous Effects

[0027] According to the present application, it has the effect that a safe operation region of a semiconductor, a circuit module, and an electrical and electronic device can be searched for, and a functional degradation of a circuit over time can be autonomously tested and monitored.

[0028] In addition, unlike the conventional method, even when a device under test (DUT) is driven, it has the effect that real-time characteristic diagnosis (such as normal test and time variation analysis) of a test target can be performed.

[0029] In addition, due to these advantages, degradation of a circuit function and a change in quality over time can be confirmed, and thus it can be applied to electrical and electronic circuits and systems requiring high safety, including mobile objects such as autonomous vehicles and drones. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 FIG. 1 is a diagram illustrating a configuration of a device according to the related art.

[0031] Figure 2 FIG. 2 is a diagram for describing an operation according to the related art. Figure 3

[0032] Figure 4 FIG. 3 is a diagram illustrating a self-diagnosis apparatus for electronic devices according to one embodiment of the present application.

[0033] Figure 5 FIG. 4 is a diagram illustrating an exemplary configuration of a safe region test controller according to one embodiment of the present application.

[0034] Figure 6 FIG. 5 is a diagram illustrating an exemplary operation timing chart of a self-diagnosis apparatus for electronic devices according to one embodiment of the present application.

[0035] Figure 7 FIG. 6 is a diagram for describing an exemplary operation of a self-diagnosis apparatus for electronic devices according to one embodiment of the present application. Figure 8 DETAILED DESCRIPTION

[0036] ​​The specific structure and function descriptions of the embodiments of the present application disclosed herein are merely illustrative for the purpose of describing the embodiments according to the concept of the present application and these embodiments according to the concept of the present application can be implemented in various forms and should not be interpreted as being limited to the embodiments described herein.

[0037] Embodiments according to the concept of the present application can be modified in various ways and can have various forms, so that the embodiments will be shown in the drawings and described in detail herein. However, it should be understood that the embodiments according to the concept of the present application are not intended to be limited to the specific disclosed forms, but include all modifications, equivalents and substitutions falling within the spirit and scope of the present application.

[0038] Unless otherwise defined, all terms used herein, including technical terms or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present application pertains. General terms defined in a dictionary should be interpreted to have meanings consistent with the context in which the terms are used in the relevant art and should not be interpreted to have idealistic or overly formalistic meanings unless explicitly defined in the present disclosure.

[0039] Hereinafter, exemplary embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0040] Figure 4 FIG. 1 is a diagram illustrating a self-diagnosis apparatus for an electronic device according to one embodiment of the present application, Figure 5 FIG. 2 is a diagram illustrating an exemplary configuration of a safety region test controller according to one embodiment of the present application.

[0041] Referring to Figure 4 and Figure 5 , a self-diagnosis apparatus for an electronic device according to one embodiment of the present application includes a vector memory 10, a test data memory 20, and a safety region test controller 30.

[0042] The vector memory 10 is a component in which test function codes for testing a test target equipped with a plurality of cores performing arithmetic operations, function test expected values corresponding to function tests according to the test function codes, design for test (DFT) test codes for testing, DFT test expected values corresponding to DFT tests according to the DFT test codes, and non-test function codes for general arithmetic operations or operations of a device under test (DUT) are stored.

[0043] More specifically, the vector memory 10 can be divided into a non-test code region and a test code region. The non-test code region stores non-test function codes for general arithmetic operations or operations of a test target, and the test code region includes test function codes, and the DFT test codes store test expected values corresponding to each code.

[0044] Here, the DFT test code includes a scan code for driving a scan chain of a logic cell connection network constituting an internal circuit of the DUT and a built-in self-test (BIST) code for driving a BIST circuit for self-test of an internal cell array. The DFT test code can be configured in a format different from that of the test function code and is operated as a separate channel.

[0045] Meanwhile, the test function code can be configured to have the same format as the non-test function code and is transmitted and controlled through the same instruction decoder and the same scheduler channel. The test function code is formed to drive the core and the periphery of the DUT in as many areas as possible in as short a period of time as possible to allow efficient testing to be performed.

[0046] For example, the DUT can be an electronic device mounted on a mobile object including an autonomous vehicle or a drone, and the test function code, the DFT test code, the function test expectation value, the DFT test expectation value, and the non-test function code can be configured to be input and re-input through an external device.

[0047] The test data memory 20 is a component for storing test data including a DFT test code result value, a test function code result value, and a non-test function code result value, the DFT test code result value being a result of DFT test according to the DFT test code, the test function code result value being a result of function test according to the test function code, and the non-test function code result value being a result of function test according to the non-test function code.

[0048] The safe region test controller 30 is a component for performing functions of selecting one of the test function code, the DFT test code, and the non-test function code to select a test mode, controlling an environmental variable of a test signal applied to the DUT in response to the selected test mode, and testing the DUT, comparing a function test expectation value stored in the vector memory 10 with a test function code result value stored in the test data memory 20, and comparing a DFT test expectation value stored in the vector memory 10 with a DFT test code result value stored in the test data memory 20 to output comparison result information.

[0049] The safe region test controller 30 can include a component for controlling a voltage and a frequency applied to the DUT, a component for selecting a test code, and a component for comparing an actual test result with an expectation value stored in the vector memory 10. A specific configuration of the safe region test controller 30 will be described below.

[0050] For example, the safe region test controller 30 can periodically allocate a partial section of an operation section, which exists between a boot section that boots the DUT and a termination section that terminates the operation of the DUT, to a section that executes a test pattern according to a test function code, thereby controlling execution of a test pattern according to the test function code in the operation section.

[0051] In addition, for example, the safe region test controller 30 can be formed to control a test function code result value to be accumulated in the test data memory 20, which is obtained by changing an environmental variable (such as a voltage, a clock frequency, and a temperature) that constitutes a test signal applied to the DUT from a minimum value to a maximum value in a test pattern according to a test function code, compare the test function code result value accumulated in the test data memory 20 with a function test expected value stored in the vector memory 10, determine a section in which the test function code normally operates and a section in which the test function code abnormally operates, and output the determination result by including the determination result in comparison result information.

[0052] Hereinafter, a detailed description will be given of the safe region test controller 30 with reference to Figure 4 A detailed configuration of the safe region test controller 30 will be additionally described.

[0053] A detailed configuration of the safe region test controller 30 will be additionally described. Figure 4 The safe region test controller 30 includes a self-test controller 100, a test pattern selector 110, a voltage controller 120, a clock controller 130, a temperature controller 140, a data comparator 150, a network interface 160, a voltage register 170, a clock register 180, a temperature register 190, a temperature detector 200, a current-voltage detector 210, a data buffer memory 220, and a program memory 230.

[0054] The self-test controller 100 performs a function of setting a test environment and a test period for the DUT and a function of outputting an early warning information according to time variation information of test data with reference to information output from the data comparator 150.

[0055] The test pattern selector 110 selects a test code to be applied to the DUT to perform a function of selecting a test pattern for the DUT.

[0056] The voltage controller 120 performs a function of controlling a voltage applied to the DUT according to a test pattern selected by the test pattern selector 110.

[0057] The voltage register 170 stores voltage environment variables including minimum and maximum values of a voltage applied to the DUT by the voltage controller 120, and step values, i.e., unit voltage change values in the case where the voltage is gradually increased from the minimum value to the maximum value, the case where the voltage is gradually decreased from the maximum value to the minimum value, and the case of binary search for a boundary line between a failure voltage section and an operating voltage section. The binary search has an additional effect of shortening the test time.

[0058] The clock controller 130 performs a function of controlling a clock applied to the DUT according to a test mode selected by the test mode selector 110.

[0059] The clock register 180 stores clock environment variables including minimum and maximum values of a frequency of a clock applied to the DUT by the clock controller 130, step values, i.e., unit frequency change values and minimum and maximum delay values of the clock, step values, i.e., unit delay change values and minimum and maximum duty cycle values of the clock in the case where the delay value of the clock is increased from the minimum delay value to the maximum delay value, the case where the delay value of the clock is decreased from the maximum delay value to the minimum delay value, and the case of binary search for a boundary line between a failure delay section and an operating delay section, and step values, i.e., unit duty cycle change values in the case where the duty cycle of the clock is increased from the minimum value of the duty cycle to the maximum value thereof, the case where the duty cycle of the clock is decreased from the maximum value to the minimum value, and the case of binary search for a boundary line between a failure duty cycle section and an operating duty cycle section.

[0060] The temperature controller 140 performs a function of controlling a temperature of components (e.g., cores, memories, and boards) constituting the DUT according to a test mode selected by the test mode selector 110.

[0061] The temperature register 190 stores temperature environment variables including temperature values and cooling fan driving values for controlling or suspending a process of testing the DUT in response to heat generated in the DUT in the process of testing the DUT.

[0062] The data comparator 150 performs a function of comparing a functional test expected value stored in the vector memory 10 with a test functional code result value stored in the test data memory 20, and a function of comparing a DFT test expected value stored in the vector memory 10 with a DFT test code result value stored in the test data memory 20.

[0063] The network interface 160 performs a function of supporting network connection with an external device.

[0064] The temperature detector 200 detects the temperature of components constituting the DUT to transmit the detected temperature to the self-test controller 100 during testing of the DUT.

[0065] The current-voltage detector 210 measures the leakage current of the input / output terminal or the power supply terminal of the DUT to transmit the leakage current to the self-test controller 100 before and after testing of the DUT.

[0066] The data buffer memory 220 stores data related to testing, and the program memory 230 stores programs used in testing.

[0067] Figure 6 FIG. 1 is a diagram illustrating an exemplary operation timing chart of a self-diagnosis apparatus for an electronic device according to one embodiment of the present application.

[0068] In Figure 6 In the above-described example, the system is the DUT, and the basic operations include a boot section TO as an initial value setting operation, operation / function test sections T1_1 to T1_n that perform tasks, and an end section T2.

[0069] In the boot section TO, the DFT check mode is executed after the initial value setting operation of the system, and a test is performed on the DFT circuit of the system. When the test of the DFT circuit ends, the test result is stored in the DFT test data storage area of the test data memory 20.

[0070] In the operation / function test sections T1, tasks of an application program are executed, and a function test mode is executed at regular intervals. In the function test mode, the values of environmental variables including voltage, frequency, and temperature are changed from a minimum value to a maximum value to find a section in which the function test code normally operates and a section in which the function test code abnormally operates. The function test is periodically and repeatedly performed, and the function test result is stored in the function code test data storage area of the test data memory 20.

[0071] In a method of implementing the function test mode, in addition to the method of performing the function test at regular periods as in the above-described example, a setting for executing the function test mode can be implemented when the tasks of the system are terminated due to the application program and thus the system enters an idle state.

[0072] In the end section T2, before the system enters a final standby state or a shutdown state, the system enters the DFT test mode to test the DFT circuit of the system. When the test of the DFT circuit ends, the test result is stored in the DFT test data storage area of the test data memory 20.

[0073] In addition, since the DFT circuit is designed to operate at a low speed, the purpose of which is only to confirm whether the circuit is connected, without directly affecting the operation of the functional circuit, the DFT circuit is generally not greatly affected by environmental variables, and has no relation to the function including the deceleration and abnormal timing of the system. Therefore, here, it is not necessary to set a safe operation area for searching in the operation / function test section Tl.

[0074] Figure 7 and Figure 8 is a diagram for describing exemplary operation of a self-diagnosis apparatus for an electronic device according to an embodiment of the present application, which shows a task flow for searching a safe operation area of a DUT.

[0075] Further referring to Figure 7 and Figure 8 , first, in operation S10, a process of storing a test code and an expected value to be transmitted through a network in a vector memory 10 is performed.

[0076] In operation S20, a process of selecting whether to apply a test in an idle state of the DUT or in its normal mode is performed. Here, when the idle mode is selected, the test is performed only when the DUT is in the idle state without a task to be executed, and when the normal mode is selected, the process switches to operation S30 and a test code application period for periodically activating a test mode is set.

[0077] In operation S40, an application range of a voltage, a frequency, a clock duty, and a test interval for executing a test code are set, and the setting can be automatically set according to a program previously input in the system or a value corrected through a network.

[0078] In operation S50, when the setting of the environmental variable is completed, a measurement program for a safe operation area is performed.

[0079] In operation S70, an operation variable of the DUT is deployed from a minimum value to a maximum value according to a predetermined step, and a test is performed, and in operation S90, a test result is stored in a test data memory 20.

[0080] In operations S100 and S110, a data comparator 150 compares the test result with the expected value stored in the vector memory 10 to determine whether a defect occurs, and stores a determination result in a data buffer memory 220 within a safe area test controller 30.

[0081] Here, when a defect occurs during deployment of an input variable with respect to the DUT, the process switches to operation S80 to reset the DUT and deploy a next input variable to continue the test.

[0082] In operation S120, it is determined whether the deployment of the operation variable is completed. When the deployment of the operation variable is not completed, the process switches to operation S60, and when the deployment of the operation variable is completed, the process switches to operation S130.

[0083] When the deployment of the operation variable is completed, when compared with the data recorded in operation S130, it is analyzed whether the safe operation area is changed, and when the change in the safe operation area is detected in operation S140, the detection result is transmitted to the warning system in operation S150, or transmitted to the outside through the network in operation S160.

[0084] As described in detail above, according to the present application, it has the effect that the safe operation area of a semiconductor, a circuit module, and an electrical and electronic device can be searched, and the functional degradation of a circuit over time can be autonomously tested and monitored.

[0085] In addition, unlike the conventional method, even when the DUT is driven, it has the effect that real-time characteristic diagnosis (such as normal test and time variation analysis) of the DUT can be performed.

[0086] In addition, due to these advantages, the degradation of the circuit function and the change in quality over time can be confirmed, and thus it can be applied to electrical and electronic circuits and systems requiring high safety, including autonomous vehicles and mobile objects such as drones.

[0087] (Explanation of reference numerals)

[0088] 10: vector memory

[0089] 20: test data memory

[0090] 30: safe area test controller

[0091] 100: self-test controller

[0092] 110: test mode selector

[0093] 120: voltage controller

[0094] 130: clock controller

[0095] 140: temperature controller

[0096] 150: data comparator

[0097] 160: network interface

[0098] 170: voltage register

[0099] 180: clock register

[0100] 190: temperature register

[0101] 200: temperature detector

[0102] 210: current-voltage detector

[0103] 220: data buffer memory

[0104] 230: program memory

Claims

1. A self-diagnostic device for an electronic device, the self-diagnostic device comprising: A vector memory is configured to store test function codes for testing a device under test equipped with multiple cores performing arithmetic operations, functional test expectation values ​​corresponding to functional tests based on the test function codes, design test codes for testing, design test expectation values ​​for testing corresponding to design tests based on the design test codes for testing, and non-test function codes for general arithmetic operations or operations of the device under test. A test data storage device is configured to store test data, which includes design test code result values, test function code result values, and non-test function code result values. The design test code result values ​​are the results of design tests based on the design test code, the test function code result values ​​are the results of function tests based on the test function code, and the non-test function code result values ​​are the results of function tests based on the non-test function code. as well as A safe zone test controller is configured to select a test mode from the test function code, the design test code for testing, and the non-test function code. The environmental variables applied to the device under test are controlled in response to the selected test mode, and the device under test is tested. The expected value of the functional test stored in the vector memory is compared with the result value of the test functional code stored in the test data memory; The design test expectation value stored in the vector memory is compared with the design test code result value stored in the test data memory to output comparison result information.

2. The self-diagnostic device according to claim 1, wherein, The safe zone test controller periodically allocates a portion of the operation zone to the zone that executes the test mode according to the test function code. The portion of the operation zone exists between the guide zone that guides the device under test and the termination zone that terminates the operation of the device under test, so as to control the execution of the test mode according to the test function code in the operation zone.

3. The self-diagnostic device according to claim 2, wherein, The safe zone test controller controls the accumulation of test function code result values ​​in the test data memory. These test function code result values ​​are obtained in the test mode by changing the environmental variables constituting the test signal applied to the device under test from a minimum to a maximum value according to the test function code. The accumulated test function code result values ​​in the test data memory are compared with the expected function test values ​​stored in the vector memory to determine the sections where the test function code operates normally and the sections where the test function code operates abnormally. The determination results are output by including the determination results in the comparison result information, wherein the environmental variables include voltage, clock frequency, and temperature.

4. The self-diagnostic device according to claim 1, wherein, The external device allows input of the test function code, the design test code for testing, the functional test expectation, the design test expectation for testing, and the non-test function code stored in the vector memory.

5. The self-diagnostic device according to claim 2, wherein, The safe zone test controller includes: The self-test controller is configured to set the test environment and test cycle for the device under test, and output advance warning information based on the time change information of the test data; A test mode selector configured to select a test mode for the device under test; A voltage controller configured to control the voltage applied to the device under test according to a test mode selected by the test mode selector; A clock controller configured to control the clock applied to the device under test according to a test mode selected by the test mode selector; A data comparator configured to compare functional test expectation values ​​stored in the vector memory with test functional code result values ​​stored in the test data memory, and to compare design test expectation values ​​for testing stored in the vector memory with design test code result values ​​for testing stored in the test data memory; and A network interface that is configured to support network connections with external devices.

6. The self-diagnostic device according to claim 5, wherein, The safe zone test controller also includes a voltage register configured to store voltage environment variables, including the minimum and maximum values ​​of the voltage applied to the device under test by the voltage controller, and a step value, i.e., the unit voltage change value when the voltage gradually increases from the minimum to the maximum value, when the voltage gradually decreases from the maximum value to the minimum value, and when a binary search is performed on the boundary line between the fault voltage segment and the operating voltage segment.

7. The self-diagnostic device according to claim 5, wherein, The safe zone test controller further includes a clock register configured to store clock environment variables, including: the minimum and maximum frequency of the clock applied to the device under test by the clock controller; the unit frequency change value of the clock, and the minimum and maximum delay values ​​of the clock; a first step value, i.e., the unit delay change value when the clock delay value is increased from the minimum to the maximum delay value, decreased from the maximum to the minimum delay value, and when a binary search is performed on the boundary line between the fault delay segment and the operating delay segment; the minimum and maximum duty cycle of the clock; and a second step value, i.e., the unit duty cycle change value when the clock duty cycle is increased from the minimum to the maximum, decreased from the maximum to the minimum duty cycle, and when a binary search is performed on the boundary line between the fault duty cycle segment and the operating duty cycle segment.

8. The self-diagnostic device according to claim 5, wherein, The safe zone test controller includes: A temperature controller configured to control the temperature of the device under test according to a test mode selected by the test mode selector; A temperature register, configured to store temperature environment variables, including temperature values ​​and cooling fan drive values, is used to control or pause the testing process of the device under test in response to the heat generated in the device under test during the testing process.

9. The self-diagnostic device according to claim 8, wherein, The safe zone test controller also includes a temperature detector configured to detect the temperature of the device under test (DUT) and send the detected temperature to the self-test controller during the testing of the DUT.

10. The self-diagnostic device according to claim 5, wherein, The safe zone test controller also includes a current-voltage detector configured to measure leakage current at the input / output terminals or power terminals of the device under test (DUT) to transmit the leakage current to the self-test controller before and after the DUT testing process.

11. The self-diagnostic device according to claim 1, wherein, The device under test includes electronic devices installed on mobile objects, including autonomous vehicles or drones, electronic circuits formed by information and communication technology components, including semiconductors or displays, or electronic devices installed on test devices.

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