Semiconductor device

Abstract

Provided is a semiconductor device that is suitable for cost reduction, does not reduce the destruction tolerance of RBSOA or the like, and can reduce the recovery loss when FWD is operating. The semiconductor device includes a FWD region formed on a substrate, having a p-type anode region on the upper surface side of the substrate, a first p-type contact region having a higher p-type impurity concentration than the p-type anode region, and a first trench; an IGBT region formed on the substrate, surrounding the FWD region with a boundary region therebetween when viewed from above, having an n-type emitter region on the upper surface side of the substrate, a second p-type contact region, and a second trench; and a peripheral region surrounding the FWD region, the boundary region, and the IGBT region when viewed from above, the first trench being formed in a ring shape along the outer edge of the FWD region when viewed from above, the second trench being formed in a ring shape along the outer edge of the boundary region when viewed from above, and only a p-type region being present on the upper surface side of the boundary region.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Typically, power devices face various requirements, including withstand voltage retention and ensuring a safe operating area to prevent damage during operation. One key requirement is low loss. Low loss in power devices leads to miniaturization and weight reduction, and broadly speaking, it protects the environment by reducing energy consumption. Furthermore, the aim is to achieve these requirements at the lowest possible cost.

[0003] As one approach to addressing the aforementioned issues, a reverse-conducting insulated gate bipolar transistor (RC-IGBT) is proposed, which integrates the characteristics of both an IGBT and a diode in a single device. This reverse-conducting IGBT presents several technical challenges, one of which is the high recovery loss during diode operation.

[0004] Regarding reverse-conducting IGBTs, during FWD operation, the diode's anode portion and n... - The PN junction formed by the drift layer becomes forward biased, and holes flow into drift layer 1, causing conductivity modulation, which can reduce the forward voltage drop. However, if the p-type impurity concentration in the anode region is high and there are a large number of excess carriers, the carriers inside the device are difficult to expel, resulting in increased recovery loss.

[0005] Patent Document 1 discloses a countermeasure to this problem. Patent Document 1 discloses a structure in which the diode region is surrounded by the IGBT region. Furthermore, it discloses that the anode region formed in the diode region has both a high-concentration anode region and a low-concentration anode region. However, regarding the semiconductor device of Patent Document 1, depending on the formation of the trench between the IGBT region and the FWD region, it is possible that the breakdown voltage will decrease or the reverse bias safe operating area (RBSOA) during IGBT operation will be reduced.

[0006] Patent Document 1: Japanese Patent Application Publication No. 2015-165542

[0007] As mentioned above, with respect to existing RC-IGBTs, depending on the formation of the trench between the IGBT region and the FWD region, it is possible to cause a decrease in withstand voltage or a reduction in the reverse bias safe operating area when the IGBT operates. Summary of the Invention

[0008] The present invention was proposed to solve the aforementioned problems and aims to provide a semiconductor device that is suitable for cost reduction, does not reduce the damage resistance of RBSOA, and can reduce recovery loss during FWD operation.

[0009] The semiconductor device of the present invention is characterized by having: an FWD region formed on a substrate, having a p-type anode region, a first p-type contact region with a p-type impurity concentration higher than that of the p-type anode region, and a first trench on the upper surface side of the substrate; an IGBT region formed on the substrate, which, when viewed from above, is surrounded by a boundary region, having an n-type emitter region, a second p-type contact region, and a second trench on the upper surface side of the substrate; and an outer peripheral region that, when viewed from above, surrounds the FWD region, the boundary region, and the IGBT region, wherein the first trench is formed in a ring shape along the outer edge of the FWD region when viewed from above, the second trench is formed in a ring shape along the outer edge of the boundary region when viewed from above, and only a p-type region is present on the upper surface side of the boundary region.

[0010] Other features of the present invention will be set forth below.

[0011] The effects of the invention

[0012] According to the present invention, at the boundary between the IGBT region and the FWD region, there is a boundary region on the upper side that has only a p-type region. This boundary region is surrounded by two annular grooves, so that the damage resistance of the RBSOA and other components will not be reduced, and the recovery loss during FWD operation can be reduced. Attached Figure Description

[0013] Figure 1 This is a top view of the semiconductor device involved in Embodiment 1.

[0014] Figure 2 This is a partial enlarged view of the semiconductor device involved in Embodiment 1.

[0015] Figure 3 This is a cross-sectional view of the semiconductor device according to Embodiment 1.

[0016] Figure 4 This is a cross-sectional view of the semiconductor device according to Embodiment 1.

[0017] Figure 5 This is a cross-sectional view of the semiconductor device according to Embodiment 1.

[0018] Figure 6 This is a partial enlarged view of the semiconductor device involved in Embodiment 2.

[0019] Figure 7 This is a cross-sectional view of the semiconductor device involved in Embodiment 2.

[0020] Figure 8 This is a cross-sectional view of the semiconductor device involved in Embodiment 2.

[0021] Figure 9 This is a cross-sectional view of the semiconductor device involved in Embodiment 2.

[0022] Figure 10 This is a partial enlarged view of the semiconductor device involved in Embodiment 3.

[0023] Figure 11 This is a cross-sectional view of the semiconductor device involved in Embodiment 3.

[0024] Figure 12 This is a cross-sectional view of the semiconductor device involved in Embodiment 3.

[0025] Figure 13 This is a cross-sectional view of the semiconductor device involved in Embodiment 3.

[0026] Figure 14 This is a partial enlarged view of the semiconductor device involved in Embodiment 4.

[0027] Figure 15 This is a cross-sectional view of the semiconductor device involved in Embodiment 4.

[0028] Figure 16 This is a cross-sectional view of the semiconductor device involved in Embodiment 4.

[0029] Figure 17 This is a cross-sectional view of the semiconductor device involved in Embodiment 4.

[0030] Figure 18 This is a partial enlarged view of the semiconductor device involved in Embodiment 5.

[0031] Figure 19 This is a cross-sectional view of the semiconductor device according to Embodiment 5.

[0032] Figure 20 This is a cross-sectional view of the semiconductor device according to Embodiment 5.

[0033] Figure 21 This is a cross-sectional view of the semiconductor device according to Embodiment 5.

[0034] Figure 22 This is a partial enlarged view of the semiconductor device involved in Embodiment 6.

[0035] Figure 23 This is a cross-sectional view of the semiconductor device according to Embodiment 6.

[0036] Figure 24 This is a cross-sectional view of the semiconductor device according to Embodiment 6.

[0037] Figure 25 This is a cross-sectional view of the semiconductor device according to Embodiment 6.

[0038] Figure 26 This is a partial enlarged view of the semiconductor device according to Embodiment 7.

[0039] Figure 27 This is a cross-sectional view of the semiconductor device according to Embodiment 7.

[0040] Figure 28 This is a cross-sectional view of the semiconductor device according to Embodiment 7.

[0041] Figure 29 This is a cross-sectional view of the semiconductor device according to Embodiment 7.

[0042] Figure 30 This is a partial enlarged view of the semiconductor device according to Embodiment 8.

[0043] Figure 31 This is a cross-sectional view of the semiconductor device according to Embodiment 8.

[0044] Figure 32 This is a cross-sectional view of the semiconductor device according to Embodiment 8.

[0045] Figure 33 This is a cross-sectional view of the semiconductor device according to Embodiment 8.

[0046] Figure 34 This is a partial enlarged view of the semiconductor device according to Embodiment 9.

[0047] Figure 35 This is a cross-sectional view of the semiconductor device according to Embodiment 9.

[0048] Figure 36 This is a cross-sectional view of the semiconductor device according to Embodiment 9.

[0049] Figure 37 This is a cross-sectional view of the semiconductor device according to Embodiment 9.

[0050] Figure 38 This is a partial enlarged view of the semiconductor device according to Embodiment 10.

[0051] Figure 39 This is a cross-sectional view of the semiconductor device according to Embodiment 10.

[0052] Figure 40 This is a cross-sectional view of the semiconductor device according to Embodiment 10.

[0053] Figure 41 This is a cross-sectional view of the semiconductor device according to Embodiment 10.

[0054] Figure 42 This is a partial enlarged view of the semiconductor device according to Embodiment 11.

[0055] Figure 43 This is a cross-sectional view of the semiconductor device according to Embodiment 11.

[0056] Figure 44 This is a cross-sectional view of the semiconductor device according to Embodiment 11.

[0057] Figure 45 This is a cross-sectional view of the semiconductor device according to Embodiment 11. Detailed Implementation

[0058] The semiconductor device according to the embodiments will be described with reference to the accompanying drawings. Identical or corresponding structural elements are labeled with the same reference numerals, and sometimes repeated descriptions are omitted.

[0059] Implementation method 1.

[0060] Figure 1 This is a top view of the semiconductor device 100 according to Embodiment 1. Figure 1 The image shows the overall state of a semiconductor device in its chip configuration. This semiconductor device is an RC-IGBT having an IGBT region 101, an FWD region 102, an outer peripheral region 103, and a gate pad region 104. The main electrode region is formed by the IGBT region 101 and the FWD region 102. When viewed from above, the IGBT region 101 surrounds the FWD region 102 through a boundary region. Furthermore, an outer peripheral region 103 is formed around the main electrode region. When viewed from above, the outer peripheral region 103 surrounds the FWD region 102, the boundary region, and the IGBT region 101.

[0061] Figure 2 yes Figure 1 An enlarged top view of the dashed-lined area. Figure 2 For ease of explanation, the electrodes are omitted and only the upper surface of the substrate is shown. A boundary region 105 is provided between the IGBT region 101 and the FWD region 102. The IGBT region 101 and the FWD region 102 are formed by multiple unit cell regions. In the region sandwiched by trenches, one of the repeating structures in the length direction is defined as a unit cell.

[0062] In FWD region 102, multiple dummy trenches 40 are formed side-by-side. Along the dummy trenches 40 are formed a p-type anode region 5 and a first p-type contact region 6 with a higher p-type impurity concentration than the p-type anode region 5. The first p-type contact region 6 is p... + The FWD region 102 has a first groove 30 at its outer edge. The first groove 30 forms a ring shape along the outer edge of the FWD region 102 when viewed from above.

[0063] In the IGBT region 101, multiple trenches 50 are formed in parallel. Along the trenches 50, n-type emitter regions 3 and second p-type contact regions 4 are alternately arranged. The second p-type contact region 4 is a p... + The IGBT region 101 has a second groove 32. When viewed from above, the second groove 32 forms a ring shape along the outer edge of the boundary region 105.

[0064] Boundary region 105 is the region sandwiched between the first groove 30 and the second groove 32 when viewed from above. Figure 2 In this example, the boundary region 105 is quadrilateral in shape. Only p-type regions exist on the upper surface of the boundary region 105. According to one example, such a p-type region has a first p-type region 38 and a second p-type region 39 with a lower p-type impurity concentration than the first p-type region 38. The first p-type region 38 has a ring-shaped shape that surrounds the FWD region 102 when viewed from above.

[0065] Additionally, a p-type well region 16 is formed in the outer peripheral region 103 to surround the IGBT region 101. Around the outer periphery of the p-type well region 16 formed in the outer peripheral region 103, an FLR (Field Limming Ring) can be provided, consisting of a p-type end-well layer of a p-type semiconductor surrounding the cell region, or a VLD (Variation of Lateral Doping) can be provided, consisting of a p-type well layer with a concentration gradient surrounding the cell region. Corresponding to the breakdown voltage design of the semiconductor device 100, the number of annular p-type end-well layers used in the FLR and the concentration distribution of the VLD are selected.

[0066] exist Figure 2 The image shows a quadrilateral frame with an "×" symbol inside. This quadrilateral frame and its inner side constitute the contact area 15. In the contact area 15, the emitter electrode 13 is in contact with the upper surface of the substrate Sb. Outside the contact area 15, the substrate Sb is not in contact with the emitter electrode 13.

[0067] Figure 3 , Figure 4 , Figure 5 They are respectively Figure 2 The sectional views shown are along line A′-A′, line B′-B′, and line C′-C′. Figure 3-5 The substrate Sb is shown. The substrate Sb has n - Type 1 drift layer. In Figure 3 The diagram shows an emitter electrode 13 disposed on the upper surface of the substrate Sb. An n-type buffer layer 10 is formed on the lower surface of the substrate Sb. In the IGBT region 101, a p-type collector layer 11 is formed below the buffer layer 10, and in the FWD region 102, an n-type collector layer 11 is formed below the buffer layer 10.+ A cathode layer 12 of a certain type is formed. A collector electrode 14 is formed below the collector layer 11 and the cathode layer 12.

[0068] The trench 50 of the IGBT region 101 has a gate insulating film 7 on the inner wall of the trench and a buried gate electrode 8 in contact with the gate insulating film 7. An interlayer insulating film 9 is disposed between the buried gate electrode 8 and the emitter electrode 13, and they are electrically insulated. Moreover, an n-channel MOSFET is formed in the IGBT region 101, which has a drift layer 1, a p-type channel doped portion 2, an n-type emitter region 3, a gate insulating film 7, and a buried gate electrode 8. In addition to this MOSFET structure, the IGBT also includes a collector layer 11.

[0069] In the FWD region 102, a diode structure is formed by the p-type anode region 5, the first p-type contact region 6, the drift layer 1, and the cathode layer 12.

[0070] like Figure 3-5 As shown, in the boundary region 105, the first p-type region 38 and the second p-type region 39 are in contact with the emitter electrode 13.

[0071] Figure 1 The gate pad region 104 is connected to the gate wiring formed inside the IGBT region 101. The area directly below the gate pad region 104 is electrically separated from the emitter electrode, for example, by an oxide film. Alternatively, a p-type end-well layer can be formed over approximately the entire area directly below the aforementioned oxide film, and an n-type end-well layer can also be formed. - Type 1 drift layer. Features that have not been recorded so far will be described below.

[0072] The first feature is that the FWD region 102 has a first groove 30 formed in an annular shape, and a second groove 32 formed at a fixed interval surrounding the first groove 30, thereby separating the FWD region 102 and the IGBT region 101.

[0073] The second feature is that the boundary region 105 has a first p-shaped region 38 and a second p-shaped region 39. The contact region 15 contacts both the first p-shaped region 38 and the second p-shaped region 39. When viewed from above, the second p-shaped region 39 contacts the second groove 32, while the first p-shaped region 38 does not contact the second groove 32. In this embodiment, the distance between the first groove 30 and the second groove 32 is greatest at the corner portion, and is less than or equal to this distance and is fixed at the other locations. Furthermore, in this embodiment, the first groove 30 and the second groove 32 are formed as quadrilaterals, but the corners can also be curved to make the distance between the grooves at the corners similar to the distance between the grooves at the other locations.

[0074] The third feature is that the anode of FWD region 102 is composed of p-type anode region 5, which is p-shaped. + A first p-type contact region 6 is formed, which is formed as a line in the length direction parallel to the groove. The first p-type contact region 6 is formed on a unit basis and has an elongated shape parallel to the first groove 30 when viewed from above.

[0075] The fourth feature is that the high-concentration second p-type contact region 4 of the IGBT region 101 is formed in a manner that overlaps with the p-type well region 16, which is not connected to the channel doped portion 2 and the n-type emitter region 3. When viewed from above, the p-type well region 16 and the second p-type contact region 4 are in contact.

[0076] The fifth feature is that the contact region 15 of the IGBT region 101 includes a second p-type contact region 4, and also includes a p-type well region 16. Figure 5 The diagram shows the second p-type contact region 4, the p-type well region 16, and the emitter electrode 13 in contact.

[0077] The sixth feature is that the area ratio of the first p-type contact region 6 at FWD region 102 is lower than the area ratio of the p-type anode region 5. According to other examples, when viewed from above, the sum of the area ratios of the first p-type contact region 6 and the first p-type region 38 of each unit cell at FWD region 102 and boundary region 105 is smaller than the sum of the area ratios of the p-type anode region 5 and the second p-type region 39.

[0078] The seventh feature is that, in the boundary region 105, the area ratio of the first p-type region 38 is lower than that of the second p-type region 39.

[0079] The eighth feature is that the area ratio of the first p-type contact region 6 at FWD region 102 is lower than the area ratio of the second p-type contact region 4 at IGBT region 101. According to other examples, when viewed from above, the sum of the area ratios of the first p-type contact region 6 and the first p-type region 38 per unit cell in FWD region 102 and boundary region 105 is smaller than the area ratio of the second p-type contact region 4 per unit cell in IGBT region 101.

[0080] The ninth feature is that the area ratio of the first p-type region 38 at the boundary region 105 is lower than the area ratio of the second p-type contact region 4 at the IGBT region 101.

[0081] Regarding the manufacturing method of this embodiment, since it can be manufactured using conventional IGBT manufacturing technology by changing the pattern during photolithography, detailed descriptions are omitted.

[0082] Next, the operation of the semiconductor device according to this embodiment will be explained. First, the operation of the semiconductor device as an IGBT will be explained. The IGBT is turned on by applying a positive voltage to the buried gate electrode 8, which turns on the n-channel MOSFET. The n-channel MOSFET has a drift layer 1, a channel doped portion 2, an n-type emitter region 3, a gate insulating film 7, and a buried gate electrode 8. Electrons are injected from the n-type emitter region 3 and holes flow into the collector layer 11, causing conductivity modulation in the drift layer 1. This reduces the voltage between the emitter and collector, thus turning on the IGBT.

[0083] Next, the IGBT is turned off by applying a negative voltage to the buried gate electrode 8. If the n-channel MOSFET is turned off, the minority carriers accumulated in the drift layer 1 are discharged from the emitter electrode 13 and the collector electrode 14, and the drift layer 1 is gradually depleted. By sharing the voltage with the depleted region, the voltage between the emitter and collector increases, achieving the off state.

[0084] Next, the semiconductor device according to this embodiment will be described as operating as a diode. The diode structure has a p-type anode region 5, a first p-type contact region 6, a drift layer 1, and a cathode layer 12. When the FWD is operating, the on state is that the IGBT paired with the FWD is in the off state, and a positive voltage is applied to the emitter electrode 13 relative to the collector electrode 14. The conductivity is modulated by the inflow of holes from the anode region formed by the p-type anode region 5 and the first p-type contact region 6 and the inflow of electrons from the cathode region having the cathode layer 12, and the diode becomes the conducting state.

[0085] Next, if the IGBT paired with the FWD becomes on, a negative voltage is applied to the emitter electrode 13 relative to the collector electrode 14. Holes from the drift layer 1 are released from the p-type anode region 5 and the first p-type contact region 6 to the emitter electrode 13, and electrons are released from the cathode layer 12 to the collector electrode 14. However, excess carriers near the anode region disappear, and current continues to flow until the PN junction formed by the p-type anode region 5, the first p-type contact region 6, and the drift layer 1 becomes reverse biased. Moreover, as excess carriers near the anode region are released, if the PN junction formed by the p-type anode region 5, the first p-type contact region 6, and the drift layer 1 becomes reverse biased, the reverse recovery current begins to decrease. If excess carriers in the drift layer 1 are discharged, the recovery process is completed, and the process becomes cut off. Furthermore, the first p-type region 38 and the second p-type region 39 function in the same way as the p-type anode region 5 and the first p-type contact region 6.

[0086] In the RC-IGBT, an FWD region 102 is formed adjacent to the IGBT region 101. When the IGBT operates, holes diffuse from the collector layer 11 into both the IGBT region 101 and the FWD region 102. Therefore, when the IGBT is turned off during operation, a portion of the holes that have flowed into the FWD region 102, except for those in the IGBT region 101, are discharged from the emitter electrode 13.

[0087] Therefore, the hole current is concentrated in the IGBT region near the FWD region 102, and the potential of the channel doped portion 2 becomes high. If a voltage to eliminate the built-in potential is applied to the p-type impurity regions, such as the n-type emitter region 3 and the channel doped portion 2 that forms a pn junction with the n-type emitter region 3, the thyristor formed by the n-type emitter region 3, the channel doped portion 2, the drift layer 1, and the collector layer 11 is turned on. As a result, control based on the gate electrode cannot be achieved, and depending on the situation, the device may be damaged. This situation is called the reverse bias safe operating area (RBSOA). Moreover, since the peripheral region 103 also contains hole components that diffuse to the peripheral portion, it is possible for the safe operating area to decrease further.

[0088] However, in this embodiment, based on features one, two, four, and five, it is possible to prevent the reverse bias safe operating area from decreasing during IGBT operation. First, as in the second feature, the boundaries of the IGBT region 101 and the FWD region 102 are separated by a second trench 32 and a first trench 30, respectively. In the boundary region 105, the trenches surround the FWD region 102 at fixed intervals. Since no n is formed between the first trench 30 and the second trench 32... + The emitter and other n-type impurity regions form a first p-type region 38 and a second p-type region 39, thus preventing the formation of parasitic thyristors. Furthermore, the first p-type region 38 and the second p-type region 39 of the boundary region 105 are grounded with the emitter electrode 13, thereby preventing the deterioration of the reverse bias safe operating region.

[0089] Furthermore, since the IGBT region 101 and the FWD region 102 are separated by trenches, the p-type channel doped portion 2 and the p-type anode region 5 are not connected. Therefore, hole current entering the FWD region 102 and the boundary region 105 does not flow into the IGBT region 101. Thus, the deterioration of the reverse bias safe operating region can be further prevented.

[0090] Furthermore, as a fourth and fifth feature, the high-concentration second p-type contact region 4 of the IGBT region 101 is formed in a manner that overlaps with or contacts the p-type well region 16, and the contact region 15 of the IGBT region 101 includes the second p-type contact region 4 and the p-type well region 16. Therefore, when the IGBT is turned off, holes present in the peripheral region 103 flow from the p-type well region 16 through the second p-type contact region 4 to the contact region 15, thus suppressing the inflow of hole current into the unit interior where the n-type emitter region 3 is formed. Therefore, the reduction of the safe operating area can be suppressed. Typically, countermeasures against hole inflow from the peripheral region with a high concentration and deep p-type diffusion layer are insufficient, but this feature can improve this.

[0091] Furthermore, based on the second, third, sixth, and seventh features, recovery losses during FWD operation can be reduced. As the second and third features, a p-type anode region 5, a first p-type contact region 6, a first p-type region 38, and a second p-type region 39 are formed in the FWD region 102 and the boundary region 105, reducing the effective impurity concentration of the diode's anode. Moreover, since the emitter electrode 13 is in contact with the p-type anode region 5, the first p-type contact region 6, the first p-type region 38, and the second p-type region 39, the concentration of incoming hole current can be prevented. Therefore, holes near the anode can be efficiently discharged during recovery operation, reducing recovery losses.

[0092] The forward voltage drop and recovery loss of a diode are in a trade-off relationship with the anode concentration. Reducing the effective anode concentration is effective when it is desirable to reduce recovery loss. As described in features six and seven, recovery loss can be reduced by decreasing the area of ​​the first p-type contact region 6, which has a high concentration. Setting the area ratio of the first p-type contact region 6 to, for example, approximately 10-50% can effectively reduce recovery loss. Furthermore, according to features eight and nine, by setting a high p-type impurity concentration in the IGBT region 101, the deterioration of the reverse bias safe operating region can be suppressed, and by setting a low p-type impurity concentration in the FWD region 102 and the boundary region 105, the recovery loss during FWD operation can be reduced.

[0093] Furthermore, as in the third feature, the first p-type contact region 6 and the first p-type region 38 are formed into a long p-type region in the FWD region 102 and the boundary region 105, thus forming a narrow contact hole, thereby stabilizing the contact width. This allows for a stable formation of the p-type impurity concentration in the anode region of the FWD region 102 and the boundary region 105.

[0094] The variations, modifications, or alternatives described in Embodiment 1 can be applied to the semiconductor device involved in the following embodiments. The differences between the following embodiments and Embodiment 1 will be primarily explained for the semiconductor device involved in the embodiments.

[0095] Implementation method 2.

[0096] Figure 6 This is a partial top view of the semiconductor device involved in Embodiment 2. Figure 6 and Figure 1 The top view corresponds to the dashed line portion. Figure 7-9 They are respectively Figure 6 The sectional views shown are along line A′-A′, line B′-B′, and line C′-C′.

[0097] Both the first p-type region 38 and the second p-type region 39 are in contact with the second trench 32. Figure 6 As shown, when viewed from above, the second p-shaped region 39 and the first p-shaped region 38 are in contact with the second groove 32. Figure 7 As shown in the cross-section, the second p-type region 39 and the first p-type region 38 are in contact with the second trench 32. Moreover, the portion of the first p-type region 38 that is in contact with the second trench 32 when viewed from above is opposite to the n-type emitter region 3.

[0098] When the IGBT is in the ON state, hole current flows into the IGBT region 101 from the collector side, and some current also flows through the boundary region 105 and the FWD region 102. Therefore, at the boundary of the IGBT region 101, the current tends to concentrate when the IGBT is off. In particular, near the n-type emitter region 3, the resistance of the channel doped portion 2 directly below the n-type emitter region becomes high, which easily leads to latch-up and causes the deterioration of the reverse bias safe operating region.

[0099] In this embodiment, because the p-type impurity concentration on the IGBT region side of the boundary region 105 is set high, the component of hole current released from the boundary region 105 to the emitter electrode 13 during IGBT operation increases, which can suppress the reduction of the reverse bias safe operating region. Furthermore, since the first p-type region 38 is disposed near the n-type emitter region 3, which is prone to latch-up, the reduction of the reverse bias safe operating region during IGBT operation can be further suppressed.

[0100] Implementation method 3.

[0101] Figure 10 This is a partial top view of the semiconductor device involved in Embodiment 3. Figure 10 and Figure 1 The top view corresponds to the dashed line portion. Figure 11-13They are respectively Figure 10 The sectional views shown are along line A′-A′, line B′-B′, and line C′-C′.

[0102] The first p-type contact region 6 formed in the FWD region 102 and the first p-type region 38 formed in the boundary region 105 are composed of a plurality of rectangular patterns extending in the longitudinal direction. Furthermore, when the length of the rectangular pattern in the longitudinal direction is defined as L1 and the interval as W1, L1 ≥ W1. The first p-type contact region 6 is formed on a unit basis and has a plurality of rectangular portions parallel to the first trench 30 when viewed from above. Moreover, the length of each of the plurality of rectangular portions in the longitudinal direction is greater than the distance between the plurality of rectangular portions. Additionally, when viewed from above, the area of ​​the first p-type contact region 6 at each unit of the FWD region 102 is smaller than the area of ​​the p-type anode region 5.

[0103] Therefore, the contact width can be stabilized during manufacturing, and the p-type impurity concentration in the p-type anode region 5 can be stably formed. This allows for a stable improvement in recovery characteristics. Furthermore, by forming the first p-type contact region 6 to be long and large in the long side direction, manufacturing fluctuations can be reduced, thus stabilizing the recovery characteristics.

[0104] Implementation method 4.

[0105] Figure 14 This is a partial top view of the semiconductor device involved in Embodiment 4. Figure 14 and Figure 1 The top view corresponds to the dashed line portion. Figure 15-17 They are respectively Figure 14 The sectional views shown are along line A′-A′, line B′-B′, and line C′-C′.

[0106] The p-type anode region 5 has a portion that is linearly formed when viewed from above and has a portion in which the first p-type contact region 6 is formed, and a portion that is linearly formed when viewed from above and has a portion in which the first p-type contact region 6 is not formed. Moreover, by alternately setting the first p-type region 38 and the second p-type region 39 when viewed from above in the boundary region 105, the p-type region becomes annular.

[0107] Moreover, according to one example, the sum of the areas of the first p-type contact region 6 and the first p-type region 38 is smaller than the sum of the areas of the p-type anode region 5 and the second p-type region 39.

[0108] According to the semiconductor device of Embodiment 4, the size of the first p-type contact region 6 can be selected to a size that can be stably formed in manufacturing, and the total area of ​​the first p-type contact region 6 of the entire FWD region 102 can be smaller than the total area of ​​the p-type anode region 5. Therefore, the p-type impurity concentration of the anode region of the FWD region 102 can be stably formed, and the recovery characteristics can be stably improved. The FWD region 102 has unit cells that do not include the first p-type contact region 6, thus the size of one unit cell of the first p-type contact region 6 is increased to some extent. Therefore, the size of the contact region 15 of the first p-type contact region 6 is increased, thereby reducing dimensional fluctuations and stabilizing the recovery characteristics.

[0109] Implementation method 5.

[0110] Figure 18 This is a partial top view of the semiconductor device according to Embodiment 5. Figure 18 and Figure 1 The top view corresponds to the dashed line portion. Figure 19-21 They are respectively Figure 18 The sectional views shown are along line A′-A′, line B′-B′, and line C′-C′.

[0111] When viewed from above, the first p-type contact region 6 and the p-type anode region 5 are alternately arranged, and the first p-type region 38 and the second p-type region 39 are alternately arranged. According to one example, when viewed from above, the area of ​​the first p-type contact region 6 is smaller than the area of ​​the p-type anode region 5. In other words, when viewed from above, the area of ​​the first p-type contact region 6 in each unit is smaller than the area of ​​the p-type anode region 5.

[0112] According to the semiconductor device of Embodiment 5, the size of the first p-type contact region 6 can be selected to a size that can be stably formed in manufacturing, and the total area of ​​the first p-type contact region 6 throughout the FWD region 102 can be smaller than the total area of ​​the p-type anode region 5. Therefore, p-type impurities in the p-type anode region 5 of the FWD region 102 can be stably formed, thus reliably improving the recovery characteristics. Furthermore, by alternately arranging the first p-type contact region 6 and the p-type anode region 5, the first p-type contact region 6 is locally configured, thereby improving the recovery characteristics during FWD operation.

[0113] Implementation method 6.

[0114] Figure 22 This is a partial top view of the semiconductor device according to Embodiment 6. Figure 22 and Figure 1 The top view corresponds to the dashed line portion. Figure 23-25 They are respectively Figure 22The sectional views shown are along line A′-A′, line B′-B′, and line C′-C′.

[0115] The dumb trenches 40 are arranged in a grid pattern in the FWD region 102 when viewed from above. That is, the FWD region 102 is a grid-like structure divided by the dumb trenches 40. A first p-type contact region 6 and a p-type anode region 5 are formed in the region divided by these dumb trenches. According to one example, the area of ​​the first p-type contact region 6 in each unit is smaller than the area of ​​the p-type anode region 5. Figure 22 As shown, when viewed from above, multiple regions are provided that have a first p-type contact region 6 and a p-type anode region 5, wherein the area of ​​the first p-type contact region 6 is smaller than the area of ​​the p-type anode region 5.

[0116] According to this embodiment, p-type impurities in the FWD region 102 can be stably formed, thereby achieving a stable improvement in recovery characteristics. Furthermore, by making the size of the p-type contact region of the unit portion of the FWD region 102 larger, dimensional fluctuations can be reduced, thus stabilizing the recovery characteristics.

[0117] Implementation method 7.

[0118] Figure 26 This is a partial top view of the semiconductor device according to Embodiment 7. Figure 26 and Figure 1 The top view corresponds to the dashed line portion. Figure 27-29 They are respectively Figure 26 The sectional views shown are along line A′-A′, line B′-B′, and line C′-C′.

[0119] The trench spacing in FWD region 102 is wider than the trench spacing in IGBT region 101. The spacing is an interval. Figure 26 In this example, since there is only one dummy trench 40, the spacing between the dummy trenches can be considered infinitely large, larger than the spacing between the trenches 50 in the IGBT region 101. If this spacing relationship is satisfied, multiple dummy trenches 40 can also be formed. Furthermore, according to one example, the area of ​​the first p-type contact region 6 of each unit cell in the FWD region 102 is smaller than the area of ​​the p-type anode region 5.

[0120] By adjusting the trench spacing as described above, when the IGBT is disconnected and a voltage is applied, the electric field strength directly below the trench in the FWD region 102 is stronger than that directly below the trench in the IGBT region 101. Therefore, avalanche breakdown can occur in the FWD region 102 instead of the IGBT region 101 during an avalanche, thus suppressing overvoltage damage. In other words, by setting the avalanche breakdown point to the FWD region 102, overvoltage damage can be prevented.

[0121] Implementation method 8.

[0122] Figure 30 This is a partial top view of the semiconductor device according to Embodiment 8. Figure 30 and Figure 1 The top view corresponds to the dashed line portion. Figures 31-33 They are respectively Figure 30 The sectional views shown are along line A′-A′, line B′-B′, and line C′-C′.

[0123] The width of the first p-type region 38 at the boundary region 105 is wider than the width of the first p-type contact region 6 in the FWD region 102. Therefore, when viewed from above, the area ratio of the first p-type region 38 in the boundary region 105 is greater than the area ratio of the first p-type contact region 6 in the FWD region 102 excluding the trenched portion. That is, the effective concentration of the anode in the boundary region 105 is higher than the effective concentration in the portion of the FWD region 102 excluding the trenched portion, i.e., the "surface mesa".

[0124] In this embodiment, since the effective p-type impurity concentration of the boundary region 105 is set higher than that of the FWD region 102, the hole current released from the boundary region 105 to the emitter electrode 13 increases during IGBT operation, thus suppressing the reduction of the reverse bias safe operating region. Furthermore, since the p-type impurity concentration near the n-type emitter region 3, which is prone to latch-up, is also increased, the reduction of the reverse bias safe operating region during IGBT operation can also be suppressed.

[0125] In addition to the features described above, the width of the first p-type contact region 6 near the boundary region 105 in the FWD region 102 can be made wider than the width of the first p-type contact region 6 not located near the boundary region 105. According to other examples, the width of multiple first p-type contact regions 6 can also gradually decrease with distance from the boundary region 105. Thus, by making the high-concentration first p-type contact regions 6 large at a unit location near the IGBT in the FWD region 102, the reverse bias safe operating area during IGBT operation can be improved.

[0126] Implementation method 9.

[0127] Figure 34 This is a partial top view of the semiconductor device according to Embodiment 9. Figure 34 and Figure 1 The top view corresponds to the dashed line portion. Figures 35-37 They are respectively Figure 34 The sectional views shown are along line A′-A′, line B′-B′, and line C′-C′.

[0128] The width of the first p-type region 38 at the boundary region 105 is narrower than the width of the first p-type contact region 6 in the FWD region 102. Therefore, when viewed from above, the area ratio of the first p-type region 38 in the boundary region 105 is smaller than the area ratio of the first p-type contact region 6 in the FWD region 102 excluding the trenched portion. That is, the effective concentration of the anode in the boundary region 105 is lower than the effective concentration in the portion of the FWD region 102 excluding the trenched portion, i.e., the "surface mesa." Thus, it has characteristics opposite to those of the semiconductor device in Embodiment 8.

[0129] When the diode operates, the boundary region 105 and IGBT region 101 near the FWD region 102 have p-type impurities and are structurally operated as parasitic diodes. Preferably, the boundary region 105 and IGBT region 101 do not operate as diodes. In this embodiment, by reducing the average impurity concentration at the anode of the boundary region 105, recovery loss can be effectively reduced.

[0130] In addition to the features described above, the width of the first p-type contact region 6 near the boundary region 105 in the FWD region 102 can be made narrower than the width of the first p-type contact region 6 not located near the boundary region 105. According to other examples, the width of multiple first p-type contact regions 6 can also gradually increase with distance from the boundary region 105. Thus, by making the high-concentration first p-type contact regions 6 small at a unit location near the IGBT in the FWD region 102, the aforementioned effect can be achieved. That is, by making the portion of the FWD region 102 near the boundary region 105 a low-concentration p-anode portion, the recovery characteristics can be improved.

[0131] Implementation method 10.

[0132] Figure 38 This is a partial top view of the semiconductor device according to Embodiment 10. Figure 38 and Figure 1 The top view corresponds to the dashed line portion. Figures 39-41 They are respectively Figure 38 The sectional views shown are along line A′-A′, line B′-B′, and line C′-C′.

[0133] Regarding the unit cells in IGBT region 101 that are in contact with boundary region 105, the area ratio of the second p-type contact region 4 is smaller compared to unit cells that are not in contact with boundary region 105. According to other examples, regarding a plurality of unit cells in IGBT region 101 near boundary region 105, the area ratio of the second p-type contact region 4 can be set smaller compared to other unit cells. To set the area ratio of the second p-type contact region 4 smaller, for example in… Figure 1 The portion having the second p-type contact region 4 can be replaced with the channel doped portion 2. This reduces the average concentration of p-type impurities in the IGBT region 101 near the FWD region 102. Consequently, hole diffusion in the IGBT region 101 during the on-state of FWD operation is reduced, thus lowering recovery loss.

[0134] The unit cell that reduces the area ratio of the second p-type contact region 4 can be one or more. According to other examples, the area ratio of the second p-type contact region 4 of each unit cell can also gradually decrease as it moves away from the boundary region 105.

[0135] Implementation method 11.

[0136] Figure 42 This is a partial top view of the semiconductor device according to Embodiment 11. Figure 42 and Figure 1 The top view corresponds to the dashed line portion. Figures 43-45 They are respectively Figure 42 The sectional views shown are along line A′-A′, line B′-B′, and line C′-C′.

[0137] Regarding the unit cells in IGBT region 101 that are in contact with boundary region 105, the area ratio of the second p-type contact region 4 is larger than that of unit cells that are not in contact with boundary region 105. According to other examples, for a plurality of unit cells in IGBT region 101 that are close to boundary region 105, the area ratio of the second p-type contact region 4 can be set larger compared to other unit cells. Furthermore, according to other examples, the area ratio of the second p-type contact region 4 can also be increased across the entire unit cell region surrounded by the trench.

[0138] As a result, the average concentration of p-type impurities in the IGBT region 101 near the boundary region 105 increases. Therefore, similar to Embodiment 1, the effect of preventing the reduction of the reverse bias safe operating area during IGBT operation can be improved.

[0139] In embodiments 1-11, RC-IGBTs were described, but the features of these embodiments can be applied to MOSFETs, etc. Furthermore, a Si substrate can be used as the substrate Sb, but the substrate Sb can also be formed from a wide-bandgap semiconductor. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, or diamond. As a unit structure near the emitter electrode 13 of the IGBT, an example is a unit where the trench gate extends in a strip-like pattern along one direction, but the aforementioned features can be applied to a unit structure called a grid type where the trench gate extends longitudinally and laterally, and a unit structure other than the trench type called a planar type. Furthermore, the features involved in the embodiments described so far can be combined and used.

[0140] Explanation of the label

[0141] 3n-type emitter region, 4 second p-type contact region, 5 p-type anode region, 6 first p-type contact region, 30 first trench, 32 second trench, 40 dumb trench, 50 trench, 101 IGBT region, 102 FWD region, 103 peripheral region, 104 gate pad region

Claims

1. A semiconductor device, characterized in that, have: The FWD region is formed on the substrate and has a p-type anode region, a first p-type contact region with a p-type impurity concentration higher than that of the p-type anode region, and a first trench on the upper surface side of the substrate. The IGBT region is formed on the substrate and surrounds the FWD region with a boundary region when viewed from above. It has an n-type emitter region, a second p-type contact region, and a second trench on the upper surface side of the substrate. The outer peripheral region, which, when viewed from above, surrounds the FWD region, the boundary region, and the IGBT region; and The emitter electrode on the upper surface of the substrate, When viewed from above, the first groove forms a ring shape along the outer edge of the FWD region. When viewed from above, the second groove forms a ring shape along the outer edge of the boundary region. The upper surface of the boundary region has only a p-type region. The p-type region includes a first p-type region and a second p-type region with a lower p-type impurity concentration than the first p-type region. The first p-type region and the second p-type region are in contact with the emitter electrode. When viewed from above, if the area ratio of the first p-type contact area of ​​each unit in the FWD region is set as the first area ratio, the area ratio of the first p-type contact area of ​​each unit in the boundary region is set as the second area ratio, and the area ratio of the second p-type contact area of ​​each unit in the IGBT region is set as the third area ratio, the sum of the first area ratio and the second area ratio is less than the third area ratio.

2. The semiconductor device according to claim 1, characterized in that, When viewed from above, if the area ratio of the p-type anode region of each unit in the FWD region is set as the fourth area ratio, and the area ratio of the second p-type region of each unit in the boundary region is set as the fifth area ratio, the sum of the first area ratio and the second area ratio is less than the sum of the fourth area ratio and the fifth area ratio.

3. The semiconductor device according to claim 1, characterized in that, The outer peripheral region has a p-shaped well region, which is in contact with the second p-shaped contact region when viewed from above.

4. The semiconductor device according to claim 1, characterized in that, The first p-type contact area is formed on a unit basis and has an elongated shape parallel to the first groove when viewed from above. The first p-shaped region has a ring-shaped shape that surrounds the FWD region when viewed from above.

5. The semiconductor device according to claim 1, characterized in that, When viewed from above, the second p-shaped region is in contact with the second groove, while the first p-shaped region is not in contact with the second groove.

6. The semiconductor device according to claim 1, characterized in that, When viewed from above, the second p-shaped region, the first p-shaped region, and the second trench are in contact.

7. The semiconductor device according to claim 6, characterized in that, The portion of the first p-type region that contacts the second trench when viewed from above is opposite to the n-type emitter region.

8. The semiconductor device according to claim 1, characterized in that, The first p-type contact area is formed in units of each unit and has multiple rectangular portions parallel to the first groove when viewed from above. The length of each of the multiple rectangular portions is greater than the distance between the multiple rectangular portions.

9. The semiconductor device according to claim 1, characterized in that, The p-type anode region has a portion that is linearly formed when viewed from above and has part of the first p-type contact region formed therein, and a portion that is linearly formed when viewed from above and has part of the first p-type contact region not formed therein. When viewed from above, the first p-shaped region and the second p-shaped region are alternately set, so that the p-shaped region becomes a ring.

10. The semiconductor device according to claim 9, characterized in that, The sum of the areas of the first p-type contact region and the first p-type region is smaller than the sum of the areas of the p-type anode region and the second p-type region.

11. The semiconductor device according to claim 1, characterized in that, When viewed from above, the first p-type contact area and the p-type anode area are alternately arranged. When viewed from above, the first p-shaped region and the second p-shaped region are set alternately.

12. The semiconductor device according to claim 8, characterized in that, When viewed from above, the area of ​​the first p-type contact region is smaller than the area of ​​the p-type anode region.

13. The semiconductor device according to claim 11, characterized in that, When viewed from above, the area of ​​the first p-type contact region is smaller than the area of ​​the p-type anode region.

14. The semiconductor device according to claim 1, characterized in that, The FWD area has grooves that are set in a grid pattern when viewed from above. When viewed from above, multiple regions are provided that form the first p-type contact region and the p-type anode region, wherein the area of ​​the first p-type contact region is smaller than the area of ​​the p-type anode region.

15. The semiconductor device according to any one of claims 1 to 14, characterized in that, The trench spacing in the FWD region is wider than the trench spacing in the IGBT region.

16. The semiconductor device according to claim 1, characterized in that, When viewed from above, the area ratio of the first p-type region in the boundary region is greater than the area ratio of the first p-type contact region in the FWD region excluding the portion where the groove is formed.

17. The semiconductor device according to claim 1, characterized in that, When viewed from above, the area ratio of the first p-type region in the boundary region is smaller than the area ratio of the first p-type contact region in the FWD region excluding the portion where the groove is formed.

18. The semiconductor device according to any one of claims 1 to 14, characterized in that, For the unit cells in the IGBT region that are in contact with the boundary region, the area ratio of the second p-type contact region is smaller than that of the unit cells that are not in contact with the boundary region.

19. The semiconductor device according to any one of claims 1 to 14, characterized in that, For the unit cells in the IGBT region that are in contact with the boundary region, the area ratio of the second p-type contact region is larger than that of the unit cells that are not in contact with the boundary region.

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