Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The method of fabricating a minimum fin structure length includes forming a fin structure extending along a first direction on a substrate, forming a first single diffusion isolation structure and a second single diffusion isolation structure extending along a second direction and separating the fin structure into a first portion, a second portion, and a third portion. A fin cut fabrication process is then performed, such as forming a patterned mask on the substrate, wherein the patterned mask includes an opening exposing the first single diffusion isolation structure, the second portion, and the second single diffusion isolation structure, and subsequently removing the first portion to the third portion.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, specifically a method for improving the viewing window during photolithography using a single-diffusion isolation structure. Background Technology

[0002] In recent years, with the continuous shrinking of field-effect transistor (FET) device dimensions, the development of existing planar FET devices has reached the limits of fabrication technology. To overcome these limitations, replacing planar FET devices with non-planar FET devices, such as fin field-effect transistors (Fin FETs), has become the mainstream development trend. Because the three-dimensional structure of Fin FETs increases the contact area between the gate and the fin structure, it further enhances the gate's control over the carrier channel region, thereby reducing the drain-induced barrier lowering (DIBL) effect faced by small-sized devices and suppressing the short-channel effect (SCE). Furthermore, since Fin FETs have a wider channel width for the same gate length, they can achieve double the drain drive current. Moreover, the threshold voltage of the transistor device can be controlled by adjusting the work function of the gate.

[0003] In current fin field-effect transistor (FET) fabrication processes, after forming shallow trench isolation around the fin structure, a portion of the fin structure and the shallow trench isolation is typically removed by etching to form a groove. An insulating material is then filled in to form a single-diffused isolation structure, separating the fin structure into two parts. However, current fabrication processes for single-diffused isolation structures and metal gates still face many bottlenecks, such as the window limit of photolithography. Therefore, improving existing fin field-effect transistor fabrication processes is a crucial current research topic. Summary of the Invention

[0004] This invention discloses a method for fabricating a minimum fin-like structure length. First, a fin-like structure is formed extending along a first direction on a substrate. Then, a first monodiffusion isolation structure and a second monodiffusion isolation structure are formed extending along a second direction, dividing the fin-like structure into a first part, a second part, and a third part. Next, a fin-like structure cutting process is performed, for example, first forming a patterned mask on the substrate, wherein the patterned mask includes an opening exposing the first monodiffusion isolation structure, the second part, and the third monodiffusion isolation structure, and then removing the first part and the third part.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a fin structure extending on a substrate along a first direction, a first monodiffusion isolation structure extending on one side of the fin structure along a second direction, and a second monodiffusion isolation structure extending on the other side of the fin structure along the second direction. The first monodiffusion isolation structure includes a first side contacting the fin structure and a second side not contacting any fin structure, while the second monodiffusion isolation structure includes a third side contacting the fin structure and a fourth side not contacting any fin structure. Attached Figure Description

[0006] Figures 1 to 6 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0007] Figure 7 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0008] Figures 8 to 10 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0009] Explanation of main component symbols

[0010] 12: Base

[0011] 14: Virtual Area

[0012] 16: Active (Powered) Region

[0013] 18: Fin-like structure

[0014] 20: Protrusion

[0015] 22: First monodiffusion isolation structure

[0016] 24: Second monodiffusion isolation structure

[0017] 26: Groove

[0018] 28: Part One

[0019] 30: Part Two

[0020] 32: Part Three

[0021] 34: Dielectric layer

[0022] 36: Patterned Mask

[0023] 38: Shallow trench isolation

[0024] 40: Gate structure

[0025] 42: Gate structure

[0026] 44: Gate Structure

[0027] 46: Gate structure

[0028] 48: Gate structure

[0029] 50: Gate dielectric layer

[0030] 52: Gate material layer

[0031] 54: Spacer wall

[0032] 56: Doped region

[0033] 58: Source / Drain Region

[0034] 60: Protrusion Detailed Implementation

[0035] Please refer to Figures 1 to 6 , Figures 1 to 6 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein... Figures 1 to 6 The lower left half shows a cross-sectional view along the tangent AA' in each figure. Figures 1 to 6 The lower right half shows a cross-sectional view along the tangent BB' in each figure. For example... Figure 1 As shown, a substrate 12, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, is first provided. Then, a dummy region 14 and an active region 16 are defined on the substrate 12, and a plurality of fin structures 18 are formed on the substrate 12, spanning the dummy region 14 and the active region 16. The dummy region 14 is preferably used in subsequent fabrication processes to form the minimum-length fin structures and the dummy gate structures spanning it, while the active region 16 is used to form standard-length fin structures and the active gate structures and metal-oxide-semiconductor transistor elements disposed thereon. In this embodiment, although ten fin structures 18 are used as an example, their number can be arbitrarily adjusted according to product requirements and is not limited to this.

[0036] According to a preferred embodiment of the present invention, the fin structure 18 is preferably fabricated using techniques such as sidewall image transfer (SIT). The procedure generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on the substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layers. The patterned sacrificial layers are then removed, and etching is performed under the cover of the spacers, transferring the pattern formed by the spacers into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0037] In addition, the formation of the fin structure 18 may also include first forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 through an etching process to form the fin structure 18. Alternatively, the fin structure 18 may be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial fabrication process to grow a semiconductor layer, such as silicon-germanium, on the substrate 12 exposed above the patterned hard mask layer. This semiconductor layer can then serve as the corresponding fin structure 18. These embodiments of forming the fin structure 18 are all within the scope of this invention.

[0038] like Figure 2 As shown, then, depending on the manufacturing process requirements, a photolithography and etching process or a fin removal process can be used to selectively remove parts of the fin structure 18 outside the dummy region 14 and the active region 16, such as parts of the fin structure 18 adjacent to the top and bottom of the dummy region 14. Figure 2 As shown in the lower left part, after removing part of the fin structure 18, the remaining fin structure 18 above and below the dummy area 14 is preferably formed into protrusions 20 on the base 12. The height of the protrusions 20 can be adjusted according to the manufacturing process requirements, for example, it can be less than half or one-third of the overall height of the original fin structure 18 on both sides. These are all within the scope of the present invention.

[0039] like Figure 3 As shown, a single diffusion break (SDB) structure is then formed on both sides of the dummy region 14, such as a first SDB structure 22 and a second SDB structure 24 spanning the fin structure 18. In this embodiment, the steps of forming the first SDB structure 22 and the second SDB structure 24 can be performed by first forming a patterned mask (not shown) on the substrate 12, and then using the patterned mask (not shown) to perform an etching process to remove a portion of the fin structure 18 on both sides of the dummy region 14 along a direction perpendicular to the fin structure 18 to form a groove 26 or a single diffusion break groove, and at the same time dividing each fin structure 18 into three parts. Taking the grooves 26 formed on both sides of the dummy region 14 as an example, the grooves 26 preferably divide each fin structure 18 into a first part 28 located on the left side of the first monodiffusion isolation structure 22, a third part 32 located on the right side of the second monodiffusion isolation structure 24, and a second part 30 located between the first monodiffusion isolation structure 22 and the second monodiffusion isolation structure 24. The grooves 26 formed therein are used to define the position where the subsequent monodiffusion isolation structure is formed.

[0040] Subsequently, a dielectric layer 34 may be selectively formed in the grooves 26 and fill each groove 26. A planarization process, such as etch-back and / or chemical mechanical polishing, is used to remove part of the dielectric layer 34. Then, a photolithography and etching process is performed to remove part of the dielectric layer 34 outside the grooves 26, so that the remaining dielectric layer 34 is slightly lower than the top surface of each fin structure 18 to form the first monodiffusion isolation structure 22 and the second monodiffusion isolation structure 24. In this embodiment, each fin structure 18 preferably extends along a first direction (e.g., the X direction), and the first monodiffusion isolation structure 22 and the second monodiffusion isolation structure 24 on both sides of the dummy area 14 extend along a second direction (e.g., the Y direction) perpendicular to the first direction.

[0041] like Figure 4 As shown, a fin-like structure cutting and fabrication process is then performed to remove the first portion 28 and the third portion 32 of the aforementioned fin-like structure 18. In this embodiment, the fin-like structure cutting and fabrication process may include first forming a patterned mask 36, for example, patterning a photoresist onto the substrate 12, wherein the patterned mask 36 preferably covers a portion of the first single-diffusion isolation structure 22, the second portion 30 located in the dummy region 14, a portion of the second single-diffusion isolation structure 24, and the active region 16 adjacent to the dummy region 14, and exposes other areas not covered by the patterned mask 36.

[0042] like Figure 5 As shown, an etching process is then performed using a patterned mask 36 to remove the first monodiffusion isolation structure 22, the second portion 30, the second monodiffusion isolation structure 24, and the fin-like structures 18 outside the active region 16, such as the first portion 28 and the third portion 32. Afterwards, the patterned mask 36 is removed, forming a shallow trench isolation (STI) 38 surrounding the dummy region 14 and the active region 16. In this embodiment, the monodiffusion isolation structures and the shallow trench isolation 38 are preferably formed at different stages and may contain the same or different materials. For example, the first monodiffusion isolation structure 22 and the second monodiffusion isolation structure 24 preferably contain silicon nitride, while the shallow trench isolation 38 contains silicon oxide, but this is not a limitation.

[0043] like Figure 6As shown, gate structures 40, 42, 44, 46, and 48 are then formed on the fin-like structure 18 of the dummy region 14 and the active region 16. In this embodiment, the gate structures 40, 42, 44, 46, and 48 can be fabricated according to the manufacturing process requirements using methods such as a gate-first fabrication process, a gate-last fabrication process with a high-k-first dielectric layer, or a gate-last fabrication process with a high-k-last dielectric layer. Taking the high dielectric constant dielectric layer fabrication process of this embodiment as an example, a gate dielectric layer 50 or dielectric layer, a gate material layer 52 made of polysilicon and a selective hard mask (not shown) can be sequentially formed on the substrate 12. A patterned photoresist (not shown) is used as a mask to perform a pattern transfer fabrication process. In a single etching or successive etching step, part of the gate material layer 52 and part of the gate dielectric layer 50 are removed. Then the patterned photoresist is stripped to form gate structures 40, 42, 44, 46 and 48 on the substrate 12, which are composed of the patterned gate dielectric layer 50 and the patterned gate material layer 52.

[0044] Subsequently, spacer walls 54 can be formed on the sidewalls of each gate structure 40, 42, 44, 46, and 48 according to the manufacturing process requirements. Doped regions 56 or source / drain regions 58 can be formed in the fin-like structures 18 on both sides of the spacer wall 54. For example, a doped region 56 can be formed between the gate structures 40 and 42 of the dummy region 14, and source / drain regions 58 can be formed on both sides of the gate structure 46 of the active region 16. In this embodiment, each spacer wall 54 can be a single spacer wall or a composite spacer wall. For example, it can include a bias spacer wall and a main spacer wall. The bias spacer wall and the main spacer wall can contain the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The source / drain region 58 may contain different dopants and epitaxial materials depending on the conductivity type of the transistor. For example, the source / drain region 58 of the NMOS region may contain silicon carbide (SiC) or silicon phosphide (SiP), while the source / drain region 58 of the PMOS region may contain silicon germanide (SiGe), but is not limited to these.

[0045] A dielectric layer (not shown) can then be formed to cover each gate structure 40, 42, 44, 46, and 48. Then, according to the fabrication process requirements, a metal gate replacement process can be performed to convert each gate structure 40, 42, 44, 46, and 48 into a metal gate. Since converting each gate structure 40, 42, 44, 46, and 48 into a metal gate using a metal gate replacement process is a well-known technique in the art, it will not be described in detail here. It should be noted that the second portion 30 of the fin-like structure separated in the dummy region 14 according to the aforementioned fabrication process is preferably a fin-like structure with a minimum length. Therefore, the dummy region 14 is only sufficient to form gate structures 40, 42, or more specifically, dummy gate structures at the head and tail ends of the second portion 30 of the fin-like structure 18, and cannot form an actual operating gate structure 46 that can together with the source / drain regions 58 on the left and right sides, as the standard-length fin-like structure 18 in the active region 16 can.

[0046] Please refer to again Figure 6 , Figure 6 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. For example... Figure 6 As shown, the semiconductor device mainly includes a dummy region 14 and an active region 16 defined on a substrate 12. A plurality of fin structures 18 extend along a first direction, such as the X direction, in the dummy region 14 and the active region 16. A first monodiffusion isolation structure 22 extends along a second direction, such as the Y direction, on one side of the fin structure 18 in the dummy region 14 (as shown on the left). A second monodiffusion isolation structure 24 extends along the same second direction on the other side of the fin structure 18 in the dummy region 14 (as shown on the right). A gate structure 40 extends along the Y direction and overlaps one side of the fin structure 18 in the dummy region 14 (as shown on the left). A gate structure 42 extends along the Y direction and overlaps the other side of the fin structure 18 in the dummy region 14 (as shown on the right). A gate structure 44 extends along the Y direction on one side of the fin structure 18 in the active region 16 (as shown on the left). A gate structure 48 extends along the Y direction on the other side of the fin structure 18 in the active region 16 (as shown on the right). A gate structure 46 extends along the Y direction between the gate structures 44 and 48 in the active region 16.

[0047] In detail, the edge of the gate structure 40 in the dummy region 14 is preferably flush with the left edge of the fin structure 18, and the edge of the gate structure 42 is flush with the right edge of the fin structure 18. The first monodiffusion isolation structure 22 includes a first side, for example, the right side, which contacts the fin structure 18, and a second side, for example, the left side, which does not contact any fin structure 18. Similarly, the second monodiffusion isolation structure 24 includes a third side, for example, the left side, which contacts the fin structure 18, and a fourth side, for example, the right side, which does not contact any fin structure 18.

[0048] Additionally from Figure 6Looking at the cross-sectional view at the lower right, the bottom of the first monodiffusion isolation structure 22 on the left side of the dummy region 14 and the bottom of the second monodiffusion isolation structure 24 on the right side are both slightly lower than the top of the base 12. Or, from another angle, the top of the base 12 directly below the first monodiffusion isolation structure 22 is lower than the top of the base 12 directly below the fin structure 18 in the dummy region 14. Similarly, the top of the base 12 directly below the second monodiffusion isolation structure 24 is also lower than the top of the base 12 directly below the fin structure 18.

[0049] Please refer to again Figure 7 , Figure 7 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. For example... Figure 7 As shown in the lower right part, compared to the previous embodiment where the first part 28 and the third part 32 were removed by a fin-shaped structure cutting process so that the left side of the first single-diffusion isolation structure 22 does not contact any fin-shaped structure 18 and the right side of the second single-diffusion isolation structure 24 does not contact any fin-shaped structure 18, another embodiment of the present invention can be selected to retain part of the fin-shaped structure 18 to form a protrusion 60 when the first part 28 and the third part 32 are removed by a fin-shaped structure cutting process, so that the right side of the first single-diffusion isolation structure 22 contacts the fin-shaped structure 18 and the left side contacts the protrusion 60, while the left side of the second single-diffusion isolation structure 24 contacts the fin-shaped structure 18 and the right side contacts the protrusion 60. This variation is also within the scope of the present invention.

[0050] Please refer to again Figures 8 to 10 , Figures 8 to 10 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 8 As shown, compared to the aforementioned Figures 3 to 5 In this embodiment, grooves 26 are formed on both sides of the dummy region 14, and a dielectric layer 34 is filled into the grooves 26 to form a first single-diffusion isolation structure 22 and a second single-diffusion isolation structure 24 before the fin structure cutting and fabrication process is performed. This invention can be... Figure 3 An etching process is performed using a patterned mask (not shown) to remove portions of the fin structure 18 on both sides of the dummy area 14 along a direction perpendicular to the fin structure 18 to form a groove 26 and to divide each fin structure 18 into three parts. The groove 26 can also be called a single diffusion isolation groove.

[0051] like Figure 9 As shown, the process proceeds directly after the aforementioned groove 26 is formed. Figures 4 to 5 The fin-like structure cutting and manufacturing process, for example, uses a patterned mask 36 as a mask to remove the fin-like structure 18 outside the dummy area 14 and the active area 16, such as the first part 28 and the third part 32, and then removes the patterned mask 36.

[0052] Then as Figure 10As shown, a dielectric layer 34 is formed in the grooves 26, filling each groove 26 and the area surrounding the grooves 26. A subsequent etching process removes a portion of the dielectric layer 34, forming a first single-diffusion isolation structure 22 and a second single-diffusion isolation structure 24 within the grooves 26, and simultaneously forming shallow trench isolation 38 beside the first single-diffusion isolation structure 22 and the second single-diffusion isolation structure 24. Since the first single-diffusion isolation structure 22, the second single-diffusion isolation structure 24, and the shallow trench isolation 38 are formed simultaneously in this stage, they preferably contain the same material, such as silicon oxide. Further processing can then be performed... Figure 6 The manufacturing process involves forming a gate structure on the fin-shaped structure 18 of the dummy region 14 and the active region 16, which will not be described in detail here.

[0053] In summary, this invention primarily discloses a method for fabricating a fin-like structure with the minimum required length. The method involves first dividing the fin-like structure of the dummy region 14 into three parts using a first and a second single-diffusion isolation structure. Then, a patterned mask is formed and applied to the first, second, and second portions of the fin-like structure located between the two single-diffusion isolation structures. Finally, a fin-like structure cutting process is used to remove the first and third portions on either side of the two single-diffusion isolation structures. Compared to current fin-like structure cutting processes using patterned masks, which cannot precisely remove fin-like structures outside the dummy or active regions due to the limitations of the photolithography window, this invention utilizes two single-diffusion isolation structures to expand the photolithography window, thereby improving the focus shift problem. Furthermore, since the second part 30 of the fin structure separated in the dummy region 14 using the aforementioned manufacturing process is preferably a fin structure with the minimum length, only two dummy gate structures 40 and 42 can be formed at the head and tail ends of the fin structure. Instead, it cannot form a gate structure 46 that can be formed together with the source / drain regions 58 on the left and right sides, as the fin structure with the standard length in the active region 16 can.

[0054] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for fabricating a minimum fin-like structure length, characterized in that, Include: A fin-like structure is formed extending along the first direction onto the substrate; The first and second monodiffusion isolation grooves are formed and extend along the second direction, dividing the fin-like structure into a first part, a second part, and a third part; as well as The first part and the third part are removed by a fin-like structure cutting and fabrication process. While removing the first part and the third part, a portion of the fin-like structure is retained to form a protrusion, so that the first side of the first monodiffusion isolation structure contacts the fin-like structure and the second side contacts the protrusion.

2. The method of claim 1, wherein the first portion is located on one side of the first monodiffusion isolation groove and the third portion is located on one side of the second monodiffusion isolation groove.

3. The method of claim 1, wherein the second portion is located between the first monodiffusion isolation groove and the second monodiffusion isolation groove.

4. The method of claim 1, further comprising forming a dielectric layer in the first monodiffusion isolation groove and the second monodiffusion isolation groove to form the first monodiffusion isolation structure and the second monodiffusion isolation structure.

5. The method of claim 4, wherein the second portion contacts the first monodiffusion isolation structure and the second monodiffusion isolation structure.

6. The method of claim 1, wherein the fin-like structure cutting and fabrication process comprises: A patterned mask is formed on the first single-diffusion isolation groove, the second portion, and the second single-diffusion isolation groove; and Remove the first part and the third part.

7. The method of claim 1, further comprising: A first gate structure is formed extending along the second direction on one side of the second portion; and A second gate structure is formed extending along the second direction on the other side of the second portion.

8. The method of claim 7, wherein the edge of the first gate structure is flush with the edge of the second portion.

9. The method of claim 7, wherein the edge of the second gate structure is flush with the edge of the second portion.

10. The method of claim 1, wherein the first direction is perpendicular to the second direction.

11. A semiconductor element, characterized in that, Include: Fin-like structures extend along a first direction onto the substrate; A first monodiffusion isolation structure extends along a second direction on one side of the fin structure, wherein the first monodiffusion isolation structure includes a first side contacting the fin structure and a second side contacting a protrusion formed by the retained fin structure; A second monodiffusion isolation structure extends along the second direction to the other side of the fin structure; as well as A first gate structure extends along the second direction on one side of the fin structure and is located directly on the top surface of the fin structure, wherein the first monodiffusion isolation structure is adjacent to the first gate structure, and the sidewall of the first gate structure is flush with the sidewall of the fin structure and the sidewall of the first monodiffusion isolation structure.

12. The semiconductor device of claim 11, wherein the second monodiffusion isolation structure includes a third side contacting the fin structure and a fourth side contacting a protrusion formed by the retained fin structure.

13. The semiconductor device of claim 11, further comprising: A second gate structure extends along the second direction on the other side of the fin structure.

14. The semiconductor device of claim 13, wherein the edge of the second gate structure is flush with the edge of the fin structure.

15. The semiconductor device of claim 11, wherein the top of the substrate located directly below the first monodiffusion isolation structure is lower than the top of the substrate located directly below the fin structure.

16. The semiconductor device of claim 11, wherein the top of the substrate located directly below the second monodiffusion isolation structure is lower than the top of the substrate located directly below the fin structure.

17. The semiconductor element of claim 11, wherein the first direction is perpendicular to the second direction.

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