Array substrate and manufacturing method thereof

Abstract

An array substrate and a manufacturing method thereof include: a substrate; scan lines and gates formed on the substrate, the gates being conductively connected to the scan lines; a first insulating layer covering the scan lines and gates; a drain electrode, a pixel electrode, a source electrode, and a data line formed on the first insulating layer, wherein the pixel electrode and the drain electrode are formed by patterning a first transparent conductive layer and are conductively connected to each other; the data line and the source electrode are formed by patterning a second metal layer and are conductively connected to each other; the source electrode and the drain electrode are spaced apart to form a channel region; a metal oxide semiconductor layer covering at least the drain electrode, the channel region, and the source electrode, the metal oxide semiconductor layer filling the channel region and being conductively connected to the drain electrode and the source electrode; and an insulating light-shielding layer covering the metal oxide semiconductor layer, the insulating light-shielding layer and the metal oxide semiconductor layer being arranged to overlap each other. The array substrate and the manufacturing method thereof not only save costs but also reduce photoinduced leakage.

Description

Technical Field

[0001] The present invention relates to the technical field of display devices, and in particular to an array substrate and a manufacturing method thereof. Background Art

[0002] Metal oxide TFTs are thin-film transistors that use metal oxide (such as IGZO) as the semiconductor layer. Currently, compared to low-temperature polysilicon TFTs and amorphous silicon TFTs, metal oxide TFTs have attracted widespread attention due to their advantages such as higher electron mobility, high transmittance, low leakage current, low deposition temperature, and low manufacturing cost. However, in the metal oxide TFT structure, in order to prevent etching damage to the metal oxide back channel, an etch stop layer (ESL) structure is usually used to prevent back channel etching damage, but this requires an additional photomask. In addition, before the S / D (source / drain) electrodes of the metal oxide TFT are fabricated, a conductor treatment is usually performed to ensure good ohmic contact between the S / D and the metal oxide semiconductor layer. This increases process complexity and cost, and indirectly reduces the market competitiveness of metal oxides. Summary of the Invention

[0003] In view of this, the present invention provides an array substrate and a manufacturing method thereof, which not only saves costs but also reduces the photo-induced leakage phenomenon.

[0004] An array substrate, comprising:

[0005] substrate;

[0006] A scan line and a gate are formed on the substrate, wherein the gate is conductively connected to the scan line;

[0007] a first insulating layer covering the scan line and the gate;

[0008] A drain electrode, a pixel electrode, a source electrode, and a data line are formed on the first insulating layer, wherein the pixel electrode and the drain electrode are formed by patterning the first transparent conductive layer and are conductively connected to each other, the data line and the source electrode are formed by patterning the second metal layer and are conductively connected to each other, and the source electrode and the drain electrode are spaced apart to form a channel region;

[0009] a metal oxide semiconductor layer covering at least the drain electrode, the channel region and the source electrode, the metal oxide semiconductor layer filling the channel region and being conductively connected to the drain electrode and the source electrode;

[0010] The insulating light-shielding layer covers the metal oxide semiconductor layer, and the insulating light-shielding layer and the metal oxide semiconductor layer are overlapped with each other.

[0011] In an embodiment of the present invention, the first transparent conductive layer is further overlapped and disposed below the source electrode and the data line.

[0012] In an embodiment of the present invention, the metal oxide semiconductor layer covers the drain, the channel region and the source; or, the metal oxide semiconductor layer covers the drain, the channel region, the source and the data line.

[0013] In an embodiment of the present invention, an orthographic projection of the metal oxide semiconductor layer on the substrate coincides with an orthographic projection of the insulating light-shielding layer on the substrate.

[0014] In an embodiment of the present invention, the insulating light-shielding layer is made of molybdenum oxide or copper nitride.

[0015] A method for manufacturing an array substrate, the method comprising:

[0016] providing a substrate;

[0017] forming a first metal layer on the substrate, and performing patterning on the first metal layer so that the first metal layer forms a scanning line and a gate, and the scanning line and the gate are conductively connected;

[0018] forming a first insulating layer covering the scan line and the gate on the substrate;

[0019] forming a first transparent conductive layer and a second metal layer on the first insulating layer, and patterning the first transparent conductive layer and the second metal layer so that the first transparent conductive layer forms a drain electrode and a pixel electrode, and the second metal layer forms a source electrode and a data line, wherein the pixel electrode is conductively connected to the drain electrode, the data line is conductively connected to the source electrode, and the source electrode and the drain electrode are spaced apart to form a channel region;

[0020] A metal oxide semiconductor film and an insulating light-shielding film covering the drain, pixel electrode, channel region, source and data line are sequentially formed on the first insulating layer. The insulating light-shielding film and the metal oxide semiconductor film are patterned to form an insulating light-shielding layer from the insulating light-shielding film and a metal oxide semiconductor layer from the metal oxide semiconductor film. The insulating light-shielding layer and the metal oxide semiconductor layer are overlapped with each other up and down. The metal oxide semiconductor layer fills the channel region and is conductively connected to the drain and source.

[0021] In an embodiment of the present invention, forming the first transparent conductive layer and the second metal layer on the first insulating layer, and patterning the first transparent conductive layer and the second metal layer so that the first transparent conductive layer forms the drain electrode and the pixel electrode, and the second metal layer forms the source electrode and the data line, includes:

[0022] forming the first transparent conductive layer and the second metal layer in sequence on the first insulating layer;

[0023] forming a first photoresist layer on the second metal layer, and exposing the first photoresist layer using a half-tone mask, wherein the half-tone mask includes a fully transparent area, a semi-transparent area, and an opaque area, wherein the semi-transparent area corresponds to the drain electrode and the pixel electrode, the opaque area corresponds to the source electrode and the data line, and the fully transparent area corresponds to the channel area and other areas;

[0024] developing the first photoresist layer to form a first photoresist portion at a position corresponding to the drain electrode and the pixel electrode, forming a second photoresist portion at a position corresponding to the source electrode and the data line, and completely removing the first photoresist layer at positions corresponding to the channel region and other regions, wherein the thickness of the first photoresist portion is less than that of the second photoresist portion;

[0025] Sequentially etching the second metal layer and the first transparent conductive layer that are exposed but not covered by the first light-blocking portion or the second light-blocking portion to remove the second metal layer and the first transparent conductive layer at the locations;

[0026] performing ashing thinning on the first photoresist portion and the second photoresist portion to completely remove the first photoresist portion, but still retain the second photoresist portion after thinning;

[0027] Etching the exposed portion of the second metal layer not covered by the first photoresist portion to remove the second metal layer at that portion and expose the first transparent conductive layer thereunder, wherein the exposed first transparent conductive layer forms the drain electrode and the pixel electrode;

[0028] The second photoresist portion is removed to expose the second metal layer, and the exposed second metal layer forms the source electrode and the data line, and the first transparent conductive layer is overlapped and disposed below the source electrode and the data line.

[0029] In an embodiment of the present invention, forming the first transparent conductive layer and the second metal layer on the first insulating layer, and patterning the first transparent conductive layer and the second metal layer so that the first transparent conductive layer forms the drain electrode and the pixel electrode, and the second metal layer forms the source electrode and the data line, includes:

[0030] First, forming the first transparent conductive layer on the first insulating layer, and performing patterning on the first transparent conductive layer so that the first transparent conductive layer forms the drain electrode and the pixel electrode;

[0031] Then forming the second metal layer on the first insulating layer, and performing patterning on the second metal layer so that the second metal layer forms the source electrode and the data line;

[0032] or:

[0033] First, forming the second metal layer on the first insulating layer, and performing patterning on the second metal layer so that the second metal layer forms the source electrode and the data line;

[0034] Then, the first transparent conductive layer is formed on the first insulating layer, and the first transparent conductive layer is patterned so that the first transparent conductive layer forms the drain electrode and the pixel electrode.

[0035] In an embodiment of the present invention, patterning the insulating light-shielding film and the metal oxide semiconductor film so that the insulating light-shielding film forms the insulating light-shielding layer and the metal oxide semiconductor film forms the metal oxide semiconductor layer comprises:

[0036] forming a second photoresist layer on the insulating light-shielding film;

[0037] exposing and developing the second photoresist layer to retain the second photoresist layer at least at positions corresponding to the drain electrode, the channel region, and the source electrode;

[0038] The insulating light-shielding film and the metal oxide semiconductor film that are exposed but not covered by the second photoresist layer are etched in sequence to remove the insulating light-shielding film and the metal oxide semiconductor film at that position, and the remaining insulating light-shielding film forms the insulating light-shielding layer, and the remaining metal oxide semiconductor film forms the metal oxide semiconductor layer.

[0039] In an embodiment of the present invention, the above-mentioned manufacturing method further includes:

[0040] forming a second insulating layer on the first insulating layer, covering the pixel electrode and the insulating light-shielding layer;

[0041] A second transparent conductive layer is formed on the second insulating layer, and the second transparent conductive layer is patterned to form a common electrode.

[0042] The array substrate of the present invention utilizes a halftone mask to form pixel electrodes, source electrodes, drain electrodes, and data lines, eliminating the need for a mask for forming data lines and thus reducing costs. Furthermore, because the pixel electrodes and drain electrodes are made of the same conductive material, the pixel electrodes can be considered to be in direct contact with the metal oxide semiconductor layer, reducing the impedance of the ohmic contact and enhancing the conductive properties. Finally, the metal oxide semiconductor layer of the array substrate is covered with an insulating light-shielding layer. Therefore, during the film formation, exposure, development, and etching stages, the metal oxide semiconductor layer is protected by the insulating light-shielding layer. This effectively isolates the metal oxide semiconductor layer from moisture and oxygen generated during these processes, preventing them from corroding the metal oxide semiconductor layer. This effectively protects the electrical properties of the metal oxide semiconductor layer, preventing rapid oxidation and aging, and improving the stability and lifespan of the metal oxide TFT. Furthermore, because the insulating light-shielding layer above the metal oxide semiconductor layer provides light-shielding properties, it effectively blocks ambient light from irradiating the channel region of the metal oxide TFT component, reducing the photoinduced leakage current effect of the metal oxide TFT and further improving the stability and lifespan of the metal oxide TFT. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figures 1a to 11 Schematic diagram of a cross-sectional manufacturing process of a method for manufacturing an array substrate of the present invention;

[0044] Figure 2a yes Figure 1b The cross-sectional structural diagram of the array substrate along the AA direction is shown;

[0045] Figure 2b yes Figure 1i The cross-sectional structural diagram of the array substrate along the BB direction is shown;

[0046] Figure 2c yes Figure 1k The cross-sectional structure diagram of the array substrate along the CC direction is shown;

[0047] Figure 2d yes Figure 11 The cross-sectional structure diagram of the array substrate along the DD direction is shown;

[0048] Figures 3a to 3c Schematic diagram of a cross-sectional manufacturing process of another preferred embodiment of step S2 of the method for manufacturing an array substrate of the present invention;

[0049] Figure 4a yes Figure 3a The cross-sectional structural diagram of the array substrate along the EE direction is shown;

[0050] Figure 4b yes Figure 3b The cross-sectional structure diagram of the array substrate along the FF direction is shown. DETAILED DESCRIPTION

[0051] To facilitate understanding by those skilled in the art, the present application describes the specific implementation process of the technical solution provided by the present application through the following embodiments.

[0052] As shown in Figure 1 to Figure 11 、 Figures 2a to 2d 、 Figures 3a to 3c as well as Figure 4a and 4b As shown, the present invention provides a method for manufacturing an array substrate, the manufacturing method comprising:

[0053] S1: Provide a substrate 11, which can be made of materials such as glass, quartz, acrylic or polycarbonate. Form a first metal layer 12 on the entire surface of the substrate 11, and perform a patterning process on the first metal layer 12 so that the first metal layer 12 forms a scan line 121 and a gate 122, and the scan line 121 and the gate 122 are conductively connected; wherein the first metal layer 12 can be made of copper and molybdenum niobium (Cu / MoNb), or copper and molybdenum (Cu / Mo); the second insulating layer 23 can be made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two. Form a first insulating layer 13 covering the scan line 121 and the gate 122 on the substrate 11; the first insulating layer 13 can be made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0054] S2: forming a first transparent conductive layer 14 and a second metal layer 15 on the first insulating layer 13, and patterning the first transparent conductive layer 14 and the second metal layer 15 so that the first transparent conductive layer 14 forms a drain electrode 141 and a pixel electrode 142, and the second metal layer 15 forms a source electrode 151 and a data line 152, the pixel electrode 142 is conductively connected to the drain electrode 141, the data line 152 is conductively connected to the source electrode 151, and the source electrode 151 and the drain electrode 141 are spaced apart to form a channel region 101;

[0055] In this embodiment, if Figure 1d to Figure 1i as well as Figure 2a and Figure 2b As shown, a first transparent conductive layer 14 and a second metal layer 15 are formed on the first insulating layer 13, and the first transparent conductive layer 14 and the second metal layer 15 are patterned so that the first transparent conductive layer 14 forms a drain electrode 141 and a pixel electrode 142, and the second metal layer 15 forms a source electrode 151 and a data line 152, including:

[0056] A first transparent conductive layer 14 and a second metal layer 15 are sequentially formed on the first insulating layer 13;

[0057] A first photoresist layer 16 is formed on the second metal layer 15 and exposed using a half-tone mask 17. The half-tone mask 17 includes a fully transparent area 171, a semi-transparent area 172, and an opaque area 173. The semi-transparent area 172 corresponds to the drain 141 and the pixel electrode 142, the opaque area 173 corresponds to the source 151 and the data line 152, and the fully transparent area 171 corresponds to the channel area 101 and other areas.

[0058] The first photoresist layer 16 is developed to form a first photoresist portion 161 at a position corresponding to the drain electrode 141 and the pixel electrode 142, and a second photoresist portion 162 at a position corresponding to the source electrode 151 and the data line 152. The first photoresist layer 16 is completely removed at positions corresponding to the channel region 101 and other regions. The thickness of the first photoresist portion 161 is less than that of the second photoresist portion 162.

[0059] The second metal layer 15 and the first transparent conductive layer 14 that are exposed but not covered by the first photoresist portion 161 or the second photoresist portion 162 are sequentially etched to remove the second metal layer 15 and the first transparent conductive layer 14 at the locations;

[0060] The first photoresist portion 161 and the second photoresist portion 162 are ashed and thinned to completely remove the first photoresist portion 161 , but the second photoresist portion 162 is still retained after thinning;

[0061] The exposed portion of the second metal layer 15 not covered by the first photoresist portion 161 is etched to remove the second metal layer 15 at that portion and expose the first transparent conductive layer 14 thereunder. The exposed first transparent conductive layer 14 forms the drain electrode 141 and the pixel electrode 142.

[0062] The second photoresist portion 162 is removed to expose the second metal layer 15 , and the exposed second metal layer 15 forms the source electrode 151 and the data line 152 . The first transparent conductive layer 14 is overlapped and disposed below the source electrode 151 and the data line 152 .

[0063] In another preferred embodiment, Figures 3a to 3c as well as Figure 4a and 4b As shown, the first transparent conductive layer 14 and the second metal layer 15 are formed on the first insulating layer 13, and the first transparent conductive layer 14 and the second metal layer 15 are patterned so that the first transparent conductive layer 14 forms a drain electrode 141 and a pixel electrode 142, and the second metal layer 15 forms a source electrode 151 and a data line 152, including:

[0064] First, a first transparent conductive layer 14 is formed on the first insulating layer 13, and the first transparent conductive layer 14 is patterned to form a drain electrode 141 and a pixel electrode 142 on the first transparent conductive layer 14; then, a second metal layer 15 is formed on the first insulating layer 13, and the second metal layer 15 is patterned to form a source electrode 151 and a data line 152 on the second metal layer 15; or: first, a second metal layer 15 is formed on the first insulating layer 13, and the second metal layer 15 is patterned to form a source electrode 151 and a data line 152 on the second metal layer 15; then, a first transparent conductive layer 14 is formed on the first insulating layer 13, and the first transparent conductive layer 14 is patterned to form a drain electrode 141 and a pixel electrode 142 on the first transparent conductive layer 14.

[0065] S3: A metal oxide semiconductor film 18 and an insulating light-shielding film 19 covering the drain 141, the pixel electrode 142, the channel region 101, the source 151 and the data line 152 are formed in sequence on the first insulating layer 13, and the insulating light-shielding film 19 and the metal oxide semiconductor film 18 are patterned to form an insulating light-shielding layer 191 and the metal oxide semiconductor film 18 into a metal oxide semiconductor layer 181. The insulating light-shielding layer 191 and the metal oxide semiconductor layer 181 are overlapped with each other up and down, and the metal oxide semiconductor layer 181 fills the channel region 101 and is conductively connected to the drain 141 and the source 151.

[0066] The insulating light-shielding film 19 and the metal oxide semiconductor film 18 are patterned to form an insulating light-shielding layer 191 and a metal oxide semiconductor layer 181, including: forming a second photoresist layer 21 on the insulating light-shielding film 19; exposing and developing the second photoresist layer 21 to retain the second photoresist layer 21 at least at positions corresponding to the drain 141, the channel region 101 and the source 151; and sequentially etching the exposed insulating light-shielding film 19 and the metal oxide semiconductor film 18 that are not covered by the second photoresist layer 21 to remove the insulating light-shielding film 19 and the metal oxide semiconductor film 18 at that position, so that the remaining insulating light-shielding film 19 forms the insulating light-shielding layer 191, and the remaining metal oxide semiconductor film 18 forms the metal oxide semiconductor layer 181.

[0067] S4: forming a second insulating layer 23 covering the insulating light shielding layer 191 on the first insulating layer 13; the second insulating layer 23 is made of, for example, silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0068] S5: A second transparent conductive layer is formed entirely on the second insulating layer 23, and the second transparent conductive layer is patterned to form a common electrode 24 on the second transparent conductive layer. The common electrode 24 is disposed corresponding to the pixel electrode 142. In this embodiment, the second transparent conductive layer is made of a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0069] The present invention also provides an array substrate formed by the above-mentioned manufacturing method.

[0070] In this embodiment, the array substrate includes: a substrate 11; a scan line 121 and a gate 122 formed on the substrate 11, the gate 122 being conductively connected to the scan line 121; a first insulating layer 13 covering the scan line 121 and the gate 122; a drain electrode 141, a pixel electrode 142, a source electrode 151, and a data line 152 formed on the first insulating layer 13. The pixel electrode 142 and the drain electrode 141 are formed by patterning the first transparent conductive layer 14 and are conductively connected to each other. The data line 152 and the source electrode 151 are formed by patterning the second metal layer 15 and are conductively connected to each other. The source electrode 151 and the drain electrode 141 are spaced apart to form a channel region 101.

[0071] In this embodiment, the array substrate further includes: a metal oxide semiconductor layer 181 covering at least the drain 141 , the channel region 101 and the source 151 . The metal oxide semiconductor layer 181 fills the channel region 101 and is conductively connected to the drain 141 and the source 151 .

[0072] In this embodiment, the first transparent conductive layer 14 is made of a transparent metal oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO). Therefore, when the metal oxide semiconductor layer 181 is conductively connected to the drain electrode 141, and the drain electrode 141 is conductively connected to the rear pixel electrode 142, it is effectively equivalent to a direct conductive connection between the metal oxide semiconductor layer 181 and the pixel electrode 142. This can reduce the ohmic contact resistance between the metal oxide semiconductor layer 181 and the pixel electrode 142, thereby enhancing the conductive properties.

[0073] In this embodiment, the array substrate further includes an insulating light-shielding layer 191 overlying the metal oxide semiconductor layer 181. The insulating light-shielding layer 191 overlaps the metal oxide semiconductor layer 181. The insulating light-shielding layer 191 is made, for example, of an insulating blackened metal oxide such as copper nitride or molybdenum oxide. Therefore, the metal oxide semiconductor layer 181 is protected by the insulating light-shielding layer 191 during each of the film formation, exposure, development, and etching stages. This effectively isolates the metal oxide semiconductor layer 181 from moisture and oxygen generated during these processes, preventing them from corroding the metal oxide semiconductor layer 181. This effectively protects the electrical properties of the metal oxide semiconductor layer 181, preventing rapid oxidation and aging, and improving the stability and lifespan of the metal oxide TFT. Furthermore, because the insulating light-shielding layer 191 overlying the metal oxide semiconductor layer 181 provides light-shielding properties, it effectively blocks ambient light from reaching the channel region 101 of the metal oxide TFT component, reducing the photoinduced leakage current effect of the metal oxide TFT and further improving the stability and lifespan of the metal oxide TFT.

[0074] In this embodiment, a first transparent conductive layer 14 is further overlapped and disposed below the source electrode 151 and the data line 152. Optionally, the source electrode 151 and the data line 152 are conductively connected to the first transparent conductive layer 14. If a portion of the data line 152 is damaged, the first transparent conductive layer 14 can continue to conductively connect the entire data line 152 to the source electrode 151, thereby automatically repairing the data line 152.

[0075] In this embodiment, the metal oxide semiconductor layer 181 covers the drain 141 , the channel region 101 and the source 151 ; alternatively, the metal oxide semiconductor layer 181 covers the drain 141 , the channel region 101 , the source 151 and the data line 152 .

[0076] In this embodiment, the orthographic projection of the metal oxide semiconductor layer 181 on the substrate 11 overlaps with the orthographic projection of the insulating light-shielding layer 191 on the substrate 11. Therefore, the entire metal oxide semiconductor layer 181 is completely covered by the insulating light-shielding layer 191, ensuring that no part of the metal oxide semiconductor layer 181 is affected during the film formation, exposure, development, and etching stages, thereby effectively achieving the light-shielding effect of the insulating light-shielding layer. Of course, the insulating light-shielding layer 191 only covers the channel region 101, effectively shielding the channel region 101 of the metal oxide TFT device from ambient light.

[0077] The array substrate of the present invention utilizes a halftone mask 17 to form the pixel electrodes 142, source electrodes 151, drain electrodes 141, and data lines 152, eliminating the need for a mask for forming the data lines 152 and thus reducing costs. Furthermore, because the pixel electrodes 142 and drain electrodes 141 are made of the same conductive material, the pixel electrodes 142 can be considered to be in direct contact with the metal oxide semiconductor layer 181, reducing the resistance of the ohmic contact and enhancing the conductive properties. Finally, the metal oxide semiconductor layer 181 of the array substrate is covered with an insulating light-shielding layer 191. Therefore, during the film formation, exposure, development, and etching stages, the metal oxide semiconductor layer 181 is protected by the insulating light-shielding layer 191. This effectively isolates the metal oxide semiconductor layer 181 from moisture and oxygen generated during these processes, preventing them from corroding the metal oxide semiconductor layer 181. This effectively protects the electrical properties of the metal oxide semiconductor layer 181, preventing rapid oxidation and aging, and improving the stability and lifespan of the metal oxide TFT. On the other hand, since the insulating light-shielding layer 191 above the metal oxide semiconductor layer 181 has a light-shielding effect, it can effectively block the ambient light from irradiating the channel region 101 of the metal oxide TFT component, thereby reducing the photogenerated leakage current effect of the metal oxide TFT and further improving the stability and life of the metal oxide TFT.

[0078] In this document, directional terms such as "up," "down," "left," "right," "front," and "back" are defined based on the positions of structures in the accompanying drawings and their relative positions to each other, for the sake of clarity and convenience in presenting the technical solution. It should be understood that the use of directional terms does not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein, are used solely for distinctions and are not intended to limit quantity or order.

[0079] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with this profession can make some changes or modifications to the technical contents disclosed above without departing from the scope of the technical solution of the present invention, which are equivalent embodiments of equivalent changes. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate includes: base (11); A scanning line (121) and a gate (122) are formed on the substrate (11), wherein the gate (122) is conductively connected to the scanning line (121); a first insulating layer (13) covering the scanning line (121) and the gate (122); A drain electrode (141), a pixel electrode (142), a source electrode (151) and a data line (152) are formed on the first insulating layer (13), wherein the pixel electrode (142) and the drain electrode (141) are formed by patterning the first transparent conductive layer (14) and are conductively connected to each other, the data line (152) and the source electrode (151) are formed by patterning the second metal layer (15) and are conductively connected to each other, and the source electrode (151) and the drain electrode (141) are spaced apart to form a channel region (101); a metal oxide semiconductor layer (181) covering at least the drain electrode (141), the channel region (101) and the source electrode (151), wherein the metal oxide semiconductor layer (181) fills the channel region (101) and is conductively connected to the drain electrode (141) and the source electrode (151); An insulating light-shielding layer (191) covers the metal oxide semiconductor layer (181), and the insulating light-shielding layer (191) and the metal oxide semiconductor layer (181) are arranged to overlap each other.

2. The array substrate according to claim 1, wherein: The first transparent conductive layer (14) is also overlapped and arranged below the source electrode (151) and the data line (152).

3. The array substrate according to claim 1, wherein: The metal oxide semiconductor layer (181) covers the drain electrode (141), the channel region (101) and the source electrode (151); or, the metal oxide semiconductor layer (181) covers the drain electrode (141), the channel region (101), the source electrode (151) and the data line (152).

4. The array substrate according to any one of claims 1 to 3, wherein: The orthographic projection of the metal oxide semiconductor layer (181) on the substrate (11) coincides with the orthographic projection of the insulating light-shielding layer (191) on the substrate (11).

5. The array substrate according to any one of claims 1 to 3, characterized in that: The insulating light-shielding layer (191) is made of molybdenum oxide or copper nitride.

6. A method for manufacturing an array substrate, characterized in that: The production method comprises: providing a substrate (11); forming a first metal layer (12) on the substrate (11), and performing a patterning process on the first metal layer (12) so that the first metal layer (12) forms a scanning line (121) and a gate (122), wherein the scanning line (121) and the gate (122) are conductively connected; forming a first insulating layer (13) covering the scanning line (121) and the gate (122) on the substrate (11); A first transparent conductive layer (14) and a second metal layer (15) are formed on the first insulating layer (13); the first transparent conductive layer (14) and the second metal layer (15) are patterned so that the first transparent conductive layer (14) forms a drain electrode (141) and a pixel electrode (142); and the second metal layer (15) forms a source electrode (151) and a data line (152); the pixel electrode (142) is conductively connected to the drain electrode (141); the data line (152) is conductively connected to the source electrode (151); and the source electrode (151) and the drain electrode (141) are spaced apart to form a channel region (101); A metal oxide semiconductor film (18) and an insulating light-shielding film (19) are sequentially formed on the first insulating layer (13) to cover the drain electrode (141), the pixel electrode (142), the channel region (101), the source electrode (151) and the data line (152). The insulating light-shielding film (19) and the metal oxide semiconductor film (18) are patterned so that the insulating light-shielding film (19) forms an insulating light-shielding layer (191) and the metal oxide semiconductor film (18) forms a metal oxide semiconductor layer (181). The insulating light-shielding layer (191) and the metal oxide semiconductor layer (181) are arranged to overlap each other. The metal oxide semiconductor layer (181) fills the channel region (101) and is conductively connected to the drain electrode (141) and the source electrode (151).

7. The method for manufacturing an array substrate according to claim 6, wherein: The method comprises forming a first transparent conductive layer (14) and a second metal layer (15) on the first insulating layer (13), patterning the first transparent conductive layer (14) and the second metal layer (15), so that the first transparent conductive layer (14) forms a drain electrode (141) and a pixel electrode (142), and the second metal layer (15) forms a source electrode (151) and a data line (152), comprising: forming a first transparent conductive layer (14) and a second metal layer (15) in sequence on the first insulating layer (13); forming a first photoresist layer (16) on the second metal layer (15), and exposing the first photoresist layer (16) using a half-tone mask (17), wherein the half-tone mask (17) comprises a fully transparent area (171), a semi-transparent area (172), and an opaque area (173), wherein the semi-transparent area (172) corresponds to the drain electrode (141) and the pixel electrode (142), the opaque area (173) corresponds to the source electrode (151) and the data line (152), and the fully transparent area (171) corresponds to the channel area (101) and other areas; Developing the first photoresist layer (16) to form a first photoresist portion (161) at a position corresponding to the drain electrode (141) and the pixel electrode (142), forming a second photoresist portion (162) at a position corresponding to the source electrode (151) and the data line (152), and completely removing the first photoresist layer (16) at positions corresponding to the channel region (101) and other regions, wherein the thickness of the first photoresist portion (161) is less than the thickness of the second photoresist portion (162); Sequentially etching the exposed second metal layer (15) and the first transparent conductive layer (14) that are not covered by the first light-resisting portion (161) or the second light-resisting portion (162) to remove the second metal layer (15) and the first transparent conductive layer (14) at the location; Performing ashing and thinning on the first light-resistance portion (161) and the second light-resistance portion (162), so as to completely remove the first light-resistance portion (161), but still retain the second light-resistance portion (162) after thinning; Etching the exposed portion of the second metal layer (15) not covered by the first photoresist portion (161) to remove the second metal layer (15) at that position and expose the first transparent conductive layer (14) underneath, wherein the exposed first transparent conductive layer (14) forms the drain electrode (141) and the pixel electrode (142); The second photoresist portion (162) is removed to expose the second metal layer (15), and the exposed second metal layer (15) forms the source electrode (151) and the data line (152), and the first transparent conductive layer (14) is also overlapped and arranged below the source electrode (151) and the data line (152).

8. The method for manufacturing an array substrate according to claim 6, wherein: The method comprises forming a first transparent conductive layer (14) and a second metal layer (15) on the first insulating layer (13), patterning the first transparent conductive layer (14) and the second metal layer (15), so that the first transparent conductive layer (14) forms a drain electrode (141) and a pixel electrode (142), and the second metal layer (15) forms a source electrode (151) and a data line (152), comprising: Firstly, a first transparent conductive layer (14) is formed on the first insulating layer (13), and the first transparent conductive layer (14) is patterned so that the first transparent conductive layer (14) forms the drain electrode (141) and the pixel electrode (142); Then, a second metal layer (15) is formed on the first insulating layer (13), and the second metal layer (15) is patterned so that the second metal layer (15) forms the source electrode (151) and the data line (152); or: First, a second metal layer (15) is formed on the first insulating layer (13), and the second metal layer (15) is patterned so that the second metal layer (15) forms the source electrode (151) and the data line (152); Then, a first transparent conductive layer (14) is formed on the first insulating layer (13), and the first transparent conductive layer (14) is patterned so that the first transparent conductive layer (14) forms the drain electrode (141) and the pixel electrode (142).

9. The method for manufacturing an array substrate according to claim 6, wherein: The above-mentioned patterning process of the insulating light-shielding film (19) and the metal oxide semiconductor film (18) so that the insulating light-shielding film (19) forms an insulating light-shielding layer (191) and the metal oxide semiconductor film (18) forms a metal oxide semiconductor layer (181) comprises: forming a second photoresist layer (21) on the insulating light-shielding film (19); exposing and developing the second photoresist layer (21) to retain the second photoresist layer (21) at least at positions corresponding to the drain electrode (141), the channel region (101), and the source electrode (151); The insulating light-shielding film (19) and the metal oxide semiconductor film (18) that are not covered by the second photoresist layer (21) and are exposed are sequentially etched to remove the insulating light-shielding film (19) and the metal oxide semiconductor film (18) at that position, and the remaining insulating light-shielding film (19) forms an insulating light-shielding layer (191), and the remaining metal oxide semiconductor film (18) forms a metal oxide semiconductor layer (181).

10. The method for manufacturing an array substrate according to claim 6, wherein: The production method further comprises: forming a second insulating layer (23) on the first insulating layer (13) to cover the pixel electrode (142) and the insulating light-shielding layer (191); A second transparent conductive layer is formed on the second insulating layer (23), and the second transparent conductive layer is patterned so that the second transparent conductive layer forms a common electrode (24).

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