A method for forming a three-dimensional phase change memory and a three-dimensional phase change memory

Abstract

The embodiment of the present application provides a forming method of a three-dimensional phase change memory and the three-dimensional phase change memory, wherein the method comprises the following steps: adopting a plurality of initial etching patterns extending along a first direction, etching a first mask layer to form a first etching mask layer; forming a second mask layer on the surface of the first etching mask layer; adopting a plurality of secondary etching patterns extending along a second direction, etching the second mask layer and the first etching mask layer in sequence to form a secondary etching mask layer, wherein the secondary etching mask layer has a grid-shaped pattern; and etching a phase change memory cell layer to form a columnar phase change memory cell by taking the secondary etching mask layer as a mask.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor, and relate to, but are not limited to, a forming method of a three-dimensional phase change memory and the three-dimensional phase change memory. BACKGROUND

[0002] Phase change memory (PCM) is a non-volatile solid-state storage technology that utilizes a reversible, thermally assisted switching of a phase change material between states having different resistances. The phase change material in a PCM cell can be located between two electrodes, and a current can be applied to repeatedly switch the phase change material (or portions thereof that block current paths) between two phases to store data.

[0003] In a three-dimensional phase change memory (3D PCM), a memory chip is composed of many memory arrays, which have individual word lines (WL) and bit lines (BL). In each array, self-aligned PCM cells are formed at the intersection points of the mutually perpendicular WL and BL, the PCM cells are vertical square pillars, in contact with top and bottom BL contacts, and the WL is in the middle of the PCM cell.

[0004] In related technologies, when manufacturing a PCM cell, a double patterning technology is respectively used to form structures in the WL and BL directions, and in the formation of the structures in the WL or BL direction, multiple deposition layers are deposited and two times of partial etching are respectively performed, so that four times of partial etching and eight deposition layers are needed to form one PCM cell, and after the etching is completed, the excess deposition layer material needs to be removed, so that the etching process is very complex. In addition, in the process of forming a 2-stack or 4-stack 3D PCM, the number of times of partial etching increases to 4 or 8, and the number of deposition layers formed also increases by one or four times. That is, as the number of stacks of 3D PCM increases, the number of times of etching process increases by several times, which greatly increases the manufacturing cost. SUMMARY

[0005] Therefore, embodiments of the present application provide a forming method of a three-dimensional phase change memory and the three-dimensional phase change memory.

[0006] The technical scheme of the embodiments of the present application is as follows:

[0007] The forming method of a three-dimensional phase change memory provided by the embodiments of the present application comprises the following steps.

[0008] The first mask stack is etched by using a plurality of initial etching patterns extending in the first direction to form a first etching mask stack.

[0009] forming a second mask layer on the surface of the first etching mask layer;

[0010] forming a second mask layer on the surface of the first etching mask layer;

[0011] forming a second mask layer on the surface of the first etching mask layer;

[0012] In some embodiments, the stack structure further comprises: a plurality of bit lines extending along the first direction and arranged along the second direction, and at least one bit line contact on each of the bit lines, the bit line contact being used to connect the bit line and the phase change memory cell stack.

[0013] In some embodiments, the first mask layer comprises, from bottom to top, a first mask layer, a second mask layer and a third mask layer;

[0014] forming the first etching mask layer by the following steps:

[0015] etching the third mask layer based on a plurality of initial etching patterns extending along the first direction to form a third etching mask layer having the initial etching patterns;

[0016] etching the second mask layer using the third etching mask layer as a mask and removing the remaining third etching mask layer to form a second etching mask layer having the initial etching patterns; wherein the first mask layer and the second etching mask layer constitute the first etching mask layer.

[0017] In some embodiments, the first mask layer further comprises, from top to bottom, a first mandrel layer, a first dielectric layer and a first barrier layer;

[0018] correspondingly, before etching the third mask layer based on a plurality of initial etching patterns extending along the first direction, the method further comprises:

[0019] performing a patterning process on the first barrier layer to form a first etching barrier layer;

[0020] etching the first dielectric layer and the first mandrel layer using the first etching barrier layer as a mask and removing the remaining first etching barrier layer to form a first etching mandrel layer;

[0021] depositing a first spacer on both sides of each first mandrel body in the first etching mandrel layer based on the mandrel pattern of the first etching mandrel layer, wherein the first spacer has the initial etching pattern;

[0022] removing the first etching mandrel layer to form a plurality of initial etching patterns extending along the first direction.

[0023] In some embodiments, the third mask layer is etched by the following steps:

[0024] etching the third mask layer to form the third etching mask layer with the first spacer as a mask.

[0025] In some embodiments, the second mask stack is formed by the following steps:

[0026] depositing a second mandrel layer, a second dielectric layer and a second barrier layer on the surface of the second etching mask layer in sequence;

[0027] wherein the second mandrel layer, the second dielectric layer and the second barrier layer constitute the second mask stack.

[0028] In some embodiments, the second etching mask stack is formed by the following steps:

[0029] etching the second barrier layer to form a second etching barrier layer using a plurality of second etching patterns extending along the second direction;

[0030] etching the second dielectric layer and the second mandrel layer in sequence with the second etching barrier layer as a mask, and removing the remaining second etching barrier layer to form a second etching mandrel layer;

[0031] depositing a second spacer on both sides of each second mandrel body in the second etching mandrel layer based on the mandrel pattern of the second etching mandrel layer;

[0032] removing the second etching mandrel layer;

[0033] etching the first etching mask stack with the second spacer as a mask to form the second etching mask stack.

[0034] In some embodiments, the second etching mask stack is formed by the following steps:

[0035] etching the second etching mask layer with the second spacer as a mask to form a second second etching mask layer;

[0036] removing the second spacer; wherein the first mask layer and the second second etching mask layer constitute the second etching mask stack.

[0037] In some embodiments, the secondary etching mask stack is formed by the following steps:

[0038] Using the second spacer as a mask, the second etching mask layer and the first etching mask layer are etched sequentially to form a second etching mask layer and a first etching mask layer.

[0039] Remove the second spacer; wherein the secondary second etching mask layer and the first etching mask layer constitute the secondary etching mask stack.

[0040] In some embodiments, the phase change memory cell stack includes a bottom stack and a top stack stacked sequentially from bottom to top;

[0041] Correspondingly, the phase-change memory is obtained through the following steps:

[0042] Using the secondary etching mask stack as a mask, the top stack is etched in the first step to form a top stack unit;

[0043] A first encapsulation layer is deposited on the surface of the top stacked unit;

[0044] Using the top stacked unit with the first encapsulation layer as a mask, the bottom stacked unit is etched a second time to form a phase change memory unit;

[0045] A second encapsulation layer is deposited on the surface of the phase change memory cell to obtain the columnar phase change memory cell.

[0046] In some embodiments, the top stack comprises, from bottom to top, the following layers: a PCM element layer, a first electrode layer, and a hard mask layer;

[0047] The top layer is first etched using the following steps:

[0048] Using the secondary etching mask stack as a mask, the hard mask layer, the first electrode layer and the PCM element layer are sequentially etched to form a hard etching mask layer, a first etching electrode layer and a PCM etching element layer. A first via is formed that penetrates the hard etching mask layer, the first etching electrode layer and the PCM etching element layer, and a top stack unit is formed around the first via.

[0049] The deposition of a first encapsulation layer on the surface of the top stacked unit includes:

[0050] A first encapsulation material is deposited on the sidewall of the first via and on the surface of the hard etched mask layer to form the first encapsulation layer.

[0051] In some embodiments, the bottom stack includes, sequentially from bottom to top: a third electrode layer, a selector layer, and a second electrode layer;

[0052] The bottom stack is subjected to a second etching by the following steps:

[0053] The second electrode layer, the selector layer, and the third electrode layer are sequentially subjected to a second etching with the top stack unit with the first encapsulation layer as a mask. After the etching, a second etching electrode layer, an etching selector layer, and a third etching electrode layer are formed, and a second via hole penetrating through the second etching electrode layer, the etching selector layer, and the third etching electrode layer, and the phase change memory cell located around the second via hole are formed.

[0054] The second encapsulation layer is formed by depositing on the surface of the phase change memory cell, including:

[0055] The second encapsulation layer is formed by depositing a second encapsulation material on the sidewall of the second via hole and the surface of the phase change memory cell.

[0056] In some embodiments, the method further includes:

[0057] The gap material layer is formed by filling the gap material on the surface of the second encapsulation layer.

[0058] The remaining hard etching mask layer in the top stack is removed to expose the first etching electrode layer in the top stack unit.

[0059] In some embodiments, the method further includes:

[0060] A word line contact is formed on the first etching electrode layer in each exposed top stack unit.

[0061] The word lines extending along the second direction and arranged along the first direction are formed on the word line contact, thereby forming the phase change memory. The word line contact is used to connect the first etching electrode layer and the word line, and the material of the word line includes copper.

[0062] Alternatively,

[0063] The word lines are formed on the first etching electrode layer in each exposed top stack unit, and the material of the word lines includes tungsten.

[0064] The embodiments of the present application provide a three-dimensional phase change memory formed by the above method, and the three-dimensional phase change memory includes at least: a columnar phase change memory cell.

[0065] In the embodiment of the present application, the first mask stack is etched by a plurality of initial etching patterns extending along a first direction, and the second mask stack and the first etching mask stack are etched based on a plurality of secondary etching patterns extending along a second direction, to form a secondary etching mask stack with a grid pattern, so that the phase change memory cell stack is etched based on the secondary etching mask stack, to obtain the phase change memory cell. In this way, the number of etching times and the number of deposited layers can be reduced by at least half, to form the PCM cell of the three-dimensional phase change memory, thereby reducing the process steps and manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS

[0066] Figures 1-1 to 1-2 Structure schematic diagram of a structure formed after double patterning in the direction of bit line and word line in the related art;

[0067] Figure 2 Flowchart of a forming method of a three-dimensional phase change memory provided in the embodiment of the present application;

[0068] Figure 3 Schematic diagram of a stack structure provided in the embodiment of the present application;

[0069] Figures 4-1 to 4-32 Schematic diagram of a forming process of a three-dimensional phase change memory provided in the embodiment of the present application. DETAILED DESCRIPTION

[0070] The exemplary embodiments of the present application will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals can be used to refer to like elements throughout. The purpose of the exemplary embodiments is to enable those skilled in the art to practice the present application without unduly compromising its desired advantages and features. Accordingly, the exemplary embodiments can not include all of the features that can be necessary to practice the present application.

[0071] In the following description, numerous specific details are given to provide a thorough understanding of the present application. However, it will be apparent that the present application can be practiced without these specific details. In other instances, well-known methods have not been described in detail in order not to unnecessarily obscure the present application.

[0072] In the drawings, the size of layers, regions, elements and / or the relative sizes of the same can be exaggerated for clarity. Like reference numbers and symbols can be used to denote like elements throughout.

[0073] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0074] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0075] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a scope less than the scope of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between or between any horizontal pair of top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow, and a layer can include multiple layers.

[0076] In conjunction with Figure 1-1 and Figure 1-2 In the related art, in the process of forming a 3D PCM memory, the WL and the BL are formed by using a double patterning technology, which requires two partial etchings and multiple deposition layers to be formed to form the WL or the BL, respectively. As shown in FIG. 1, a first partial etching is performed on a substrate 100 to form a first layer 110, and a second partial etching is performed on the first layer 110 to form a second layer 120. Then, a third layer 130 is formed on the second layer 120, and a fourth layer 140 is formed on the third layer 130. Finally, a fifth layer 150 is formed on the fourth layer 140, and a sixth layer 160 is formed on the fifth layer 150. The WL and the BL are formed by using the sixth layer 160 as a mask to etch the fifth layer 150, the fourth layer 140, the third layer 130, the second layer 120, and the first layer 110. Figure 1-1As shown, the structure after double patterning in the word line WL direction in the related art, Figure 1-2 For the structure after double patterning in the bit line BL direction, more etching steps are needed, which causes the extension of process time and the increase of process cost.

[0077] Based on this, the embodiment of the present application provides a preparation method of a three-dimensional phase change memory, Figure 2 The flow chart of the manufacturing method of the three-dimensional phase change memory provided by the embodiment of the present application is shown in Figure 2 As shown, the method comprises:

[0078] Step S101: providing a stack structure; the stack structure comprises a phase change memory cell stack and a first mask stack which are stacked in sequence.

[0079] Figure 3 The stack structure provided by the embodiment of the present application is shown in Figure 3 The stack structure comprises, from bottom to top, a phase change memory cell stack 120 and a first mask stack 130.

[0080] In some embodiments, the stack structure further comprises: a substrate (not shown in the figure) at the bottom layer of the stack structure, and a plurality of bit lines 101 above the substrate and extending along the first direction. Figure 3

[0081] Here, the substrate can be a silicon substrate, or can comprise other semiconductor elements, such as germanium (Ge), or comprise semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InP) or indium antimonide (InSb), or comprise other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), gallium indium arsenide (GaInAs), indium gallium phosphide (GaInP), and / or indium gallium arsenide phosphide (GaInAsP) or a combination thereof.

[0082] ​The substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side. Ignoring the flatness of the top and bottom surfaces, a direction perpendicular to the top and bottom surfaces of the substrate is defined as a third direction. In the direction of the top and bottom surfaces (i.e., the plane in which the substrate lies), two mutually perpendicular directions, a first direction and a second direction, are defined. The first direction is defined along the extension direction of the plurality of bit line structures, and the arrangement direction of the bit line structures is defined as the second direction. The planar orientation of the substrate can be determined based on the first and second directions. Here, the first direction, the second direction, and the third direction are mutually perpendicular. In this embodiment, the first direction is defined as the X direction, the second direction as the Y direction, and the third direction as the Z direction.

[0083] Please continue reading Figure 3 In this embodiment, the plurality of bit lines 101 extending along the X direction can be metal bit lines. These mutually parallel bit lines 101 can be formed by depositing a metal layer and then patterning it using photolithography. In some embodiments, the bit lines 101 can be formed using copper (Cu), or other metals such as tungsten (W), cobalt (Co), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof.

[0084] In some embodiments, bit line contacts 102 may also be formed on the bit line 101. The bit line contacts 102 are used to connect the bit line 101 and the phase change memory cell stack 120. The material of the bit line contacts is different from that of the bit line, for example, it may be a metal such as tungsten. In some embodiments, the material of the bit line contacts may also be the same as that of the bit line, so that the bit line with contacts can be formed directly, thereby further reducing the formation steps of the phase change memory.

[0085] In some embodiments, peripheral wiring can be formed on the substrate simultaneously with the bit line 101. Figure 3 (Not shown). Peripheral wiring can be used to connect any digital, analog, and / or mixed-signal peripheral devices suitable for 3D PCM operation. For example, peripheral devices may include one or more of the following: data buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers, charge pumps, or any active or passive components of circuitry (e.g., transistors, diodes, resistors, or capacitors). The material of the peripheral wiring may be metallic copper to further reduce BL and WL resistances and the overall RC delay.

[0086] Step S102: Using multiple initial etching patterns extending along the first direction, etch the first mask stack to form a first etching mask stack.

[0087] First, a plurality of initial etching patterns extending along the X direction are used to etch the first mask layer 130 to form a first etching mask layer, where the plurality of initial etching patterns extending along the first direction can be a plurality of etching patterns parallel to the bit line, and the first etching mask layer is used to further form etching patterns of the phase change memory extending along the X direction.

[0088] Step S103: forming a second mask layer on the surface of the first etching mask layer.

[0089] The second mask layer is deposited on the surface of the first etching mask layer, and the second mask layer is used to form etching patterns of the phase change memory extending along the Y direction.

[0090] Step S104: using a plurality of secondary etching patterns extending along the second direction to sequentially etch the second mask layer and the first etching mask layer to form a secondary etching mask layer, where the secondary etching mask layer has a grid pattern.

[0091] Here, when the patterns of the first etching mask layer having the X direction etching patterns and the second etching mask layer having the Y direction etching patterns converge in the secondary etching mask layer, a grid pattern intersecting along the X direction and the Y direction is formed on the surface of the secondary etching mask layer.

[0092] Step S105: using the secondary etching mask layer as a mask to etch the phase change memory cell layer to form columnar phase change memory cells; where the first direction is perpendicular to the second direction.

[0093] Using the secondary patterned first mask layer having the grid pattern as a mask, the phase change memory cell layer 120 is etched, so that the etched phase change memory cell layer has the same grid pattern as the secondary patterned first mask layer, to form columnar phase change memory cells.

[0094] In the embodiments of the present application, the first mask layer is etched by using a plurality of initial etching patterns extending along the X direction, and the second mask layer and the first etching mask layer are secondarily etched based on a plurality of secondary etching patterns extending along the Y direction to form a secondary etching mask layer having a grid pattern, so that the phase change memory cell layer is etched based on the secondary etching mask layer to form columnar phase change memory cells. In this way, the number of etching times and the number of deposited layers can be reduced by at least half, and the PCM cells of the three-dimensional phase change memory are formed, so that the process steps are reduced and the manufacturing cost is reduced.

[0095] The embodiments of the present application further provide a method for manufacturing a three-dimensional phase change memory, and the method comprises:

[0096] Step S201: Provide a stacked structure.

[0097] The stacked structure includes a phase change memory cell stack and a first mask stack stacked sequentially along the Z direction; the first mask stack includes at least: a first mask layer, a second mask layer, a third mask layer, a first core layer, a first dielectric layer, and a first barrier layer stacked sequentially from bottom to top.

[0098] See Figure 4-1 This is a schematic diagram of the stacked structure provided in the embodiment of this application. The first mask stack 130 in the stacked structure includes: a first mask layer 1301a, a second mask layer 1301b, a third mask layer 1301c, a first core layer 1312, a first dielectric layer 1313 and a first barrier layer 1314 stacked sequentially along a third direction.

[0099] Step S202: Pattern the first barrier layer to form a first etch barrier layer.

[0100] First, see Figure 4-2 An etching pattern is used to etch the first barrier layer 1314 located at the top of the first mask stack 130 to form the first etch barrier layer 1314'. Figure 4-3 for Figure 4-2 Top view, such as Figure 4-3 As shown, the first etch barrier layer 1314' has a plurality of groove patterns that are parallel to each other along a first direction.

[0101] In this embodiment, the first barrier layer is used to form the groove pattern, and the first barrier layer may be formed by SiN material deposition.

[0102] Step S203: Using the first etch barrier layer as a mask, etch the first dielectric layer and the first mandrel layer in sequence, and remove the remaining first etch barrier layer to form the first etch mandrel layer.

[0103] See Figure 4-4 Using the first etch barrier layer 1314' as a mask, the first dielectric layer 1313 and the first mandrel layer 1312 are sequentially etched along the Z direction, and the remaining first etch barrier layer 1314' is removed to form the first etch dielectric layer 1313' and the first etch mandrel layer 1312'. The first etch dielectric layer 1313' and the first etch mandrel layer 1312' respectively form a plurality of first mandrel bodies M1, and a groove pattern is formed between every two adjacent first mandrel bodies M1. Figure 4-5 for Figure 4-4 Top view, such as Figure 4-5 As shown, the first etching dielectric layer 1313' and the first etching core layer 1312' have multiple parallel groove patterns extending along the X direction on a plane parallel to the substrate.

[0104] In this embodiment, the first dielectric layer may be formed by deposition of SiON material; the material of the first core layer may be polycrystalline silicon.

[0105] Step S204: Based on the mandrel pattern of the first etched mandrel layer, deposit and form a first spacer on both sides of each first mandrel body in the first etched mandrel layer; wherein the first spacer has the initial etch pattern.

[0106] Here, the mandrel pattern of the first etched mandrel layer is the pattern of multiple parallel grooves extending along the X direction formed in step S203. See also the embodiments in this application. Figure 4-6 The first spacer can be formed in the following two ways:

[0107] Method 1: First, based on the multiple first mandrels M1 formed after etching, a thin film of uniform thickness can be deposited on the entire surface of the semiconductor device to cover the mandrel pattern of the first etched mandrel layer; then, the entire surface of the semiconductor device can be subjected to oxide / nitride chemical mechanical planarization (CMP) to remove the thin film deposited on the surface of the first etched dielectric layer 1313', exposing the first etched dielectric layer 1313'; then, a mask pattern is formed on the surface of the planarized thin film and the first etched dielectric layer 1313', and then, based on the mask pattern, a thin film of a certain size is etched using an etching process to obtain the first spacers S11, S12, S13 and the etched holes located between two adjacent first spacers.

[0108] Method 2: First, based on the multiple first mandrels M1 formed after etching, a thin film material is deposited between adjacent first mandrels M1 to form a thin film of uniform thickness; then, a mask pattern is formed on the surface of the thin film and the first etching medium layer 1313'; then, based on the mask pattern, a thin film of a certain size is etched using an etching process to obtain first spacers S11, S12, S13, etc., and etched holes located between two adjacent first spacers.

[0109] Figure 4-7 for Figure 4-6 Top view, such as Figure 4-7 As shown, the first spacers S11, S12, and S13 form an initial etching pattern in a direction perpendicular to the substrate. The plurality of spacers with the initial etching pattern are used to form a second etching mask layer. Here, the initial etching pattern is a plurality of parallel line features extending along the X direction and arranged along the Y direction.

[0110] It should be noted that the etching selectivity of the deposited film material is greater than that of the first dielectric layer material in the above two methods, that is, the etching rate of the film material is much greater than that of the first dielectric layer material under the adopted etching process.

[0111] In the embodiments of the present application, the film can be formed by any deposition process, for example, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or a coating process, etc. The material of the deposited film can be a SiO2 layer.

[0112] Step S205: removing the first etching mandrel layer to form a plurality of initial etching patterns extending along the first direction.

[0113] The top first etching dielectric layer 1313' can be removed by using a strong selective etching liquid, and the first spacers S11, S12, and S13 are reserved to form a plurality of initial etching patterns extending along the X direction. Subsequently, the top is processed by using a CMP process to remove part of the top surface of the first etching mandrel layer 1312' and the first spacers S11, S12, and S13, so as to form first spacers with initial etching patterns and a flat surface.

[0114] Step S206: etching the third mask layer based on the plurality of initial etching patterns extending along the first direction to form a third etching mask layer with the initial etching patterns.

[0115] Step S207: etching the second mask layer with the third etching mask layer as a mask, and removing the remaining third etching mask layer to form a second etching mask layer with the initial etching patterns; wherein the first mask layer and the second etching mask layer constitute the first etching mask stack.

[0116] Referring to Figure 4-8 The third mask layer 1301c is etched along the Z direction with the first spacers S11, S12, and S13 as a mask to obtain a third etching mask layer 1301c'. Referring to Figure 4-9 The second mask layer 1301b is continuously etched with the third etching mask layer 1301c' as a mask, so that the second etching mask layer 1301b' has initial etching patterns, and the etching stops on the first mask layer 1301a. As Figure 4-9 The first mask layer 1301a and the second etching mask layer 1301b' constitute the first etching mask stack 130'. Figure 4-10 ForFigure 4-9 The top view shows that the first etching mask stack 130' has multiple initial etching patterns extending along the X direction.

[0117] In some embodiments, the first mask layer, the second mask layer, and the third mask layer may be an amorphous carbon layer (ACL), a spin-on hard mask layer (SOH), a polycrystalline silicon layer, or a silicon oxynitride layer.

[0118] In this embodiment, the first spacer is formed using a self-aligned double patterning (SADP) technique. Since the imaging cycle in SADP imaging is only half that of traditional etching imaging, the cost of the 3D PCM forming process is further reduced.

[0119] Step S208: Form a second mask stack on the surface of the first etched mask stack.

[0120] like Figure 4-11 As shown, a second mask stack 132 is formed on the surface of the first etching mask stack. Here, the second mask stack 132 includes a second core layer 1322, a second dielectric layer 1323, and a second barrier layer 1324 stacked sequentially along the Z direction. The second mask stack 132 is used to form a secondary etching pattern in the Y direction.

[0121] In this embodiment, the second barrier layer 1324 is used to form the secondary etching pattern, and the second barrier layer can be formed by SiN material deposition.

[0122] Step S209: Using the multiple secondary etching patterns extending along the second direction, etch the second barrier layer to form a second etching barrier layer.

[0123] See Figure 4-12 By employing multiple secondary etching patterns extending along the Y direction, the second barrier layer 1324 in the second mask stack is etched along the Z direction to obtain the second etch barrier layer 1324'. Figure 4-13 for Figure 4-12 The top view shows that multiple parallel secondary etching patterns extending along the Y direction are formed on the second etching barrier layer 1324'.

[0124] Step S210: Using the second etch barrier layer as a mask, etch the second dielectric layer and the second mandrel layer in sequence, and remove the remaining second etch barrier layer to form the second etch mandrel layer.

[0125] See Figure 4-14Using the second etch barrier layer 1324' as a mask, the second dielectric layer 1323 and the second mandrel layer 1322 are sequentially etched along the Z direction, and the second etch barrier layer 1324' is removed to form the second etch dielectric layer 1323' and the second etch mandrel layer 1322'. The second etch dielectric layer 1323' and the second etch mandrel layer 1322' correspondingly form a plurality of second mandrel bodies M2, and a groove pattern is formed between every two adjacent second mandrel bodies M2. Figure 4-15 for Figure 4-14 The top view shows that the second etching medium layer 1323' and the second etching core layer 1322' have multiple parallel secondary etching patterns extending along the Y direction on a plane parallel to the substrate.

[0126] In this embodiment of the application, the material of the second dielectric layer can be SiON; the material of the second core layer can be polycrystalline silicon.

[0127] Step S211: Based on the mandrel pattern of the second etched mandrel layer, deposit a second spacer located on both sides of each second mandrel body in the second etched mandrel layer.

[0128] Here, the mandrel pattern of the second etched mandrel layer is the plurality of parallel secondary etched patterns extending along the Y direction formed in step S210. See also the embodiments of this application. Figure 4-16 The second spacer can be formed in the following two ways:

[0129] Method 1: First, based on the second mandrel M2 formed after etching, a relatively uniform thin film (not shown in the figure) can be deposited on the entire surface of the semiconductor device. The secondary etching pattern is covered by this thin film. Then, CMP treatment is performed on the entire surface of the semiconductor device to remove the thin film deposited on the surface of the second dielectric layer 1323, exposing the second etched dielectric layer 1323'. Then, a mask pattern is formed on the surface of the planarized thin film and the second etched dielectric layer 1323'. Based on the mask pattern, a thin film of a certain size is etched using an etching process to obtain the second spacers S21, S22, and S23, and the etched holes located between two adjacent second spacers.

[0130] Method 2: First, based on the second mandrel M2 formed after etching, a thin film material can be deposited between adjacent second mandrels to form a thin film of uniform thickness; then, a mask pattern is formed on the surface of the thin film and the second etching medium layer 1323'; then, based on the mask pattern, a thin film of a certain size is etched using an etching process to obtain the second spacers S21, S22, S23 and the etched holes located between two adjacent second spacers.

[0131] Figure 4-17 forFigure 4-16 FIG. 6 is a top view of the second spacer S21, S22, S23, wherein the second spacer S21, S22, S23 has a second feature pattern, and the second spacer is used to form a second etching mask layer. Here, the second feature pattern is a plurality of parallel line features extending along the Y direction and arranged along the X direction, corresponding to the second etching pattern.

[0132] It should be noted that in the above two manners, the etching selectivity ratio of the deposited thin film material is greater than the etching selectivity ratio of the second dielectric layer material, that is, under the adopted etching process, the etching rate of the thin film material is much greater than the etching rate of the second dielectric layer material.

[0133] In the embodiments of the present application, the deposited thin film can be formed by any deposition process, for example, CVD process, PVD process, ALD process, spin coating process or coating process. The material of the deposited layer thin film can be a SiO2layer.

[0134] Step S212: removing the second etching mandrel layer; performing second etching on the first etching mask layer stack with the second spacer as a mask to form the second etching mask layer stack.

[0135] The top second etching dielectric layer 1323' is removed using a highly selective etching liquid, and only the second spacer S21, S22, S23 is reserved to form a plurality of second feature patterns extending along the Y direction. Subsequently, the top is processed by using a CMP process to remove the remaining second etching mandrel layer 1322' on the top and part of the top surface of the second spacer S21, S22, S23, and to form a second spacer with a second feature pattern and a flat surface.

[0136] In some embodiments, the second etching on the first etching mask layer stack to form the second etching mask layer stack in step S212 can be realized by the following manner:

[0137] Manner one: performing second etching on the second etching mask layer with the second spacer as a mask to form a second second etching mask layer; removing the second spacer, wherein the first mask layer and the second second etching mask layer constitute the second etching mask layer stack.

[0138] Referring to Figure 4-18 The second second etching mask layer 1301b" is formed by performing second etching on the second etching mask layer 1301b' with the second spacer S21, S22, S23 with a second feature pattern as a mask. The second etching mask layer stack 1301 is composed of the unetched first mask layer 1301a and the second second etching mask layer 1301b" after etching. ” is composed of the unetched first mask layer 1301a and the second second etching mask layer 1301b ” after etching. Figure 4-19 Figure 4-18 ​a top view of the second etching mask layer 1301b ” has a grid-like pattern in the plane parallel to the substrate plane.

[0139] Secondly, the second etching mask layer 1301b' is etched by taking the second spacer S21, S22, S23 with the second feature pattern as a mask to form a second etching mask layer 1301b'', and the first mask layer 1301a is etched to form a first etching mask layer 1301a.

[0140] Referring to Figure 4-20 Secondly, the second etching mask layer 1301b' is etched by taking the second spacer S21, S22, S23 with the second feature pattern as a mask to form a second etching mask layer 1301b'', and the first mask layer 1301a is etched to form a first etching mask layer 1301a. ’ The second etching mask layer 1301b ” is etched by taking the second spacer S21, S22, S23 with the second feature pattern as a mask to form a second etching mask layer 1301b'', and the first mask layer 1301a is etched to form a first etching mask layer 1301a. ’ The second etching mask layer 1301b ” is etched by taking the second spacer S21, S22, S23 with the second feature pattern as a mask to form a second etching mask layer 1301b'', and the first mask layer 1301a is etched to form a first etching mask layer 1301a. Figure 4-21 Figure 4-20 Referring to ” a top view of the second etching mask layer 1301b ’ has a grid-like pattern in the plane parallel to the substrate plane.

[0141] Step S213: taking the second etching mask layer as a mask, the top layer is etched to form a top layer unit.

[0142] As shown in Figure 4-22 The phase change memory cell layer 120 includes a top layer 121 and a bottom layer 122. The top layer 121 includes, in the Z direction, a hard mask layer 1204, a first electrode layer 1201c, and a PCM element layer 1203 in sequence. The bottom layer 122 includes, in the Z direction, a second electrode layer 1201b, a selector layer 1202, and a third electrode layer 1201a in sequence.

[0143] Referring to Figure 4-23 ​In step S213, using the secondary etching mask stack as a mask, the hard mask layer 1204, the first electrode layer 1201, and the PCM element layer 1203 are sequentially etched to form the hard etching mask layer 1204', the first etching electrode layer 1201c', and the PCM etching element layer 1203', and to form a first through hole 1 penetrating the hard etching mask layer 1204', the first etching electrode layer 1201c', and the PCM etching element layer 1203', and a top stacked unit column 10, 20, and 30 arranged sequentially along the X direction around the first through hole.

[0144] Figure 4-24 for Figure 4-23 The top view shows that the top stacked unit column 10 includes top stacked units 11, 12, and 13 arranged sequentially along the Y direction parallel to the substrate plane; the top stacked unit column 20 includes top stacked units 21, 22, and 23 arranged sequentially along the Y direction parallel to the substrate plane; and the top stacked unit 30 includes top stacked unit columns 31, 32, and 33 arranged sequentially along the Y direction parallel to the substrate plane. In this embodiment, the top stacked units are arranged according to... Figure 4-24 The arrangement of these elements forms a top-layered unit structure.

[0145] In the embodiments of this application, the PCM element layer includes PCM elements, which are generally chalcogenide compound materials, such as GST (germanium antimony tellurium); the first electrode layer can be a carbon electrode layer; and the hard mask layer can be a silicon nitride layer.

[0146] Step S214: A first encapsulation layer is deposited on the surface of the top stacked unit. Using the top stacked unit with the first encapsulation layer as a mask, the bottom stacked unit is etched a second time to form a phase change memory cell.

[0147] See Figure 4-25 In step S213, a first encapsulation material is deposited on the sidewall of the first through-hole 1 and the surface of the hard etch mask layer 1204' to form the first encapsulation layer Y1, which is used to protect the PCM element exposed after etching.

[0148] In this embodiment, the first encapsulation material can be a ceramic-based encapsulation material, a plastic-based encapsulation material, or other encapsulation and protective material with insulating properties, and is not limited thereto. A bidirectional threshold switch (OTS) is arranged in the selector layer, and the material of the OTS may include Zn. x Te y 、Ge x Te y 、Nb x O y Si x As y Tez The second electrode layer and the third electrode layer can be carbon electrode layers.

[0149] Referring to Figure 4-26 The second electrode layer 1201b, the selector layer 1202 and the third electrode layer 1201a are sequentially etched to form a second etched electrode layer 1201b', an etched selector layer 1202' and a third etched electrode layer 1201a', and a second via hole 2 and the phase change memory cell columns 101, 201, 301 around the second via hole 2 are formed through the second etched electrode layer 1201b', the etched selector layer 1202' and the third etched electrode layer 1201a'. Figure 4-27 Referring to Figure 4-26 The phase change memory cell columns 101, 201, 301 respectively include phase change memory cells 111, 112, 113, 211, 212, 213, 311, 312, 313 arranged in the Y direction on the substrate plane.

[0150] Step S215: A second encapsulation layer is deposited on the surface of the phase change memory cell, and a gap material is filled in the surface of the second encapsulation layer to form a gap material layer.

[0151] Referring to Figure 4-28 A second encapsulation material is deposited on the surface of the phase change memory cell to form the second encapsulation layer Y2.

[0152] In the embodiments of the present application, the second encapsulation layer Y2 is used to protect the electrode material and the OTS material exposed after etching, and the material of the second encapsulation layer can be a ceramic-based encapsulation material, a plastic-based encapsulation material or other encapsulation protection materials with insulation effect, which are not limited herein.

[0153] Referring to Figure 4-29 A gap material is filled in the surface of the second encapsulation layer Y2 and the gap of the second via hole 2 to form a gap material layer G, and in the embodiments of the present application, the ALD-ox, SOD or flow CVD-ox with low thermal conductivity can be used to fill the gap, and in some embodiments, the low-conformal TEO can be used to fill the gap to form an air gap.

[0154] Step S216: The remaining hard etching mask layer in the top layer is removed to expose the first etched electrode layer in the top layer unit.

[0155] Referring to Figure 4-30The CMP process is used to remove the top hard etch mask layer, as well as portions of the first encapsulation layer Y1, the second encapsulation layer Y2, and the interstitial material layer G on the hard etch mask layer, to expose the first etch electrode layer 1201c. ’ Here, the first etched electrode layer 1201c is exposed. ’ It has a flat structure on a plane parallel to the substrate.

[0156] Step S217: On the first etched electrode layer in each exposed top stacked cell, a word line contact is formed; multiple word lines extending along the second direction and arranged along the first direction are formed on the word line contact, thereby forming the three-dimensional phase change memory.

[0157] See Figure 4-31 On the first electrode layer of each exposed top stacked cell, a word line contact 103 is formed. Above each word line contact, a plurality of word lines 104 extending in the X direction and arranged parallel to each other in the Y direction are formed to create the three-dimensional phase-change memory 300. The three-dimensional phase-change memory 300 sequentially includes, along the Z direction: bit line 101, bit line contact 102, phase-change memory cell 200, word line contact 103, and word line 104. Figure 4-32 for Figure 4-31 In the top view, the three-dimensional phase-change memory 300 has word lines 104 and bit lines 101 that are perpendicular to each other in a plane parallel to the substrate, and in the region where the mutually perpendicular word lines and bit lines intersect, there are columnar phase-change memory cells 200 located between the word lines and bit lines.

[0158] The material of word line contact 103 can be different from that of word line 104; or, the material of word line contact 103 can be the same as that of word line 104. When the material of word line contact 103 is the same as that of word line 104, word lines can be formed directly on the exposed first etched electrode layer without forming word line contacts.

[0159] In some embodiments, peripheral metal wiring can be formed simultaneously with word lines to further reduce word line resistance and overall RC delay.

[0160] In this embodiment, by using a two-stage etching mask stack, the memory cell stack is formed in one step during etching, which not only reduces the number of mask deposition layers but also saves etching process steps, thereby reducing the manufacturing cost of 3D PCM. In some embodiments, using the same material as the word lines to form word line contacts can further reduce the forming process of 3D PCM.

[0161] This application provides a three-dimensional phase change memory, which includes phase change memory cells having a grid pattern.

[0162] In some embodiments, the three-dimensional phase change memory further comprises: a plurality of bit lines extending along the X direction and arranged along the Y direction; and at least one bit line contact above the plurality of bit lines, the bit line contact being used to connect the bit lines and the phase change memory cell stack.

[0163] In some embodiments, the three-dimensional phase change memory further comprises: an encapsulation layer around the etched phase change memory cell, the encapsulation layer comprising: a first encapsulation layer on a surface of the top stack cell, and a second encapsulation layer on a surface of the bottom stack cell; and a gap material layer on a surface of the second encapsulation layer.

[0164] In some embodiments, the three-dimensional phase change memory further comprises: a word line contact on a first electrode layer in the top stack cell, and a plurality of word lines extending along the Y direction and arranged along the X direction above the word line contact.

[0165] In some embodiments, the three-dimensional phase change memory further comprises: a peripheral metal wiring around the phase change memory device.

[0166] In the embodiments of the present application, a three-dimensional phase change memory is provided, which is formed by any one of the forming methods of the three-dimensional phase change memory described above. The PCM cell of the three-dimensional phase change memory is formed by half of the number of etching times and half of the number of thin film deposition layers, so as to reduce the process steps of the three-dimensional phase change memory and reduce the manufacturing cost of the phase change memory. Meanwhile, the formation of the plurality of copper metal BLs and WLs further reduces the resistance of the BLs and WLs and the overall RC delay, and the three-dimensional phase change memory further provides the peripheral metal wiring formed simultaneously with the BLs and WLs respectively.

[0167] In the several embodiments of the present application, it should be understood that the disclosed device and method can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There can be another division for actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling or direct coupling between each component can be indirect coupling through some interface units.

[0168] The disclosed features in the several method or device embodiments of the present application can be combined with each other without conflict, to obtain new method embodiments or device embodiments.

[0169] The above merely describes some embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for forming a three-dimensional phase-change memory, characterized in that, The method includes: A stacked structure is provided; the stacked structure includes a phase change memory cell stack and a first mask stack stacked sequentially; The first mask stack is etched using multiple initial etching patterns extending along a first direction to form a first etching mask stack; A second mask stack is formed on the surface of the first etched mask stack; Multiple secondary etching patterns extending along a second direction are used to sequentially etch the second mask stack and the first etching mask stack to form a secondary etching mask stack, wherein the secondary etching mask stack has a grid pattern; Using the secondary etching mask stack as a mask, the phase change memory cell stack is etched to form a columnar phase change memory cell; wherein, the first direction and the second direction are perpendicular to each other; The first mask stack includes at least: a first mask layer, a second mask layer, a third mask layer, a first core layer, a first dielectric layer, and a first barrier layer stacked sequentially from bottom to top; The method for forming the plurality of initial etching patterns includes: The first barrier layer is patterned to form a first etch barrier layer; Using the first etch barrier layer as a mask, the first dielectric layer and the first mandrel layer are etched sequentially, and the remaining first etch barrier layer is removed to form the first etch mandrel layer. Based on the mandrel pattern of the first etched mandrel layer, a first spacer is deposited on both sides of each first mandrel body in the first etched mandrel layer; wherein the first spacer has the initial etch pattern. Remove the first etched mandrel layer to form a plurality of initial etched patterns extending along the first direction.

2. The method according to claim 1, characterized in that, The stacked structure further includes: Multiple bit lines extending along the first direction and arranged along the second direction, and at least one bit line contact located on each of the bit lines, the bit line contact being used to connect the bit lines and the phase change memory cell stack.

3. The method according to claim 1, characterized in that, The first etching mask stack is formed by the following steps: Based on a plurality of initial etching patterns extending along the first direction, the third mask layer is etched to form a third etching mask layer having the initial etching patterns; Using the third etching mask layer as a mask, the second mask layer is etched, and the remaining third etching mask layer is removed to form a second etching mask layer with the initial etching pattern; wherein, the first mask layer and the second etching mask layer constitute the first etching mask stack.

4. The method according to claim 3, characterized in that, The third mask layer is etched using the following steps: Using the first spacer as a mask, the third mask layer is etched to form the third etched mask layer.

5. The method according to claim 3, characterized in that, The second mask stack is formed by the following steps: A second core layer, a second dielectric layer, and a second barrier layer are sequentially deposited on the surface of the second etch mask layer. The second core layer, the second dielectric layer, and the second barrier layer constitute the second mask stack.

6. The method according to claim 5, characterized in that, The secondary etching mask stack is formed through the following steps: The second barrier layer is etched by using multiple secondary etching patterns extending along the second direction to form a second etch barrier layer; Using the second etch barrier layer as a mask, the second dielectric layer and the second mandrel layer are etched sequentially, and the remaining second etch barrier layer is removed to form the second etch mandrel layer; Based on the mandrel pattern of the second etched mandrel layer, a second spacer is deposited on both sides of each second mandrel body in the second etched mandrel layer; Remove the second etched mandrel layer; Using the second spacer as a mask, the first etching mask stack is etched a second time to form the second etching mask stack.

7. The method according to claim 6, characterized in that, The secondary etching mask stack is formed through the following steps: Using the second spacer as a mask, the second etching mask layer is etched a second time to form a second second etching mask layer; Remove the second spacer; wherein the first mask layer and the second etch mask layer constitute the second etch mask stack.

8. The method according to claim 6, characterized in that, The secondary etching mask stack is formed through the following steps: Using the second spacer as a mask, the second etching mask layer and the first etching mask layer are etched sequentially to form a second etching mask layer and a first etching mask layer. Remove the second spacer; wherein the secondary second etching mask layer and the first etching mask layer constitute the secondary etching mask stack.

9. The method according to claim 8, characterized in that, The phase change memory cell stack includes a bottom stack and a top stack, which are stacked sequentially from bottom to top. Correspondingly, the phase-change memory is obtained through the following steps: Using the secondary etching mask stack as a mask, the top stack is etched in the first step to form a top stack unit; A first encapsulation layer is deposited on the surface of the top stacked unit; Using the top stacked unit with the first encapsulation layer as a mask, the bottom stacked unit is etched a second time to form a phase change memory unit; A second encapsulation layer is deposited on the surface of the phase change memory cell to obtain the columnar phase change memory cell.

10. The method according to claim 9, characterized in that, The top stack comprises, from bottom to top, the following layers: a PCM element layer, a first electrode layer, and a hard mask layer; The top layer is first etched using the following steps: Using the secondary etching mask stack as a mask, the hard mask layer, the first electrode layer and the PCM element layer are sequentially etched to form a hard etching mask layer, a first etching electrode layer and a PCM etching element layer. A first via is formed that penetrates the hard etching mask layer, the first etching electrode layer and the PCM etching element layer, and a top stack unit is formed around the first via. The deposition of a first encapsulation layer on the surface of the top stacked unit includes: A first encapsulation material is deposited on the sidewall of the first via and on the surface of the hard etched mask layer to form the first encapsulation layer.

11. The method according to claim 9, characterized in that, The bottom stack comprises, from bottom to top, the following layers: a third electrode layer, a selector layer, and a second electrode layer; The bottom stack is etched a second time using the following steps: Using the top stacked unit with the first encapsulation layer as a mask, the second electrode layer, the selector layer and the third electrode layer are sequentially etched to form a second etched electrode layer, an etched selector layer and a third etched electrode layer, and a second via penetrating the second etched electrode layer, the etched selector layer and the third etched electrode layer, and the phase change memory cell located around the second via. The deposition of a second encapsulation layer on the surface of the phase-change memory cell includes: A second encapsulation material is deposited on the sidewall of the second via and on the surface of the phase change memory cell to form the second encapsulation layer.

12. The method according to claim 11, characterized in that, The method further includes: A gap material is filled on the surface of the second encapsulation layer to form a gap material layer; Remove the remaining hard etch mask layer in the top stack to expose the first etch electrode layer in the top stack unit.

13. The method according to claim 12, characterized in that, The method further includes: A word line contact is formed on the first etched electrode layer in each exposed top stack cell; Multiple word lines extending along the second direction and arranged along the first direction are formed on the word line contacts to form the phase change memory; wherein, the word line contacts are used to connect the first etched electrode layer and the word lines, and the material of the word lines includes copper; or, Multiple word lines are formed on the first etched electrode layer in each exposed top stacked cell, the word lines being made of tungsten.

14. A three-dimensional phase-change memory, formed using the method for forming a three-dimensional phase-change memory according to any one of claims 1 to 13, characterized in that, The three-dimensional phase change memory includes at least: columnar phase change memory cells.

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