Non-volatile phase-change memory devices and related row decoding methods

Abstract

Embodiments of this disclosure relate to non-volatile phase-change memory devices and related row decoding methods. In one embodiment, the non-volatile memory device includes a memory array comprising a plurality of memory sections, each memory section having a corresponding plurality of memory cells arranged in rows and columns, wherein the memory sections are arranged in groups, each group of memory sections having a plurality of corresponding memory sections arranged in rows and a plurality of corresponding word lines extending through the corresponding memory sections, wherein the memory cells of a group of memory sections are coupled to the corresponding word lines and a row decoder, the row decoder including a pre-decoding stage configured to perform selection, in which the row decoder selects word lines extending through the group of memory sections and deselects other word lines extending through the group of memory sections, and a subsequent deselection, in which the row decoder deselects all word lines extending through the group of memory sections.

Description

[0001] Related applications

[0002] This application claims priority to Italian patent application No. 102021000004973, filed on March 3, 2021, which is incorporated herein by reference. Technical Field

[0003] This invention relates to a non-volatile phase-change memory device comprising a distributed row decoder having n-channel MOSFET transistors; furthermore, this invention relates to a corresponding row decoding method. Background Technology

[0004] As is well known, in phase-change type non-volatile memories (so-called PCM or ePCM, embedded phase-change memory), information is stored by utilizing phase-change materials, which have the property of being able to switch between phases with considerably different resistivity values. In particular, these materials can switch between an amorphous phase with high resistivity and a crystalline or polycrystalline phase with low resistivity. Therefore, in a phase-change memory cell, for each phase (amorphous or crystalline) of the corresponding phase-change memory element, different values ​​of the data items stored in the cell can be associated.

[0005] For example, elements from Group VI of the periodic table, such as tellurium (Te), selenium (Se), or antimony (Sb), can be used as phase-change memory elements; these are called chalcogenides or chalcogenide materials. Alloys composed of germanium (Ge), antimony (Sb), and tellurium (Te), called GST (with the chemical composition Ge₂Sb₂Te₅), are currently widely used in these memory elements.

[0006] Phase switching in a memory element can be achieved by locally increasing the temperature of the phase change material region, for example, by passing an electrically programmed current through resistive electrodes (often called heaters) arranged in contact with the phase change material region. This current generates the temperature distribution required for the phase transition through the Joule effect.

[0007] Specifically, when the phase change material is in a high-resistivity amorphous state (the so-called reset state), a first current pulse (the so-called set pulse) needs to be applied, which has a duration and amplitude that allows the material to cool slowly. When subjected to this treatment, the phase change material changes its state and switches from a high-resistivity state to a low-resistivity crystalline state (the so-called set state). Conversely, when the phase change material is in the set state, a second current pulse (the reset pulse) with a high amplitude and a short duration needs to be applied to return the material to the high-resistivity amorphous state.

[0008] Reading data items stored in a memory cell can be performed by applying a sufficiently low voltage to the storage element of the phase change material without causing it to generate considerable heat, and then reading the value of the current flowing in the memory cell. Assuming that the current is proportional to the conductivity of the phase change material, the phase in which the material is located can be determined, thereby deriving the data item stored in the memory cell.

[0009] Specifically, read structures for differential-type PCM memory devices are known, in which two memory cells in relative states are associated with each bit of the word to be read (consisting of an appropriate number of bits in a known manner). For example, if the first memory cell (so-called direct cell) and the second memory cell (so-called complementary cell) associated with the bit are in a set state and a reset state, respectively, then the bit has a value of "1", and if the first memory cell and the second memory cell are in a reset state and a set state, respectively, then the bit has a value of "0". Differential-type read architectures offer advantages in reliability for storing data items redundantly, and do not require a reference current for performing reads simply by comparing the corresponding currents flowing in the cells associated with the same bit.

[0010] Memory cells are organized into memory arrays, and specifically arranged in rows formed by word lines and columns formed by bit lines (BLs).

[0011] like Figure 1 As schematically shown, each memory cell 2 includes a phase-change element 2a and a selector element 2b, such as a MOSFET transistor or (e.g., Figure 1 (Shown) A BJT transistor electrically connected to a heater associated with a phase-change element 2a (not shown) to selectively allow electrical programming or read current to pass through.

[0012] In the case of BJT-type selector elements, phase-change element 2a is coupled between the emitter terminal of the BJT transistor (in the PNP type example) of the corresponding selector element 2b and the corresponding bit line BL; furthermore, the base terminal of selector element 2b is electrically coupled to the corresponding word line WL. The base terminals of selector elements 2b in the same row of memory cells 2 are coupled to the same word line WL, and the phase-change elements 2a of memory cells 2 in the same column are coupled to the same bit line BL. The collector terminal of the BJT transistor of selector element 2b is set to a reference voltage, such as ground reference voltage GND.

[0013] Using a BJT-type selector element 2b offers several advantages over MOSFET technology, such as reducing the total area occupied by the memory cell 2 and increasing the integration density of the memory device. However, compared to using MOSFET transistors, using a BJT-type selector element requires careful consideration of the base current of the corresponding BJT transistor, which flows along the word line WL and can itself determine an undesirable voltage drop along the word line WL. Specifically, when the word lines WL are not addressed (i.e., when they are deselected), they are biased to a high bias voltage, which can lead to high leakage current toward the base terminals of the BJT transistor, resulting in voltage variations along the word line WL and high power consumption by a charge pump (not shown) designed to generate the aforementioned bias voltage.

[0014] In this regard, Figure 2 A memory array 3 of a phase-change type memory device 1 is shown, wherein memory cells 2 are coupled to corresponding word lines WL (arranged in rows) and corresponding bit lines BL (arranged in columns). The phase-change element 2a of the memory cell 2 is schematically represented here by corresponding resistor elements.

[0015] Specifically, Figure 2 It shows the relationship with R BL The bit line BL and R represent WL The parasitic resistance (or line resistance) associated with the word line WL is represented; in addition, the parasitic base resistance of the BJT transistor of the selector element 2b of memory cell 2 is represented by RB.

[0016] exist Figure 2 In the example described, the base terminals of selector elements 2b in the same row are coupled to the same metallization line, which is contacted by corresponding word lines WL at regular intervals (every four memory cells 2 in this example) (in this example, the word lines WL are arranged at a higher metallization level than the base metallization line in the layout of the memory array 3).

[0017] As shown in the figure, the memory device 1 also includes a row decoder 4 and a column decoder 5, which are configured to address and bias the word line WL and bit line BL in an appropriate manner each time a memory operation (programming and reading) is selected.

[0018] Specifically, during programming (or writing) and read operations, the word line WL that is addressed and selected is typically biased to the ground reference voltage GND (in this example, the BJT transistor is pnp type); when not selected, the same word line WL is biased to a positive voltage of the appropriate value.

[0019] Therefore, the current (with potentially high values ​​depending on the operation being performed) circulates along the selected word line WL, and this current causes a line voltage drop due to the resistance associated with the same word line WL (which consists of the parasitic line resistance RWL and the base resistance RB). Consequently, as a result of this voltage drop, the bias condition of the memory cell 2 varies along the same word line WL depending on its location in the memory array 3.

[0020] To mitigate this drawback, it has been proposed to divide the memory array 3 into several parts (so-called tiles), each tile comprising a certain number (e.g., equal to 256, 512, or 1024) of local word lines and local bit lines, which constitute portions of the corresponding rows and columns of the entire memory array 3. In this case, the selected word consists of a certain number of bits distributed across different tiles, thereby limiting the number of selected memory cells and thus limiting the impact of voltage drop on the word lines within each tile. This solution envisions multiplexing operations and row address decoding operations during reads, which would enable the selection of memory cells 2 addressed in various tiles to reconstruct the data word.

[0021] For example, Figure 3 A portion of the memory array 3 of the memory device 1 is shown, comprising a group of five tiles arranged side by side in the same row; as previously described, each tile (denoted by 6) is formed by a certain number of memory cells arranged in local word lines WL and local bit lines BL (not shown here).

[0022] In this configuration, the line decoder 4 includes: a main line decoding unit 8 associated with the tile group 6 and configured to provide address decoding and bias signals based on address signals received at the input; and a plurality of local line decoding units 9 coupled to the main line decoding unit 8, each local line decoding unit 9 for each tile 6 of the group. Specifically, the aforementioned local line decoding units 9 perform the function of locally selecting word lines WL within each tile 6, i.e., bringing the word lines WL to the ground reference voltage GND.

[0023] In this case, the column decoder 5 includes a plurality of local column decoding units 10, each piece 6 corresponding to one local column decoding unit 10, which enables the selection and biasing of the local bit lines BL associated with the memory cells that must be read, and connects them to the corresponding sense amplifiers (SA) 11, which are configured to compare the read current of the memory cells (direct and complementary) associated with each bit of the data word.

[0024] In the example described, 32 memory cells are read for each tile 6 (i.e., 16 data bits, given the differential nature of the read operation), resulting in sixteen sense amplifiers 11 for each tile 6; the resulting readings are composed of double words, each word consisting of 32 data bits plus 7 error correction code (ECC) bits plus 1 redundancy bit. Therefore, a total of 40+40 bits corresponding to two words are read, corresponding to 160 physically addressed cells.

[0025] Generally, the number of memory cells read within each chip 6 depends on the maximum voltage drop that can be maintained on the word line WL; for example, in the illustrated case, reading 32 memory cells may require a voltage drop of approximately 100mV on the local word line WL of chip 6.

[0026] An example of a row decoding architecture for a non-volatile memory device comprising multiple tiles is described in U.S. Patent Application Publication No. 2019 / 0206488. This architecture envisions each word line (WL) of each tile being coupled to a pull-up stage formed by a PMOS transistor. This solution is particularly advantageous when the PMOS transistors are low-voltage transistors (e.g., those with a channel length of 0.18 μm obtained in SOI technology and capable of maintaining a voltage in a region of 1.6 V) to include the area occupied by the pull-up stage associated with the tile. These low-voltage transistors are capable of conducting high currents even at relatively low gate-source voltages, and therefore can deselect word lines (WL) particularly quickly even when the voltage set on the word lines (WL) is relatively low; this speed is particularly useful during reads. However, the limitation on the types of PMOS transistors that can be used can prove to be overly restrictive for a large number of applications. In practice, for example, some applications may require the use of different types of transistors, such as transistors capable of operating at higher voltages (e.g., equal to 3.6 V), in order to reduce costs or meet constraints imposed by the manufacturing process. These transistors are characterized by a larger channel length and greater thickness of the gate oxide, and in order to conduct current satisfactorily, they must be biased at high voltages or must have a larger channel width. Therefore, known solutions are unsatisfactory in this case because they require high area consumption and / or word line WL settings at high voltages when deselected, resulting in high static and dynamic leakage. Summary of the Invention

[0027] The embodiments provide a row decoding architecture for non-volatile memory devices, particularly phase-change type non-volatile memory devices, which overcomes the shortcomings of the prior art. Attached Figure Description

[0028] To better understand the invention, preferred embodiments thereof will now be described by way of non-limiting example only with reference to the accompanying drawings, wherein:

[0029] Figure 1 This is a schematic diagram of a phase-change memory cell of a known type;

[0030] Figure 2 This is a schematic illustration of a portion of a memory array that is a known type of non-volatile memory device;

[0031] Figure 3 A portion of a memory array of a known type of non-volatile memory device is shown, divided into tiles;

[0032] Figure 4 A circuit diagram showing a portion of this non-volatile memory device is provided. It illustrates a portion of the memory array of the non-volatile memory device. The non-volatile memory device is of the phase-change type and includes... Figure 1 The memory cell shown in the figure; and

[0033] Figure 5 A simplified block diagram of an electronic system incorporating this memory device is shown. Detailed Implementation

[0034] In a manner similar to that previously mentioned, memory array 3 is divided into several parts, known as tiling; specifically, Figure 3 The first and second tiles, represented by 6' and 6" respectively, form part of a tile group 16 (e.g., comprising five tiles). The tile group 16 is arranged in the same row and collectively undergoes the operation of reading words consisting of a certain number of bits. The memory array 3 includes multiple tile groups arranged in columns. Figure 4 Only one set of pieces is visible in the image. Furthermore... Figure 4 The diagram illustrates a single word line WL that extends ohmically through the puzzle group 16 and then through the first puzzle 6′ and the second puzzle 6″. Without implying any general loss of generality, it is assumed below that each puzzle is traversed by 1024 word lines, which are grouped into 32 word line WL subgroups, each subgroup therefore comprising 32 word lines WL. In the following description, reference will be made to a single subset of the thirty-two word lines WL extending through the puzzle group 16, and more precisely through five sections of puzzles aligned with each other (in other words, through a group of sections of puzzles arranged in a row), unless otherwise specified. Furthermore, Figure 4 The word line WL shown in the figure is the first of the thirty-two word lines WLs that are a subset of the thirty-two word lines WLs considered in this specification.

[0035] The non-volatile memory device 1 includes a main row decoding unit 28, which is designed to generate address decoding signals based on address signals received at an input (not shown), as described in more detail below. In other words, the main row decoding unit 28 serves as a pre-decoding unit.

[0036] Furthermore, for each tile group, the non-volatile memory device 1 includes a shared pull-up stage 29 and a plurality of local row decoding stages that are identical to each other and equal to the number of tiles present in the tile group 16, each local row decoding stage being associated with a corresponding tile; specifically, Figure 4 The diagram illustrates the first line decoding level and the second local line decoding level, specified by 30′ and 30″ respectively and associated with the first piece 6′ and the second piece 6″ respectively. Furthermore, the shared pull-up level 29 and the first local line decoding level 30′ and the second local line decoding level 30″ are described with reference to a single subset of the thirty-two word lines WL.

[0037] More specifically, the shared pull-up decoding stage 29 includes a number of PMOS transistors (e.g., enriched) equal to the number of word lines WL, which is a subset of the word lines WL; in Figure 4 In the example shown, these PMOS transistors are therefore numbered 32 and are respectively controlled by M p0,0 -M p0,31 Indicates (in) Figure 4 Only transistor M is shown in the image. p0,0 and M p0,31 In the following text, PMOS transistor M... p0,0 -M p0,31 Known as the word line deselect transistor M p0,0 -M p0,31 .

[0038] Refer to the k-th word line to deselect transistor M p0，k (where k = 1, 2, ..., 31), and the corresponding source extrema are connected to node NV. read / write The corresponding drain terminal is connected to the corresponding word line WL, that is, connected to the k-th word line WL that crosses the chip group 16; in addition, there is a deselect transistor M on the k-th word line. p0,k The gate terminal is the address decoding signal SECT_LX generated by the main decoding unit 28. <k>Also in Figure 4 The diagram shows node N31, which is in contact with the thirty-two word lines WL.

[0039] For each word line WL in a subset of word lines WL, the shared pull-up stage 29 also includes, for example, a word line deselect transistor M. p0,0 -M p0,31 Another PMOS transistor M of the same type p1,k In the following text, PMOS transistor M... p1,0 -M p1,31 Known as the group deselect transistor M p1,0 -Mp 1,31 .

[0040] More specifically, consider the k-th word line WL, and the corresponding group deselect transistor M. p1,k The source and drain terminals are connected to node NV respectively. read / write And the k-th word line WL; in addition, there exists the k-th group of selection transistors M. p1,k The gate terminal is the address decoding signal SECT_PX generated by the main decoding unit 28. <j>Specifically, the reference address decoding signal SECT_PX <j>The index j iterates through the thirty-two word line subset WL of the puzzle group 16; in this regard, it is expected that each activation will use the thirty-two address decoding signals SECT_PX. <j>One of the address decoding signals is used to select the corresponding subset of word lines WL. The selection of these individual tile groups is performed in a manner known per se by using additional address decoding signals, and therefore will not be described further; thus, unless otherwise stated, this specification will refer only to tile group 16.

[0041] Regarding the local line decoding level, the first local line decoding level 30' described below is associated with the first piece 6'. The second local line decoding level 30' associated with the second piece 6' is indicated by superscripts in the same manner as the components of the first local line decoding level 30'. Again, in this case, the description refers to a single subset of the thirty-two word lines WL, unless otherwise stated.

[0042] In detail, the first local line decoding stage 30' includes a local pull-down stage 31 and a local pull-up stage 32.

[0043] Local pull-down stage 31 includes: group selection transistor M n This is an NMOS transistor (enriched transistor); and another NMOS transistor whose number is equal to the number of word lines WL, a subset thereof, which, for example, has a group select transistor M. n Same type. Figure 4 In the example shown, the NMOS transistor is therefore numbered 32, and is respectively by M n0 -M n31 Indicates (in) Figure 4 Only transistor M is shown in the image. n0 and M n31 In the following text, NMOS transistor M... n0 -M n31 Known as word line select transistor M n0 -M n31 .

[0044] More specifically, word line selection transistor M n0 -M n31 The source terminal is connected to the group selection transistor M. n The drain terminal is connected to the ground reference voltage GND. This is present in the group select transistor M. n The gate terminal contains the address decoding signal SECT_PX. <j>Furthermore, consider the k-th word line selection transistor M. nk The corresponding drain terminal is connected to the k-th word line WL.

[0045] For each word line WL of a subset of word lines WL, the local pull-up stage 32 of the first local line decoding stage 30' includes a corresponding NMOS transistor M. pu,k (exist Figure 4 Only transistor M is shown in the image. pu，0 and M pu，31 ), which, for example, has a group selection transistor M n The same type, and referred to below as the additional pull-up transistor M. pu,k .

[0046] The k-th additional pull-up transistor M pu,k The drain and source terminals are connected to node NV respectively. read / write And the k-th word line WL; exists in the k-th additional pull-up transistor M pu,k The gate terminal contains the address decoding signal SECT_NPX. <j>It is generated by the main line decoding unit 28 and is equal to the aforementioned address decoding signal SECT_PX. <j>The logical negation.

[0047] For example, when the address decoding signals SECT_PX, SECT_NPX and SECT_LX are equal to "0" and "1" respectively, they can use voltage values ​​of 0V and 3.6V.

[0048] This has been described with reference to the reading steps of memory array 3, and specifically, for example, it has been described with reference to the steps of reading memory cells 2 arranged along the k-th word line WL of a subset of the j-th word line WL passing through the tile group 16. Regarding the operation of the local line decoding level, subsequent processing is initially limited to the description of the first local line decoding level 30'.

[0049] Initially, all word lines (WL) are deselected; for this purpose, the main line decoding unit 28 had previously set SECT_PX. <j>='0', SECT_NPX='1' and SECT_LX ='0', where i = 0, ..., 31. Furthermore, in a manner known per se, the main row decoding unit 28 will decode node NV... read / write Set to voltage V read It is, for example, equal to 1.6V and can be lower than voltage V. write The latter is written by the master decoding unit 28 at node NV. read / write The voltage set on it. For example, voltage V. write It can be equal to 3.6V.

[0050] Therefore, referring to the k-th word line WL, the corresponding word line selection transistor M nk Group selection transistor M n This is disabled to decouple the word line WL from the ground reference voltage GND; conversely, the corresponding word line deselect transistor Mp is disabled. 0，k and the corresponding group to deselect transistor Mp 1,k Turning on (i.e., above the threshold) causes the word line WL to be set to voltage V. high Approximately equal to voltage V read This results in the deselection of the word line WL. Additionally, the corresponding pull-up transistor M... pu,k It is also higher than the threshold because SECT_NPX <j>='1'.

[0051] Next, in order to select the k-th word line WL, the main line decoding unit 28 sets SECT_PX. <j>='1',SECT_NPX <j>='0',SECT_LX <k>='1', and for each i different from k, maintain SECT_LX ='0'. This requires the content described below.

[0052] All additional pull-up transistors M pu,0 -M pu,31 Banned because of SECT_NPX <j>='0'; Similarly, all thirty-two groups deselect transistor M p1,0 -M p1,31 All are prohibited because of SECT_PX <j>= '1'. Furthermore, at voltage V high Below, all word lines WL except the k-th word line WL remain deselected. In fact, referring to the i-th word line WL (i is different from k), the corresponding word line deselection transistor M is found. p0,i and the corresponding word line selection transistor M ni Each exceeds the threshold and is disabled because of SECT_LX. = '0'. Specifically, the word line selects transistor M. ni The fact that it is prohibited causes the i-th word line WL to be decoupled from the ground reference voltage GND, although the group selection transistor M n In SECT_PX <j>=1 is above the threshold. Additionally, the word line deselects transistor M. p0,i Keep the i-th word line WL connected to node NV read / write Therefore, the i-th word line WL remains at voltage V. high .

[0053] In contrast, the k-th word line WL is selected; that is, since the corresponding word line selector transistor M... nk Above the threshold (SECT_LX) <k>= '1'), and together with the group selection transistor Mn, forms a connection toward the ground reference voltage GND, thus causing the voltage V low The first approximation is equal to the ground reference voltage GND; furthermore, the k-th word line WL and node NV read / write Decoupling occurs because the corresponding group deselects transistor M. p1,k The corresponding word line deselects transistor M. p0,k and the corresponding additional pull-up transistor M pu,k It is prohibited. Specifically, because of SECT_LX <k>='1', the corresponding word line deselects transistor M. p0,k It is prohibited.

[0054] Again, refer to the group to deselect transistor M. p1,k And word line deselect transistor M p0，k For practical purposes, they form NAND-type logic circuits, which are configured to decode the address signal SECT_PX. <j>and address decoding signal SECT_LX <k>If at least one of them is equal to "0", that is, whenever the k-th word line WL is not selected, the k-th word line WL is coupled to node NV. read / write Therefore, the aforementioned voltage V is set on the k-th word line WL. high .

[0055] In fact, when the k-th word line WL is selected, it is found that for each i different from k, the i-th word line deselects the transistor M. p0,i Keeping it above the threshold ensures that the i-th word line WL remains deselected and is at voltage V. high Only the k-th word line WL is brought to voltage V. low As long as it is related to node NV read / write Decouple and couple to the ground reference voltage GND.

[0056] After reading memory cell 2 coupled to the k-th word line WL in a manner known per se, the k-th word line WL is deselected again; that is, it is brought back to voltage V. high Therefore, the address decoding signal SECT_PX <j>and SECT_NPX <j>They are set to '0' and '1' respectively, and the address decoding signal SECT_LX <k>It is set to '0' again, while the address decoding signal SECT_LX (i is different from k) remains equal to '0'. Specifically, the address decoding signal SECT_PX <j>and SECT_LX <k>The fact that it was set to '0' caused the word line select transistor M to... nk Group selection transistor M n The suppression of this process decouples the k-th word line WL from the ground reference voltage GND, and also causes the word line deselect transistor M to be deselected. p0,k and group deselect transistor M p1,k It becomes higher than the threshold, thus coupling the k-th word line WL to node NV. read / write In addition, the address decoding signal SECT_NPX <j>The fact that it is set to equal to '1' enables the thirty-two additional pull-up transistors M pu,0 -M pu,31 It becomes above the threshold; however, only the kth additional pull-up transistor M pu,k Current is effectively passed through (together with word line deselect transistors Mp0,k and group deselect transistors Mp1,k) so that the k-th word line WL can locally increase its own voltage to voltage V. high In fact, as mentioned earlier, all 31 word lines WL except for the k-th word line WL are already at voltage V. high Because the corresponding word line deselects transistor M p0,i (i is different from k) has remained above the threshold.

[0057] In fact, even assuming that high-voltage transistors are used in the shared pull-up stage 29, and in the local pull-down stage 31 and local pull-up stage 32 of the first local row decoding stage 30', this will be described below.

[0058] Due to the kth additional pull-up transistor M pu，k It is an NMOS transistor, therefore it enables the deselection of the k-th word line WL to be more efficient than that of the word line deselection transistor M. p0，k Much faster, and group deselect transistor M p1,k It is possible to have a relatively low voltage V read (As mentioned before, this is performed under conditions such as, for example, equal to 1.6V). In practice, an additional pull-up transistor M... pu，k Benefiting from the high charge carrier mobility and high gate-source voltage typical of NMOS transistors (approximately 2V in this example, although V... read (low value), and therefore can quickly cancel the selection of the k-th word line WL, so that it reaches the voltage V included in all cases. high This provides benefits in reducing static and dynamic leakage. Since a shared pull-up stage 29 is not required to manage the fast deselection of the word line WL, the word line deselection transistor M... p0,k and group deselect transistor M p1,k These can be high-voltage types and have channels of limited width because they do not need to handle high current, but are limited to being used as buffers for selecting the k-th word line WL. Furthermore, during writing, and therefore when the aforementioned voltage V... write Appears at node NV read / write When the word line is selected, transistor M is deselected. p0,k and group deselect transistor M p1,k The management of the k-th word line WL approximately reaches voltage V when deselected. write Although they have a voltage of no more than 3.6V at their own gate terminals (according to this example). This task cannot be accomplished by an additional pull-up transistor M. pu,k It will only be executed if it is driven with a significantly higher gate voltage (in this case, in the range of 6V).

[0059] Regarding the second local line decoding stage 30", it operates in the same manner as the first local line decoding stage 30', as it is identical to the first local line decoding stage 30' and receives the same signals. However, the k-th word line WL, the local pull-down stage 31 of the first local line decoding stage 30', and the k-th additional pull-up transistor M are typically considered. pu,k The contact point is located on the left side of the first piece 6' (see reference). Figure 4 The first point of the k-th word line WL (as shown in the orientation) is further coupled to the k-th word line deselect transistor M. p0,k and the k-th group deselect transistor M p1,k The second local line decoding stage 30” has a local pull-down stage 31' and a kth additional pull-up transistor M. pu,k The second point of the k-th word line WL is contacted between the first piece 6' and the second piece 6" . The aforementioned first and second points of the k-th word line WL represent the first node and the second node of the k-th word line WL, respectively, which are distributed along the latter; more specifically, apart from the first node that coincides with the end of the k-th word line WL facing the shared pull-up stage 29, the second node of the k-th word line WL contacted by the subsequent local line decoding stage (not shown) and other nodes (not shown) are arranged between corresponding pairs of adjacent pieces. In other words, with regard to the k-th word line WL, the local pull-down stage and the local pull-up stage of each local line decoding stage are coupled to the same node of the k-th word line WL, which is arranged upstream of the corresponding piece.

[0060] Shared pull-up stage 29 is shared among the tiles of tile group 16, located on one side of tile group 16, and acts as a pull-up to node NV. read / write The logic circuitry decouples / couples the selected / deselected word line WL, specifically decoupling / coupling the corresponding terminals of the word line WL. Local pull-down stages 31, 31' locally couple the selected / deselected word line to / from the ground reference voltage GND, and specifically, the coupling / decoupling occurs along the corresponding nodes of the word line WL; in other words, the local pull-down stages 31, 31' are spatially distributed along the tile group 16. Furthermore, local pull-up stages 32, 32' are spatially distributed along the tile group 16 and controlled to quickly restore the voltage V in the corresponding nodes of the word line WL. high Thus, word lines WL will not be deselected solely by the shared pull-up stage 29, which would result in a lack of delay and voltage uniformity due to the parasitic resistance and capacitance distributed along each word line WL.

[0061] The advantages of this solution are clear from the preceding description. It should be noted again that, according to this solution, the local row decoding stage is formed solely by NMOS transistors, thus offering an advantage in area reduction because it eliminates the need to provide N-type corresponding wells for forming PMOS transistors within the local row decoding stage.

[0062] Furthermore, due to only NV read / write Selective decoupling of the word line selected by the node is performed by the shared pull-up stage 29, while the local pull-up stages 32 and 32' simply restore the voltage V at the corresponding point of the previously selected word line WL. high Therefore, each local pull-up stage can include only one additional pull-up transistor M for each word line WL. pu,k This further saves area. In fact, considering, for example, the local pull-up stage 32 of the k-th word line and the first local line decoding stage 30', the latter does not require the presence of a deselect transistor M with the drive group. p1,k And word line deselect transistor M p0,k Instead of a pair of corresponding NMOS transistors driven by complementary signals, only an additional pull-up transistor M exists. p1,k That's enough.

[0063] The aforementioned advantages make the use of non-volatile memory device 1 in electronic system 130 particularly advantageous, such as Figure 5 The illustration is shown in the image.

[0064] Electronic system 130 can be used in electronic devices such as: PDAs (personal digital assistants); portable or fixed computers that may have wireless data transmission capabilities; mobile phones; digital audio players; cameras or video cameras; or other portable devices capable of processing, storing, sending and receiving information.

[0065] In detail, the electronic system 130 includes a non-volatile memory device 1 and a controller 131 (e.g., equipped with a microprocessor, DSP, or microcontroller), both of which are coupled to a bus 136, which is designed to route signals (e.g., for address selection) to the non-volatile memory device 1.

[0066] In addition, the electronic system 130 may optionally include one or more of the following coupled to the bus 136: an input / output device 132 (e.g., having a keyboard and a display) for inputting and displaying data; a wireless interface 134, such as an antenna, for transmitting and receiving data via a radio frequency wireless communication network; RAM 135; a battery 137 which can be used as a power source in the electronic system 130; and a camera and / or video camera 138.

[0067] Finally, it is clear that modifications and variations may be made to the content described and shown herein without departing from the scope of the invention as defined by the appended claims.

[0068] For example, the shared pull-up stage 29 may differ from those already described; for example, the word line deselects the transistor M. p0,k and the corresponding group to deselect transistor M p1,k Each pair of NAND circuits formed can be replaced by different circuits that perform the same function, and again formed only by PMOS transistors.

[0069] Similarly, for line decoding, different and / or additional line address decoding signals can be used relative to those already shown; furthermore, different combinations of address decoding signals can be used.

[0070] Furthermore, the first local line decoding stage 30' may not have a corresponding local pull-up stage 32, since the latter is coupled to the end of the word line WL, and the shared pull-up stage 29 is also coupled to the end of the word line WL; however, in this case, the shared pull-up stage 29 should be formed by a larger PMOS transistor in order to ensure the same deselect rate.

[0071] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art based on the description. Therefore, the appended claims are intended to cover any such modifications or embodiments.< / j> < / k> < / j> < / k> < / j> < / j> < / k> < / j> < / k> < / k> < / j> < / j> < / j> < / k> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / k>

Claims

1. A non-volatile memory device, comprising: a memory array comprising a plurality of memory portions, each memory portion comprising a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions comprising a plurality of respective memory portions arranged in rows, and a plurality of respective word lines extending through the respective memory portions, and wherein the memory cells of the memory portions in the group are coupled to the respective word lines; and a row decoder comprising a pre-decoding stage configured to perform a selection in which the row decoder selects word lines extending through a group of memory portions, and a subsequent deselection in which the row decoder deselects all the word lines extending through the group of memory portions, the row decoder further comprising, for each group of memory portions: a shared pull-up stage configured to decouple, or couple, each word line extending through the group of memory portions from, or to, a node at a first reference potential when the word line is respectively selected or deselected, so as to apply a deselection voltage to each word line when deselected; a plurality of pull-down stages distributed along the group of memory portions, each pull-down stage configured to locally couple each word line extending through the group of memory portions to a node at a second reference potential when selected, so as to locally apply a selection voltage on the word line, wherein each pull-down stage is further configured to locally decouple each word line extending through the group of memory portions from the node at the second reference potential when deselected; and a plurality of local pull-up stages distributed along the group of memory portions, each local pull-up stage comprising, for each word line extending through the group of memory portions, a corresponding local pull-up transistor of NMOS type, wherein the local pull-up transistor of each local pull-up is configured to: locally decouple the corresponding word line from the node at the first reference potential when one of the word lines extending through the group of memory portions is selected; and locally couple the corresponding word line to the node at the first reference potential when all the word lines extending through the group of memory portions are deselected, so as to locally restore the deselection voltage on the previously selected word line.

2. The non-volatile memory device of claim 1, wherein for each group of memory portions, the corresponding shared pull-up stage comprises, for each word line extending through the group of memory portions, corresponding deselection logic circuitry comprising a plurality of respective PMOS transistors coupled to the word line and to the node at the first reference potential.

3. The non-volatile memory device of claim 2, wherein each deselect logic circuit comprises a respective first PMOS transistor and a respective second PMOS transistor, each of the respective first PMOS transistor and the respective second PMOS transistor having a conductive terminal coupled to a corresponding one of the word lines and to a node at the first reference potential, and wherein each deselect logic circuit is configured to: turn on the respective first PMOS transistor when the corresponding one of the word lines is deselected; turn off the respective first PMOS transistor when the corresponding one of the word lines is selected; and turn off the respective second PMOS transistor when one of the word lines extending through the group of memory portions is selected, and otherwise turn on the respective second PMOS transistor.

4. The non-volatile memory device of claim 1, wherein for each group of memory portions, the corresponding word lines extend through the group of memory portions starting from a corresponding shared pull-up stage.

5. The non-volatile memory device of claim 4, wherein each pull-down stage is coupled to a corresponding node of each word line extending through the group of memory portions, the node of each word line coupled to the pull-down stage being arranged upstream of the corresponding memory portion, wherein each pull-down stage is configured to, when selected, couple the corresponding node of each word line to a node at the second reference potential, and when deselected, decouple the corresponding node of each word line from the node at the second reference potential.

6. The non-volatile memory device of claim 5, wherein in each local pull-up stage, each local pull-up transistor has conductive terminals coupled to a node at the first reference potential and to a node of a corresponding word line to which the corresponding pull-down stage is coupled, respectively.

7. The non-volatile memory device of claim 1, wherein each memory cell comprises a respective selector and a respective phase change element configured to provide a first resistance value or a second resistance value that can be associated with a corresponding logical data.

8. The memory device of claim 7, wherein the selector is a bipolar transistor.

9. An electronic device comprising: the memory device of claim 1; a controller; and a bus configured to electrically couple the controller and the memory device.

10. A row decoding method for a non-volatile memory device, the non-volatile memory device comprising a memory array comprising a plurality of memory portions, each memory portion comprising a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of the memory portions comprising a plurality of respective memory portions arranged in rows, and a plurality of respective word lines extending through the respective memory portions, and wherein the memory cells of the memory portions in the group are coupled to a respective word line, the method comprising: ​ selecting word lines of a group extending through the memory portion and deselecting other word lines of the group extending through the memory portion; subsequently deselecting all word lines of the group extending through the memory portion; and performing for each group of the memory portion, wherein performing comprises: decoupling or coupling, through a shared pull-up stage, a node at a first reference potential from or to each word line of the group extending through the memory portion when the word line is respectively selected or deselected, so as to apply a deselect voltage on each word line when deselected; locally coupling, through each of a plurality of pull-down stages distributed along the group of the memory portion, each word line of the group extending through the memory portion to a node at a second reference potential when the word line is selected, so as to locally apply a select voltage on the word line; locally decoupling, through each of the plurality of pull-down stages, each word line of the group extending through the memory portion from the node at the second reference potential when the word line is deselected; controlling a plurality of local pull-up stages distributed along the group of the memory portion, each local pull-up stage comprising, for each word line of the group extending through the memory portion, a corresponding local pull-up transistor of NMOS type, wherein controlling comprises: controlling the local pull-up transistor of each local pull-up stage so that, when one of the word lines of the group extending through the memory portion is selected, the local pull-up transistor locally decouples the corresponding word line from the node at the first reference potential; and controlling the local pull-up transistor of each local pull-up stage so that, when all word lines extending through the group of the memory portion are deselected, the local pull-up transistor locally couples the corresponding word line to the node at the first reference potential so as to locally restore the deselect voltage on the previously selected word line.

11. The decoding method of claim 10, wherein for each group of the memory portion, the corresponding shared pull-up stage comprises, for each word line of the group extending through the memory portion, a corresponding deselect logic circuit comprising a plurality of respective PMOS transistors, and the deselect logic circuit is coupled to the word line and to the node at the first reference potential.

12. The decoding method of claim 10, wherein for each group of memory portions, the corresponding word lines extend through the memory portions in the group starting from a corresponding shared pull-up stage, wherein each pull-down stage is coupled to a corresponding node of each word line extending through the group of memory portions, the node of each word line coupled to the pull-down stage being arranged upstream of the corresponding memory portion, wherein locally coupling each selected word line to a node at the second reference potential comprises: coupling, through the pull-down stage, the corresponding node of the selected word line to the node at the second reference potential; and wherein locally decoupling each deselected word line from the node at the second reference potential comprises decoupling, through the pull-down stage, the corresponding node of each deselected word line.

13. The decoding method of claim 12, wherein in each local pull-up stage, each local pull-up transistor has a conductive terminal coupled to the node at the first reference potential and to the node of the corresponding word line to which the corresponding pull-down stage is coupled, respectively.

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