Method of performing write operations in phase change memory, corresponding apparatus and computer program product

Abstract

Embodiments of the present disclosure relate to a method of performing write operations in a phase change memory, a corresponding device and a computer program product. A writable memory portion of the PCM is coupled to a non-volatile memory storing information indicating whether a latest write operation to the writable memory portion uses a first set of current pulses or a second set of current pulses (the second set of current pulses uses a lower current value than the first set of current pulses). Transitioning from the first group to the second group in response to a command to perform a write operation on the writable memory portion using a pulse of the second group of current pulses, and if the stored information indicates that the latest write operation uses a pulse of the first group of current pulses, applying a blanking current pulse to the cells of the writable memory portion in the reset state; a write operation is performed on the writable memory portion using the second set of current pulses, and the non-volatile memory portion is updated to indicate that the latest write operation is performed using the second set of current pulses.

Description

Cross-reference to related applications

[0001] This application claims priority to Italian Patent Application No. 102024000025794, filed on November 15, 2024, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0002] This manual relates to data storage technology.

[0003] One or more embodiments may be applied to computer storage technologies such as non-volatile memory (NVM), such as phase-change memory (PCM), such as embedded phase-change memory (ePCM) and / or non-volatile memory ePCM (ePCM NVM). Background Technology

[0004] Phase-change memory (PCM) is a computer storage technology, also known as memory technology, and is typically a non-volatile random access memory technology that can be embedded in integrated circuit (IC) semiconductor devices.

[0005] Typically, PCM operates bit-by-bit because the heat generated by the current flowing through the heated material (called the phase change material, including, for example, chalcogenide glasses, such as germanium antimony tellurium (GST)) is used to melt and quench the phase change material, making it amorphous, or to keep such the phase change material within its crystallization temperature range, thereby transforming it into a crystalline state.

[0006] Therefore, PCM memory cells can use this phase change material to store 1 bit of information because the two states of the phase change material (i.e., amorphous or crystalline) have different resistance values, which helps to distinguish one state from the other. In other words, each of the two states corresponds to a different value for a single bit.

[0007] Therefore, phase change materials can exist stably in two states: an amorphous or disordered state, characterized by high resistivity, i.e., high resistance, for example, about 0.6 MΩ, representing a low logic state, such as '0', characterized by a low current flowing through it; or a crystalline or ordered state, characterized by low resistivity, i.e., low resistance, for example, lower than that of the amorphous state, for example, about 18 kΩ, representing a high logic state, such as '1', characterized by a high current flowing through it.

[0008] PCM memory cells can switch between two states by heating the phase change material differently. That is, by applying current to the phase change material for a given time to switch to the first state, and by applying different values ​​of current to the phase change material for different times to switch to the second state.

[0009] For example, a "set" write operation for a specific cell (i.e., setting the cell to a high logic level) can be performed by applying a current (e.g., a triangular current pulse) to the phase change material of such a specific cell, which heats the corresponding phase change material to above the crystallization temperature associated with such a corresponding phase change material, but below the melting temperature associated with the same phase change material, within a given time.

[0010] For example, a “reset” write operation for a specific cell (i.e., setting the cell to a low logic level) can be performed by applying a current (e.g., a short rectangular current pulse) to the phase change material of such a specific cell, which heats the corresponding phase change material to above the melting temperature associated with such corresponding phase change material within a given time, for example, shorter than the time considered in a “set” write operation.

[0011] For example, a specific cell readout operation can be performed by testing the resistance value of the phase change material of the specific cell (e.g., by a current pulse) to detect the current phase of the phase change material, i.e., whether it is amorphous or crystalline.

[0012] It should be noted that in the following description, "set" write operation and "reset" write operation can be collectively referred to as write operation. Therefore, the write operation performed on a given cell can be a set write operation, that is, setting the given cell to a high logic level, or a reset write operation, that is, setting the given cell to a low logic level.

[0013] Single-ended PCM is a type of PCM in which a single unit corresponds to a single bit (i.e., 1 unit / bit).

[0014] The read operation in a single-ended PCM is performed using a reference current, which is provided, for example, by a reference current generator, and the sense amplifier operates as follows: at one terminal, it receives the current from the PCM cell to be read, and at the other terminal, it receives the reference current provided by the reference current generator.

[0015] U.S. Patent Application Publication No. 2009 / 0161417 A1 discloses a two-unit PCM architecture per bit (i.e., 2 units / bit), a PCM architecture in which two units contain one data bit, and one of the two units (i.e., the complementary unit) is programmed to be the complementary state of the other unit. Therefore, a differential read operation is performed by reading the bit stored in one of the two units and comparing it with the bit stored in the complementary unit to determine the bit.

[0016] Differential read operations take into account both the stored values ​​of such data in the direct form cells (i.e., high or low logic levels, respectively) and the stored values ​​of such data in the complementary form cells (i.e., low or high logic levels, respectively).

[0017] Therefore, the result of the differential readout operation is obtained using a sensing amplifier configured to receive the current of the “direct” cell that must be read, i.e., containing data in direct form, at one terminal, such as on the first side, e.g., the left side, or on the second side, e.g., the right side, and to receive the current of the corresponding complementary cell, i.e., containing data in complementary form, at another terminal, such as on the second side or the first side, respectively.

[0018] Therefore, the "direct" cell and the complementary cell are configured to be in opposite states. For example, if one of the two cells (e.g., the direct cell) is in the SET state (characterized by low resistance and high current), the complementary cell is in the RESET state (characterized by high resistance and low current), and vice versa.

[0019] Therefore, the sensing amplifier is configured to compare the current received from the direct cell with the current received from the associated complementary cell, and: if the current received from the direct cell is higher than the current received from the associated complementary cell, the sensing amplifier will be configured to read a logic level equal to 1 ("a"), i.e., a high logic level, and if the current received from the direct cell is lower than the current received from the associated complementary cell, the sensing amplifier will be configured to read a logic level equal to 1 ("zero"), i.e., a low logic level.

[0020] Therefore, bit reading operations in a two-cell PCM per bit can be more reliable than bit reading operations in a single-ended PCM, because the read window of a two-cell PCM per bit is twice as wide as that of a single-ended PCM.

[0021] The read window in a two-cell PCM per bit depends on the difference between the current flowing in the direct cell and the current flowing in the associated complementary cell, which corresponds to the difference between the current flowing in the cell set to high logic level (i.e., the current flowing in the direct or complementary cell) and the current flowing in the cell set to low logic level (i.e., the current flowing in the complementary or direct cell accordingly).

[0022] Conversely, the read window in a single-ended PCM depends on the difference between the current flowing in the cell (i.e., the current flowing in a cell set to high or low logic level) and a reference current located between the current flowing in a cell set to high logic level and the current flowing in a cell set to low logic level.

[0023] Therefore, the two-cell PCM architecture per bit improves the reliability of read operations because the read operation is based on differential reading, so no reference current is required, and the read window is doubled because of the two-cell PCM architecture per bit.

[0024] Furthermore, the two-cell PCM architecture per bit typically offers greater robustness, reliability, and thermal retention than the single-ended PCM architecture because it features information redundancy, i.e., a single bit is stored in two cells instead of a single cell, and the possibility of implementing a differential read strategy, i.e., allowing the contents of a cell to be read without using a reference current.

[0025] Figure 1 The conventional structure of a PCM array ARR is shown.

[0026] PCM arrays (ARRs) (e.g., two-cell PCM arrays per bit) may include one or more groups of cells coupled together, for example, including Figure 1 Unit C in i-1,j C i,j C i+1,j and C i+2,j These are collectively referred to as reference C.

[0027] It should be noted that Figure 1 The resistance in the circuit is not a physical component, but is caused by parasitic connections.

[0028] It should be noted that such a set or multiple sets of units C can be included in different subsets of the array, for example, in the first subset of the PCM array ARR, for example, a subset of the PCM array that includes units coupled to the first side (e.g., the left side) of the sensing amplifier; or in the second subset of the PCM array ARR, for example, a subset of the PCM array that includes units coupled to the second side (e.g., the right side) of the sensing amplifier.

[0029] It should be noted that if a direct element is included in the first subset of the PCM array ARR, then the corresponding complementary element is included in the second subset of the PCM array ARR, and vice versa.

[0030] A PCM array includes one or more groups of cells arranged as word lines WL and bit lines BL. The word lines WL are the rows of the array, and the bit lines BL are the columns of the array.

[0031] Each of the multiple cells C is coupled to the corresponding bit line BL and the corresponding word line WL, for example, via a bipolar transistor used as a selector.

[0032] Each of the multiple cells C is coupled to a different pair of lines including bit line BL and word line WL, such that the corresponding bit line BL and corresponding word line WL to which a given cell is coupled can be regarded as providing coordinates to explicitly identify such a given cell.

[0033] For example, Figure 1 The unit group C shown is included in the word line WL j In this context, each such unit C is also coupled to a corresponding bit line, for example, with... Figure 1 Bitline BL i-1 BL i BL i+1 Or BL i+2 These bit lines are coupled together and are collectively referred to as reference lines (BLs).

[0034] It should be noted that the cells C of the PCM array ARR can also be organized into tiles, which are memory sub-blocks (i.e., array sub-blocks) comprising cells arranged as bit lines BL and word lines WL. Each tile in such a tile is independently accessible and operable.

[0035] The temperature stability of the state of PCM cell C (i.e., the stability of cell C in its amorphous and crystalline states) depends on the current value used to program these cells C, specifically the current value used to perform a "set" write operation on cells programmed to a high logic level (cells in the "set" state) and a "reset" write operation on cells programmed to a low logic level (cells in the "reset" state).

[0036] To improve the temperature stability of the PCM unit at high temperatures, such as temperatures reaching up to 400°C during welding operations, the current value used to program the PCM unit under such high-temperature conditions should be higher than the current value used to program the PCM unit under lower-temperature conditions, such as the temperature conditions associated with normal operation of the PCM.

[0037] It should be noted that under these lower temperature conditions, such as those associated with normal operation of the PCM, the current used to program this PCM unit is referred to as the user pulse in the following description.

[0038] It should be noted that under the previously described high-temperature conditions, i.e., at temperatures above those associated with normal operation of the PCM, such as temperatures achievable during soldering operations, the current used to program the PCM unit is referred to as a power pulse in the following description.

[0039] It should be noted that the current values ​​included in the range related to the current of the power supply pulse are higher than the current values ​​included in the range related to the current of the user pulse.

[0040] For example, the current of a power pulse can be approximately 350 microamps (µA), while the current of a user pulse can be approximately 150 µA.

[0041] However, even if the temperature stability of the PCM cell state is improved by using a power pulse instead of a user pulse, in the case of a write operation cycle, using such a power pulse (with a current value higher than that of the user pulse) instead of the user pulse will cause the PCM cell to degrade faster.

[0042] Therefore, given the above, write operations (set write operations and / or reset write operations) can be performed by applying two types of pulses to the PCM cell: a user pulse with a current value lower than the power supply pulse, which, compared to the power supply pulse, causes reduced temperature stability and degradation of the PCM cell during write operation cycles. Thus, this user pulse can be used under temperature conditions associated with normal PCM operation so that more write operation cycles can be applied to the PCM cell; and a power supply pulse with a current value higher than the user pulse, which, compared to the user pulse, causes more stable temperature (i.e., better retention to allow cell contents to be maintained even at the previously described high temperatures (e.g., during soldering)) and more severe degradation of the PCM cell during write operation cycles.

[0043] It should be noted that by using a set user pulse or a set power pulse to keep the phase change material within its crystallization temperature range, thereby switching it to the crystallization state, the PCM unit can be set to the "set" state to store a high logic level.

[0044] Similarly, by resetting the user pulse or resetting the power pulse to melt and quench the phase change material, thereby making it amorphous, the PCM cell can be set to a "reset" state to store a low logic level.

[0045] In view of the above, the PCM according to the known solution has a first part of memory configured to be written by a power pulse, for example by soldering; and a second part of memory configured to be written by a user pulse, for example during normal operation of the PCM.

[0046] In known solutions, the first part of the memory is always rewritten via a power pulse, and the second part of the memory is always rewritten via a user pulse.

[0047] Therefore, transitions between power pulses and user pulses are not allowed, resulting in a limitation on the number of cycles that can be used to perform write operations on the first part of the memory.

[0048] Solutions that facilitate the transition between power pulses and user pulses would be beneficial in order to reduce PCM cell degradation during write operation cycles without losing or impairing retention capabilities at high temperatures (e.g., during soldering).

[0049] There is a need in the field for solutions that facilitate the transition between power pulses and user pulses to reduce the degradation of PCM cells during cycling without losing their retention capability during soldering. Summary of the Invention

[0050] One or more embodiments relate to a method for performing a write operation in a phase-change memory.

[0051] One or more embodiments relate to a corresponding memory device and a corresponding computer program product that can be loaded into at least one processing circuit (e.g., a computer) and includes a software code portion for performing the steps of the method when the product is run on at least one processing circuit.

[0052] As used herein, references to such computer program products are to be understood as equivalent to references to computer-readable media containing instructions for controlling a processing system in order to coordinate the implementation of methods according to one or more embodiments.

[0053] The solutions described herein include a method for performing write operations in a phase-change memory (PCM) device that includes a writable memory portion.

[0054] Each writable memory portion (e.g., a word of memory) is coupled to a corresponding non-volatile memory portion, for example, coupled to an additional non-volatile bit, in which information is stored indicating whether the latest write operation performed on the writable memory portion was performed via a pulse in a first set of current pulses (referred to as a power pulse in the following description) or via a pulse in a second set of current pulses (referred to as a user pulse in the following description).

[0055] It should be noted that the current value of the pulses included in the second group of current pulses (i.e., user pulses) is lower than the current value of the pulses included in the first group of current pulses (i.e., power supply pulses).

[0056] The method described herein includes: receiving a command to perform a write operation on a writable memory portion via a first set of current pulses or a pulse included in a second set of current pulses; thus, receiving a command to perform a write operation via a pulse included in the first set of current pulses or a command to perform a write operation via a pulse included in the second set of current pulses; in response to information stored in the corresponding non-volatile memory portion instructing a latest write operation to be performed on the writable memory portion via a pulse included in the first set of current pulses and in response to the received command instructing the aforementioned write operation to be performed via a pulse included in the second set of current pulses; detecting a transition from the first set of current pulses to the second set of current pulses; and in response to detecting the transition from the first set of current pulses to the second set of current pulses: applying a blanking current pulse to a cell in the writable memory portion in a “reset” state; setting information stored in the corresponding non-volatile memory portion to instruct a latest write operation to be performed on the writable memory portion via a pulse included in the second set of current pulses; and performing a write operation on the writable memory portion via a pulse included in the second set of current pulses, i.e., via a “set” current pulse and / or a “reset” current pulse included in the second set of current pulses.

[0057] Therefore, the solution described in this paper helps reduce the degradation of PCM cells during cycles, i.e., during write operation cycles, without losing or impairing their retention capabilities at high temperatures, such as during soldering. Attached Figure Description

[0058] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0059] Figure 1 It is the traditional structure of PCM arrays;

[0060] Figure 2 The behavior of the current flowing in the PCM cell after the transition from a power pulse to a user pulse is shown;

[0061] Figure 3 This is a block diagram related to a method for performing write operations based on the transition from a power pulse to a user pulse;

[0062] Figure 4 This is a block diagram related to a method for performing write operations based on the transition from user pulses to power pulses; and

[0063] Figure 5 This is a block diagram related to methods for performing write operations that take into account the transition from power pulses to user pulses (and vice versa). Detailed Implementation

[0064] Unless otherwise stated, the corresponding numbers and symbols in different figures usually refer to the corresponding parts.

[0065] These figures are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0066] The feature edges drawn in the diagram do not necessarily indicate the end of the feature range.

[0067] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more specific details, or may be obtained through other methods, components, materials, etc. In other instances, known structures, materials, or operations are not shown or described in detail, so that certain aspects of the embodiments are not obscured.

[0068] References to "embodiment" or "an embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described in connection with that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more places in this specification do not necessarily refer to the same embodiment.

[0069] Furthermore, in one or more embodiments, specific configurations, structures, or characteristics can be combined in any suitable manner.

[0070] The headings / references used herein are provided for convenience only and are not intended to limit the scope or range of protection of the embodiments.

[0071] For the sake of simplicity and ease of interpretation, throughout the description, unless the context otherwise indicates, the same reference numerals will be used to denote the same parts or elements in the corresponding figures, and the corresponding descriptions will not be repeated for each figure.

[0072] As described above, the solutions described herein aim to facilitate the transition between using power pulses and using user pulses during write operations (and vice versa) to reduce PCM cell degradation during cycles, i.e. during write operation cycles, and maintain retention capabilities at high temperatures, such as during soldering.

[0073] The first solution that allows this transition includes: when the PCM cell is expected to be exposed to high-temperature conditions, i.e., temperatures higher than those associated with normal PCM operation, such as temperatures achievable during soldering operations, performing set and / or reset write operations using power pulses; thus, for example, such power pulses can be used to store data in PCM cell C before soldering; and when the PCM cell is expected to operate under normal (standard) conditions, i.e., when the PCM cell is not exposed to such high-temperature conditions, performing set and / or reset write operations using user pulses; thus, for example, such user pulses can be used to store data in PCM cell C after soldering.

[0074] It should be noted that in the following description, the term "first group of current pulses" refers to a set of power pulses that are set or reset power pulses and have a higher value than the corresponding set or reset user pulses.

[0075] Similarly, it should be noted that in the following description, the term "second group of current pulses" refers to a set of user pulses that are set or reset user pulses and have a lower value than the corresponding set or reset power pulse.

[0076] Figure 2 This specification illustrates an embodiment of the transition from a power pulse PR, intended for storing PCM cell contents prior to soldering, to a user pulse U, intended for cycling the PCM cell after soldering (i.e., for performing subsequent write operations after soldering). SET or U RESET The current I flowing in the PCM cell C afterwards cells Behavior 10.

[0077] It should be noted that the transitions between write operations using the power pulse PR, for example, Figure 2 The first cell distribution 100 (i.e., indicating a given current I) is shown in response to a reset write operation performed via a reset power pulse PR. cells The number of units N that flow through cells (distribution of the data), and user pulse U SET or U RESET The use requires multiple set user pulses U SET and reset user pulse U RESET Loops, for example, references Figure 2 An exemplary sequence of cell distributions 102-110 is provided to obtain a distribution open window for easy reading operations.

[0078] In fact, this distribution opening window is defined as the current difference between the lowest current flowing in the cells of the cell distribution acquired in response to a set write operation (e.g., the lowest current flowing out of the cells in set cell distributions 102, 106, or 110) and the highest current flowing in the cells of the cell distribution acquired in response to a reset write operation (e.g., the highest current flowing out of the cells in reset cell distributions 100, 104, or 108).

[0079] Therefore, a wider distribution window makes read operations less likely to fail because the current flowing in the cell is higher in the "set" state and further away from the current flowing in the cell in the "reset" state.

[0080] Due to the cell's "power memory effect," a request is made for multiple set user pulses U used to obtain the desired distributed open window. SET and reset user pulse U RESET The loop causes PCM cells previously written via a reset write operation using the reset power pulse PR to become unusable by using the set user pulse U. SET The set write operation moves through the states included in the desired set cell distribution because of this set user pulse U. SET The current value is lower than the reset power pulse PR used to reset the write operation.

[0081] For example, Figure 2 The following unit distribution sequence is shown:

[0082] The first distribution 100 of the cell is associated with the cell set to a "reset" state by a first reset write operation performed via a reset power pulse PR. This first distribution 100 indicates the current I given after such a first reset write operation. cells The unit N that flows through cells The number.

[0083] The second distribution 102 of this unit is connected via the first set user pulse U SET The second distribution 103, associated with the cell set to the "set" state by the first set write operation, indicates that after this first set write operation, i.e., after the first write operation cycle performed via the user pulse, a given current I... cells The unit N that flows through cells The number.

[0084] The third distribution 104 of this unit is connected via the first reset user pulse U RESETThe cell set to "reset" state due to the second reset write operation is associated with this third distribution 104, indicating that after this second reset write operation, i.e., after the second write operation cycle performed via the user pulse, the given current I... cells The unit N that flows through cells The number.

[0085] The fourth distribution 106 of this unit is connected via the second set user pulse U SET The cell set to the "set" state by the second set write operation is associated with this fourth distribution 206, which indicates that after this second set write operation, i.e., after the third write operation cycle performed via the user pulse, a given current I... cells The unit N that flows through cells The number.

[0086] The fifth distribution 108 of this unit is connected via the second reset user pulse U RESET The cell set to "reset" state due to the third reset write operation is associated with this fifth distribution 106, which indicates that after this third reset write operation, i.e., after the fourth write operation cycle performed via the user pulse, the given current I... cells The unit N that flows through cells The number.

[0087] The sixth distribution 110 of this unit is connected via the third set user pulse U SET The cell set to the "set" state by the third set write operation is associated with this sixth distribution 100, which indicates that after this third set write operation, i.e., after the fifth write operation cycle performed via the user pulse, a given current I... cells The unit N that flows through cells The number.

[0088] It should be noted that Figure 2 The number of iterations considered is just an example; therefore, more iterations may be needed to obtain the desired distribution opening window.

[0089] It should be noted that such a cycle is expensive in terms of both time and power consumption; therefore, solutions that avoid such cycles can be advantageous.

[0090] To facilitate the transition between using power pulses and user pulses during write operations without performing a user pulse U set operation. SET and reset user pulse U RESETThe solution described in this paper uses a loop to obtain the desired distribution open window and associates additional non-volatile bits (or more than one bit) with each memory portion, for example, with each word of memory that can be written (i.e., with the writable portion of the memory).

[0091] For example, each memory address may include an additional non-volatile bit for addressing the corresponding memory portion that can be written to.

[0092] It should be noted that in the following description, the term "writable memory portion" refers to a portion of memory that can be written to in response to a write command, such as a word in memory.

[0093] Similarly, it should be noted that in the following description, the term "non-volatile memory portion" refers to the additional non-volatile bits associated with the corresponding writable memory portion.

[0094] For a given portion of a writable memory (e.g., addressed via a corresponding memory address that includes such an additional non-volatile bit), the additional non-volatile bit indicates the type of the latest pulse used to program (i.e., write) the contents of that memory portion, namely a power pulse or a user pulse.

[0095] For example, if a portion of the memory (such as a word of the memory) has been written via a power pulse (e.g., in response to a power write command instructing a write operation to be performed using a power pulse), an additional non-volatile bit can be set to a high logic level.

[0096] Otherwise, if this portion of the memory is written via a user pulse (e.g., in response to a user write command instructing a write operation to be performed using a user pulse), the additional non-volatile bit can be set to a low logic level.

[0097] The PCM array ARR can be organized so that, for example, a set of data bits (i.e., a 128-bit word) is associated with each memory address. Therefore, the additional non-volatile bits described earlier can also be included in the set of data bits associated with the corresponding memory address.

[0098] Therefore, the solution described herein refers to a method in which each writable memory portion (e.g., each writable word of memory) can be addressed via a corresponding memory address, and in which non-volatile memory portions (i.e., (a plurality of) additional non-volatile bits) can be included in such corresponding memory address; or in the form of a set of bits (preferably, words) coupled to such corresponding memory address.

[0099] Therefore, the solution described in this paper can identify whether there is a transition from a power pulse to a user pulse, or vice versa, based on the state of the additional nonvolatile bits and the type of write operation to be performed (e.g., based on whether the write command to be performed is a power write command or a user write command).

[0100] If a transition from a power pulse to a user pulse is detected, that is, if the type of the latest pulse used to program that memory portion is a power pulse but the write command is a user write command, the solution described herein can be configured to perform a restore or blanking sequence step and a power-to-user write step.

[0101] If a transition from a user pulse to a power pulse is detected, that is, if the additional non-volatile bits associated with a portion of memory to be written to via a write command indicate that the latest pulse used to program that portion of memory is a user pulse, but the write command is a power write command, then the solution described herein can be configured to perform a user-to-power write step.

[0102] Figure 3 Block diagram 20 is shown in relation to a method for performing a write operation based on the transition from a power pulse to a user pulse.

[0103] exist Figure 3 In the first write step 200, a portion of the memory, such as a word, is written via a power write command that instructs the use of power pulses to perform the write operation.

[0104] Therefore, in this first write step 200, the additional non-volatile bit associated with the memory portion is set to indicate that the type of the latest pulse is a power pulse, for example, by assuming a high logic level (set state).

[0105] In the second write step 202, a user write command is received, which instructs the user to perform a write operation on the memory portion using a user pulse.

[0106] Therefore, in this second write step 202, a transition from a power pulse to a user pulse is detected.

[0107] therefore, Figure 3 Block diagram 20 continues with recovery or blanking sequence step 204, wherein a recovery blanking pulse is applied to the cells: these cells are set to a "reset" state due to the write operation performed in the first write step 200 according to the power write command, and these cells are included in the portion of memory to be written according to the user write command received in the second write step 202.

[0108] This recovery or blanking sequence step 204 is used to utilize the set user pulse U SET Perform a set write operation to mitigate (e.g., by eliminating) the cell "power memory effect" to facilitate the movement of PCM cells previously written via a reset write operation using the reset power pulse PR, even when the set user pulse U is in a state included in the desired set cell distribution (i.e., the set cell distribution associated with the desired distribution open window). SET The current value is lower than the reset power pulse PR used for the previous reset write operation.

[0109] Therefore, the problems previously described related to obtaining the desired distribution of the opening window to facilitate read operations are also alleviated.

[0110] Note that this recovery blanking pulse can be a set power supply pulse. Alternatively, this recovery blanking pulse can have a maximum value or shape that differs from the maximum value and / or shape of the set power supply pulse. In this case, the maximum value and / or shape of the recovery blanking pulse can be selected based on the technique used to implement the PCM memory, provided that this recovery blanking pulse can mitigate (e.g., by erasing) the effects of the previously described "power memory effect" on those cells that are in a reset state after a write operation performed using a reset power supply pulse.

[0111] Then, in the power-to-user write step 206, a write operation is performed on the portion of the memory to be written according to the user write command received in the second write step 202, so that the corresponding data is stored by applying user pulses to the cells included in the memory portion.

[0112] Furthermore, in the power-to-user write step 206, the additional non-volatile bit associated with the memory portion is set to indicate that the type of the latest pulse used for the write operation is a user pulse, for example, by assuming a low logic level (reset state).

[0113] Therefore, the solution described herein relates to a method 20 for performing a write operation in a phase-change memory (PCM) device, the PCM device including a writable memory portion, i.e., a memory portion that can be written in response to a write command, such as a writable word of the memory.

[0114] Each writable memory portion (e.g., each word of memory) is coupled to a corresponding non-volatile memory portion, for example, coupled to additional non-volatile bits or multiple additional non-volatile bits, in which information is stored indicating whether the latest write operation performed on the writable memory portion was performed via pulses included in a first set of current pulses (i.e., power pulses) or via pulses included in a second set of current pulses (i.e., user pulses).

[0115] It should be noted that the current values ​​of the pulses included in the second group of current pulses (including the previously described user pulses) are lower than the current values ​​of the pulses included in the first group of current pulses (including the previously described power pulses).

[0116] For example, this method 20 includes, in the previously described second write step 202, receiving a command to perform a write operation on a writable memory portion via a first set of current pulses (power pulses) or pulses included in a second set of current pulses; thus, receiving a power write command instructing a write operation via a power pulse or a user write command instructing a write operation via a user pulse. In response to: information stored in the corresponding non-volatile memory portion (e.g., in the previously described second write step 202) again instructing a latest write operation to be performed on the writable memory portion via pulses included in the first set of current pulses (i.e., via power pulses); and the received command instructing the aforementioned write operation to be performed via pulses included in the second set of current pulses, i.e., by determining that the received command is a user write command instructing a write operation to be performed via user pulses included in the second set of current pulses, for example, in the previously described second write step 202, detecting again the transition from the first set of current pulses (i.e., performing a write operation on the considered writable memory portion using power pulses) to the second set of current pulses (i.e., performing a write operation on the considered writable memory portion using user pulses). In response to the detection of a transition from a first set of current pulses including such power pulses to a second set of current pulses including such user pulses: for example, in the previously described recovery or blanking sequence step 204, a blanking current pulse (e.g., the previously described recovery blanking pulse used in such recovery or blanking sequence step 204) is applied to the cell of the writable memory portion in the "reset" state, i.e., a current pulse capable of mitigating (e.g., eliminating) the effects of the previously described cell "power memory effect"; for example, in the previously described power-to-user write step 206, information stored in the corresponding non-volatile memory portion is set to indicate the latest write operation performed on the writable memory portion via pulses included in the second set of current pulses (i.e., via user pulses); and for example, in the previously described power-to-user write step 206, a write operation is performed again on the writable memory portion via pulses included in the second set of current pulses, i.e. via user pulses.

[0117] It should be noted that such a given current pulse (e.g., the recovery or blanking pulse of the recovery or blanking sequence step 204 described earlier) can be included in the first set of current pulses, and thus is a set of power supply pulses.

[0118] Alternatively, such a given current pulse may not be included in this first set of current pulses, and therefore its maximum value and / or shape may differ from the maximum value and / or shape of the set power pulse included in the first set of current pulses.

[0119] In this case, the maximum value and / or shape of a given current pulse can be selected based on the technique used to implement the PCM memory, provided that such a given current pulse can mitigate (e.g., eliminate) the effects of the previously described "power memory effect" in those cells that are in a reset state after a write operation is performed using a reset power pulse.

[0120] Figure 4 A block diagram 30 is shown related to a method for performing a write operation based on the transition from a user pulse to a power pulse.

[0121] exist Figure 4 In the initial write step 300, a portion of the memory, such as a word, is written via a user write command that instructs the write operation to be performed using a user pulse.

[0122] Therefore, in this initial write step 300, the additional non-volatile bit associated with the memory portion is set to indicate that the type of the latest pulse is a user pulse, for example, by assuming a low logic level (reset state).

[0123] In a separate write step 302, a power write command is received, which instructs the memory portion to be written using a power pulse.

[0124] Therefore, in this additional write step 302, a transition from a user pulse to a power pulse is detected.

[0125] Therefore, in the user-to-power write step 304, a write operation is performed on the portion of the memory to be written according to the power write command received in the additional write step 302, and thus, the corresponding data is stored by applying power pulses to the cells included in the memory portion.

[0126] It should be noted that even if these cells have already stored the expected data, power pulses will be applied to the cells of the memory section to be written. Therefore, even if the expected state has been written via user pulses, every cell included in the memory section to be written (not just the cells whose state has been changed) will be rewritten using power pulses.

[0127] In fact, by using a higher current from the power supply pulse instead of a lower current from the user pulse to write the contents of the cell, the retention of the contents in each cell of this memory section can be improved.

[0128] Furthermore, in the user-to-power write step 304, an additional non-volatile bit associated with the memory portion is set to indicate that the type of the latest pulse used to perform a write operation on the considered portion of the memory is a power pulse, for example, by assuming a high logic level (set state).

[0129] Therefore, method 30 of the solution described herein may include receiving a command to perform a write operation (power-on write operation or user write operation) on a writable memory portion (e.g., a word of memory) associated with a corresponding non-volatile memory portion (e.g., one or more additional non-volatile bits). In response to: information stored in the corresponding non-volatile memory portion (e.g., in a previously described additional write step 302) indicating a latest write operation to be performed on the writable memory portion via pulses included in a second set of current pulses (i.e., via user pulses), and the received command indicating to perform the aforementioned write operation via pulses included in a first set of current pulses, i.e., by determining that the received command is a power-on write command indicating to perform a write operation via power pulses included in the first set of current pulses, for example, by again detecting the transition from the second set of current pulses (i.e., performing a write operation on the writable memory portion under consideration using user pulses) to the first set of current pulses (i.e., performing a write operation on the writable memory portion under consideration using power pulses) in the previously described additional write step 302. In response to the detection of a transition from a second set of current pulses including such user pulses to a first set of current pulses including such power pulses: for example, in the previously described user-to-power write step 304, information stored in the corresponding non-volatile memory portion is set to indicate the latest write operation performed on the writable memory portion via pulses included in the first set of current pulses (i.e., via power pulses); and, for example, in the previously described user-to-power write step 304, the write operation is performed on the writable memory portion via pulses included in the first set of current pulses (i.e., via power pulses), thereby rewriting all the cells to be written according to the received command to improve retention by applying the aforementioned pulses to all cells of the writable memory portion, regardless of whether their state is "set" or "reset".

[0130] Figure 5 A block diagram 40 is shown related to a method for performing a write operation that takes into account the transition from a power pulse to a user pulse (and vice versa).

[0131] Figure 5 Block diagram 40 can begin with write command block 400, which receives write commands, namely power write commands or user write commands.

[0132] In response to the receipt of a write command, block diagram 40 may continue to a first check block 402, which may be configured to verify whether the received write command is a power write command.

[0133] If the received write command is a power write command, then block diagram 40 can be followed as follows: Figure 5 The branch indicated by Y1 in the attached diagram continues to the first read bit block 404.

[0134] Otherwise, if the received write command is a user write command, then block diagram 40 can be executed according to... Figure 5 The branch indicated by the reference numeral N1 in the attached figure continues to the second read bit block 414.

[0135] In the first read bit block 404, additional non-volatile bits associated with a portion of the memory can be read, such as a word of memory to be written according to a received write command.

[0136] The second check block 406 can be configured to verify whether the read value of the additional non-volatile bit indicates that the type of the latest pulse applied to the memory portion is a power pulse.

[0137] For example, this second check block 406 can be configured to verify whether the value stored in the additional nonvolatile bits corresponds to a high logic level (set state).

[0138] If the read value of the additional non-volatile bit indicates that the type of the latest pulse applied to the memory portion to be written is a power pulse (set state), then block diagram 40 can be followed as follows: Figure 5 The branch indicated by Y2 in the attached diagram continues to the first write block 408.

[0139] Otherwise, if the read value of the additional non-volatile bits indicates that the type of the latest pulse applied to the memory portion to be written is a user pulse (reset state), then block diagram 40 can be executed as follows: Figure 5 The branch indicated by N2 in the attached diagram continues to the user-to-power write block 412.

[0140] In the first write block 408, a standard write operation can be performed using power pulses according to the received write command.

[0141] In fact, since the previous write operation was performed using a power pulse with an additional non-volatile bit indication, there will be no problem when performing another write operation using a power pulse.

[0142] Therefore, in this first write block 408, the data stored in the cells included in the memory portion to be written, i.e., its state, can be verified, and power pulses can be sent only to those cells whose state must be changed according to the received write command.

[0143] It should be noted that in this first write block 408, non-volatile bits are appended (using...) Figure 5 Middle reference power bits PB Val The value of (indicated) is not modified; therefore, this additional non-volatile bit PB... Val This indicates that the type of the latest pulse applied to this memory section is a power pulse.

[0144] For example, the additional non-volatile bits PB provided by the first write block 408 as output Val The value can be a high logic level.

[0145] Then, block diagram 40 can continue to the ending block 410.

[0146] Therefore, in the user-to-power write block 412, the write operation as previously described in the user-to-power write step 304 can be performed by applying power pulses to the cells included in the portion of the memory to be written, according to the received write command.

[0147] Similarly, even if these cells have already stored the expected data, power pulses will be applied to the cells of the memory section to be written to. Therefore, even if the cells have already been written to the expected state via user pulses, each cell in the memory section to be written to (not just the cells that change their state) will be rewritten using power pulses.

[0148] In this way, by using a higher current from the power supply pulse instead of a lower current from the user pulse to write content, the retention of content in each cell included in this memory section can be improved.

[0149] Furthermore, in this user-to-power write block 412, the additional non-volatile bits PB associated with this memory portion Val It has been modified to indicate that the type of the latest pulse applied to this memory section is a power pulse.

[0150] For example, the additional non-volatile bits PB written from the user to the power supply to the output of block 412. Val The value can be a high logic level (set state).

[0151] It should be noted that for the additional non-volatile bits PB Val This modification of the value can be performed via a power pulse to improve its retention.

[0152] Then, block diagram 40 can continue to the ending block 410.

[0153] In the second read bit block 414, additional non-volatile bits associated with a portion of the memory can be read, such as a word of memory to be written according to a received write command.

[0154] The third check block 416 can be configured to verify whether the read value of the additional non-volatile bit indicates that the type of the latest pulse applied to the memory portion is a power pulse.

[0155] For example, this third check block 416 can be configured to verify whether the value stored in the additional nonvolatile bits corresponds to a high logic level (set state).

[0156] If the read value of the additional non-volatile bit indicates that the type of the latest pulse applied to the memory portion to be written is a power pulse (set state), then block diagram 40 can be followed as follows: Figure 5 The branch indicated by the reference numeral Y3 in the attached figure continues to the recovery or blanking sequence block 418.

[0157] Otherwise, if the read value of the additional non-volatile bits indicates that the type of the latest pulse applied to the memory portion to be written is a user pulse (reset state), then block diagram 40 can be executed as follows: Figure 5 The branch indicated by the reference numeral N3 in the attached diagram continues to the second write block 424.

[0158] The recovery or blanking sequence block 418 can be configured to apply the previously described recovery and blanking pulses to cells that are in a "reset" state due to a previous write operation performed using a power pulse and are included in the memory portion to be written according to the received write command.

[0159] In this way, as previously described, it is possible to use the set user pulse U SET Perform a set write operation to mitigate (e.g., by eliminating) the cell "power memory effect" to facilitate the movement of PCM cells previously written via a reset write operation using the reset power pulse PR, even when the set user pulse U is in a state included in the desired set cell distribution (i.e., the set cell distribution associated with the desired distribution open window). SET The current value is lower than the reset power pulse PR used for the previous reset write operation.

[0160] Therefore, the problems previously described related to obtaining the desired distribution of the opening window to facilitate read operations are also alleviated.

[0161] Therefore, block diagram 40 can continue to clear bit block 420, where additional non-volatile bits PB associated with the memory portion to be written (reset state) can be modified. Val This indicates that the type of the latest pulse applied to this memory portion is a user pulse.

[0162] For example, the additional non-volatile bits PB can be modified. Val The value is set to a low logic level (reset state).

[0163] Furthermore, it should be noted that for the additional non-volatile bits PB Val The value can be modified via a power pulse to improve its retention.

[0164] Then, block diagram 40 can continue to power-to-user write block 422, wherein a write operation as previously described in power-to-user write step 206 is performed by applying user pulses to cells included in the memory portion to be written, based on the received write command.

[0165] Due to the addition of nonvolatile bits PB Val The value of PB in the power-to-user write block 422 can remain unchanged (because it has already been modified in the clear bit block 420), therefore the additional non-volatile bit PB output by this power-to-user write block 422... Val The value can be, for example, a low logic level (reset state).

[0166] Then, block diagram 40 can continue to the ending block 410.

[0167] In the second write block 424, a standard write operation can be performed using a user pulse according to the received write command.

[0168] In fact, since the previous write operation was performed using user pulses, as indicated by the additional non-volatile bits, there will be no problem when performing another write operation using user pulses.

[0169] Therefore, in this second write block 424, the data stored in the cells included in the memory portion to be written, i.e., its state, can be verified, and user pulses can be sent only to those cells whose state must be changed according to the received write command.

[0170] It should be noted that in this second write block 424, the non-volatile bit PB is added. Val The value of PB is not modified; therefore, this additional non-volatile bit PB Val This indicates that the type of the latest pulse applied to this memory section is a user pulse (reset state).

[0171] For example, the additional non-volatile bits PB provided by the second write block 424 as output Val The value can be a low logic level (reset state).

[0172] Then, block diagram 40 can continue to the ending block 410.

[0173] Therefore, the solution described herein can refer to a method, for example, according to the method of block diagram 40 above, which includes performing the following operations on a writable memory portion (such as a word) that must be written via a write command and associated with a corresponding non-volatile memory portion (e.g., with a corresponding additional non-volatile bit):

[0174] In response to information stored in the corresponding non-volatile memory portion: for example, as a result of the operation performed in the first check block 402, if the received write command is a power write command, then the latest write operation performed on the writable memory portion is performed via pulses included in the first set of current pulses (i.e., via power pulses), and the received write command instructs to perform such a write operation via pulses included in the first set of current pulses; that is, if the write command is a power write command instructing to perform a write operation via power pulses included in the first set of current pulses, then according to... Figure 5 The branches indicated by reference numerals Y1 and Y2 in the attached diagram maintain a first set of current pulses, including power pulses, to perform a write operation; and

[0175] If a first set of current pulses, including power pulses, is maintained to perform a write operation: for example, as described in the first write block 408, information stored in the corresponding non-volatile memory portion is maintained to indicate the latest write operation performed on the writable memory portion via pulses included in the first set of current pulses (i.e., via power pulses); and, for example, again as described in the first write block 408, such pulses are applied (preferably only to) the cell whose state must be changed via pulses included in the first set of current pulses (i.e., via power pulses) to perform a write operation on the writable memory portion.

[0176] Similarly, the method according to the solution described herein (e.g., the method according to block diagram 40 above) may include: for a writable memory portion (e.g., a word) that must be written via a write command and associated with a corresponding non-volatile memory portion (e.g., with a corresponding additional non-volatile bit), the following operations are performed:

[0177] In response to information stored in the corresponding non-volatile memory portion: for example, as a result of the operation performed in the first check block 402, if the received write command is a power-on write command, then the latest write operation performed on the writable memory portion is performed via pulses included in the second set of current pulses (i.e., via user pulses), and the received write command instructs to perform such a write operation via pulses included in the second set of current pulses; that is, if the write command is a user write command instructing to perform a write operation via user pulses included in the second set of current pulses, then according to... Figure 5 The branches indicated by reference numerals N1 and N3 in the attached figures maintain a second set of current pulses, including the user pulse, to perform the write operation; and

[0178] If a second set of current pulses, including a user pulse, is maintained to perform a write operation: for example, as described in the second write block 424, information stored in the corresponding non-volatile memory portion is maintained to indicate the latest write operation performed on the writable memory portion via pulses included in the second set of current pulses (i.e., via user pulses); and, for example, again as described in the second write block 424, such pulses are applied (preferably only to) the cell whose state must be changed via pulses included in the second set of current pulses (i.e., via user pulses) to perform a write operation on the writable memory portion.

[0179] It should be noted that in the solution according to this specification, the operation of setting information stored in the corresponding non-volatile memory portion (i.e., (a plurality of) additional non-volatile bits) can be performed via pulses included in the first set of current pulses (i.e., via power pulses), for example in the power-to-user write step 206, user-to-power write step 304 and / or clear bit block 420 described above, to improve retention.

[0180] It should be noted that the solutions described in this paper can be applied to different types of phase change memories, such as: single-ended NVM PCM, i.e., non-volatile phase change memory with a 1 cell / bit architecture; two-cell NVM PCM per bit, i.e., non-volatile phase change memory with a 2 cell / bit architecture; and multi-level NVM PCM, i.e., non-volatile phase change memory with a multi-level architecture, and thus configured to store multiple bits per cell.

[0181] It should be noted that even if the additional non-volatile bits are described as being associated with each memory address of a given portion of the addressing memory (e.g., associated with each memory-addressed address of a word in the addressing memory), different granularities can be considered.

[0182] For example, the granularity of a memory portion associated with additional nonvolatile bits can include: a single word of memory; multiple words of memory, such as a page consisting of 16 words; or a portion of a word, such as a single byte of a word.

[0183] Note that even if the modification of the value of the additional non-volatile bit is described as being performed via a power pulse to improve its retention, the value of this additional non-volatile bit can also be modified via a user pulse.

[0184] It should be noted that redundancy can also be used to map additional non-volatile bits. Therefore, the effect of additional non-volatile bits can be achieved through multiple additional non-volatile bits, such as 3 bits, and the state indicated by the result is determined based on the value of most of the bits.

[0185] Therefore, in the solution described herein, the non-volatile memory portion (e.g., one or more additional non-volatile bits associated with the writable memory portion (e.g., a word of memory) can be configured to preferably store a first logic level or a second logic level in either a high logic level or a low logic level via a plurality of redundant bits in order to be able to detect and correct errors in the information stored therein, such first logic level being different from such second logic level.

[0186] For example, the first logic level can be a high logic level, and the second logic level can be a low logic level. Similarly, the first logic level can be a low logic level, and the second logic level can be a high logic level.

[0187] Therefore, according to the above description, if the logic level corresponds to the first logic level, then the logic level indicates the latest write operation performed on the writable memory portion via pulses included in the first set of current pulses (i.e., via power supply pulses).

[0188] The difference is that if the logic level corresponds to the second logic level, then the logic level indicates the latest write operation performed on the writable memory portion via pulses included in the second set of current pulses (i.e., via user pulses).

[0189] In the solutions described herein, such a writable memory portion (i.e., a memory portion that can be written to in response to power or a user write command) can be: a single word of a PCM device; multiple words of a PCM device, such as a page of a PCM device; or a portion of a word of a PCM device, such as a single byte of a word.

[0190] Furthermore, the solutions described in this paper can involve PCM devices with the following structures: single-ended architecture, i.e., one unit per bit; two-unit architecture, i.e., two units per bit; or multi-level architecture, i.e., an architecture configured to store multiple bits for each unit.

[0191] The solutions described herein facilitate methods for performing write operations in phase-change memory (PCM) devices that include writable memory portions, such as multiple words of memory.

[0192] Each writable memory portion (e.g., a word of memory) is coupled to a corresponding non-volatile memory portion, for example, with additional non-volatile bits stored in the memory portion indicating whether the latest write operation performed on the writable memory portion was performed via a pulse in a first set of current pulses (referred to as a power pulse in the following description) or via a pulse in a second set of current pulses (referred to as a user pulse in the following description).

[0193] It should be noted that the current value of the pulses included in the second group of current pulses (i.e., user pulses) is lower than the current value of the pulses included in the first group of current pulses (i.e., power supply pulses).

[0194] The method described in this article includes the following steps:

[0195] A command to perform a write operation on a writable memory portion (e.g., a word of memory) is received via a pulse included in a first set of current pulses or a second set of current pulses. Therefore, a command to perform a write operation is received via a pulse included in the first set of current pulses (i.e., a power write command indicating that a write operation is performed via a power pulse) or via a pulse included in the second set of current pulses (i.e., a user write command indicating that a write operation is performed via a user pulse).

[0196] In response to information stored in the corresponding non-volatile memory portion instructing a latest write operation to be performed on the writable memory portion via pulses included in the first set of current pulses (i.e., via power pulses), and in response to a received command instructing the aforementioned write operation to be performed via pulses included in the second set of current pulses (i.e., via user pulses), a transition from the first set of current pulses (i.e., from power pulses) to the second set of current pulses (i.e., to user pulses) is detected; and in response to detecting the transition from the first set of current pulses to the second set of current pulses: a blanking current pulse is applied to the cell of the writable memory portion in the "reset" state, i.e., a current pulse capable of mitigating (e.g., eliminating) the effect of the previously described cell "power memory effect"; information stored in the corresponding non-volatile memory portion is set to instruct a latest write operation to be performed on the writable memory portion via pulses included in the second set of current pulses (i.e., via user pulses); and a write operation is performed on the writable memory portion via pulses included in the second set of current pulses, i.e. via "set" user current pulses and / or "reset" user current signals included in the second set of current pulses.

[0197] The solution described in this paper may include the following steps:

[0198] In response to information stored in the corresponding non-volatile memory portion instructing a latest write operation to be performed on the writable memory portion via pulses included in the second set of current pulses (i.e., via user pulses), and in response to a received command instructing the aforementioned write operation to be performed via pulses included in the first set of current pulses (i.e., via power pulses), a transition from the second set of current pulses (i.e., from user pulses) to the first set of current pulses (i.e., to power pulses) is detected; if a transition from the second set of current pulses to the first set of current pulses is detected, information stored in the corresponding non-volatile memory portion is set to instruct a latest write operation to be performed on the writable memory portion via pulses included in the first set of current pulses (i.e., via power pulses); and the aforementioned pulses are applied to all cells of the writable memory portion via pulses included in the first set of current pulses (i.e., via power pulses), regardless of whether their state is set or reset, to perform a write operation on the writable memory portion.

[0199] The solutions described in this paper also relate to a phase-change memory (PCM) device that includes a writable memory portion, such as multiple words.

[0200] Each writable memory portion (e.g., a word of memory) is coupled to a corresponding non-volatile memory portion, for example, (multiple) additional non-volatile bits, in which information is stored indicating whether the latest write operation performed on the writable memory portion was performed via pulses included in a first set of current pulses (i.e., via power supply pulses) or via pulses included in a second set of current pulses (i.e., via user pulses), wherein the current value of the pulses included in the second set of current pulses is lower than the current value of the pulses included in the first set of current pulses.

[0201] The PCM device is configured to implement method 20, 30 or 40 as previously described.

[0202] Furthermore, the solution described herein also relates to a computer program product that can be loaded into the control unit of a phase-change memory (PCM) device, the PCM device including a writable memory portion, such as multiple words of memory.

[0203] Each writable memory portion (e.g., each word) is coupled to a corresponding non-volatile memory portion, for example, (multiple) additional non-volatile bits, which stores information indicating whether the latest write operation performed on the writable memory portion was performed via pulses included in a first set of current pulses (i.e., via power supply pulses) or via pulses included in a second set of current pulses (i.e., via user pulses), wherein the current value of the pulses included in the second set of current pulses is lower than the current value of the pulses included in the first set of current pulses.

[0204] The computer program product includes a portion of software code configured to cause the PCM device to perform method 20, 30, or 40 according to this specification in response to the computer program product running in the control unit of the PCM device.

[0205] Therefore, the solution described in this paper helps to reduce the degradation of PCM cells during write operation cycles (which exists when only power pulses are considered) without losing or impairing their retention capability at high temperatures (e.g., during soldering) (if only user pulses are considered).

[0206] Without prejudice to the fundamental principles, details and embodiments may vary, even significantly, relative to what has been described by way of example only, without departing from the scope of the embodiments.

[0207] The claims are an integral part of the technical teachings provided with respect to the embodiments.

[0208] The scope of protection is determined by the appended claims.

Claims

1. A method for performing a write operation in a phase-change memory (PCM) device, the PCM device including a writable memory portion, each writable memory portion coupled to a corresponding non-volatile memory portion, the non-volatile memory portion being configured to store information indicating whether a recent write operation performed on the writable memory portion was performed using pulses including a first set of current pulses or a second set of current pulses, wherein pulses in the second set of current pulses have a lower current value than pulses included in the first set of current pulses, the method comprising: Receive a command to perform a write operation on a portion of the writable memory using pulses from either the first set of current pulses or the second set of current pulses; The information stored in the corresponding non-volatile memory portion indicates that the latest write operation performed on the writable memory portion used a pulse from the first set of current pulses, and the received command indicates that the write operation will use a pulse from the second set of current pulses, then: The transition from the first group of current pulses to the second group of current pulses is detected from the information. as well as In response to the first detection: A blanking current pulse is applied to the cells of the writable memory portion that are in a reset state; The write operation is performed on the writable memory portion using the pulses included in the second set of current pulses; as well as The information stored in the corresponding non-volatile memory portion is configured to indicate that the latest write operation was performed using a pulse from the second set of current pulses.

2. The method of claim 1, further comprising: wherein the information stored in the respective non-volatile memory portion indicates that the latest write operation performed on the writable memory portion used pulses from the second set of current pulses; and wherein the received command indicates that the write operation will use pulses from the first set of current pulses. The second detection is performed from the information to transition from the second group of current pulses to the first group of current pulses; as well as In response to the second detection: The write operation is performed on the writable memory portion using pulses from the first set of current pulses applied to all the cells of the writable memory portion, regardless of whether the cell is in a set state or a reset state. as well as The information stored in the corresponding non-volatile memory portion is configured to indicate that the latest write operation was performed using a pulse from the first set of current pulses.

3. The method of claim 2, wherein each writable memory portion is addressable via a corresponding memory address, and wherein the non-volatile memory portion is included in the corresponding memory address.

4. The method of claim 2, wherein each writable memory portion is addressable via a corresponding memory address, and wherein the non-volatile memory portion is included in a set of bits coupled to the corresponding memory address.

5. The method of claim 1, wherein the corresponding non-volatile memory portion uses one or more bits to store a first logic level or a second logic level, the first logic level indicating that the most recent write operation performed on the writable memory portion used a pulse from the first set of current pulses, and the second logic level indicating that the most recent write operation performed on the writable memory portion used a pulse from the second set of current pulses.

6. The method of claim 1, further comprising: wherein the information stored in the respective non-volatile memory portion indicates that the latest write operation performed on the writable memory portion used a pulse from the first set of current pulses; and wherein the received command indicates that the write operation will use a pulse from the first set of current pulses. Maintain the first set of current pulses; as well as The first set of current pulses is maintained: The write operation is performed on the writable memory portion by applying the pulse to the cell whose state must be changed, using the pulse from the first set of current pulses. as well as The information stored in the corresponding non-volatile memory portion is maintained to indicate that the latest write operation performed on the writable memory portion used pulses included in the first set of current pulses.

7. The method of claim 1, further comprising: wherein the information stored in the respective non-volatile memory portion indicates that the latest write operation performed on the writable memory portion used a pulse from the second set of current pulses; and wherein the received command indicates that the write operation will use a pulse from the second set of current pulses. Maintain the second set of current pulses; as well as The second set of current pulses is maintained: The write operation is performed on the writable memory portion by applying the pulse to the cell whose state must be changed, using the pulse from the second set of current pulses. as well as The information stored in the corresponding non-volatile memory portion is maintained to indicate that the latest write operation performed on the writable memory portion used a pulse from the second set of current pulses.

8. The method of claim 1, wherein setting the information includes using a pulse from the first set of current pulses to write to the corresponding portion of the non-volatile memory.

9. The method of claim 1, wherein the writable memory portion comprises a single word of the PCM device.

10. The method of claim 1, wherein the writable memory portion comprises a plurality of words of the PCM device.

11. The method of claim 1, wherein the writable memory portion comprises a portion of a word of the PCM device.

12. The method of claim 1, wherein the PCM device is a single-ended PCM having a one-cell-per-bit architecture.

13. The method of claim 1, wherein the PCM device is a two-cell PCM having a two-cell-per-bit architecture.

14. The method of claim 1, wherein the PCM device is a multi-level PCM configured to store multiple bits for each unit.

15. A phase-change memory (PCM) device, comprising: The writable memory portion, each writable memory portion coupled to a corresponding non-volatile memory portion, the non-volatile memory portion being configured to store information indicating whether the latest write operation performed on the writable memory portion was performed using pulses including a first set of current pulses or a second set of current pulses, wherein the pulses in the second set of current pulses have a lower current value than the pulses included in the first set of current pulses. The PCM device is configured to implement the method according to claim 1.

16. A computer program product capable of being loaded into a control unit of a phase-change memory (PCM), the PCM including a writable memory portion, each writable memory portion coupled to a corresponding non-volatile memory portion, the non-volatile memory portion being configured to store information indicating whether a recent write operation performed on the writable memory portion was performed using pulses including a first set of current pulses or a second set of current pulses, wherein pulses in the second set of current pulses have a lower current value than pulses included in the first set of current pulses, the computer program product including a portion of software code configured to, in response to the computer program product running in the control unit of the PCM device, cause the PCM device to implement the method according to claim 1.

17. A method of operating a phase-change memory (PCM) device, the PCM device including a writable memory portion, the method comprising: The first write operation is performed on the writable memory portion using a pulse from the first set of current pulses; Information indicating that the first write operation was performed using a pulse from the first set of current pulses is stored in a non-volatile memory portion coupled to the writable memory portion; A command is received to perform a second write operation on the writable memory portion using pulses from a second set of current pulses, wherein the pulses from the second set of current pulses have a lower current value than the pulses included in the first set of current pulses. A blanking current pulse is applied to the cells of the writable memory portion that are in a reset state; The second write operation is performed on the writable memory portion using a pulse from the second set of current pulses; as well as The non-volatile memory portion stores information indicating that the second write operation is performed using a pulse from the second set of current pulses.

18. The method of claim 17, further comprising: Receive a command to perform an additional write operation on the writable memory portion using a pulse from the first set of current pulses; The additional write operation is performed on the writable memory portion using pulses from the first set of current pulses applied to all the cells of the writable memory portion, regardless of whether the cell is in a set or reset state. as well as The non-volatile memory portion stores information indicating that the additional write operation was performed using a pulse from the first set of current pulses.

19. A method of operating a phase-change memory (PCM) device, the PCM device including a writable memory portion, the method comprising: The first write operation is performed on the writable memory portion using a pulse from the second set of current pulses; Information indicating that the first write operation was performed using a pulse from the second set of current pulses is stored in a non-volatile memory portion coupled to the writable memory portion; A command is received to perform a second write operation on the writable memory portion using pulses from a first set of current pulses, wherein the pulses in the second set of current pulses have a lower current value than the pulses included in the first set of current pulses. The second write operation is performed on the writable memory portion using pulses from the first set of current pulses applied to all cells of the writable memory portion, regardless of whether the cell is in a set state or a reset state. as well as The non-volatile memory portion stores information indicating that the second write operation was performed using a pulse from the first set of current pulses.

20. The method of claim 19, further comprising: Receive a command to perform an additional write operation on the writable memory portion using a pulse from the second set of current pulses; A blanking current pulse is applied to the cells of the writable memory portion that are in a reset state; The additional write operation is performed on the writable memory portion using a pulse from the second set of current pulses; as well as The non-volatile memory portion stores information indicating that the additional write operation was performed using a pulse from the second set of current pulses.

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