Shutdown protection circuit, shutdown protection method and self-powered system

Abstract

The application discloses a shutdown protection circuit, a sampling comparison circuit and a logic circuit are coupled, a feedback comparison circuit is also coupled with the logic circuit, and the logic circuit is coupled with an RS flip-flop; the logic circuit processes output signals of the sampling comparison circuit and the feedback comparison circuit and gives the RS flip-flop; and an output end of the RS flip-flop controls current discharge of an auxiliary winding. The application also discloses a shutdown protection method, which comprises detecting a feedback voltage and a sampling voltage; when it is detected that the feedback voltage is greater than the second voltage for a duration that has lasted a first delay time and at the same time it is detected that the sampling voltage is less than a sampling threshold voltage, the opening current discharge of an auxiliary winding powered by a working voltage is given, and the system enters a shutdown mode. The application can make the working voltage discharge current discharge under specific conditions, thereby accelerating power-down of the working voltage.

Description

Technical Field

[0001] This invention relates to the field of electronic information, and in particular to a shutdown protection circuit, a shutdown protection method, and a self-powered system. Background Technology

[0002] In typical SSR secondary-side feedback systems, OLP (Optical Line Protection) is a core performance indicator. OLP protection monitors the line in real time and automatically shuts down the main power switch when an anomaly is detected, thus providing protection. Therefore, OLP protection is an essential requirement for SSR IC circuits. In traditional applications, OLP protection generally does not cause additional OLP false protection issues in the system because its protection method is directly linked to the output voltage and is independent of the input energy: when the optocoupler feedback voltage remains consistently higher than a certain threshold for SSR Low Side connection or consistently lower than a certain threshold for SSR High Side connection, and this continues for one debounce cycle T_debounce, the OLP protection system stops switching (i.e., shuts down the main power switch) and then enters the restart phase.

[0003] In a typical VDD RC boot system, as shown in the attached... Figure 1 As shown, after the OLP protection stops the switch, the system needs to perform a UVLO reset and restart (UVLO is short for "undervoltage lockout"). During the UVLO reset and restart process, the operating voltage VDD will drop, and the restart time is relatively long. Therefore, during the UVLO reset and restart process, there will be no OLP false protection due to rapid power-on / off; that is, the system does not respond to rapid input changes during the restart phase.

[0004] In a typical high-voltage self-powered SSR system, as shown in the attached... Figure 2 As shown, with the SSR IC circuit system transitioning from a typical VDDRC boot system to a high-voltage self-powered system, the OLP protection restart logic can no longer use the original ULVO zero-restart method. This is because the VDD of the high-voltage self-powered system is continuously powered by the JEFT transistor and stabilized at a constant value.

[0005] Therefore, the OLP protection logic designed in existing high-voltage self-powered systems generally exhibits the following sequence: (1) Entering the output overload state; (2) Maintaining for more than one debounce cycle T_debounce; (3) Triggering OLP protection (while VDD is stabilized at a constant value); (4) Timing a certain time as the delay time T_delay for OLP protection; (5) The system enters the power-on restart, and all protections are cleared (i.e., OLP protection stops).

[0006] When OLP protection is triggered due to output overload and VDD is stabilized at a constant value, OLP protection will be delayed. After the OLP protection delay ends, the system will enter normal boot-up and restart.

[0007] In a high-voltage self-powered system, a continuously high FB will trigger the OLP protection logic. However, insufficient input energy in shutdown mode can also cause FB to go high, making the condition that "FB going high" triggers "OLP protection" not unique. If the OLP protection logic is triggered in shutdown mode, and the auxiliary winding charge is sufficient to maintain VDD for a relatively long time (>T_debounce) to prevent the system from dropping to UVLO, then as the input AC OFF and BUS energy drop, the system will enter an OLP protection delay state (i.e., OLP Delay state, extending the OLP protection time) due to failure to shut down normally. In this state, fast power-on / off will be exempt from response. Because the IC does not respond to input power-on during the OLP protection delay, the system cannot respond to output in a timely manner, thus losing the ultra-fast start-up advantage inherent in high-voltage self-powered systems.

[0008] When OLP protection is triggered in shutdown mode, and VDD is stabilized at a constant value for a relatively long period, OLP protection delay will also occur. However, the delay time is longer in this case, preventing the system from entering fast boot mode. Therefore, this type of OLP protection delay is considered a false OLP protection event.

[0009] As explained above, existing technologies lack a clear method for distinguishing between OLP protection triggered by power-off and OLP protection triggered by overload. Furthermore, existing technologies typically extend the OLP protection debounce period (OLP debounce time) to discharge more VDD charge, thereby enabling a faster UVLO reset and restart after AC OFF. This approach has significant limitations. This is because: the size of the auxiliary winding capacitor and the load both require the system's minimum OLP debounce time to be much higher than practically acceptable, but the practically acceptable OLP debounce time cannot be significantly affected by short-circuit peak power consumption. Additionally, the system's heat generation during a short circuit also constrains the OLP debounce time. In summary, this ultimately leads to an unreasonable design, resulting in false OLP protection due to rapid power-on and power-off, thus impacting the customer's user experience. Summary of the Invention

[0010] This invention addresses the shortcomings of existing technologies by providing a shutdown protection circuit, a shutdown protection method, and a self-powered system.

[0011] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0012] This invention discloses a shutdown protection circuit, including a sampling comparison circuit, a logic circuit, a feedback comparison circuit, and an RS flip-flop. The sampling comparison circuit is coupled to the logic circuit, the feedback comparison circuit is also coupled to the logic circuit, and the logic circuit is coupled to the RS flip-flop. The sampling comparison circuit compares the acquired sampled voltage with a sampling threshold voltage and outputs a third output signal. The feedback comparison circuit compares the acquired feedback voltage with a second voltage and outputs a fourth output signal. The logic circuit performs logical operations on the third and fourth output signals and outputs the processing result to the input of the RS flip-flop. The output of the RS flip-flop controls the current discharge of the auxiliary winding, which is used to supply power to the operating voltage.

[0013] Optionally, a first delay circuit is coupled between the sampling comparison circuit and the logic circuit, and the first delay circuit is used to perform a delay processing on the third output signal for a period of up to a first delay time before outputting a first output signal to the logic circuit; a second delay circuit is coupled to the output terminal of the feedback comparison circuit, and the second delay circuit is used to perform a delay processing on the fourth output signal for a period of up to a second delay time before outputting a second output signal.

[0014] Optionally, the first delay time is less than the second delay time, the second delay time is equal to the duration of the debounce cycle of the OLP protection, and the second output signal is used to characterize the end of the debounce cycle and the start of the OLP protection.

[0015] Optionally, the logic circuit includes a first logic gate circuit coupled to the first input terminal of the RS flip-flop. The first logic gate circuit performs an AND operation on the first output signal and the inverted fourth output signal and outputs the result to the RS flip-flop. The second input terminal of the RS flip-flop is coupled to the feedback comparison circuit and acquires the fourth output signal.

[0016] Optionally, the logic circuit further includes a second logic gate circuit coupled to the second input terminal of the RS flip-flop; the second logic gate circuit is electrically connected to the fourth output signal, the second output signal and the undervoltage lockout signal used to indicate that the system has entered the undervoltage lockout state, and performs a three-input OR gate operation on the fourth output signal, the second output signal and the undervoltage lockout signal before outputting it to the RS flip-flop.

[0017] This invention also discloses a shutdown protection method, including...

[0018] When a power-off signal is input, the operating voltage begins to drop, the OLP protection is triggered, and a debounce cycle is waited for.

[0019] Detect feedback voltage and sampling voltage;

[0020] When the feedback voltage is detected to be greater than the second voltage, the duration for which the feedback voltage is greater than the second voltage is timed;

[0021] When the duration of the timing feedback voltage being greater than the second voltage has lasted for a first delay time and the sampling voltage is simultaneously detected to be less than the sampling threshold voltage, the opening current of the auxiliary winding supplying the working voltage is discharged, and the system enters the shutdown mode; the first delay time is less than the duration of the debounce cycle.

[0022] Optional, also includes

[0023] When the duration for which the timing feedback voltage is greater than the second voltage has lasted for the second delay time, the auxiliary winding stops discharging current, and the system exits the shutdown mode;

[0024] The second delay time is greater than the first delay time, and the second delay time is equal to the duration of the dejittering cycle.

[0025] Optional, also includes

[0026] When the feedback voltage is detected to be less than the second voltage, the auxiliary winding stops current discharge, and the system exits the shutdown mode.

[0027] Optional, also includes

[0028] When the operating voltage drops below the third voltage, the system enters an undervoltage lockout state, the auxiliary winding stops discharging current, and the system exits the shutdown mode.

[0029] The present invention also discloses a self-powered system, including the shutdown protection circuit described above.

[0030] This invention enables the working voltage to discharge current under specific conditions through certain logic optimizations, without significantly altering the logic framework of the OLP protection, thereby accelerating the power-off of the working voltage.

[0031] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0033] Figure 1 The circuit diagram of a typical VDD RC starting system is shown.

[0034] Figure 2 The circuit diagram of a typical high-voltage self-powered system is shown.

[0035] Figure 3 The circuit diagram of the shutdown protection circuit of Embodiment 1 is shown;

[0036] Figure 4 The diagram shows the waveforms of each output signal in the shutdown protection method of Embodiment 2 when the feedback voltage is less than the second voltage;

[0037] Figure 5 The diagram shows a waveform of the shutdown protection method in Embodiment 2 when the feedback voltage is greater than the second voltage and the sampling voltage is less than the sampling threshold voltage. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0039] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0040] This invention discloses a shutdown protection circuit and a shutdown protection method, applicable to high-voltage self-powered systems. Addressing the problem of high-voltage self-powered systems failing to quickly switch on and off due to the inability to rapidly clear the operating voltage VDD, thus causing false tripping of the OLP protection, this invention optimizes the logic based on the behavioral and timing characteristics of rapid switching on and off to avoid false triggering of the OLP protection caused by rapid switching on and off.

[0041] It should be understood that the working characteristic of OLP protection is that it triggers the logic of OLP protection when an abnormality is detected (output overload). The output overload state is characterized by the feedback voltage VFB. When the feedback voltage VFB is detected to be greater than the second voltage VFB_OLP, it indicates that the load has been overloaded. After maintaining a de-jittering cycle, OLP protection is executed. The working method of OLP protection is to turn off the main power switch.

[0042] Example 1:

[0043] This embodiment discloses a shutdown protection circuit that, by discharging the auxiliary winding current in shutdown mode, enables the auxiliary winding voltage to be discharged as quickly as possible, thereby accelerating the power-off of the operating voltage VDD. This invention optimizes the logic to address the behavioral and timing characteristics of rapid power-on and power-off. By discharging the current (bleed) when the operating voltage VDD is in a specific mode, it avoids the problem of false triggering of the OLP protection caused by rapid power-on and power-off, thus achieving rapid power-on and power-off of the system.

[0044] This implementation example is attached. Figure 3 As shown, the circuit includes a first delay circuit 20, a second delay circuit 30, a feedback comparator circuit, a sampling comparator circuit, and a logic circuit 10. The sampling comparator circuit includes a third operational amplifier U3, the feedback comparator circuit includes a fourth operational amplifier U4, and the logic circuit 10 includes a first logic gate circuit and a second logic gate circuit. In this embodiment, the first logic gate circuit is a two-input AND gate (AND_1), and the second logic gate circuit is a three-input OR gate (OR_1). In other embodiments, the first logic gate circuit can also be a circuit structure capable of implementing a two-input AND gate operation, and the second logic gate circuit can also be a circuit structure capable of implementing a three-input OR gate operation.

[0045] The non-inverting input of the third operational amplifier U3 is connected to the sampling voltage VCS_sample, and the inverting input is connected to the maximum threshold voltage of the sampling voltage, i.e., the sampling threshold voltage VCS_max. The output of the third operational amplifier U3 is electrically connected to the input of the first delay circuit 20. The output of the first delay circuit 20 is connected to the non-inverting input of the first operational amplifier U1, and the inverting input of the first operational amplifier U1 is connected to the fourth voltage V4. The third output signal Vout3 from the third operational amplifier U3 is input to the first operational amplifier U1 after being delayed by the first delay circuit 20. The first operational amplifier U1 processes the third output signal Vout3 and the fourth voltage V4 and outputs the first output signal Vout1 through its output. The delay time of the first delay circuit 20 is the first delay time T1. In this embodiment, since the first delay circuit 20 plays the role of delaying the transmission of signals, the operation settings of the first operational amplifier U1 are convenient for representing the delayed transmission of the third output signal Vout3 through the first output signal Vout1. In other embodiments, the first delay circuit 20 may adopt other structures.

[0046] The inverting input of the fourth operational amplifier U4 is connected to the feedback voltage VFB, and the non-inverting input is connected to the second voltage VFB_OLP. When the feedback voltage VFB is greater than the second voltage VFB_OLP, the OLP protection is triggered. Specifically, the output of the fourth operational amplifier U4 is electrically connected to the input of the second delay circuit 30. The output of the second delay circuit 30 is connected to the non-inverting input of the second operational amplifier U2, and the inverting input of the second operational amplifier U2 is connected to the fifth voltage V5. The fourth output signal Vout4 from the fourth operational amplifier U4 is input to the second operational amplifier U2 after being delayed by the second delay circuit 30. The second operational amplifier U2 processes the fourth output signal Vout4 and the fifth voltage V5 and outputs the second output signal Volp through its output. The delay time of the second delay circuit 30 is the second delay time T2. In this embodiment, since the second delay circuit 30 serves to delay the transmission of signals, the operational settings of the second operational amplifier U2 facilitate the representation of the delayed fourth output signal Vout4 by the second output signal Volp. In other embodiments, the second delay circuit 30 may adopt other structures.

[0047] In this embodiment, the second delay time T2 is greater than the first delay time T1, and the second delay time T2 is the same as the debounce period of the OLP protection. In this embodiment, the first delay time T1 is 10ms and the second delay time T2 is 180ms. Other values ​​may be selected in other embodiments, and are not limited to this embodiment.

[0048] The second output signal Volp indicates that the debounce period T_debounce of the OLP protection has ended. Since the OLP protection is activated after the debounce period T_debounce ends, this embodiment uses the second output signal Volp to indicate the activation of the OLP protection.

[0049] The output of the fourth operational amplifier U4 is also electrically connected to the input of the first inverter N1. The fourth output signal Vout4 of the fourth operational amplifier U4 is inverted by the first inverter N1 and output as an inverted fourth output signal Vout4, i.e., output (-Vout4). The output of the first inverter N1 is electrically connected to the input of the second inverter N2. The fourth output signal Vout4 of the fourth operational amplifier U4 remains unchanged after being inverted twice by the first inverter N1 and the second inverter N2, and is output by the second inverter N2, i.e., the second inverter N2 outputs the fourth output signal Vout4.

[0050] The output of the first inverter N1 is also electrically connected to one input of the AND gate AND_1, the output of the first delay circuit 20 is also electrically connected to the other input of the AND gate AND_1, and the output of the AND gate AND_1 is connected to the first input S of the RS flip-flop.

[0051] The output of the second inverter N2 is connected to one input of the OR gate OR_1. The other inputs of the OR gate OR_1 are also connected to the second output signal Volp and the undervoltage lockout signal Vuvlo, respectively. The output of the OR gate OR_1 is connected to the second input R of the RS flip-flop. The undervoltage lockout signal Vuvlo indicates that the system has entered an undervoltage lockout state.

[0052] The first output terminal Q of the RS flip-flop outputs a first discharge current control signal Bleed_ON, which is used to control the auxiliary winding to start discharge current; the second output terminal QN of the RS flip-flop outputs a second discharge current control signal Bleed_OFF, which is used to control the auxiliary winding to stop discharge current.

[0053] In summary, this embodiment achieves the following: when the feedback voltage VFB is greater than the second voltage VFB_OLP and lasts for a first delay time T1, and simultaneously the sampling voltage VCS_sample is less than the sampling threshold voltage VCS_max, the system enters shutdown mode, starts the discharge current of the auxiliary winding, and drives the power-off of the operating voltage VDD. Once the feedback voltage VFB is less than the second voltage VFB_OLP, the system exits shutdown mode and stops the discharge current of the auxiliary winding.

[0054] Example 2:

[0055] This embodiment discloses a shutdown protection method, employing a shutdown protection circuit disclosed in Embodiment 1 to quickly discharge the auxiliary winding voltage in shutdown mode, thereby accelerating the power-down of the operating voltage VDD and preventing false protection by the OLP protection. Under normal circumstances, when a shutdown signal is input, the OLP protection is triggered, and after waiting for a debounce cycle, the OLP protection is activated. After the shutdown signal is input, the operating voltage VDD begins to drop, but because the auxiliary winding is powered, it cannot quickly drop below the third voltage V_UVLO before the end of the debounce cycle. Therefore, this embodiment accelerates the power-down of the operating voltage VDD by discharging current through the auxiliary winding during the debounce cycle.

[0056] According to the circuit logic structure of Embodiment 1, the logical function of the level acquired by the first input terminal S of the RS flip-flop is: the first input terminal S acquires a high level only when the first output signal Vout1 is high and the fourth output signal Vout4 is low. The logical function of the level acquired by the second input terminal R of the RS flip-flop is: the second input terminal R acquires a high level only when any one of the second output signal Volp, the undervoltage lockout signal Vuvlo, and the fourth output signal Vout4 is high.

[0057] Therefore, to facilitate the description of the shutdown protection method that the circuit logic in Embodiment 1 can provide, this embodiment sets the second output signal Volp of the OLP protection to a high level when it is activated, and a low level otherwise; sets the undervoltage lockout signal Vuvlo to a high level when the system enters the undervoltage lockout state, and a low level otherwise; sets the third output signal Vout3 to a low level when the sampling voltage VCS_sample is less than the sampling threshold voltage VCS_max, and a high level otherwise; and sets the fourth output signal Vout4 to a low level when the feedback voltage VFB is greater than the second voltage VFB_OLP, and a high level otherwise.

[0058] In this embodiment, the first delay time T1 is 10ms, and the second delay time T2 is 180ms. The second delay time T2 is the same as the debounce period T_debounce of the OLP protection, and the end time of the second delay time T2 is exactly the end time of the debounce period T_debounce of the OLP protection. However, it should be understood that in other embodiments, the selection values ​​of the first delay time T1 and the second delay time T2 are not limited to this embodiment, and other choices are possible. For example, the first delay time T1 can be selected as 2ms, 3ms, 5ms, etc., and the selection value of the second delay time T2 is the same as the debounce period T_debounce of the OLP protection. The selection of the debounce period T_debounce is based on the actual circuit performance and is not subject to too much constraint due to the influence of short-circuit peak power consumption and the degree of short-circuit heat generation of the system.

[0059] When the feedback voltage VFB is greater than the second voltage VFB_OLP, the fourth output signal Vout4 is low. After the debouncing delay time of the second delay time T2 ends, the second operational amplifier U2 outputs the second output signal Volp; simultaneously, the first inverter N1 outputs a high level, and the second inverter N2 outputs a low level. According to the attached... Figure 3 The structure of the second delay circuit 30 shown in this embodiment is such that during the second delay time T2, the second output signal Volp is at a low level, and after the second delay time T2 ends, the second output signal Volp is at a high level, and the OLP protection is activated.

[0060] When the feedback voltage VFB is less than the second voltage VFB_OLP, the fourth output signal Vout4 is high and the second output signal Volp is low, meaning the OLP protection is not activated. The first inverter N1 outputs a low level, and the second inverter N2 outputs a high level.

[0061] When the sampled voltage VCS_sample is less than the sampling threshold voltage VCS_max, the third output signal Vout3 is low. After the dejitter delay time of the first delay time T1 ends, the first operational amplifier U1 outputs the first output signal Vout1. Wherein, according to the attached... Figure 3 The structure of the first delay circuit 20 shown in this embodiment is such that during the first delay time T1, the first output signal Vout1 is at a low level, and after the first delay time T1 ends, the first output signal Vout1 is at a high level.

[0062] Since the sampling voltage VCS_sample is used to sample the voltage of the current flowing through the main power switch, under normal circumstances when the system is not in shutdown mode, the main power switch is on. Because there is no BUS energy drop, when a load overload occurs, the sampling voltage VCS_sample will equal the sampling threshold voltage VCS_max. However, when the system enters shutdown mode, a BUS energy drop causes a decrease in the input voltage to the system circuit. The main power switch receives insufficient energy, and because the operating voltage VDD is powered by the auxiliary winding and cannot be quickly de-energized, the main power switch remains on, causing the current flowing through it to decrease. Therefore, the sampling voltage VCS_sample may be lower than the sampling threshold voltage VCS_max. Thus, when a load overload is detected and the sampling voltage VCS_sample is lower than the sampling threshold voltage VCS_max, it should be determined that the system has entered shutdown mode, requiring control of the auxiliary winding to discharge the leakage current, thereby accelerating the decrease of the operating voltage VDD. Furthermore, it should be understood that the sampling voltage VCS_sample can never be greater than the sampling threshold voltage VCS_max.

[0063] In summary, the shutdown protection method of this embodiment controls the discharge current of the auxiliary winding voltage as follows:

[0064] As attached Figure 4 As shown, when the feedback voltage VFB is less than the second voltage VFB_OLP, the fourth output signal Vout4 is high, and the second input terminal R acquires a high level. Since the output of the first inverter N1 is low, regardless of the value of the sampling voltage VCS_sample, the AND gate AND_1 outputs a low level, causing the first input terminal S to acquire a low level. At the same time, the OR gate OR_1 outputs a high level. Therefore, according to the characteristics of the RS flip-flop itself, the first output terminal Q outputs a low level signal, and the second output terminal QN outputs a high level signal. The auxiliary winding stops current discharge, and the operating state at this time is that the system exits the shutdown mode.

[0065] As attached Figure 5 As shown, when the feedback voltage VFB is greater than the second voltage VFB_OLP, and the sampling voltage VCS_sample is less than the sampling threshold voltage VCS_max, the following states exist:

[0066] State 1: During the first delay time T1, the first output signal Vout1 is low, the AND gate AND_1 outputs a low level, and the second output signal Volp is low. Therefore, as long as the system has not entered the undervoltage lockout state (the undervoltage lockout signal Vuvlo is low), the OR gate OR_1 will output a low level. This results in the first input terminal S acquiring a low level, the second input terminal R acquiring a low level, and the output state of the RS flip-flop remaining unchanged. The discharge control of the auxiliary winding's discharge current remains unchanged. In other words, during the first delay time T1, the system has not yet entered the shutdown mode.

[0067] State 2: After the first delay time T1 ends, but during the second delay time T2, the first output signal Vout1 is high, and the AND gate AND_1 outputs a high level. Because the second output signal Volp is low, the fourth output signal Vout4 is low, and the undervoltage lockout signal Vuvlo is low due to not entering the undervoltage lockout state, the OR gate OR_1 outputs a low level. Therefore, the first input S acquires a high level, the second input R acquires a low level, the first output Q of the RS flip-flop outputs a high level signal, and the second output QN outputs a low level signal. That is, the first discharge current control signal Bleed_ON is high, and the auxiliary winding open current discharge is initiated. At this time, the system enters shutdown mode, and the operating voltage VDD is rapidly de-energized.

[0068] State 3: After the second delay time T2 ends, the second output signal Volp is high, indicating the end of the OLP protection debouncing cycle and the system activates OLP protection. At this time, the OR gate OR_1 outputs a high level, and the second input R receives a high level. Therefore, according to the characteristics of the RS flip-flop, the current operating state is that the system exits the shutdown mode. In this embodiment, the first delay time T1 is 10ms and the second delay time T2 is 180ms. However, the two debouncing times are not limited to this embodiment but depend on the influence of the system's short-circuit peak power consumption and short-circuit heat generation. The second delay time T2 must be greater than the first delay time T1.

[0069] It should be understood that once the system enters an undervoltage lockout state (i.e., the undervoltage lockout signal Vuvlo is high), the OR gate circuit OR_1 will output a high level. According to the characteristics of the RS flip-flop itself, the operating state at this time is that the system exits the shutdown mode.

[0070] Therefore, the input terminals of the OR gate circuit OR_1 are connected to the undervoltage lockout signal Vuvlo and the second output signal Volp, respectively, which can be used to supplement and improve the shutdown mode exit conditions. Once the system enters the undervoltage lockout state or enters the OLP protection start state, it will immediately exit the shutdown mode. That is, during the normal steady state, the discharge current of the auxiliary winding will not be intervened, so as to avoid the hidden danger of additional operating current affecting the power consumption and temperature rise of the system, and also prevent the problem of JFET tube reliability being affected by long-term high current operation of JFET tube.

[0071] This embodiment can discharge the auxiliary winding current during the debounce period of OLP protection when the system enters the shutdown mode and triggers OLP protection, thereby accelerating the power loss of the working voltage VDD. This allows the working voltage VDD to drop below the third voltage V_UVLO as soon as possible after shutdown, thus avoiding the false start of OLP protection after the debounce ends, avoiding the long delay of OLP protection, and realizing fast power on and off.

[0072] Example 5:

[0073] This embodiment discloses a high-voltage self-powered system, including the shutdown protection circuit of Embodiment 1 and the shutdown protection method of Embodiment 2.

[0074] This embodiment, without significantly altering the logic framework of the OLP protection, enables the auxiliary winding to discharge current (Bleed) under specific conditions through certain logic optimizations, thereby accelerating the power-off of the operating voltage VDD.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

[0076] In summary, the above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the present invention.

Claims

1. A shutdown protection circuit, characterized in that, This includes sampling comparator circuits, logic circuits, feedback comparator circuits, and RS flip-flops; The sampling comparison circuit is coupled to the logic circuit, the feedback comparison circuit is also coupled to the logic circuit, and the logic circuit is coupled to the RS flip-flop; The sampling comparison circuit compares the acquired sampling voltage with the sampling threshold voltage and then outputs a third output signal. The feedback comparison circuit compares the acquired feedback voltage with the second voltage and then outputs a fourth output signal. The first delay circuit is coupled between the sampling comparison circuit and the logic circuit. The first delay circuit is used to delay the third output signal for a period of time up to a first delay time and then output the first output signal to the logic circuit. The second delay circuit is coupled to the output terminal of the feedback comparison circuit. The second delay circuit is used to delay the fourth output signal for a period of time up to the second delay time before outputting the second output signal. The first delay time is less than the second delay time, the second delay time is equal to the duration of the debounce cycle of the OLP protection, and the second output signal is used to characterize the end of the debounce cycle and the start of the OLP protection. The logic circuit performs logical operations on the third and fourth output signals and outputs the processing result to the input of the RS flip-flop. The output of the RS flip-flop controls the current discharge of the auxiliary winding, which is used to supply power to the working voltage.

2. The shutdown protection circuit according to claim 1, characterized in that, The logic circuit includes a first logic gate circuit coupled to the first input terminal of the RS flip-flop. The first logic gate circuit performs an AND operation on the first output signal and the inverted fourth output signal and outputs the result to the RS flip-flop. The second input terminal of the RS flip-flop is coupled to the feedback comparator circuit and obtains the fourth output signal.

3. The shutdown protection circuit according to claim 2, characterized in that, The logic circuit further includes a second logic gate circuit coupled to the second input terminal of the RS flip-flop; the second logic gate circuit is electrically connected to the fourth output signal, the second output signal and the undervoltage lockout signal used to indicate that the system has entered the undervoltage lockout state, and performs a three-input OR gate operation on the fourth output signal, the second output signal and the undervoltage lockout signal before outputting it to the RS flip-flop.

4. A shutdown protection method based on the shutdown protection circuit according to any one of claims 1-3, characterized in that, include When a power-off signal is input, the operating voltage begins to drop, the OLP protection is triggered, and a debounce cycle is waited for. Detect feedback voltage and sampling voltage; When the feedback voltage is detected to be greater than the second voltage, the duration for which the feedback voltage is greater than the second voltage is timed; When the duration of the timing feedback voltage being greater than the second voltage has lasted for a first delay time and the sampling voltage is simultaneously detected to be less than the sampling threshold voltage, the opening current of the auxiliary winding supplying the working voltage is discharged, and the system enters the shutdown mode; the first delay time is less than the duration of the debounce cycle.

5. A shutdown protection method according to claim 4, characterized in that, Also includes When the duration for which the timing feedback voltage is greater than the second voltage has lasted for the second delay time, the auxiliary winding stops discharging current, and the system exits the shutdown mode; the second delay time is greater than the first delay time, and the second delay time is equal to the duration of the debouncing cycle.

6. The shutdown protection method according to claim 5, characterized in that, Also includes When the feedback voltage is detected to be less than the second voltage, the auxiliary winding stops current discharge, and the system exits the shutdown mode.

7. A shutdown protection method according to claim 6, characterized in that, Also includes When the operating voltage drops below the third voltage, the system enters an undervoltage lockout state, the auxiliary winding stops discharging current, and the system exits the shutdown mode.

8. A self-powered system, characterized in that, Includes the shutdown protection circuit as described in any one of claims 1-3.

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