Delay circuit

Abstract

The present invention provides a delay circuit that can produce the same delay time as before in a more compact size than before. The delay circuit includes: first and third transistors of a first conductivity type; second and fourth transistors of a second conductivity type; a capacitor; a constant current source; and a resistor. The first transistor has a gate connected to an input terminal, a source connected to a first power supply terminal, and a drain. The second transistor has a gate connected to the input terminal and the gate of the first transistor, a drain connected to the drain of the first transistor and the second end of the capacitor, and a source. The third transistor has a gate, a source connected to the second power supply terminal, and a drain, and the gate of the third transistor is connected to a node of the drain of the first transistor, the drain of the second transistor, and the second end of the capacitor. The fourth transistor has a gate connected to a node and the gate of the third transistor, a drain connected to the drain of the third transistor and the output terminal, and a source.

Description

Technical Field

[0001] The present invention relates to a delay circuit. Background Art

[0002] A delay circuit is known that includes a capacitor and generates a delay time corresponding to the capacitance value of the capacitor (for example, refer to Japanese Patent Application Laid-Open No. 2010-219661).

[0003] [Prior art literature]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-219661 Summary of the Invention

[0006] [Problems to be solved by the invention]

[0007] However, in the delay circuit, the longer the delay time is, the larger the capacitance value is. The increase in capacitance value will lead to an increase in the size of the capacitor, and further lead to an increase in the size of the entire delay circuit.

[0008] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a delay circuit capable of generating the same delay time as conventional circuits in a more compact size than conventional ones.

[0009] [Technical means to solve the problem]

[0010] The delay circuit of the embodiment of the present invention includes: a first transistor having a gate connected to an input terminal, a source connected to a power supply terminal supplying a first power supply voltage, and a drain; a capacitor having a first end connected to the power supply terminal supplying the first power supply voltage and a second end connected to the drain of the first transistor; a second transistor having a gate connected to the gate of the first transistor and the input terminal, a drain connected to the drain of the first transistor and the second end of the capacitor, and a source; a first constant current source connected between the source of the second transistor and a power supply terminal supplying a second power supply voltage different from the first power supply voltage; a third transistor having a gate, a drain connected to the first transistor and the input terminal, and a drain connected to the second end of the capacitor; a source and a drain connected to a power supply terminal for supplying the second power supply voltage, a gate of the third transistor connected to the drain of the first transistor, the drain of the second transistor, and a node of the second end of the capacitor; a fourth transistor having a gate connected to the node and the gate of the third transistor, a drain connected to the drain of the third transistor and an output terminal, and a source; and a resistor having a first end connected to the source of the fourth transistor and a second end connected to the power supply terminal for supplying the first power supply voltage; and the first transistor and the fourth transistor are first conductive type metal oxide semiconductor (MOS) transistors which are either p-type or n-type, and the second transistor and the third transistor are second conductive type metal oxide semiconductor transistors which are the other of p-type and n-type.

[0011] [Effects of the Invention]

[0012] According to the present invention, the same delay time as before can be produced in a more compact size than before. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a circuit diagram of a delay circuit according to a first embodiment of the present invention.

[0014] Figure 2 is a circuit diagram of a delay circuit according to a second embodiment of the present invention.

[0015] Figure 3 is a circuit diagram of a delay circuit according to a third embodiment of the present invention.

[0016] Figure 4 4 is a circuit diagram of a delay circuit according to a fourth embodiment of the present invention.

[0017] Figure 5 This is a circuit diagram showing a first modified example of the delay circuit according to the embodiment of the present invention.

[0018] Figure 6This is a circuit diagram showing a second modified example of the delay circuit according to the embodiment of the present invention.

[0019] Figure 7 This is a circuit diagram showing a third modified example of the delay circuit according to the embodiment of the present invention.

[0020] [Explanation of Symbols]

[0021] 1A~1G: Semiconductor devices

[0022] 10A~10G: Delay circuit

[0023] 3: Power terminal

[0024] 4: Ground terminal

[0025] 21: Capacitor

[0026] 22: Constant current source (first constant current source)

[0027] 31: Resistors

[0028] 41, 61: Inverter

[0029] 51: Constant current source (second constant current source)

[0030] Q1: PMOS transistor (first transistor)

[0031] Q2: NMOS transistor (second transistor)

[0032] Q3: PMOS transistor (resistor, diode)

[0033] Q4: PMOS transistor (fourth transistor)

[0034] Q5: NMOS transistor (third transistor)

[0035] Q7: PMOS transistor (fifth transistor)

[0036] Q8: NMOS transistor (sixth transistor)

[0037] Q9: PMOS transistor (seventh transistor)

[0038] Ti: Input terminal

[0039] To: output terminal

[0040] N1, N2, N3: nodes

[0041] VDD: voltage

[0042] GND: Ground voltage DETAILED DESCRIPTION

[0043] [First embodiment]

[0044] Figure 1 10A is a circuit diagram of a delay circuit 10A as an example of a delay circuit according to the first embodiment of the present invention.

[0045] Delay circuit 10A is formed on, for example, a semiconductor substrate and included in semiconductor device 1A. Delay circuit 10A includes, for example, p-type MOS transistors (hereinafter referred to as "PMOS transistors") Q1, Q3, and Q4; n-type MOS transistors (hereinafter referred to as "NMOS transistors") Q2 and Q5; a capacitor 21; and a constant current source 22.

[0046] The PMOS transistor Q1 as the first transistor has a gate connected to the input terminal Ti, and a source and a drain connected to the power supply terminal 3. The power supply terminal 3 is a terminal to which a voltage VDD as a power supply voltage is supplied.

[0047] The capacitor 21 is connected between the power supply terminal 3 and the drain of the PMOS transistor Q1. That is, the capacitor 21 has a first end connected to the power supply terminal 3 and a second end connected to the drain of the PMOS transistor Q1.

[0048] The NMOS transistor Q2 as the second transistor has a gate connected to the gate of the PMOS transistor Q1 and the input terminal Ti, a drain connected to the drain of the PMOS transistor Q1 and the second end of the capacitor 21 , and a source.

[0049] A constant current source 22, serving as a first constant current source, is connected between the source of the NMOS transistor Q2 and a ground terminal 4, serving as a power supply terminal. Ground terminal 4 is a power supply terminal to which a ground voltage GND is supplied. Ground voltage GND, serving as a power supply voltage, is a reference voltage such as 0 volts and is different from voltage VDD.

[0050] NMOS transistor Q5 as the third transistor has a gate connected to node N1 and a source and a drain connected to ground terminal 4. Node N1 is a connection point between the drains of PMOS transistor Q1 and NMOS transistor Q2 and the second end of capacitor 21.

[0051] The PMOS transistor Q4 as the fourth transistor has a gate connected to the node N1 and the gate of the NMOS transistor Q5 , a drain connected to the drain of the NMOS transistor Q5 and the output terminal To, and a source.

[0052] The PMOS transistor Q3, which functions as a resistor, has its gate and drain connected (short-circuited) and, for example, functions as a resistor having a first end, which is a gate and drain connected to each other, and a second end, which is a source. The PMOS transistor Q3, which is so-called diode-connected, has a gate and drain connected to the source of the fourth transistor as its first end, and a source connected to the power supply terminal 3 as its second end.

[0053] Here, the relationship between the conductivity types of the first to fourth transistors in the delay circuit of this embodiment is described. The conductivity type of the first transistor and the fourth transistor is a first conductivity type, which is one of the p-type and the n-type. On the other hand, the conductivity type of the second transistor and the third transistor is a second conductivity type, which is the other of the p-type and the n-type. That is, the second conductivity type is different from the first conductivity type. Figure 1 In the delay circuit 10A shown, the first conductivity type is the p-type and the second conductivity type is the n-type.

[0054] Next, the operation of the delay circuit 10A will be described.

[0055] When a low-level voltage (hereinafter referred to as "L level") is input to input terminal Ti, PMOS transistor Q1 turns on and NMOS transistor Q2 turns off. Consequently, voltage VDD, or a high-level voltage (hereinafter referred to as "H level"), is supplied to the gates of PMOS transistor Q4 and NMOS transistor Q5. Consequently, PMOS transistor Q4 turns off and NMOS transistor Q5 turns on, and the voltage output from output terminal To becomes L level.

[0056] Here, when the voltage level of the voltage input to the input terminal Ti changes from the low level to the high level, the PMOS transistor Q1 changes from on to off, and the NMOS transistor Q2 changes from off to on. When the PMOS transistor Q1 turns off and the NMOS transistor Q2 turns on, the constant current of the constant current source 22 begins to charge the capacitor 21. The capacitor 21 generates a delay time from the moment the voltage level of the voltage input to the input terminal Ti changes to the moment the voltage level of the voltage output from the output terminal To changes. Therefore, at the time when the charge starts to be charged to the capacitor 21, the voltage level of the voltage output from the output terminal To remains at the low level.

[0057] Subsequently, as the charge is charged, the voltage across capacitor 21 increases, and the voltage at node N1 decreases. Soon, when the voltage at node N1 falls below a threshold (hereinafter simply referred to as "threshold") at which the voltage level of the voltage output from the circuit (inverter) including PMOS transistor Q3, PMOS transistor Q4, and NMOS transistor Q5 transitions, the voltage level of the output voltage transitions from L to H, and an H voltage is supplied from output terminal To.

[0058] When capacitor 21 in delay circuit 10A has the same capacitance value as that of a delay circuit not including PMOS transistor Q3, delay circuit 10A can lower the threshold of the circuit including PMOS transistor Q4 and NMOS transistor Q5 compared to a delay circuit not including PMOS transistor Q3. Focusing on delay time, delay circuit 10A can produce a longer delay time than a delay circuit of the same size not including PMOS transistor Q3.

[0059] On the other hand, if the delay time of a delay circuit that does not include the PMOS transistor Q3 is the same as the delay time of the delay circuit 10A, the capacitance value of the capacitor 21 in the delay circuit 10A can be smaller than the capacitance value of the capacitor in the delay circuit that does not include the PMOS transistor Q3. In terms of circuit size, the delay circuit 10A can reduce the overall circuit size compared to a delay circuit that does not include the PMOS transistor Q3 and has the same delay time.

[0060] In addition, in this embodiment, although the example in which the PMOS transistor Q3 connected as a first-stage diode is used as the resistor is described, the resistor is not limited to this.

[0061] A resistor can be formed by a single element or multiple elements that generate a predetermined voltage drop, and a diode or resistor can also be used. Diodes include not only diode elements but also MOS transistors connected to form a diode. Furthermore, a resistor can be formed by cascading multiple MOS transistors connected to form a diode, a diode element, and a resistor.

[0062] [Second embodiment]

[0063] Figure 2 10B is a circuit diagram of a delay circuit 10B as an example of a delay circuit according to the second embodiment of the present invention.

[0064] Delay circuit 10B differs from delay circuit 10A in that it includes a PMOS transistor Q3 serving as a diode instead of a PMOS transistor Q3 serving as a resistor, and further includes a PMOS transistor Q7, an NMOS transistor Q8, and a resistor 31. However, in other respects, delay circuit 10B is substantially the same. Therefore, in this embodiment, the description will focus on the components, functions, and effects that differ from those of delay circuit 10A. Components that do not substantially differ from those of delay circuit 10A are denoted by the same reference numerals, and their description will be omitted.

[0065] Delay circuit 10B is formed on, for example, a semiconductor substrate and included in semiconductor device 1B. Delay circuit 10B further includes: a PMOS transistor Q3 serving as a resistor; PMOS transistors Q1 and Q4; NMOS transistors Q2 and Q5; a capacitor 21 and a constant current source 22; and, for example, a PMOS transistor Q7; an NMOS transistor Q8; and a resistor 31.

[0066] The PMOS transistor Q7 as the fifth transistor has a gate connected to the drain of the PMOS transistor Q4 , a source connected to the power supply terminal 3 , and a drain connected to the first end of the resistor 31 .

[0067] NMOS transistor Q8, serving as the sixth transistor, has a gate connected to the gate of PMOS transistor Q7 and the drain of PMOS transistor Q4, a source connected to ground terminal 4, and a drain connected to the second end of resistor 31 and output terminal To. The connection point between the drain of NMOS transistor Q8 and the second end of resistor 31 is referred to as node N2. In delay circuit 10B, output terminal To is connected to node N2.

[0068] The threshold of the circuit formed by PMOS transistor Q7, NMOS transistor Q8, and resistor 31 is lower than the voltage determined by the through-current flowing through the path connected to the drains of PMOS transistor Q4 and NMOS transistor Q5, and PMOS transistor Q3. Specifically, NMOS transistor Q8 is configured to turn on when the voltage level of the voltage output from the node between the drain of PMOS transistor Q4 and the drain of NMOS transistor Q5 transitions from low to high.

[0069] The threshold value of the circuit (inverter) including the PMOS transistor Q7 , the NMOS transistor Q8 , and the resistor 31 can be adjusted to a desired threshold value by changing the resistance value of the resistor 31 .

[0070] Here, the relationship between the conductivity types of the first to sixth transistors in the delay circuit of this embodiment is described. The conductivity type of the first, fourth, and fifth transistors is a first conductivity type, which is one of p-type and n-type. On the other hand, the conductivity type of the second, third, and sixth transistors is a second conductivity type, which is the other of p-type and n-type. That is, the second conductivity type is different from the first conductivity type. Figure 2 In the illustrated delay circuit 10B, the first conductivity type is the p-type and the second conductivity type is the n-type.

[0071] Next, the operation of the delay circuit 10B will be described. Note that since the operation of the components that overlap with those of the delay circuit 10A is substantially the same, the description of the operation will be simplified or omitted.

[0072] When an L-level voltage is input to input terminal Ti, an L-level voltage is output from the node between the drain of PMOS transistor Q4 and the drain of NMOS transistor Q5. An L-level voltage is applied to the gates of PMOS transistor Q7 and NMOS transistor Q8, turning PMOS transistor Q7 on and NMOS transistor Q8 off. Consequently, the voltage supplied from the node between the drain of PMOS transistor Q7 and the drain of NMOS transistor Q8 to output terminal To becomes an H-level voltage.

[0073] When the voltage input to the input terminal Ti transitions from L to H, a delay time occurs. After the delay time, the voltage output from the node between the drain of the PMOS transistor Q4 and the drain of the NMOS transistor Q5 transitions from L to H.

[0074] Shortly after the delay time has elapsed, the voltage output from the node between the drains of PMOS transistor Q4 and NMOS transistor Q5 rises only to a voltage determined by the through-current flowing through the path connected to the drains of PMOS transistor Q4 and NMOS transistor Q5, and by PMOS transistor Q3. However, the voltage rise in the voltage output from the node between the drains of PMOS transistor Q4 and NMOS transistor Q5 shortly after the delay time has elapsed causes NMOS transistor Q8 to transition from an off state to an on state.

[0075] While NMOS transistor Q8 transitions from an off state to an on state, PMOS transistor Q7 does not transition from an on state to an off state until the voltage output from the node between the drain of PMOS transistor Q4 and the drain of NMOS transistor Q5 has sufficiently risen. However, even if PMOS transistor Q7 remains on, a voltage drop occurs across resistor 31 because resistor 31 is connected between the drain of PMOS transistor Q7 and the drain of NMOS transistor Q8.

[0076] When the NMOS transistor Q8 transitions from the off state to the on state, a voltage drop occurs across the resistor 31, causing the voltage supplied from the node between the drain of the PMOS transistor Q7 and the drain of the NMOS transistor Q8 to the output terminal To to transition from the H level to the L level. Furthermore, when the PMOS transistor Q7 transitions to the off state, the voltage supplied from the node between the drain of the PMOS transistor Q7 and the drain of the NMOS transistor Q8 to the output terminal To is a L level voltage.

[0077] Thus, when the NMOS transistor Q8 changes from the off state to the on state, the voltage supplied to the output terminal To from the node of the drain of the PMOS transistor Q7 and the drain of the NMOS transistor Q8 is an L-level voltage regardless of the on / off state of the PMOS transistor Q7.

[0078] The delay circuit 10B achieves the same effects as the delay circuit 10A. Specifically, considering the circuit size, the delay circuit 10B can achieve the same delay time as the conventional circuit in a more compact size. Furthermore, considering the delay time, the delay circuit 10B can achieve a greater delay time than the conventional circuit in the same size as the conventional delay circuit.

[0079] Furthermore, according to the delay circuit 10B, the voltage level can be reliably transitioned even shortly after the delay time during which the voltage output from the drain of the PMOS transistor Q4 and the drain of the NMOS transistor Q5 has not sufficiently risen.

[0080] [Third embodiment]

[0081] Figure 3 10C is a circuit diagram of a delay circuit 10C as an example of a delay circuit according to a third embodiment of the present invention.

[0082] Delay circuit 10C differs from delay circuit 10A in that it further includes a PMOS transistor Q9 and an inverter 41, but is otherwise substantially the same. Therefore, in this embodiment, the description will focus on the components, functions, and effects that differ from those of delay circuit 10A. Components that are substantially the same as those of delay circuit 10A are denoted by the same reference numerals, and their description will be omitted.

[0083] The delay circuit 10C is formed, for example, on a semiconductor substrate and included in the semiconductor device 1C. The delay circuit 10C further includes a PMOS transistor Q3 serving as a diode; PMOS transistors Q1 and Q4; NMOS transistors Q2 and Q5; a capacitor 21 and a constant current source 22; and, for example, a PMOS transistor Q9 and an inverter 41. The PMOS transistor Q3 is connected as a diode to achieve a desired voltage drop even when leakage current flows, while also suppressing current consumption, compared to using a resistor.

[0084] The PMOS transistor Q9 as the seventh transistor has a gate, a source connected to the power supply terminal 3 , and a drain connected to the source of the PMOS transistor Q4 and the gate and drain of the diode-connected PMOS transistor Q3 .

[0085] Inverter 41 has an input terminal connected to the drain of PMOS transistor Q4 and an output terminal connected to the gate of PMOS transistor Q9. The connection point between the input terminal of inverter 41 and output terminal To is referred to as node N3. In delay circuit 10C, the drain of PMOS transistor Q4 and the drain of NMOS transistor Q5 are connected to node N3.

[0086] Here, the relationship between the conductivity types of the first to seventh transistors in the delay circuit of this embodiment is described. The conductivity type of the first, fourth, fifth, and seventh transistors is a first conductivity type, which is one of the p-type and n-type. On the other hand, the conductivity type of the second, third, and sixth transistors is a second conductivity type, which is the other of the p-type and n-type. That is, the second conductivity type is different from the first conductivity type. Figure 3 In the illustrated delay circuit 10C, the first conductivity type is the p-type and the second conductivity type is the n-type.

[0087] Next, the operation of the delay circuit 10C will be described. Note that since the operation of the components that overlap with those of the delay circuit 10A is substantially the same, the description of the operation will be simplified or omitted.

[0088] When an L-level voltage is input to input terminal Ti, an L-level voltage is output from the node between the drain of PMOS transistor Q4 and the drain of NMOS transistor Q5. The gate of PMOS transistor Q9 receives a voltage based on the voltage output from the drain of PMOS transistor Q4. In delay circuit 10C, the voltage output from the node between the drain of PMOS transistor Q4 and the drain of NMOS transistor Q5 is supplied to the gate of PMOS transistor Q9 via inverter 41. At this time, since an H-level voltage is supplied to the gate of PMOS transistor Q9, PMOS transistor Q9 is in an OFF state.

[0089] When the voltage level of the voltage input to the input terminal Ti changes from L to H, a delay time occurs. The voltage level of the voltage output from the node between the drain of the PMOS transistor Q4 and the drain of the NMOS transistor Q5 changes from L to H. Since an L-level voltage is input to the gate of the PMOS transistor Q9 via the inverter 41, the PMOS transistor Q9 is turned on.

[0090] When PMOS transistor Q9 is turned on, the on-resistance of PMOS transistor Q9 is extremely small compared to that of PMOS transistor Q3. Therefore, the path connecting the drain of PMOS transistor Q4 and power supply terminal 3 via PMOS transistor Q3 can be ignored. In other words, the drain of PMOS transistor Q4 is connected to power supply terminal 3 via PMOS transistor Q9 in the on state.

[0091] Therefore, when the voltage level of the voltage input to the input terminal Ti changes from L level to H level, the voltage at the node between the drain of the PMOS transistor Q4 and the drain of the NMOS transistor Q5 can rise to the voltage VDD after a delay time.

[0092] Delay circuit 10C achieves the same effects as delay circuit 10A without increasing current consumption. Specifically, considering circuit size, delay circuit 10C can achieve the same delay time as conventional circuits in a more compact size without increasing current consumption. Furthermore, considering delay time, delay circuit 10C can achieve a longer delay time than conventional circuits in the same size as conventional delay circuits without increasing current consumption.

[0093] Furthermore, according to the delay circuit 10C, after the delay time has elapsed, the path of the current flowing from the power supply terminal 3 to the PMOS transistor Q4 is switched from the path through the PMOS transistor Q3 to the path through the PMOS transistor Q9, thereby increasing the voltage at the drains of the PMOS transistor Q4 and the NMOS transistor Q5 to the voltage VDD. By increasing the voltage at the drains of the PMOS transistor Q4 and the NMOS transistor Q5 to the voltage VDD, when an external circuit is connected to the output terminal To, the influence of a through-current flowing into the external circuit can be suppressed.

[0094] In addition, in this embodiment, although the example in which the PMOS transistor Q3 connected in a first-stage diode is used as the diode is described, the diode is not limited to this.

[0095] The diode is not limited to a MOS transistor connected in a diode, and a diode element may also be applied. In addition, the diode may be configured by connecting a plurality of MOS transistors or diode elements connected in a diode in cascade.

[0096] [Fourth embodiment]

[0097] Figure 4 10D is a circuit diagram of a delay circuit 10D as an example of a delay circuit according to a fourth embodiment of the present invention.

[0098] The delay circuit 10D is formed on, for example, a semiconductor substrate and included in the semiconductor device 1D. While the delay circuit 10D differs from the delay circuit 10A in that it further includes a constant current source 51, the delay circuit 10D is substantially the same in all other respects. Therefore, in this embodiment, the description will focus on the components, functions, and effects that differ from those of the delay circuit 10A. Components that are substantially the same as those of the delay circuit 10A are denoted by the same reference numerals, and their description will be omitted.

[0099] The delay circuit 10D further includes a PMOS transistor Q3 serving as a resistor; PMOS transistors Q1 and Q4; NMOS transistors Q2 and Q5; a capacitor 21; a constant current source 22; and, for example, a constant current source 51. The constant current source 51, serving as a second constant current source, is connected between the drain of the PMOS transistor Q4 and the drain of the NMOS transistor Q5.

[0100] Here, the relationship between the conductivity types of the first to seventh transistors in the delay circuit of this embodiment is the same as the relationship between the conductivity types of the first to seventh transistors in the delay circuit of the third embodiment. That is, the first, fourth, fifth, and seventh transistors are of the first conductivity type, and the second, third, and sixth transistors are of the second conductivity type. Figure 4 The delay circuit 10D shown as an example is one in which the first conductivity type is p-type and the second conductivity type is n-type.

[0101] Next, the operation of the delay circuit 10D will be described. Note that since the operation of the components that overlap with those of the delay circuit 10A is substantially the same, the description of the operation will be simplified or omitted.

[0102] When an L-level voltage is input to the input terminal Ti, an L-level voltage is output from the node between the drain of the PMOS transistor Q4 and the constant current source 51. The constant current source 51 supplies a predetermined constant current to the drain of the NMOS transistor Q5.

[0103] When the voltage input to the input terminal Ti changes from L to H, a delay time occurs. After the delay time, the voltage output from the node between the drain of the PMOS transistor Q4 and the constant current source 51 changes from L to H.

[0104] Here, the threshold value of the circuit including the PMOS transistor Q3, the PMOS transistor Q4, the constant current source 51, and the NMOS transistor Q5 is determined by the predetermined constant current supplied by the constant current source 51, the voltage determined by the PMOS transistor Q3, and the gate-source voltage of the PMOS transistor Q4. On the other hand, the threshold value of the circuit including the PMOS transistor Q3, the PMOS transistor Q4, and the NMOS transistor Q5, excluding the constant current source 51 connected between the drain of the PMOS transistor Q4 and the drain of the NMOS transistor Q5, is determined by the threshold voltage of the PMOS transistor Q4, the threshold voltage of the NMOS transistor Q5, and the voltage dropped by the PMOS transistor Q3.

[0105] Therefore, in a delay circuit that does not include the constant current source 51, the delay time generated is affected by the voltage VDD of the power supply terminal 3. In other words, in a delay circuit that does not include the constant current source 51 connected between the drain of the PMOS transistor Q4 and the drain of the NMOS transistor Q5, the delay time generated is highly dependent on the voltage VDD.

[0106] In contrast, in a delay circuit such as delay circuit 10D, which includes a constant current source 51 connected between the drain of PMOS transistor Q4 and the drain of NMOS transistor Q5, the generated delay time is not affected by the voltage VDD of power supply terminal 3. In other words, the generated delay time is independent of the voltage VDD.

[0107] The delay circuit 10D achieves the same effects as the delay circuit 10A. Specifically, considering the circuit size, the delay circuit 10D can achieve the same delay time as conventional circuits in a more compact size. Furthermore, considering the delay time, the delay circuit 10D can achieve a greater delay time than conventional circuits in the same size as conventional delay circuits.

[0108] Furthermore, according to the delay circuit 10D, by including the constant current source 51 , a delay time that does not depend on the voltage VDD can be generated.

[0109] Furthermore, the present invention is not limited to the above-described embodiments. In practice, the present invention can be implemented in various forms other than the above-described examples, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, in addition to the above-described configuration examples, configurations can be modified to appropriately combine the components of delay circuits 10A to 10D, such as delay circuits 10E, 10F, and 10G described later (first, second, and third modifications).

[0110] Figure 5 、 Figure 6 and Figure 7 10E, 10F, and 10G are circuit diagrams of a delay circuit according to a first modification example, a second modification example, and a third modification example, respectively, of the delay circuit according to the embodiment of the present invention.

[0111] Delay circuits 10E, 10F, and 10G are formed on a semiconductor substrate, similar to delay circuits 10A to 10D described above, and are included in semiconductor devices 1E, 1F, and 1G. Delay circuit 10E, unlike delay circuit 10B, further includes a constant current source 51. That is, delay circuit 10E, unlike delay circuit 10A, further includes a PMOS transistor Q7, an NMOS transistor Q8, a resistor 31, and a constant current source 51. Delay circuit 10E achieves the same effects as delay circuits 10A, 10B, and 10D.

[0112] Compared to the delay circuit 10C, the delay circuit 10F is further configured to include a constant current source 51. That is, compared to the delay circuit 10A, the delay circuit 10F is further configured to include a PMOS transistor Q9, an inverter 41, and a constant current source 51. The delay circuit 10F can achieve the same effects as the delay circuits 10A, 10C, and 10D.

[0113] Compared to delay circuit 10E, delay circuit 10G is further configured to include a PMOS transistor Q9, inverter 41, and inverter 61. That is, compared to delay circuit 10A, delay circuit 10G is further configured to include a PMOS transistor Q7, an NMOS transistor Q8, a resistor 31, a constant current source 51, a PMOS transistor Q9, inverter 41, and inverter 61. Inverter 61 has an input terminal connected to node N2 and an output terminal connected to node N3. Delay circuit 10G achieves the same effects as delay circuits 10A, 10B, 10C, and 10D.

[0114] Alternatively, the delay circuit 10G may be configured by omitting at least one of the two inverters 41 and 61 and the constant current source 51. In the delay circuit 10G in which the two inverters 41 and 61 are omitted, the voltage output from the drain of the PMOS transistor Q4 is directly applied to the gate of the PMOS transistor Q9.

[0115] Furthermore, the delay circuit of the present embodiment described above may also employ a configuration in which the voltage level of the voltage input to the input terminal Ti is inverted and the voltage is output from the output terminal To. In this case, for example, the delay circuit 10G can be modified by changing the connection position of the inverter 41 or the inverter 61. Specifically, in the delay circuit 10G, the inverter 61 may be provided in the path connecting the node N3 and the gate of the PMOS transistor Q9, or the inverter 41 may be provided in the path connecting the node N2 and the node N3.

[0116] Furthermore, as another configuration example of the delay circuit of the embodiment, a configuration may be adopted in which the conductivity types (p-type and n-type) of the semiconductor elements and the connection relationships between the terminals and the elements are reversed compared to the delay circuit described above.

[0117] The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims

1. A delay circuit, characterized in that: include: a first transistor having a gate connected to the input terminal, a source connected to a power supply terminal for supplying a first power supply voltage, and a drain; a capacitor having a first end connected to a power supply terminal supplying the first power supply voltage and a second end connected to a drain of the first transistor; a second transistor having a gate connected to the gate of the first transistor and the input terminal, a drain connected to the drain of the first transistor and the second end of the capacitor, and a source; a first constant current source connected between a source of the second transistor and a power supply terminal that supplies a second power supply voltage different from the first power supply voltage; a third transistor having a gate, a source connected to a power supply terminal for supplying the second power supply voltage, and a drain, wherein the gate of the third transistor is connected to a node formed by the drain of the first transistor, the drain of the second transistor, and the second end of the capacitor; a fourth transistor having a gate connected to the node and the gate of the third transistor, a drain connected to the drain of the third transistor and an output terminal, and a source; as well as a resistor having a first end connected to the source of the fourth transistor and a second end connected to a power supply terminal for supplying the first power supply voltage; and The first transistor and the fourth transistor are first conductivity type metal oxide semiconductor transistors, which are either p-type or n-type. The second transistor and the third transistor are second conductivity type metal oxide semiconductor transistors, which is the other of p-type and n-type.

2. The delay circuit according to claim 1, wherein: Also includes: a fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor are further connected between the drain of the fourth transistor and the output terminal; as well as a resistor having a first end and a second end; and The fifth transistor is a first conductive type metal oxide semiconductor transistor having a gate connected to the drain of the fourth transistor, a source connected to a power supply terminal for supplying the first power supply voltage, and a drain connected to the first end of the resistor. The sixth transistor is a second-conductivity-type metal oxide semiconductor transistor having a gate connected to the gate of the fifth transistor and the drain of the fourth transistor, a source connected to the power supply terminal supplying the second power supply voltage, and a drain connected to the second end of the resistor and the output terminal.

3. The delay circuit according to claim 2, wherein: The resistor is a diode having a first end connected to the source of the fourth transistor and a second end connected to a power supply terminal for supplying the first power supply voltage, and The delay circuit includes a seventh transistor having a gate connected to the drain of the sixth transistor, the second end of the resistor and the output terminal, a source connected to the power supply terminal supplying the first power supply voltage, and a drain connected to the source of the fourth transistor and the first end of the diode.

4. The delay circuit according to claim 3, wherein: A voltage is supplied to the gate of the seventh transistor based on a voltage output from the drain of the fourth transistor.

5. The delay circuit according to claim 1, wherein: The resistor is a diode having a first end connected to the source of the fourth transistor and a second end connected to a power supply terminal for supplying the first power supply voltage, and The delay circuit includes: a seventh transistor having a gate, a source connected to a power supply terminal supplying the first power supply voltage, and a drain connected to a source of the fourth transistor and a first end of the diode; and The inverter has an input terminal connected to the drain of the fourth transistor and an output terminal connected to the gate of the seventh transistor.

6. The delay circuit according to claim 1, wherein: The resistor is a diode having a first end connected to the source of the fourth transistor and a second end connected to a power supply terminal for supplying the first power supply voltage, and The delay circuit includes a seventh transistor having a gate, a source connected to a power supply terminal for supplying the first power supply voltage, and a drain connected to the source of the fourth transistor and the first end of the diode; A voltage is supplied to the gate of the seventh transistor based on a voltage output from the drain of the fourth transistor.

7. The delay circuit according to any one of claims 1 to 6, characterized in that A second constant current source is included, and the second constant current source is connected between the drain of the fourth transistor and the drain of the third transistor.

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