Oscillation signal generation circuit and filtering circuit

Abstract

A filtering circuit includes a filter, a frequency divider, and a control circuit. The filter is used to generate a first oscillation signal according to a control signal in a first mode, and perform filtering processing according to the control signal in a second mode. The frequency of the first oscillation signal is determined according to the control signal. The frequency divider is coupled to the filter and used to divide the frequency of the first oscillation signal to generate a divided signal. The control circuit is coupled to the filter and the frequency divider and used to compare the frequency of the divided signal with the frequency of a second oscillation signal in the first mode to adjust the control signal. The center frequency of the passband of the filter in the second mode is determined according to the adjusted control signal.

Description

Technical Field

[0001] The present invention relates to a signal generation circuit, and more particularly to an oscillation signal generation circuit including a filter circuit. Background Art

[0002] When a direct up-conversion transmitter generates an output signal, a voltage-controlled oscillator is used to generate a signal to a mixer, and then the mixer mixes the signals to generate a mixed signal including a main frequency. Then, a filter is used to retain the signal with the main frequency and eliminate unwanted harmonics. However, when the mixed signal has a large bandwidth, the center frequency of the filter is usually selected by adjusting the current of the buffer amplifier and combining amplitude detection, and then through an appropriate algorithm. The above prior art is quite time-consuming to execute, and the unwanted harmonics in the mixed signal will affect the amplitude detection and reduce the accuracy. Therefore, how to quickly and accurately select the center frequency of the filter has become one of the problems that the field is eager to solve. Summary of the Invention

[0003] The present invention discloses a filter circuit, which includes a filter, a frequency divider, and a control circuit. The filter is used to generate a first oscillation signal according to a control signal in a first mode, and perform filtering processing according to the control signal in a second mode. The frequency of the first oscillation signal is determined according to the control signal. The frequency divider is coupled to the filter circuit and is used to divide the frequency of the first oscillation signal to generate a divided signal. The control circuit is coupled to the filter circuit and the frequency division circuit and is used to compare the frequency of the divided signal with the frequency of a second oscillation signal in the first mode to adjust the control signal. The center frequency of the passband of the filter in the second mode is determined according to the adjusted control signal.

[0004] The present invention discloses an oscillation signal generation circuit, which includes a filter circuit and an oscillator circuit. The filter circuit generates a first oscillation signal in a first mode, receives a second oscillation signal to adjust the frequency of the first oscillation signal, and performs filtering processing on an input signal in a second mode to generate an output signal. The center frequency of the passband of the filter circuit is determined according to the adjusted frequency of the first oscillation signal.

[0005] Compared with the known technology, the oscillation signal generation circuit of the present application can dynamically and quickly select the center frequency of the filter, reduce the time occupied by selecting the center frequency, and can reduce the influence of harmonics on amplitude detection and improve the accuracy. Brief Description of the Drawings

[0006] The embodiments of the present application can be best understood when reading the following embodiments and the accompanying drawings. It should be noted that, according to the standard operating habits in the art, the various features in the figures are not drawn to scale. In fact, in order to describe clearly, the sizes of some features may be deliberately enlarged or reduced.

[0007] Figure 1 In some embodiments of the present invention, it is a schematic diagram of an oscillation signal generation circuit.

[0008] Figure 2 In some embodiments of the present invention, it is a schematic diagram of a filter circuit.

[0009] Figure 3 In some embodiments of the present invention, it is a schematic diagram of the operation of an oscillation signal generation circuit. Detailed Embodiments

[0010] When describing the frequency of a signal in the present application, those of ordinary skill in the art should understand that the frequency is the maximum frequency in the bandwidth of the signal. For example, the frequency is the position where the peak is located after the signal is Fourier-transformed, where the bandwidth is the full width at half maximum (FWHM) of the frequency distribution of the signal. In some embodiments, the frequency is the center frequency of the signal. Therefore, when describing the frequency of a signal in the present application, it does not mean that the signal only has that frequency, and it may include components of other frequencies.

[0011] Figure 1 According to some embodiments of the present invention, it is a schematic diagram of an oscillation signal generation circuit 10. The oscillation signal generation circuit 10 can operate in a first mode and a second mode to generate an oscillation signal Sosc, such as a local oscillation signal including an in-phase signal I and a quadrature signal Q. For example, in the first mode, the oscillation signal generation circuit 10 can select (or determine) the frequency of the oscillation signal Sosc according to the oscillation signal S1. In the second mode, the oscillation signal generation circuit 10 can generate the oscillation signal Sosc according to the oscillation signal S1 and the selected / determined frequency.

[0012] For ease of understanding, hereinafter, the first mode and the second mode are respectively referred to as the calibration mode and the normal mode. However, the present invention is not limited thereto. In this embodiment, in the calibration mode, the oscillation signal generation circuit 10 is used to generate an oscillation signal S2 based on the oscillation signal S1, and determine the frequency fout of the output signal Sout in the normal mode according to the frequency f2 of the oscillation signal S2. In the normal mode, the oscillation signal generation circuit 10 can generate the output signal Sout based on the oscillation signal S1 and the frequency fout determined in the calibration mode, and then generate the oscillation signal Sosc. That is to say, the frequency of the oscillation signal Sosc can be determined / calibrated in advance in the calibration mode.

[0013] For example, when starting the oscillation signal generation circuit 10, the oscillation signal generation circuit 10 first enters the calibration mode. In the calibration mode, after the oscillation signal generation circuit 10 determines the frequency f2 of the oscillation signal S2 that can match the frequency f1 of the oscillation signal S1 based on the oscillation signal S1, the oscillation signal generation circuit 10 then enters the normal mode. So that the oscillation signal generation circuit 10 can obtain the output signal Sout based on the frequency f2 of the oscillation signal S2 in the normal mode.

[0014] As Figure 1 shown, the oscillation signal generation circuit 10 includes an oscillator circuit 100, a filter circuit 200, and an oscillation source 300 (such as a crystal oscillator). The oscillator circuit 100 is coupled to the oscillation source 300, and the filter circuit 200 is coupled to the oscillator circuit 100. The filter circuit 200 is also coupled to the oscillation source 300.

[0015] In the normal mode, the oscillator circuit 100 is used to generate an input signal Sin based on the oscillation signal S1, where the input signal Sin has a frequency fin. The oscillator circuit 100 includes a phase-locked loop PLL, an oscillator VCO, a frequency division circuit D2, and a mixer DSB. The phase-locked loop PLL receives the oscillation signal S1 and the frequency control signal N fed back by the oscillator VCO to generate a frequency signal Sp. The oscillator VCO generates an oscillation signal S3 according to the frequency signal Sp. The frequency division circuit D2 divides the oscillation signal S3 to generate an oscillation signal S4. The mixer DSB is used to mix the oscillation signal S3 and the oscillation signal S4 to generate the input signal Sin. In some embodiments, the frequency fin is equal to the sum of the frequency f3 of the oscillation signal S3 and the frequency f4 of the oscillation signal S4, that is, the input signal Sin is the sum frequency signal of the oscillation signal S3 and the oscillation signal S4. In some embodiments, the frequency division circuit D2 divides the frequency f3 of the oscillation signal S3 by 2 to generate the oscillation signal S4, that is, the frequency f4 is half of the frequency f3.

[0016] As Figure 1As shown, the filter circuit 200 includes a filter 210 , a frequency divider 220 and a control circuit 230 . The filter 210 is coupled to the mixer DSB, the frequency divider 220 and the control circuit 230 in the oscillator circuit 100 . The frequency divider 220 is coupled to the control circuit 230 . The control circuit 230 is also coupled to the oscillation source 300 .

[0017] In the general mode, the filter circuit 200 is used to filter the input signal Sin to generate the output signal Sout. The filter 210 receives the input signal Sin and filters the input signal Sin according to the passband of the filter 210 to generate the output signal Sout. In some embodiments, the filter 210 can be implemented as a bandpass filter. In some embodiments, the filter 210 also operates as an amplifier to amplify the input signal Sin.

[0018] In the calibration mode, the filter circuit 200 generates an oscillation signal S2 according to the oscillation signal S1. The frequency divider 220 is used to divide the oscillation signal S2 according to the frequency division factor to generate a frequency division signal Sd. The control circuit 230 is used to receive the oscillation signal S1 and generate a control signal Sc according to the frequency division signal Sd and the oscillation signal S1. The filter 210 also determines the frequency f2 of the oscillation signal S2 according to the control signal Sc to adjust and update the oscillation signal S2.

[0019] In some embodiments, the oscillation signal generating circuit 10 further includes an oscillation signal generator 400, for example, an I / Q signal generator that can decompose the oscillation signal into an in-phase part and a quadrature part. Figure 1 As shown, in the normal mode, the oscillation signal generator 400 receives the output signal Sout and generates an in-phase signal I and a quadrature signal Q accordingly.

[0020] In some embodiments, the oscillation signal generating circuit 10 further includes an input switch SW1 and an output switch SW2. The input switch SW1 is coupled between the oscillator circuit 100 and the filter circuit 200, and the output switch SW2 is coupled between the filter circuit 200 and the oscillation signal generator 400. The input switch SW1 and the output switch SW2 are used to be turned off in the calibration mode and turned on in the normal mode. In some embodiments, at least one of the input switch SW1 and the output switch SW2 may be included in the filter circuit 200. In some embodiments, the input switch SW1 may be integrated in the filter circuit 200.

[0021] refer to Figure 2 . Figure 2 According to some embodiments of the present application Figure 1 The filter 210 of the filter circuit 200 includes an output terminal T, a frequency selection circuit 212, an oscillating circuit 214 and an amplifier circuit 216.Figure 2 As shown, in filter 210, frequency selection circuit 212, startup circuit 214, and amplifier circuit 216 are coupled to output terminal T. Divider 220 is coupled to filter 210 at output terminal T. Control circuit 230 is coupled to frequency selection circuit 212 to provide control signal Sc.

[0022] In the calibration mode, frequency selection circuit 212 can set the frequency f2 of oscillation signal S2 according to control signal Sc. Startup circuit 214 is used to provide current (represented by bias current i1) to frequency selection circuit 212 via output terminal T to generate oscillation signal S2 at output terminal T. Startup circuit 214 can generate oscillation signal S2 according to the frequency f2 set by frequency selection circuit 212.

[0023] In some embodiments, frequency selection circuit 212 can be implemented using a resonator. The frequency f2 of oscillation signal S2 can be equal to the resonance frequency of the resonator. In some embodiments, the resonator can be an LC resonator, which has a variable capacitor and an inductor. In some embodiments, frequency selection circuit 212 adjusts the capacitance value of the variable capacitor according to control signal Sc to adjust the resonance frequency of the resonator. For example, control signal Sc can be implemented by a frequency control word (FCW).

[0024] In some embodiments, startup circuit 214 includes cross-coupled transistor pair CP and current source I1. Cross-coupled transistor pair CP is coupled between output terminal T and current source I1. Current source I1 is used to provide bias current i1, and cross-coupled transistor pair CP is used to generate oscillation signal S2 at output terminal T according to bias current i1.

[0025] In the calibration mode, amplifier circuit 216 can be disconnected so that it does not perform signal amplification operations. For example, amplifier circuit 216 can stop providing current (represented by bias current i2). Since amplifier circuit 216 can be disconnected in the calibration mode, output terminal T, frequency selection circuit 212, and startup circuit 214 can operate as a voltage-controlled oscillator, which adjusts the frequency f2 of the generated oscillation signal S2 by control signal Sc. The operation details are described as follows.

[0026] In the calibration mode, the control circuit 230 compares the frequency f1 of the oscillation signal S1 with the frequency fd of the frequency division signal Sd. When the frequency fd is greater than the frequency f1, the control circuit 230 may adjust the control signal Sc to reduce the frequency set by the frequency selection circuit 212, thereby reducing the frequency f2 of the oscillation signal S2 generated by the oscillation circuit 214 at the output terminal T. When the frequency fd is less than the frequency f1, the control circuit 230 may adjust the control signal Sc to increase the frequency set by the frequency selection circuit 212, thereby increasing the frequency f2 of the oscillation signal S2 generated by the oscillation circuit 214 at the output terminal T. In other words, the control circuit 230 may determine whether to increase or decrease the frequency f2 of the oscillation signal S2 based on the frequency fd of the frequency division signal Sd. In some embodiments, the frequency f2 of the oscillation signal S2 may be adjusted to be equal to or substantially equal to the center frequency predetermined to be adopted by the filter 210.

[0027] The center frequency of the filter 210 may be greater than the frequency f1 of the oscillation signal S1. In order to enable the control circuit 230 to determine the magnitude of the frequency f2 of the oscillation signal S2, the frequency divider 220 divides the oscillation signal S2 so that the frequency fd of the divided signal Sd is close to the frequency f1 of the oscillation signal S1.

[0028] In some embodiments, the current value of the bias current i1 generated by the current source I1 in the calibration mode is greater than a threshold value. When the current value of the bias current i1 is greater than the threshold value, the oscillator circuit 214 is in an oscillating state to generate an oscillation signal S2 at the output terminal T. In other words, the bias current i1 having a current value greater than the threshold value can cause the frequency selection circuit 212 and the oscillator circuit 214 to operate as an oscillator to generate the oscillation signal S2. In addition, when the current value of the bias current i1 is less than the threshold value, the oscillator circuit 214 is in a non-oscillating state. The bias current i1 having a current value less than the threshold value is not sufficient to cause the frequency selection circuit 212 and the oscillator circuit 214 to operate as an oscillator.

[0029] In the normal mode, the amplifier circuit 216 is used to receive the input signal Sin and provide a current (represented by the bias current i2) to the frequency selection circuit 212 via the output terminal T to amplify the input signal Sin and generate at least a portion of the output signal Sout at the output terminal T. The filter 210 can perform filtering processing on the input signal Sin according to the frequency f2 of the oscillation signal S2 set by the frequency selection circuit 212 in the calibration mode. The output signal Sout obtained after the input signal Sin is filtered is output at the output terminal T.

[0030] In this embodiment, the amplifier circuit 216 includes a transistor M1, a transistor M2 and a current source I2, wherein the transistor M1 and the transistor M2 are coupled between the output terminal T and the current source I2. The control terminals of the transistor M1 and the transistor M2 are used to receive the input signal Sin, amplify the input signal Sin according to the bias current i2 provided by the current source I2, and filter the input signal Sin according to the frequency f2 set by the frequency selection circuit 212 (for example, the center frequency predetermined to be used by the filter 210). After the input signal Sin passes through the amplifier circuit 216, the frequency fout of the corresponding output signal Sout is within the frequency range covered by the passband of the filter 210. In some embodiments, because the center frequency of the passband can be equal to or substantially equal to the frequency f2 of the oscillation signal S2, the frequency fout of the output signal Sout can be equal to or substantially equal to the frequency f2.

[0031] In the normal mode, the oscillator circuit 214 does not oscillate. For example, in some embodiments, the oscillator circuit 214 stops providing the bias current i1 to the frequency selection circuit 212. For another example, in some embodiments, the oscillator circuit 214 provides the bias current i1 having a current value less than the threshold to the frequency selection circuit 212, so that the oscillator circuit 214 cannot oscillate. When the current value of the bias current i1 is less than the threshold and the oscillator circuit 214 does not oscillate, the bias current i1 is provided to the amplifier circuit 216 through the output terminal T, so that the oscillator circuit 214 can generate a part of the output signal Sout at the output terminal T. It is worth noting that the oscillator circuit 214 can act as a negative resistor connected to the output terminal T and provide additional gain to improve the quality factor (Qfactor) of the frequency selection circuit 212.

[0032] In some embodiments, the input signal Sin and the output signal Sout are differential pair signals. The positive input signal Sin+ and the negative input signal Sin- of the input signal Sin are respectively input to the control terminals of the transistor M1 and the transistor M2, and the amplifier circuit 216 is used as a differential amplifier circuit. The output terminal T includes a positive output terminal T+ and a negative output terminal T-, which are respectively used to output the positive output signal Sout+ and the negative output signal Sout- of the output signal Sout. In some embodiments, the frequency divider 220 is coupled to at least one of the positive output terminal T+ and the negative output terminal T-. The frequency divider 220 generates the frequency divided signal Sd according to at least a portion of the oscillation signal S2.

[0033] refer to Figure 3 . Figure 3 FIG. 1 is a schematic diagram of the operation of the oscillation signal generating circuit 10 in some embodiments of the present invention. Figure 3Illustrates the relationship between the frequency signal Sp and the oscillation signal S2 in the calibration mode and the normal mode, where the horizontal axis is time t and the vertical axis is frequency f. The time period P1 represents the calibration mode, and the time period P2 represents the normal mode.

[0034] Before the oscillation signal generation circuit 10 enters the normal mode, the phase-locked loop PLL can first lock the frequency of the frequency signal Sp and thereby lock the frequency fin of the input signal Sin. The filter circuit 200 then determines / corrects the center frequency of the passband by setting the frequency f2 of the oscillation signal S2. Therefore, the oscillation signal generation circuit 10 operates in the calibration mode during the time period P1, causing the phase-locked loop PLL to lock the frequency fin and the filter circuit 200 to determine the frequency f2. Since the frequencies fin and f2 are known, after the input switch SW1 is turned on, the oscillation signal generation circuit 10 can enter the normal mode (as shown by the time period P2 in Figure 3 ). It should be noted that the filter circuit 200 can complete the center frequency correction before the phase-locked loop PLL completes the frequency locking. Therefore, the oscillation signal generation circuit 10 can dynamically and quickly select the center frequency of the filter circuit 200 without occupying the operation time of the system.

[0035] Description of reference numerals:

[0036] 10: Oscillation signal generation circuit

[0037] 100: Oscillator circuit

[0038] 200: Filter circuit

[0039] 300: Oscillation source

[0040] 400: Oscillation signal generator

[0041] PLL: Phase-locked loop

[0042] VCO: Voltage-controlled oscillator

[0043] DSB: Double-sideband mixer

[0044] D2: Frequency divider circuit

[0045] 210: Filter

[0046] 212: Frequency selection circuit

[0047] 214: Starting circuit

[0048] 216: Amplifier circuit

[0049] 220: Frequency divider

[0050] 230: Control circuit

[0051] T: Output terminal

[0052] T+: Positive output terminal

[0053] T-: Negative output terminal

[0054] M1: Transistor

[0055] M2: Transistor

[0056] I1: Current source

[0057] i1: Bias current

[0058] I2: Current source

[0059] i2: Bias current

[0060] CP: Cross-coupled transistor pair

[0061] Sin: Input signal

[0062] Sin+: Positive input signal

[0063] Sin-: Negative input signal

[0064] Sout: Output signal

[0065] Sosc: Oscillation signal

[0066] S1: Oscillation signal

[0067] S2: Oscillation signal

[0068] S3: Oscillation signal

[0069] S4: Oscillation signal

[0070] Sd: Divided-frequency signal

[0071] Sc: Control signal

[0072] Sp: Frequency signal

[0073] SW1: Input switch

[0074] SW2: Output switch

[0075] I: Signal

[0076] Q: Signal

[0077] N: Frequency control signal

[0078] t: Time

[0079] f: Frequency

[0080] P1: Time period

[0081] P2: Time period

Claims

1. A filter circuit, comprising: A filter, configured to generate a first oscillation signal according to a control signal in a first mode, and filter an input signal according to the control signal to generate an output signal in a second mode, wherein the frequency of the first oscillation signal is determined according to the control signal; A frequency divider, coupled to the filter, configured to divide the frequency of the first oscillation signal to generate a divided signal; And A control circuit, coupled to the filter and the frequency divider, configured to compare the frequency of the divided signal with the frequency of a second oscillation signal in the first mode to adjust the control signal, wherein the center frequency of the passband of the filter in the second mode is determined according to the adjusted control signal, wherein the frequency of the output signal is equal to the frequency of the first oscillation signal generated by the filter according to the adjusted control signal.

2. The filter circuit according to claim 1, wherein when the frequency of the divided signal is greater than the frequency of the second oscillation signal, the control circuit is configured to adjust the control signal to reduce the frequency of the first oscillation signal output by the filter, and when the frequency of the divided signal is less than the frequency of the second oscillation signal, the control circuit is configured to adjust the control signal to increase the frequency of the first oscillation signal output by the filter.

3. The filter circuit according to claim 1, wherein the filter comprises: An output terminal; A frequency selection circuit, coupled to the output terminal, configured to set the frequency of the first oscillation signal according to the control signal in the first mode, and set the center frequency of the passband according to the control signal in the second mode; An oscillation starting circuit, coupled to the output terminal, configured to supply a first current to the frequency selection circuit via the output terminal in the first mode to generate the first oscillation signal at the output terminal; And An amplifier circuit, coupled to the output terminal, configured to supply a second current to the frequency selection circuit via the output terminal in the second mode to amplify the input signal and generate at least a part of the output signal at the output terminal.

4. The filter circuit according to claim 3, wherein in the first mode, the current value of the first current is greater than a threshold value, and the oscillation starting circuit is in an oscillating state to generate the first oscillation signal at the output terminal, and in the second mode, the current value of the first current is less than the threshold value, and the oscillation starting circuit is in a non-oscillating state to generate another part of the output signal at the output terminal.

5. An oscillation signal generating circuit, comprising: A filter circuit, configured to generate a first oscillation signal in a first mode, receive a second oscillation signal to adjust the frequency of the first oscillation signal, and filter an input signal to generate an output signal in a second mode, wherein the center frequency of the passband of the filter circuit is determined according to the adjusted frequency of the first oscillation signal; And An oscillator circuit, coupled to the filter circuit, configured to receive the second oscillation signal to generate the input signal, wherein the frequency of the output signal is equal to the adjusted frequency of the first oscillation signal.

6. The oscillation signal generating circuit according to claim 5, further comprising: An input switch is selectively coupled between the oscillator circuit and the filter circuit, and is used to disconnect in the first mode and conduct in the second mode.

7. The oscillating signal generating circuit according to claim 5 further includes: An oscillating signal generator for modulating the output signal in the second mode; And An output switch is selectively coupled between the oscillating signal generator and the filter circuit, and is used to disconnect in the first mode and conduct in the second mode.

8. The oscillating signal generating circuit according to claim 5, wherein the filter circuit includes: A filter for generating the first oscillating signal in the first mode and generating the output signal in the second mode; A frequency divider for dividing the frequency of the first oscillating signal to generate a divided signal; And A control circuit for comparing the divided signal with the second oscillating signal to generate a control signal, wherein the filter is further used to adjust the frequency of the first oscillating signal according to the control signal.

9. The oscillating signal generating circuit according to claim 8, wherein the filter includes: A frequency selection circuit for setting the frequency of the first oscillating signal according to the control signal in the first mode and setting the center frequency of the passband according to the control signal in the second mode; An oscillation starting circuit for supplying a first current to the frequency selection circuit to generate the first oscillating signal in the first mode and generate a first part of the output signal in the second mode; And An amplifier circuit for supplying a second current to the frequency selection circuit in the second mode to amplify the input signal and generate a second part of the output signal.

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