Spacetime integral fusion and related systems, methods, and apparatus

Abstract

Systems, devices, and methods of operating a memory system are described. Memory-in-process-enabled memory devices and methods of performing sum and fuse-add operations within the memory-in-process-enabled memory devices are also described. Bit positions of bits stored at one or more portions of one or more memory arrays can be accessed via data lines by activating the same or different access lines. Sense circuits operatively coupled to the data lines can be temporarily formed and measured to determine a state (e.g., a count of a number of bits that are logical "1"s) of the accessed bit positions of the data lines, and the state information can be used to determine a result of a computation.

Description

[0001] Priority Statement

[0002] This application enters the national phase of international patent application PCT / US2020 / 070372, filed August 5, 2020, designating the People's Republic of China, and published in English as WO 2021 / 046566 A1 on March 11, 2021. This application claims the benefit of U.S. Provisional Patent Application Serial No. 62 / 896,242, filed September 5, 2019, concerning "Spatiotemporal Fused-Multiply-Add, and Related Systems, Methods and Devices," and U.S. Patent Application Serial No. 16 / 888,345, filed May 29, 2020, concerning "Spatiotemporal Fused-Multiply-Add, and Related Systems, Methods and Devices," pursuant to Article VIII of the Patent Cooperation Treaty. Technical Field

[0003] Embodiments of this disclosure relate to processing-in-memory, and more specifically, to processing dot product operations in memory on a memory array. More specifically, some embodiments relate to methods for processing in memory that enable dot product operations to be performed within a memory device, and related memory devices, memory systems, and electronic systems. More specifically, some embodiments relate to methods for processing in memory that enable product and fused-multiply-add operations to be performed within a memory device, and related memory devices, memory systems, and electronic systems. Background Technology

[0004] Memory devices are typically provided as internal, semiconductor-based integrated circuits in computers or other electronic systems. Many different types of memory exist, including volatile and non-volatile memory. Non-volatile memory can retrieve stored information after a power cycle and, among others, may include, but is not limited to, flash memory containing NAND or NOR flash memory, 3D XPoint memory, and ReRAM. Volatile memory may require power to maintain its data (e.g., host data, erroneous data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), content-addressable memory (CAM), and thyristor random access memory (TRAM), etc.

[0005] Electronic systems typically include multiple processing resources (e.g., one or more processors) that can retrieve and execute instructions and store the results of instruction execution in appropriate locations. A processor may include multiple functional units, such as arithmetic logic unit (ALU) circuitry, floating-point unit (FPU) circuitry, and combinational logic blocks. These functional units can be used to execute instructions by performing operations on data (e.g., one or more operands). As used herein, operations can include, for example, Boolean operations such as AND, OR, NOT, NAND, NOR, and XOR, and / or other operations (e.g., inversion, shifting, arithmetic, statistical, and many other possible operations). For example, the functional unit circuitry can be used to perform arithmetic operations such as addition, subtraction, multiplication, and division on operands through multiple operations.

[0006] Many components in an electronic system may involve providing instructions to a functional unit circuit system for execution. For example, these instructions can be executed by processing resources such as controllers and / or host processors. Data (e.g., data on which instructions can be executed) can be stored in a memory array accessible by the functional unit circuit system. Instructions and / or data can be retrieved from the memory array and ordered and / or buffered before the functional unit circuit system begins executing instructions on the data. Summary of the Invention

[0007] One or more instances relate to a method comprising: selecting a first bit location of a first bit of an operand stored in a first portion of a memory array for access, the first bit being accessible via a first data line. The method further comprises activating a first access line associated with the selected first bit location. The method further comprises accessing the first bit of the operand. The method further comprises receiving at least a portion of a computation result in response to the accessed first bit.

[0008] The method further optionally includes: selecting a first bit position of the first bit position of the operand in response to the value of a bit at the first bit position of the operator; and selecting a second bit position of the first bit position of the operand in response to the value of a bit at the second bit position of the operator. The method further optionally includes: generating a partial computation result at least in part based on the number of accessed first bits having specified bit values. The method of generating the partial computation result optionally includes: generating a summation result and carrying over. The method further includes: selecting a second bit position of the second bit of the operand for access. The method optionally includes activating a second access line associated with the selected second bit position. The method may also include accessing the second bit of the operand in response to the activated second access line. The method further optionally includes: receiving a first partial computation result in response to the accessed second bit. The method optionally includes receiving a second partial computation result in response to the accessed second bit. The method optionally includes combining the first partial computation result and the second partial computation result. The method further optionally includes: accessing the first data line at the first position using one or more of the first data line, memory elements, the first access line, and any combination or sub-combination thereof. The method further optionally includes: accessing the first data line at a corresponding first position using a parallel resistor network comprising the first data line, memory elements, and the first access line. The method of accessing the first data line optionally includes: placing a first number of series-coupled memory elements in a low-impedance mode; and, when a second number of series-coupled memory elements are in a default impedance mode: accessing a second number of series-coupled memory elements; and determining the second number of accessed series-coupled memory elements having a specified bit value. The method further optionally includes: coupling the first access line to a specified level. The method optionally includes providing a driver signal to the first data line. The method may also include reading a signal at the first data line. The method optionally includes: accessing a bit group of the first data line. The method may also include receiving intermediate calculations in response to the state of the accessed bit group of the first data line. The method may further include combining the intermediate calculations to obtain a partial calculation result. The method may further optionally include accessing a second bit at the first bit position of a second operand stored in a second portion of the memory array, the second bit being accessible via a second data line in response to an activated first access line. The method may further optionally include outputting bits common to all operator sequences. The method may optionally include assigning unique operators using operands. The method may further include activating an access line in response to determining that an operator bit is logic high.

[0009] One or more examples relate to a system comprising: a data line; an access line; a bit quantizer coupled to the data line, wherein the bit quantizer is configured to determine one or more states of the data line; and a computation unit configured to provide a computation result in response to the one or more states of the data line.

[0010] The system optionally further includes a bit aligner configured to activate one or more of the access lines. Optionally, the access lines are configured to be activated by operatively coupled to a specified level. Optionally, the computing unit is configured to asynchronously provide partial computation results corresponding to the state of the data lines. Optionally, the bit quantizer includes a voltage divider. The system optionally includes an input quantizer. The system may also optionally include an encoder. The system optionally includes a plurality of memory elements serially coupled to form the data lines and the access lines. Optionally, the computing unit is configured to obtain partial computation results corresponding to the respective states of the data lines and combine the partial computation results to obtain the final computation result. The system further includes a memory, wherein the computing unit is configured to store intermediate partial computations in the memory. The system optionally obtains partial computations at least in part based on the intermediate partial computations stored in the memory.

[0011] One or more examples relate to a circuit comprising: a first line. The circuit further comprises a plurality of second lines configured to be coupled to the first line, wherein each corresponding second line is configured to be coupled to the first line via a memory element and includes an activation element configured to alternately couple and decouple the first line to a specified voltage level. The circuit further comprises a circuit system coupled to terminals arranged such that the circuit system can measure voltage across a parallel network activated by operatively coupling the first line to a reference node.

[0012] In the circuit, a reference node is optionally arranged relative to the parallel network such that the reference node acts as a voltage divider during voltage measurement. Attached Figure Description

[0013] To facilitate identification of any particular element or action in the discussion, one or more of the most significant digits in the reference numerals refer to the drawing number in which the element is first introduced.

[0014] Figure 1A block diagram of a system including a memory device according to several embodiments of the present disclosure is shown.

[0015] Figure 2 A functional block diagram of a system 200 according to one or more embodiments is shown.

[0016] Figure 3 A diagram of spatiotemporal FMA according to one or more embodiments is shown.

[0017] Figure 4 A circuit diagram representing a resistive memory according to one or more embodiments is shown.

[0018] Figure 5 A functional block diagram of a readout amplifier controller according to one or more embodiments is shown.

[0019] Figure 6 A circuit diagram of a readout circuit for performing a spacetime FMA according to one or more embodiments is shown.

[0020] Figure 7 A circuit diagram of a readout circuit for performing a spacetime FMA according to one or more embodiments is shown.

[0021] Figure 8 A circuit diagram representing a NAND serial memory according to one or more embodiments is shown.

[0022] Figure 9 A circuit diagram of a readout circuit for performing a spacetime FMA according to one or more embodiments is shown.

[0023] Figure 10 A functional block diagram of an integrated ADC that may be included in a sense amplifier for performing spatiotemporal FMA is shown according to one or more embodiments.

[0024] Figure 11 A procedure for performing a spatiotemporal FMA according to one or more embodiments is illustrated.

[0025] Figure 12 A procedure for performing a spatiotemporal FMA according to one or more embodiments is illustrated. Detailed Implementation

[0026] Fusion-addition (FMA) and matrix multiplication operations are used in many applications, such as machine learning, image processing, artificial intelligence, system modeling (e.g., electrical systems, mechanical systems, etc.). The logic of these operations can be relatively simple (e.g., multiplication and accumulation). However, regular computer-based computation can involve processor- and memory-intensive operations, including the transfer of large amounts of data between computing cores and memory arrays.

[0027] In many cases, processing resources (e.g., processors and associated functional unit circuitry) can be located outside the memory array, and data is accessed via a bus between the processing resources and the memory array to execute instruction sets. Processing performance can be improved in processor-in-memory (PIM) devices, where the processor can be implemented inside and / or near the memory (e.g., directly on the same chip as the memory array). PIM devices can save time and / or power by reducing and eliminating external communication.

[0028] The techniques described in this article can also be applied to processing in storage (e.g., in NAND or NOR flash memory, 3DXPoint). TM (Processing, etc., can be performed on 3D cross-point memory devices, which are commercially available from Micron Technology, Inc.) PIM can also be referred to as computation in memory or computation in storage. In other words, this disclosure envisions processing or computation being performed on devices typically associated with storing or organizing data, such as memory or storage devices, which in some architectures differ from CPUs, GPUs, GPGPUs, FPGAs, ASICs, etc.

[0029] Figure 1 This is a block diagram of a system 100 including a memory device 120 according to several embodiments of the present disclosure. The memory device 120, also referred to herein as a “PIM-enabled device” or “PIM-enabled memory device,” may include any suitable memory device. For example, the memory device 120 may include volatile memory (e.g., but not limited to RAM, DRAM) and / or non-volatile memory (e.g., but not limited to flash memory, cross-point memory devices such as 3D cross-point memory devices). The memory device 120 may include a memory array 130 (i.e., containing memory cells) coupled to a readout circuitry system, as described in more detail below. According to some embodiments, the memory device 120 may include multiple memory arrays 130 organized in rows, columns, card groups, tiles, blocks, segments, or some other form.

[0030] System 100 further includes a host 111 coupled to memory device 120. Host 111 may include a host system, such as a personal laptop computer, desktop computer, digital camera, smartphone, or memory card reader, and various other types of host systems. Host 111 may include a system motherboard and / or backplane and may include multiple processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry). System 100 may include a separate integrated circuit, or host 111 and memory device 120 may both be part of the same integrated circuit (e.g., on the same chip). System 100 may include, for example, a server system and / or a high-performance computing (HPC) system and / or a portion thereof.

[0031] The host 111 may include various components, including PIM control components (e.g., control logic 131, sequencer 132), channel controller 143, and memory management unit (MMU) controller 134. Control logic 131 may be configured to execute control flow commands associated with the executing PIM program and provide compound commands to sequencer 132. Control logic 131 may be or may include a RISC-type controller configured to generate and issue a scalable set of compound operation PIM commands, which contain commands different from the DDR commands sent to sequencer 132. In some embodiments, control logic 131 may be configured to issue compound operation commands to perform bit vector operations on memory device 120. In some embodiments, compound operation commands may be transferred from control logic 131 to memory device 120 (e.g., via sequencer 132 and channel 157).

[0032] In some embodiments, control logic 131 may decode microcode instructions into function calls, which may be microcode function calls implemented by sequencer 132 associated with performing bit vector operations. The microcode function call may be an operation received and / or executed by sequencer 132 to cause memory device 120 to perform a specific bit vector operation using a readout circuitry system such as readout circuitry system 150.

[0033] As in Figure 1As shown, control logic 131 and MMU controller 134 reside on host 111, which may allow control logic 131 and / or MMU controller 134 to access virtual addresses stored on host 111 and perform virtual-to-physical address resolution (e.g., translating virtual addresses of the address space associated with an application running on host 111 into actual physical addresses of memory device 120) before transferring instructions to memory device 120. The translation can be performed at the host by looking up an address translation table (e.g., a page table) stored in memory device 120 or by performing the same operation on memory device 120. In some embodiments, control logic 131 and / or sequencer 132 reside in memory device 120, for example, in controller 140 or line decoder 146. In other embodiments, control logic 131, sequencer 132, or MMU controller 134 may be distributed such that a portion of its functionality resides on host 111 and another portion resides on memory device 120.

[0034] As used herein, a “bit vector” can refer to physically contiguous bits, whether in physically contiguous rows (e.g., horizontally oriented) or columns (e.g., vertically oriented). A PIM-enabled device can be configured to perform bit vector operations, such as logical operations and / or transfer operations, on multiple contiguous portions (e.g., “blocks”) of the physical address space. As a non-limiting example, a block of the physical address space can have a bit length of 256 bits. A block can be sequentially contiguous with other blocks in the virtual address space, or it can be non-sequentially contiguous; however, it is contiguous within the scope of a memory page. In the disclosed embodiments, the PIM-enabled device can be configured to perform the operations in the virtual address space after translating the virtual address of a virtual page to the physical address of a physical page.

[0035] The MMU controller 134 can reside on the host 111 (e.g., in...). Figure 1 As shown in the diagram, the MMU controller can be responsible for performing the translation of virtual memory addresses (e.g., addresses associated with host 111) into physical addresses (e.g., addresses associated with memory device 120). The MMU controller 134 can also perform memory protection operations, cache control, and / or bus arbitration operations.

[0036] The timing circuit system 133 can provide timing to coordinate the performance of logic operations and can be responsible for providing such timing. Figure 1The memory array 130 and other arrays in the memory array provide conflict-free access. In various embodiments, the controller 140 and / or timing management circuitry 135 can generate status information, which can be transmitted to or from the host 111, for example, via channel 157. Channel 157 can be independent of the memory interface (e.g., control bus 154) (e.g., separate from the memory interface), which can be used to transmit commands between the host 111 and the memory device 120, memory access device, or another memory interface. Non-limiting examples of memory interfaces include, but are not limited to, Double Data Rate (DDR) memory interfaces, Peripheral Component Interconnect Fast (PCIe) memory interfaces, Coherent Accelerator Processor Interface (CAPI), Compute Fast Link (CXL), Accelerator Cache Coherent Interconnect (CCIX), and combinations and sub-combinations of the foregoing.

[0037] As a non-limiting example, a DDR memory interface (e.g., control bus 154) can be used to transmit (e.g., transfer) DDR commands between host 111 and memory device 120. That is, in some embodiments, channel 157 can be used to transmit commands to induce the execution of bit-vector operations from host 111 to memory device 120, while control bus 154 can be used to transmit DRAM commands (or commands of another type of memory interface) from host 111 to memory device 120. In some embodiments, DRAM commands (or other types of commands) transmitted via control bus 154 can be commands for controlling the operation of DRAM (or commands for controlling other types of memory, memory access devices, or memory interfaces), such as, but not limited to, DDR1 SDRAM, DDR2 SDRAM, DDR3 SDRAM, DDR4, DDR5, and other versions of the DDR type protocol. In other embodiments, memory device 120 can send signals to the host via channel 157 indicating that operation is ready. In some embodiments, channel 157 is combined with control bus 154 and / or data bus 156. Furthermore, in some embodiments, the host 111 may include a plurality of memory devices 120 having multiple channels and / or control buses.

[0038] In some embodiments, the sequencer 132 may include an instruction controller, such as a Very Large Instruction Word (VLIW) type controller or a Single Instruction Multiple Data (SIMD) type controller, configured to operate on logical operation commands, and control logic 131 may be configured to issue logical operation commands to the sequencer 132 in response to signals from processing resources (e.g., CPU or GPU) (not shown) from the host 111. For example, the sequencer 132 may be configured to sequence multiple logical operations such that compound operation commands can be issued by the sequencer 132.

[0039] In some embodiments, control logic 131 may be configured to generate executable instructions, such as VLIW-type instructions or SMID-type instructions. In embodiments including a VLIW-type instruction controller, control logic 131 may be configured to generate VLIWs as bit vector operation commands. VLIWs may include microcode instructions. Sequencer 132 may be or may include a VLIW-type controller configured to decode VLIWs into multiple individual microcode instructions. For example, sequencer 132 may decode VLIWs into instructions to cause the execution of compound operations (e.g., but not limited to addition, multiplication, dot product). In some embodiments, compound operation commands may provide entry points into a sequence of VLIW instructions to cause the execution of such compound operations. In embodiments including an SMID-type instruction controller, control logic 131 may be configured to generate data units, such as but not limited to data vectors, and sequencer 132 may cause the parallel execution of a single instruction on multiple data points identified in the data units.

[0040] The sequencer 132 can be coupled to the memory device 120 and can pass commands for coordinating bit vector operations to the memory device 120 via channel 157. Microcode instructions can be executed sequentially and / or in parallel by the sequencer 132 itself and / or by other components in the memory device 120 (e.g., bit vector operation timing circuitry 139, timing circuitry 133, timing management circuitry 135, and / or readout circuitry 150).

[0041] Memory array 130 may include, for example, DRAM arrays, SRAM arrays, STT RAM arrays, PCRAM arrays, TRAM arrays, RRAM arrays, NAND flash memory arrays, and / or NOR flash memory arrays. Memory array 130 may include memory cells arranged in rows coupled by access lines (which may also be referred to herein as word lines or select lines) and columns coupled by read lines (which may also be referred to herein as data lines, bit lines, or digit lines). Although Figure 1 A single memory array is shown, but the embodiments are not limited thereto. For example, memory device 120 may include multiple memory arrays 130 (e.g., multiple memory banks of DRAM cells, NAND flash memory cells, etc.).

[0042] Memory device 120 includes an address circuitry 142 to latch address signals for data provided on data bus 156 (e.g., a data / address bus) via I / O circuitry 144. Status and / or exception information can be provided from controller 140 on memory device 120 to channel controller 143 via an interface including channel 157 (e.g., a high-speed interface (HSI)). Address signals are received via address circuitry 142 and decoded by row decoder 146 and column decoder 152 to access memory array 130. Data can be read from memory array 130 by reading the state of memory cells on the bit lines using readout circuitry 150. According to memory cell technology, the state of a memory cell can be read as, for example, voltage and / or current changes, magnetic state changes, resistivity, and quantum states, etc. Readout circuitry 150 can read and latch data pages (e.g., rows) from memory array 130. I / O circuitry 144 can be used for bidirectional data communication with host 111 via data bus 156. Write circuitry 148 can be used to write data into memory array 130. In some embodiments, write circuitry 148 is combined with read circuitry 150. In other embodiments, read circuitry 150 may be part of column decoder 152 and / or row decoder 146. In some embodiments, control bus 154 may be used as a control and address bus for DRAM control and addressing (e.g., according to a DDR protocol in which control bus 154 operates as a unidirectional data bus). Although in Figure 1 The control bus 154 and the data bus 156 are shown as separate buses, but in some embodiments, the control bus 154 and the data bus 156 may not be separate buses.

[0043] Controller 140 (e.g., a memory controller) can decode signals from host 111 provided by control bus 154. These signals may include chip enable signals, write enable signals, and address latch signals for controlling DRAM operations performed on memory array 130, including data read operations, data write operations, and data erase operations. In various embodiments, controller 140 may be responsible for executing instructions from host 111 and sequencing accesses to memory array 130. Controller 140 may include a state machine, sequencer, or some other type of controller and include hardware and / or firmware (e.g., microcode instructions) in the form of application-specific integrated circuits (ASICs). In several embodiments, controller 140 may include bit vector operation timing circuitry 139. Controller 140 may control, for example, readout circuitry 150. For example, controller 140 may control the generation and application of clock signals to compute components associated with performing bit vector operations.

[0044] As in Figure 1As shown, the bit vector operation timing circuitry system 139 may include a timing circuitry system 133 and a timing management circuitry system 135. The timing circuitry system 133 may include a FIFO buffer to provide timing coordination with the readout circuitry system 150 associated with the memory array 130 of memory cells. In some embodiments, the timing circuitry system 133 may include a state machine, such as an atomic state machine.

[0045] Timing management circuitry 135 can be configured to coordinate the timing of logical operations (e.g., sequences of logical operations) associated with bit vector operations, performed using a row address strobe (RAS) / column address strobe (CAS) component 136 associated with memory array 130. RAS component 136 can be configured to send signals (e.g., RAS / CAS signals) to memory array 130 and / or receive signals from said memory array to identify and / or select row and / or column addresses of memory array 130. In some embodiments, memory device 120 can be configured to perform DRAM operations such as memory array access requests, which can be issued by host 111 via control bus 154. In some embodiments, timing management circuitry 135 can be configured to execute instructions to control the timing of the execution of bit vector operations.

[0046] In one or more embodiments, portions of controller 140 (e.g., bit vector operation timing circuitry 139, timing circuitry 133, and / or timing management circuitry 135) may comprise a Reduced Instruction Set Computer (RISC) type controller that operates on, for example, 32- and / or 64-bit length instructions. In various embodiments, timing management circuitry 135 may be responsible for executing instructions received from timing circuitry 133 to induce bit vector operations relating to data values ​​associated with readout circuitry 150.

[0047] As further described below, in several embodiments, the readout circuitry system 150 may include multiple readout components, each of which may include a readout amplifier and a computation component. The computation component may function as an accumulator, and the readout circuitry system 150 may be used to perform bit vector operations (e.g., on data associated with complementary bit lines). In several embodiments, the readout circuitry system 150 may be used to perform bit vector operations using data stored in the memory array 130 as input and / or store the results of the operations back to the memory array 130 without transferring data via bit line address access (e.g., without issuing column decoding signals). For example, various operations (e.g., bit vector operations) may be performed using and within the readout circuitry system 150, rather than via processing resources outside the readout circuitry system 150 (e.g., via processing resources associated with host 111 and / or other processing circuitry such as ALU circuitry located on memory device 120 (e.g., controller 140 or elsewhere). In many embodiments, the readout circuitry system 150 (e.g., the plurality of readout components) can be used to perform bit vector operations in a SIMD (Single Instruction Multiple Data) manner, wherein the readout components are used as 1-bit processing elements on a per-column basis.

[0048] In other embodiments, adjacent readout components may exchange data bits with each other, thus generating computations based on multiple data sources. In other embodiments, readout components may generate different computations depending on their location within the readout circuitry system 150, thus providing computations in a VLIW or SIMD manner. In embodiments where the readout circuitry system 150 performs bit vector operations, the readout circuitry system 150 may be used as and / or referred to as a "processor in memory". As described more fully below, in some embodiments, the readout circuitry system 150 may include a sequencer (e.g., similar to sequencer 132).

[0049] In various methods, for example, data associated with operands can be read from memory via a readout circuitry and provided to an external memory array ALU circuitry via I / O lines (e.g., via local I / O lines and / or global I / O). The external memory array ALU circuitry may contain multiple registers and will perform bit-vector operations using operands, and the results can be transferred back to the array via I / O lines. In other embodiments, the readout circuitry 150 is configured to perform bit-vector operations on data stored in the memory array 130 and store the results back to the memory array 130 without enabling I / O lines (e.g., local I / O lines) coupled to the readout circuitry 150.

[0050] In several embodiments, external circuitry to the memory array 130 and readout circuitry 150 may not be required to perform operations because the readout circuitry 150 can perform appropriate bit vector operations without using external processing resources. Therefore, the readout circuitry 150 can be used to at least partially supplement and / or replace such external processing resources (or at least the bandwidth consumption of such external processing resources). However, in several embodiments, the readout circuitry 150 can also be used to perform logical operations (e.g., but not limited to, executing instructions) other than those performed by external processing resources (e.g., but not limited to, executing logical operations). For example, the host 111 and / or the readout circuitry 150 may be limited to performing only certain logical operations and / or a certain number of logical operations.

[0051] Enabling an I / O line may include enabling (e.g., but not limited to, turning on) a transistor having a gate coupled to a decoded signal (e.g., but not limited to a column decoded signal) and a source / drain coupled to the I / O line. However, embodiments are not limited to performing logic operations using a readout circuitry system (e.g., but not limited to readout circuitry system 150) without enabling the column decoded lines of the array. Regardless of whether the local I / O line is used in association with performing logic operations through readout circuitry system 150, the local I / O line may be enabled to transfer the result to the appropriate location instead of returning it to memory array 130 (e.g., but not limited to transferring it to an external register).

[0052] Various embodiments of this disclosure relate to fuse-in-memory (FMA) operations, and more specifically to performing process-in-memory (PIM) FMA operations. According to various embodiments, data to be used in one or more computations can be accessed (e.g., but not limited to, via a sequencer) and reused on multiple bits (e.g., but not limited to, being loaded into a sense amplifier array via multiple data lines). Alternatively, various embodiments may involve reusing sequencer logic on multiple bits associated with multiple data lines. Therefore, compared to conventional methods and systems, memory load and the amount of memory stored can be reduced, and thus the efficiency of the memory device can be increased and / or the latency associated with the memory device can be reduced.

[0053] For at least these reasons, the various embodiments of this disclosure, as more fully described herein, provide a technical solution to one or more problems caused by techniques that may not be reasonably performed by humans, and the various embodiments disclosed herein are rooted in computer technology in order to overcome the aforementioned problems and / or challenges. Furthermore, at least some of the embodiments disclosed herein can improve computer-related technologies by allowing computers to perform functions that were previously not possible for computers to perform.

[0054] For matrix multiplication, both the Central Processing Unit (CPU) and the Graphics Processing Unit (GPU) can decompose the input matrix into tiles, which can be allocated to processor cores. For each tile of the output matrix, the tiles of the input matrix are extracted exactly once, achieving a computational intensity close to O(N) (i.e., the processing will increase linearly and proportionally to the size of the input dataset). The size of each tile of the output matrix can be chosen to match the capacity of the target processor's L1 cache or registers.

[0055] For GPUs, tiles are selected to form a hierarchy of thread block tiles, twisted tiles, and thread tiles. This tile structure creates paths for data from global memory to shared memory (i.e., matrix to thread block tile), from shared memory to register file (i.e., thread block tile to twisted tile), and for computation results from register file to GPU core (i.e., twisted tile to thread tile).

[0056] In PIM, memory constitutes a large part of the memory hierarchy, in addition to memory arrays (e.g., but not limited to DRAM arrays) and one or more registers (e.g., but not limited to, within a sense amplifier (SA) array). However, as described more fully herein, according to various embodiments, data can be reused in PIM FMA operations through calculations on the data lines or in local-to-memory data line registers.

[0057] Figure 2 A functional block diagram of a system 200 for performing a spatiotemporal FMA according to one or more embodiments is shown. The system 200 may include a stored operand and operator 202, a bit aligner 206, a bit quantizer 210, and a computation unit 214.

[0058] The stored operands and operators 202 can typically be configured to access and receive bit sequences of operands and / or operators stored in a portion of a memory array (e.g., but not limited to memory array 130). In one or more embodiments, the stored operands and operators 202 may include one or more data lines for receiving data bits, and one or more access lines for accessing data bits via the data lines.

[0059] Bit aligner 206 can typically be configured to receive bits 204 containing data bits corresponding to operands and operators, perform one or more alignments of operand bits in response to the operator bits, and provide aligned bits 208. For the performed bit alignment, bit aligner 206 can be configured to provide aligned bits 208. Bit quantizer 210 can typically be configured to determine the number of aligned bits 208 having predetermined values ​​(e.g., but not limited to "1" or "0"). Computation unit 214 can typically be configured to determine computation result 216 based at least in part on partial result 212.

[0060] In the intended operation of system 200, bit aligner 206 may receive bits 204, which respectively contain the bits of the operand and the bits of the operator 202 stored in the operand. Bit aligner 206 may provide aligned bits 208, which correspond to one or more bits of the operand, and more specifically, to the bits at the aligned bit positions of the operand. Bit quantizer 210 may receive aligned bits 208 and may provide partial results 212, which represent a predetermined number of bits of aligned bits 208 with predetermined values. Computation unit 214 may receive multiple partial results 212, combine the multiple partial results 212 (as described more fully hereafter), and provide a computation result 216.

[0061] Figure 3 A diagram of a spatiotemporal FMA 300 according to one or more embodiments is shown. For this particular non-limiting example embodiment, a bit sequence of operand "A", a bit sequence of operator "B", a matrix 302 containing bit values ​​of partial computation results for the spatiotemporal FMA 300, a carry-over 304 containing carry-over values ​​computed during the computation of various partial computation results, and a result 306 containing a bit sequence of the result of the spatiotemporal FMA 300.

[0062] Reference Figure 3 In the example embodiments shown and discussed, matrix 302 merely represents a convenient construction of bit alignment (e.g., but not limited to, via bit aligner 206) used in embodiments of spatiotemporal FMA. It is noteworthy that the matrix is ​​not necessarily created during or in connection with embodiments of spatiotemporal FMA. In fact, matrix 302 illustrates the alignment of individual bit positions and bits of operand A during spatiotemporal FMA 300 via circuitry in memory (e.g., but not limited to, via bit aligner 206), where corresponding bit values ​​can be quantized (e.g., but not limited to, via bit quantizer 210) and combined to generate computational results (e.g., but not limited to, via computation unit 214).

[0063] exist Figure 3In an example embodiment, operand A includes the corresponding bit values ​​1 10 1 for the bits at positions A3, A2, A1, and A0. Further, operator B includes the corresponding bit values ​​1 10 1 for the bits at positions B3, B2, B1, and B0. Each column of matrix 302, i.e., Col0 to Col6, represents the bit positions and corresponding bit alignments of operand A and carry C. Each specific alignment responds to the bit value of the bit in operator B. Alternatively, the bit position of the bit in operator B with a bit value of 1 indicates whether the bit value of operand A is located in a given cell of a given row / column of matrix 302 and which bit values ​​are located in a given cell of the given row / column of the matrix. Each specific bit in the cell of result 306 represents the quantization of the aligned bit corresponding to the column and carry of matrix 302.

[0064] exist Figure 3 In the example embodiment, matrix 302 is an N×M matrix (i.e., N rows multiplied by M columns). For each row of matrix 302, the bit value at the corresponding bit position of operator B indicates whether the bit value of A is in any cell of the row. If the corresponding bit value of B is "1", then the bit value of A is in some cells of the row, but if the corresponding bit value of B is "0", then all cells of the row are "0". It is worth noting that other conventions can be used, such as using "0" to indicate that the bit value of A is in a cell of the row and using "1" to indicate that all cells of the row are "0". The bit values ​​of operator B, from the bit position of least significant bit B0 to the bit position of most significant bit B3, indicate Row0 to Row3 respectively. At each row of matrix 302 where operator B indicates the use of the bit value of operand A, the bit values ​​of operand A are used in the order of least significant bit A0 to most significant bit A3.

[0065] In each row, cell positions of bit values ​​from A0 to A3 are selected to align the bit values ​​of operand A in each column, for example, but not limited to, one or more of Col0 to Col7, for summation. Each column of matrix 302 (and the corresponding bit position in carryover 304) represents a portion of the computation result of spatiotemporal FMA 300. Notably, summation can be performed by selecting a subset of rows and performing summation within the columns of the selected subset. Such subset selection can be performed in any order that includes any order. Further, subsets of rows can be summed into partial computation results and said partial computation results can be summed. In some embodiments, subsets can be selected according to a sorting algorithm such as, but not limited to, logarithmic sorting. As a non-limiting example, the logarithmic sorting algorithm can be log_L(B) steps, where L is a hardware constraint (e.g., 2 rows or 3 rows in a subset of rows) and B is a number corresponding to the bit width of the operator.

[0066] In typical binary multiplication, for each non-zero bit in the multiplier, the multiplicand is shifted to the left as appropriate, and then the shifted bits are added together.

[0067] The bit values ​​of the result 306 are obtained by summing the bit values ​​in the columns where the corresponding bit positions of the result 306 are located. In one embodiment, the summation includes performing a logical operation of type XOR, determining whether the number of bits with the value "1" is odd or even, counting the number of bit pairs with the value "1", etc.

[0068] Therefore, if each column of matrix 302 is considered a bit alignment for a partial computation of the spatiotemporal FMA 300, and each bit position of result 306 is considered a partial result of the spatiotemporal FMA 300, then the spatiotemporal FMA 300 contains eight partial results for this particular instance. Table 1 illustrates this. Figure 3 The calculated alignment bit position for each envisioned part.

[0069] Table 1: Bit positions of bit sequence A used in some calculation results

[0070]

[0071] The third column of Table 1 shows the codes, which in one embodiment can be determined from the aligned bit positions in the second column and further aligned with the carryover bit C. Alternatively, the group of aligned bit positions can be represented by codes, here in numeric codes.

[0072] Figure 4 A circuit diagram of a readout circuit 400 according to one or more embodiments is shown. The readout circuit 400 may include one or more data lines (here, bit lines BL0 and BL1) operatively coupled to one or more readout amplifiers and operatively coupled to one or more sequencers via one or more access lines. Figure 4 In the specific, non-limiting example embodiment shown, the readout circuit 400 includes bit lines BL0 and / or BL1 for receiving bits of operand A stored along bit line BL0 in a portion of the memory array and bits of operand C stored along bit line BL1 in the memory array. BL0 and BL1 are operatively coupled to sequencer 402 via access lines, here word lines WL0 to WL3. Bit line BL0 is also operatively coupled to readout amplifier 404, and bit line BL1 is operatively coupled to readout amplifier 410. It is optional to operatively couple individual access lines to multiple data lines, and... Figure 4 Several embodiments are highlighted in the figure.

[0073] Using the readout circuit 400, multiple bits of operand A can be accessed substantially simultaneously, and computation results (e.g., but not limited to quantizing the accessed bits) can be performed during such multi-bit access. In the intended operation of the readout circuit 400, multi-bit access can be performed by activating multiple access lines (i.e., one or more word lines WL0 to WL3) corresponding to the bit positions of operand A.

[0074] Sequencer 402 can be configured to activate one or more word lines WL0 to WL3, which correspond to the bit positions of the corresponding groups of aligned bit positions shown in Table 1 and carry C, which can be locally stored by the corresponding sense amplifiers (e.g., but not limited to sense amplifiers 404 and 410). In one embodiment, sequencer 402 can be configured to determine the corresponding bit positions of the groups of aligned bit positions corresponding to a given partial computation based at least in part on operand A and operator B. Additionally or alternatively, in some embodiments, sequencer 402 can be configured to activate the corresponding word line in response to codes such as, but not limited to, those shown in the third column of Table 1 and carry that can be locally stored by each sense amplifier.

[0075] Operator B can be used as a control sequence to provide activation modes to word lines WL0-WL3. In some cases, B can be a general operator for many operands (e.g., but not limited to multipliers). In such cases, many multiplication operations can be performed in parallel (i.e., substantially simultaneously) on multiple data units, as discussed in this paper.

[0076] Returning to the intended operation of the readout circuit 400, the sequencer 402 activates word lines WL0 and WL2 to access A0 and A2 (i.e., partial calculation result 2 in Table 1), both of which are available to the readout amplifier 404 for calculation results occurring during access via bit line BL0. The readout amplifier 404, operably coupled to BL0, quantizes the number of bits accessed on bit line BL0 that are bit values ​​“1” at a given time (e.g., but not limited to, for a given access operation). With multiple bits on bit line BL0 activated, the readout amplifier 404 can immediately provide the result of the calculation (e.g., but not limited to, providing a partial result in response to a partial calculation result).

[0077] In one or more embodiments, the sense amplifier (e.g., but not limited to sense amplifier 404) can be configured to distinguish (i.e., resolve) one or more states of active bits on data lines (e.g., but not limited to bit lines BL0 and BL1). In one or more embodiments, typically, for N simultaneously active bits on the bit lines of sense circuitry 400, a state truth table provides N+1 states: a first state when all bits are 0, a second state when exactly one bit has a value of 1, a third state when exactly two bits have a value of 1, ..., and an Nth state when exactly N-1 bits have a value of 1, and an N+1th state when all N bits have a value of 1. Thus, the truth table primarily counts how many bits with a value of 1 are active on the bit lines, regardless of their position. Such a truth table can be implemented as circuitry outside of or as part of the sense amplifier, or alternatively, it can be stored as a lookup table in memory or in a register near each sense amplifier, and alternatively, the sequencer can pass table values ​​either upon request or unconditionally from the sense amplifier.

[0078] Table 2 shows truth tables according to one or more embodiments, particularly corresponding to... Figure 2 and 3 The truth table of an example embodiment.

[0079] Table 2: Truth Table

[0080]

[0081] In one or more embodiments, the sense amplifier 404 may include one or more sense amplifiers configured to resolve all N states of BL 0. In one embodiment, the sense amplifier 404 may be configured to resolve all N states of a circuit (e.g., but not limited to sense circuit 400). In such embodiments, all bits of BL 0 may be accessed simultaneously or concurrently.

[0082] In another embodiment, the readout amplifier 404 can be configured to resolve fewer than N states (i.e., N-1 or fewer states). In such an embodiment, the sequencer 402 can be configured to sequentially activate a subset of the bits of BL0. Using an example of a readout amplifier 404 configured to resolve two states, the sequencer 402 can be configured to activate at most two bits at bit line BL0 at a time. In this way, the readout amplifier 404 can operate on at most two activated bits on bit line BL0 in each access operation and accumulate the results. As a non-limiting example, the readout amplifier 404 can operate on the first two activated bits and the carry of the code in the “Code” column of Table 1, and then operate on the second two activated bits and the carry of the code of the same code, and then combine these partial calculations into a combined partial calculation.

[0083] Alternatively, these partial computations can be performed simultaneously by two different sets of sense amplifiers, which intersect two different sets of bit lines with the same operands. The ordering of the two bit sets can be performed based on the first two bits of the code in the first sense amplifier set and the second two bits of the code in the second sense amplifier set. The combination of partial results from the two sense amplifier sets, or in this case, the summation of partial results from the two sense amplifier sets, can be performed concurrently with or after the partial computations generated by these sets. It is noteworthy that the bit positions of the selected code for each set can be performed in any order, including arbitrary ordering (e.g., all first and all fourth bits in one set, and all second and all third bits in another set). The partial computation results can then be summed. In some embodiments, the partial computations can be summed according to a sorting algorithm. Non-limiting examples of sorting algorithms include logarithmic sorting algorithms. As a non-restrictive example, the logarithmic sorting algorithm can be log_L(B) steps, where L is a hardware constraint (e.g., but not limited to 2 units of 2-restricted activation corresponding to 2 positions in the "code" or 3 units of 3-restricted activation corresponding to 3 positions in the "code" chosen for the set of sense amplifiers) and B is a number corresponding to the bit width of the operator.

[0084] Although the truth table in Table 2 is an example of simultaneous 2-bit reading, i.e., using a 2-bit state table to determine the calculation result, it should be understood that 3-bit, 4-bit, and so on up to N-bit state truth tables can be used in one or more embodiments. It is worth noting that the complexity of the circuitry temporarily formed due to activation will generally be proportional to the number of bits used in the truth table.

[0085] Regarding carryover, carryover is a count of the number of 1s carried over from previous simultaneous activations. This count corresponds to the number of bit pairs with a value of "1" from the previous simultaneous activation (including the carry value when the pair was determined). In some cases, the maximum carry will depend on the state table: for a 2-bit state table, the maximum carry is 1; for a 3-bit state table, the maximum carry is 2; for a 4-bit state table, the maximum carry is 3, and so on. Therefore, the more simultaneous activations during a portion of the computation, the larger the maximum number of 1s that can be carried over.

[0086] In one embodiment, in order to include carryover from previous partial calculations in the current partial calculation, the strength of the active driver (e.g., but not limited to a current source, voltage source, or reference resistor) can be scaled as a function of the carryover from previous partial calculations.

[0087] In another embodiment, the carry-over from the previous partial calculation can be calculated as a digital value having a number of "1"s equal to the carry-over, and said digital value is summed with the bits of the activated bit position to calculate the result. As a non-limiting example, the digital value of the carry can be stored in a lookup table or circuit. The digital value can be looked up, digitally stored at the sense amplifier, and digitally combined with the subsequent partial calculation result and the carry.

[0088] In yet another embodiment, the carryover can be stored as a charge or resistance value that is essentially equal to a charge or resistance value of “1” multiplied by the carryover and then integrated with the result through one or more cycles. The charge / resistance value can be stored as an additional number of memory cells programmed with this charge / resistance value (e.g., but not limited to, locally located for a sense amplifier), the number of cells corresponding to the carryover value to be integrated with the result.

[0089] As mentioned above, in some cases, B can be a common operator for multiple operands. In such cases, multiple computations or parts thereof can be performed in parallel (i.e., substantially simultaneously) using multiple operands. As described above, and according to one or more embodiments, Figure 4 An optional operational coupling with the second bit line BL1 is shown, and operand C is located at BL1. Operand C can store a value different from that of operand A.

[0090] In the intended multiple access operation of the readout circuit 400, sequencer 402 activates WL0 and WL2 to access A0 and A2 for a first calculation, and simultaneously accesses C0 and C2 for a second calculation. Bits at A0, A2, C0, and C2 can be used to represent the results of calculations occurring during access to the corresponding bit positions of BL0 and BL1. Similar to the readout amplifier 404 described above, readout amplifier 410, operatively coupled to BL1, can be configured to quantize the number of bits accessed at BL1 (e.g., but not limited to, being configured to quantize the number of bits accessed at BL1 that are bit values ​​"1" at a given instant). With multiple bits of BL0 and BL1 active, readout amplifiers 404 and 410 can immediately provide corresponding results of the calculations (e.g., but not limited to providing partial results in response to partial calculation results).

[0091] Figure 5 A functional block diagram of an embodiment of a readout amplifier controller 500 is shown. During one or more partial computations, the readout amplifier controller 500 can typically be configured to perform one or more operations of the spatiotemporal FMA embodiment described herein. Figure 5In the specific, non-limiting example embodiment shown, the sense amplifier controller 500 includes a signal driver 502, a sense processor 504, a result register 506, and a carry-over register 508. The sense amplifier controller 500 may optionally include other registers. In some embodiments, the signal driver 502 may be combined with the sense processor 504 in a single functional unit. In some embodiments, the sense amplifier controller 500 may include a first signal driver 502 / sense processor 504 pair for word lines and a second signal driver 502 / sense processor 504 pair for bit lines. In some embodiments, the sense and drive may be implemented at one or both of the access lines and data lines.

[0092] Signal driver 502 can be configured to provide driver signals 510 for driving data lines and / or access lines, such as, but not limited to, providing signals for driving data lines and / or access lines. Figure 4 The bit lines and / or word lines are driven by a drive signal 406. In one or more embodiments, the signal driver 502 may be configured to provide a drive signal 510 in response to a value stored in the carry register 508. More specifically, the signal driver 502 may be configured to increase or decrease the level of the drive signal 510 provided during a partial computation (compared to the drive signal 510 provided during a previous partial computation) in response to a bit value stored in the carry register 508. In other words, the level of the subsequent output of the signal driver 502 (whether a current source, voltage source, or reference resistor, but not limited to this) is scaled as a function of the propagation carry (i.e., the bit value stored in the carry register 508). In another embodiment, in addition to or in lieu of the drive signal, the scaling value may be obtained by operatively coupling the sense amplifier to a plurality of additional bits stored locally on the sense amplifier, each such additional bit storing a logic "1". The number of additional bits may correspond to the carry value to be integrated at the sense amplifier (i.e., corresponding to "C" in the aligned bit position column of Table 1). Additional circuitry may be required to enable these features.

[0093] The read processor 504 can be configured to receive a read signal 512 from a data line, for example, but not limited to, receiving a read signal from a data line. Figure 4 The read signal 408 is the bit line read signal. The read processor 504 can be configured to determine the partial results and carryover stored in the result register 506 and carryover register 508 respectively in response to the read signal 512.

[0094] One or more embodiments typically involve obtaining information about an activated data line (e.g., but not limited to...). Figure 4 The state information of the bit line BL0) is converted into partial calculation results and calculation results determined in response to the partial calculation results.

[0095] In the absence of memory devices with access transistors, an intermediate circuit system can be formed and can be used to convert state information into a result. Non-limiting examples of memory devices without access transistors include resistive crosspoint memory devices and capacitive crosspoint memory devices.

[0096] In the case of resistive crosspoint memory, such as, but not limited to, resistive random access memory (ReRAM) or 3D XPoint (commercially available from Micron Technology), a parallel resistor network can be formed and the parallel resistor network can be used to convert state information into results.

[0097] Figure 6 and Figure 7 A circuit diagram of an example embodiment of a readout circuit is shown, which is temporarily activated to measure the state of a data line (e.g., but not limited to measuring the state associated with an activated bit on the data line). One or more embodiments of the readout circuit can be activated by operatively coupling the access line to a specified level, such as, but not limited to, a specified voltage level or a specified current level.

[0098] Figure 6 It shows from Figure 4 An example activation of the temporarily activated parallel resistor network (i.e., the readout circuit) of the readout circuit 400, and more generally corresponding to Figure 3 The partial calculation results of COL 2 (starting from COL 0 from right to left).

[0099] exist Figure 6 In a hypothetical example embodiment, the activated readout circuit 602 includes elements 604 and 608 (in...) Figure 6 The word lines WL2 and WL0 are depicted as switches and are activated. The activating elements are configured to operatively couple / decouple WL2 and WL0 to a specified voltage level, here but not limited to ground (GND). In one or more embodiments, activating elements 604 and 608 may be used to enable current (e.g., but not limited to...) Figure 6 The current I) in the circuit can flow at access lines such as word lines WL0 to WL2, or any suitable electronic circuit and / or device, such as, but not limited to, diodes, transistors, capacitor switches, inductive switches, current sources, and combinations thereof.

[0100] exist Figure 6 The word line WL1 is shown only to illustrate that in the example operation, word line WL1 is not operatively coupled to GND (word line WL3 is also not operatively coupled to GND, which is omitted in this figure), that is, the active element 606 is shown as an open switch, and no current flows through the resistive element 614.

[0101] Both memory cells (here, resistor elements 610 and 612) contain a bit value "1", which is pre-specified to correspond to a low resistance state of 10 ohms (as opposed to a high resistance state of, for example, but not limited to, 1000 ohms). In one or more embodiments, resistor elements 610 and 612 can be any suitable electronic circuitry and / or device selected to affect the resistance seen at the access lines (here, WL3 and WL0), such as, but not limited to, resistors, capacitors, wires / conductors, transistors, and combinations thereof.

[0102] When a current I is supplied to the bit line BL0, a circuit 600 is formed, which includes a parallel resistor network, here the readout circuit 616, and a voltage divider, here the reference node containing a current source 620.

[0103] The bit line resistance (i.e., the resistance of BL0 as seen at the readout and amplification circuit 618) can be determined as R = 1 / (1 / 10 + 1 / 10) = 5 ohms. With the current source 620 being 1AMP, the voltage read at the bit line (i.e., the readout voltage V) can be determined as V = R × I = 5 × 1 = 5V. This readout voltage indicates the state of the bit line BL0, and the readout and amplification circuit 618 can (internally) look up the readout voltage and provide the result along with a carry input response. As a non-limiting example, the readout and amplification circuit 618 may include a lookup table (LUT) configured to provide the result and carry information in response to the value of the readout voltage.

[0104] It is worth noting that, in Figure 6 In the example embodiments shown, when according to the discussion herein Figure 6 When the parallel resistor network 616 is activated, the readout voltage typically decreases by the number of cells containing bit lines with a bit value of 1. As a non-limiting example, in the case where a single cell contains a bit with a bit value of 1, the bit line resistance can be determined as R = 1 / (1 / 10 + 1 / 1000) = 9.9 ohms, and after applying a current of 1 Amp, the bit line voltage is V = 9.9 V.

[0105] As another non-limiting example, if both memory cells of the activated readout circuit 602 are in a high-resistance state, the bit line resistance can be determined to be R = 1 / (1 / 1000 + 1 / 1000) = 500 ohms, and after applying a current of 1 Amp, the bit line voltage is V = 500V. In most anticipated usage scenarios, 500V will be outside the dynamic range of the circuit, and therefore the readout voltage will be equal to the line voltage.

[0106] For reference Figure 6In some embodiments, one or more word lines may be operatively coupled to a power supply voltage to activate a parallel resistor network. Figure 7 A non-limiting example of a parallel resistor network is shown, which is activated by operatively coupling the access lines of a readout circuit (e.g., but not limited to, the word lines of readout circuit 400) to a voltage source, such that signal readout can be performed by reading the voltage at a reference base resistor node (e.g., but not limited to, a voltage divider).

[0107] exist Figure 7 In the example embodiment shown, word lines WL2 and WL0 are activated by being operatively coupled to a voltage source (e.g., but not limited to Vdd) via activation elements 706 and 708, respectively. A readout and amplification circuit 704 is operatively coupled to bit line BL0 and internally coupled to GND via an internal base resistor 718. When a current I is supplied to bit line BL0, circuit 700 is formed, comprising a parallel resistor network, here the readout circuit 720, and a voltage divider, here the reference node containing the base resistor 718.

[0108] exist Figure 7 The word line WL1 is shown only to illustrate one embodiment, wherein the word line WL1 is not operatively coupled to VDD (WL3 is also not operatively coupled to VDD, which is not depicted), that is, the activation element 710 is shown as an open switch, and no current flows through the resistive element 714.

[0109] exist Figure 7 In this circuit, word lines WL0 and WL2 are activated by being operatively coupled to a specified voltage level, where Vdd = 10V (i.e., via activation elements 708 and 706). Both memory cells (here, resistor elements 712 and 716) contain a bit value of 1 corresponding to a low-resistance state of 10 ohms (opposite to a high-resistance state of 1000 ohms). The bit line resistance can be determined as R = 1 / (1 / 10 + 1 / 10) = 5 ohms. If the base resistor 718 is 10 ohms, the voltage read at BL0 can be determined as V = R_div × Vdd = (10 / 15) × 10 = 6.67V. The read voltage can indicate the state of BL0, and the read and amplify circuit 704 can be configured to look up and provide carry and result values ​​(e.g., but not limited to, reference). Figure 6 As mentioned above, it is used as a LUT.

[0110] It is worth noting that the readout circuit 720 is formed when creating a parallel resistor network with a voltage divider, and the readout voltage will increase the number of cells containing bit lines with a bit value of 1. As a non-limiting example, in the case where only one cell has a bit with a bit value of 1, the bit line resistance can be determined as R = 1 / (1 / 10 + 1 / 1000) = 9.9 ohms, and after applying the voltage divider, V = (10 / 19.9) × 10 = 5V.

[0111] As another non-limiting example, if both memory cells of the activated circuit 702 are in a high-resistance state, the baseline resistance can be determined as R = 1 / (1 / 1000+1 / 1000) = 500 ohms, and after applying the voltage divider, the bit line voltage is V = (10 / 510) × 10 = 0.19V.

[0112] It is worth noting that this includes, but is not limited to, references. Figure 6 and Figure 7 The voltage, resistance, and current values ​​provided in the example embodiments, including the described example embodiments, are provided for illustrative purposes. In operation, voltage, resistance, and current may be affected by one or more of, for example, but not limited to, noise, inherent characteristics of the device, and parasitic impedance.

[0113] It is worth noting that those skilled in the art will understand the use of references in creating and / or performing [these actions]. Figure 5-7 The circuits and operations described herein include numerous circuits and equivalent circuits. As a non-limiting example, the readout and amplification circuits (e.g., but not limited to readout and amplification circuits 618 and 704) include voltage dividers and voltage sources, as well as access lines (e.g., but not limited to WL 0 and WL 3) operatively coupled to GND.

[0114] It is worth noting that those skilled in the art will understand that any suitable voltage readout technique can be used to read voltages associated with one or more states of one or more bit lines, including but not limited to readout and amplification circuitry 618 and readout and amplification circuitry 704. In one or more embodiments, voltage readout techniques and circuitry systems for reading voltages that are at least partially based on the symmetry of the crosspoint resistive memory can be used. As a non-limiting example, voltage readout techniques that are at least partially based on the symmetry of the crosspoint resistive memory can include, but are not limited to, bidirectional voltage level readout techniques or differential voltage level readout techniques and multi-parallel bit line readout techniques, as well as circuitry for implementing said techniques.

[0115] One or more embodiments may typically involve converting state information into the result of a bounce-back resistor memory device (e.g., but not limited to, 1D or diode-type memory cells) operating in saturation mode. In such embodiments, a driver signal may be applied to an activated word line and a readout and amplification circuitry system (e.g., but not limited to readout and amplification circuitry 618 and 704) is configured to observe the amount of bounce-back current at bit line BL0. Typically, the amount of bounce-back current may be converted to a voltage (e.g., but not limited to, via a current-to-voltage converter) and the voltage is read out to determine the number of bounce-back devices (i.e., the number of memory cells containing bits with a value of "1"), and thus the calculation result is performed.

[0116] In the foregoing example embodiments, bit access and reading can be performed destructively or non-destructively, and no particular type of reading (i.e., destructive or non-destructive) is implied, nor should it be construed as necessary to perform the described embodiments or their legal equivalents.

[0117] For capacitive crosspoint memories (such as, but not limited to, dynamic random access memory (DRAM) and hybrid random access memory (HRAM)), the techniques described above for resistive memories can be applied with only minor modifications to accommodate capacitors and charge sharing, without changing the resistors. In some cases, capacitive crosspoint memories can be destructive, although it is specifically envisioned that the circuitry could be contained within the crosspoint memory to retain data bits after a read.

[0118] Figure 8 and Figure 9 A circuit diagram is shown for converting one or more state information about the bits accessed on a data line into partial results and calculation results in the case where the memory contains NAND serial memory (e.g., NAND flash memory containing 3D flash NAND).

[0119] As used in this article, "NAND string" refers to two or more NAND cells, where the source of one NAND cell is connected to the drain of the next NAND cell.

[0120] In one or more embodiments, temperature measurement to binary decoding can be used to convert state information into a result. NAND string 800 represents a typical NAND string known to the inventors of this disclosure and includes a series-connected transistor with dual gates: a floating gate for recording bits and a control gate for bypassing data recorded at a specific NAND cell.

[0121] At NAND string 800, a bit can be recorded by placing a certain amount of charge in the floating gate of the transistor. The transistor conductivity can be controlled by this charge. For example, bit 1 can correspond to a low conduction state (or can be characterized as a high resistance state). Bypassing the NAND cell can be performed by temporarily applying a specific bias voltage to the second gate connected to WL (i.e., the control gate), which "covers up" the effect of the floating gate by reducing the resistance across the cell to its minimum (effectively turning on the transistor in the transfer transistor state).

[0122] In one embodiment, all transistors are kept in bypass operation mode, and then the bypass mode is selectively turned off for specific transistors of interest. More specifically, the bypass mode is selectively turned off to activate selected bits used for spatiotemporal FMA. This is achieved using a method that includes... Figure 8 Partial calculations are performed on word lines 0 and 2. In the first case described above, WL0 and WL2 remain inactive, and all other word lines are bypassed. In the other case described above, all word lines are initially in bypass operation mode, and then the bypass mode of WL0 and WL3 is selectively turned off.

[0123] In either case, assuming the high-resistance state (i.e., bit 1) is encoded as 1000 ohms, and the low-resistance state (i.e., bit 0) corresponds to 10 ohms and is equal to the bypass mode, the low-resistance state can therefore be ignored (relative to 1000 ohms). Thus, a NAND string 800 can be represented as an access circuit containing two resistors connected in series, as in... Figure 9 As shown in the image.

[0124] Figure 9 A circuit diagram of a readout circuit 900 is shown. The readout circuit is one of two example embodiments of readout circuits (here, readout circuit 902 and readout circuit 904) that can be used to access / read readout voltages (e.g., but not limited to bit values) from a NAND string 800.

[0125] In the intended use of the readout circuit 902, the current source 906 (e.g., but not limited to 1mA) and the readout voltage can be read at a location after the current source 906 as V = I × R = 0.001 × (1000 + 1000) = 2V.

[0126] In the intended use of the readout circuit 904, a voltage source (e.g., 1V) is applied and the voltage (Rref = 1000 ohms) is read at a position after the reference resistor 908 as V = Vref × R = 1 × (1000 + 1000) / (1000 + 1000 + 1000) = 2 / 3V.

[0127] As a non-limiting example, if only one cell in the cell has a value of 1, the bit line resistance can be determined to be R = 1000 ohms, and the output voltage will be: 1V (in the case of readout circuit 902) and 1 / 2V (in the case of 904).

[0128] As another non-limiting example, if all cells are 0 (in other words, no cells are "1"), then the bit line resistance is close to 0 ohms, and the output voltage will be close to 0V for both readout circuits 902 and 904.

[0129] In the case of readout circuits 902 and 904, the readout amplifier can use the observed output voltage to (internal) find the result and carry.

[0130] One or more embodiments of this disclosure generally relate to converting readout voltages into results and carryovers. In some embodiments, a readout amplifier for a multi-level cell NAND flash memory (e.g., but not limited to three-level cell (TLC) NAND flash memory and four-level cell (QLC) NAND flash memory) may be configured to include circuitry for finding results and carryovers in response to readout voltages.

[0131] In some embodiments, the sense amplifier may include an integrated analog-to-digital converter (ADC). Figure 10 A functional block diagram of an integrated ADC 1000 that may be included in a sense amplifier such as, but not limited to, sense amplifier 404 is shown. In one or more embodiments, the integrated ADC 1000 may include a voltage divider 1004, an input quantization 1010, and a temperature-to-binary encoding 1014.

[0132] In one or more embodiments, voltage divider 1004 may typically be configured to perform one or more voltage divisions of reference voltage 1002. Voltage divider 1004 may include one or more of any suitable electronic circuitry / devices for performing voltage division according to the disclosed embodiments, and as a non-limiting example, may include a resistor string comprising one or more resistive elements (e.g., but not limited to resistors, transistors, and diodes) connected in series. In one embodiment, the resistor string of voltage divider 1004 may be part of a bit line continuation and isolated from data bit lines.

[0133] In one or more embodiments, input quantization 1010 may typically be configured to perform one or more input quantizations of item input voltage 1008 in response to reference voltage 1006. Input quantization 1010 may include one or more of any suitable electronic circuits / devices for performing input quantization according to the disclosed embodiments, and as a non-limiting example, includes one or more voltage comparators (e.g., but not limited to one or more Schmitt triggers).

[0134] In one or more embodiments, the temperature-to-binary encoding 1014 can typically be configured to provide results and carry-over in response to a quantized input 1012. The temperature-to-binary encoding 1014 may include one or more electronic circuits / devices for performing temperature-to-binary encoding according to the disclosed embodiments, including, as a non-limiting example, gate arrays, lookup tables (LUTS), and combinations thereof.

[0135] In the intended operation of the integrated ADC 1000, when an input voltage 1008 is asserted at an input (not shown) of the integrated ADC 1000, the corresponding input quantizer of the input quantization 1010 is triggered in response to a comparison of the input voltage 1008 with a corresponding reference voltage 1006 provided by a corresponding voltage divider of the voltage divider 1004. The temperature measurement to binary encoding 1014 provides a result and carry bit in response to the quantized input 1012. The result and carry bit can be stored as a partial calculation result (e.g., but not limited to, from...). Figure 2 The bit quantizer 210 is used to generate the complete computation result (e.g., but not limited to...). Figure 2 Partial results 212).

[0136] In one or more embodiments, the circuitry for temperature measurement down to binary code 1014 (e.g., but not limited to error correction circuitry and encoder circuitry) may be routed below, above, around, or through the memory array. In one embodiment, such circuitry may be routed below the memory array, for example, but not limited to, to protect memory capacity from degradation by another routing arrangement.

[0137] Figure 11 A flowchart of an embodiment of a process 1100 for performing a spatiotemporal FMA is shown.

[0138] In operation 1102, process 1100 selects one or more locations in a portion of a memory array along a data line for access, the bits stored at those locations in said portion of the memory array being accessible via the data line. The corresponding locations may correspond to one or more bit positions of one or more bits of an operand stored along the data line. In one or more embodiments, the bits of the operator may be used to guide the selection of bit positions contained within the one or more bit positions.

[0139] In embodiments where processing is performed in memory including crossover memory, the corresponding first access line may cross the data line perpendicularly at a specific location associated with the bit position of the first bit position. In embodiments where processing is performed in memory including NAND string memory, the corresponding first access line may include or be operatively coupled to the gate of the NAND cell.

[0140] In operation 1104, process 1100 configures a signal driver in response to a carryover from a previous partial calculation. If no previous partial calculation exists, operation 1104 can be skipped. In one embodiment, configuring the signal driver may include configuring a current source to provide current at a specified level. In another embodiment, configuring the signal driver may include configuring a voltage source to provide voltage at a specified level.

[0141] In operation 1106, process 1100 generates a driver signal (e.g., but not limited to readout current or readout voltage) at the signal driver configured in operation 1104. In one or more embodiments, the driver signal may be provided to readout circuitry configured to generate a readout signal indicating the state of an activated data line, and more specifically, the number of bits with a bit value of "1" at the activated data line.

[0142] In operation 1108, process 1100 activates the access line selected in operation 1102, thereby providing the activated bit at the data line. Activating an access line may involve substantially simultaneously activating two or more locations in the portion of the memory array, and more specifically, two or more access lines associated with two or more bit positions corresponding to the two or more locations.

[0143] In operation 1110, process 1100 observes the read signal across the readout circuit, i.e., the readout signal of the readout circuit that received the driver signal in operation 1106. As described herein, in one or more embodiments, the readout signal indicates the number of active bits on the data lines. In one or more embodiments, the readout circuit may have been temporarily activated to measure the state (or a signal indicating the state) of the selected access line activated in operation 1108.

[0144] In operation 1112, process 1100 determines and stores a partial result in response to the observed readout signal.

[0145] If a subsequent partial calculation exists, in operation 1112, process 1100 determines and stores the carryover in response to the observed readout signal. The stored carryover can then be used to configure the signal driver in subsequent partial calculations.

[0146] In some embodiments, as a non-limiting example, due to hardware limitations, a subset of the access lines corresponding to the selected bit positions may be activated simultaneously, rather than activating all access lines for the selected bit positions. Therefore, in some embodiments, performing partial computations and obtaining partial results may involve performing multiple intermediate partial computations and obtaining multiple intermediate partial results.

[0147] Figure 12A flowchart is shown for an embodiment of a process 1200 that includes performing a plurality of intermediate computations. As a non-limiting example, process 1200 may be performed in place of operations 1108, 1110, 1112, and 1114 of process 1100.

[0148] In operation 1202, process 1200 activates a subset of access lines associated with locations in a portion of the memory array, such locations corresponding to a subset of bit locations in the selected bit locations.

[0149] In operation 1204, process 1200 observes intermediate read signals at data lines of the memory array. Intermediate read signals may represent activated bits on the data lines. Activated bits may correspond to bits stored at locations in the memory array associated with the access lines activated in operation 1202, and more specifically, to bits at selected bit locations in a bit sequence.

[0150] In operation 1206, process 1200 adds the observed intermediate readout signal to the previously observed intermediate readout signal (if any) calculated in the current part.

[0151] In operation 1208, process 1200 determines the carry-over in response to a read signal obtained by accumulating intermediate read signals from operation 1206.

[0152] In operation 1210, process 1200 repeats the sub-procedures of operations 1202, 1204, and 1206 until intermediate readout signals for all subsets of the access lines have been accumulated. Alternatively, the sub-procedures are repeated until intermediate readout signals corresponding to the access lines for all positions / selected bit positions used in the partial calculation have been accumulated. The resulting readout signals are essentially the sum of the accumulated intermediate readout signals.

[0153] In operation 1212, process 1200 determines a portion of the calculation result in response to a readout signal obtained from an accumulated intermediate readout signal.

[0154] One or more embodiments described herein include a method. The method may include selecting a first position for accessing a first bit of an operand stored at a first location along a data line in a memory array. The method further includes activating a first access line associated with the selected first bit position. The method further includes accessing the first bit of the operand stored at the selected first bit position. The method further includes receiving at least a portion of a computation result in response to the accessed first bit.

[0155] One or more embodiments described herein include a system. The system may include access lines, data lines, a bit quantizer, and a computation unit. The bit quantizer may be operatively coupled to the data lines. The bit quantizer may be configured to determine one or more states of the data lines. The computation unit may be configured to provide computation results in response to the one or more states of the data lines.

[0156] One or more embodiments described herein include a circuit. The circuit may include a first line, a plurality of second lines, and measurement circuitry. The plurality of second lines are configured to be coupled to the first line via memory elements positioned along the first line. Each of the plurality of second lines may include an activation element configured to alternately couple and decouple the line to a specified voltage level (e.g., but not limited to, ground voltage or supply voltage). In one embodiment, one of the plurality of second lines may include a resistive element. The circuit may also include circuitry arranged to measure voltage across a parallel network of resistors activated by operatively coupling the line to a reference node.

[0157] Another embodiment of this disclosure includes an electronic system. The electronic system may include at least one input device, at least one output device, and at least one processor device operatively coupled to the input device and the output device. The electronic system may also include at least one memory device operatively coupled to the at least one processor device and including one or more memory cell arrays and one or more fusel-add (FMA) cells coupled to the respective memory cell arrays. The FMA cells may be configured to select a first bit position of an operand stored at a data line for access. The FMA cells may be further configured to activate a first access line in response to the selected first bit position. The FMA cells may be further configured to access the first bit of the operand stored at the selected first bit position in response to the first activated access line. The FMA cells may be further configured to obtain a calculation result in response to the accessed first bit.

[0158] As is customary, the various features shown in the accompanying drawings may not be drawn to scale. The illustrations presented in this disclosure are not intended to be actual views of any particular device (e.g., but not limited to an apparatus or system) or method, but are merely idealized representations used to describe various embodiments of this disclosure. Therefore, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Additionally, some figures in the drawings may be simplified for clarity. Consequently, the drawings may not depict all components of a given device (e.g., but not limited to an apparatus) or all operations of a particular method.

[0159] As used herein, the terms "apparatus" or "memory device" may include, but are not limited to, devices having only memory. For example, an apparatus or memory device may include memory, a processor, and / or other components or functions. For example, an apparatus or memory device may include a system-on-a-chip (SoC). In some embodiments, the computing methods described herein may be applied to storage devices, such as solid-state drives. Therefore, as used herein, the term "memory device" may include storage devices.

[0160] The terms used herein, and especially in the appended claims (e.g., but not limited to the body of the appended claims), are generally intended to be “open-ended” terms (e.g., but not limited to, the term “including” should be understood as “including but not limited to”, the term “having” should be understood as “at least having”, the term “includes” should be understood as “including but not limited to”, etc.).

[0161] Furthermore, if the intent is a specific number of introduced claim statements, then such intent will be explicitly stated in the claims, and where no such statements are present, such intent does not exist. For example, to aid understanding, the appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that a claim statement introduced by the indefinite article “a” or “an” limits any particular claim containing such an introductory claim statement to an embodiment containing only one such statement, even when the same claim contains the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., but not limitingly, “a” and / or “an” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles used to introduce claim statements. As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0162] Furthermore, even when a specific number of introduced claim statements are explicitly stated, it should be understood that such statements should be interpreted as meaning at least the number stated (e.g., but not limitingly, stating "two statements" in the absence of other modifiers means at least two statements or two or more statements). Moreover, where conventions such as "at least one of A, B, and C" or "one or more of A, B, and C" are used, such constructions are generally intended to include only A, only B, only C, A and B, A and C, B and C, or A, B, and C, etc. For example, the use of the term "and / or" is intended to be interpreted in this manner.

[0163] Furthermore, any separating words or phrases presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to account for the possibility of including one, any, or both of the stated terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0164] Furthermore, the terms "first," "second," and "third," etc., are not necessarily used in this document to indicate a specific order or quantity of elements. Generally, the terms "first," "second," and "third," etc., are used to distinguish different elements as general identifiers. Unless otherwise stated, these terms should not be construed as indicating a specific order. Similarly, unless otherwise stated, these terms should not be construed as indicating a specific number of elements.

[0165] The embodiments of this disclosure described above and illustrated in the accompanying drawings do not limit the scope of this disclosure, which is covered by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. In fact, various modifications to this disclosure (such as alternative useful combinations of the described elements) will become apparent to those skilled in the art, in addition to those shown and described herein. Such modifications and embodiments also fall within the scope of the appended claims and their equivalents.

Claims

1. A method for operating a memory, comprising: Select the first bit of the first bit of the operand stored in the first part of the memory array for access, the first bit being accessible via the first data line; Activate the first access line associated with the selected first position; Access the first bit of the operand; as well as It responds to the accessed first bit and receives at least a portion of the computation result based on the truth table.

2. The method according to claim 1, further comprising: The first bit of the first bit position of the operand is selected in response to the value of the bit at the first bit position of the operator; as well as The second bit position of the first bit position of the operand is selected in response to the value of the bit at the second bit position of the operator.

3. The method according to claim 1, further comprising: A portion of the computation result is generated, at least in part, based on the number of the first bit accessed with a specified bit value.

4. The method according to claim 3, wherein generating the partial calculation result includes: Generate the summation result and carry it over.

5. The method of claim 1, further comprising: Select the second bit position of the second bit of the operand for storage or retrieval; Activate the second access line associated with the selected second bit position; as well as The second bit of the operand is accessed in response to the activated second access line.

6. The method of claim 5, further comprising: The first part of the calculation result is received in response to the accessed second bit; The second part of the calculation result is received in response to the accessed second bit; as well as Combine the calculation results from the first part and the calculation results from the second part.

7. The method of claim 1, further comprising: The first data line is accessed at the first position using one or more of the first data line, memory element, first access line, and any combination or sub-combination thereof.

8. The method of claim 1, further comprising: The first data line is accessed at the corresponding first position using a parallel resistor network including the first data line, memory element, and the first access line.

9. The method according to claim 1, wherein accessing the first data line comprises: Place the first number of series-coupled memory elements in a low-impedance mode; as well as When the second number of series-coupled memory elements are in default impedance mode: Access is made to the second number of the series-coupled memory elements; as well as Determine the second number of accessed series-coupled memory elements having a specified bit value.

10. The method of claim 1, further comprising: Couple the first access line to a specified level; Provide a driver signal to the first data line; as well as Read the signal at the first data line.

11. The method of claim 1, further comprising: Access the bit groups of the first data line; Receive intermediate calculations in response to the state of the bit group accessed on the first data line; as well as The intermediate calculations are combined to obtain partial calculation results.

12. The method of claim 1, further comprising: Access is made to a second bit at the first bit position of a second operand stored in the second part of the memory array, the second bit being accessible via a second data line in response to an activated first access line.

13. The method of claim 1, further comprising: Output the bits common to all operator sequences; Use operands to assign unique operators; as well as The access line is activated in response to the determination that the operator bit is logic high.

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