Shared vertical digit line for semiconductor devices

Abstract

The present disclosure relates to shared vertical digit lines for semiconductor devices. Systems, methods, and apparatus are provided for a vertically stacked memory cell array having horizontally oriented access devices and access lines and shared vertically oriented digit lines. The access devices have a first source / drain region and a second source / drain region separated by a channel region, and a gate opposite the channel region. A horizontally oriented access line is coupled to the gate and separated from the channel region by a gate dielectric. The memory cells have a horizontally oriented storage node coupled to the second source / drain region of the horizontally oriented access devices. The shared vertically oriented digit line is shared between two adjacent horizontally oriented access devices and coupled to the first source / drain region of the two adjacent horizontally oriented access devices.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to shared vertical digital lines for semiconductor devices. Background Technology

[0002] Memory is commonly implemented in electronic systems such as computers, cell phones, and handheld devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and can include Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Synchronous Dynamic Random Access Memory (SDRAM). Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, Nnitride read-only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random access memory), crosspoint memory, ferroelectric random access memory (FeRAM), etc.

[0003] As design rules shrink, the semiconductor space available for manufacturing memories containing DRAM arrays is decreasing. A corresponding memory cell for DRAM may include access means, such as transistors, having first and second source / drain regions separated by a channel region. The gate may be opposite to and separated from the channel region by a gate dielectric. Access lines, such as word lines, are electrically connected to the gate of the DRAM cell. The DRAM cell may include memory nodes, such as capacitor cells, coupled to a shared digital line via access means. Access means may be activated (e.g., to select a cell) via access lines coupled to access transistors. Capacitors may store charge corresponding to the data value (e.g., logic "1" or "0") of the corresponding cell. Summary of the Invention

[0004] This disclosure provides a method for forming a vertically stacked memory cell array having horizontally oriented access devices and access lines, as well as shared vertically oriented digital lines. The method includes: forming a plurality of first vertical openings having a first horizontal axis and a second horizontal axis through repeated iterative vertical stacking of a first dielectric material, a first semiconductor material having a first type of dopant, and a second dielectric material. The first vertical openings extend primarily along the second horizontal axis to form elongated vertical columns having first vertical sidewalls in the stack; depositing a third dielectric material in the plurality of first vertical openings; and forming a second vertical opening that extends through the vertical stack and primarily along the first horizontal axis to expose adjacent... The first semiconductor material has a second vertical sidewall in a first region; the second dielectric material is selectively etched along a second horizontal axis to form a plurality of first horizontal openings; a portion of the third dielectric material filling the plurality of first vertical openings between the first horizontal openings is removed to form a continuous second horizontal opening extending along the first horizontal axis; a conductive gate material recessed in the plurality of first horizontal openings is deposited on the gate dielectric material in the continuous second horizontal openings to form a horizontally oriented access line opposite to the channel region of the semiconductor material; and a plurality of third vertical openings are formed to deposit a second semiconducting material having a second type of dopant within the second vertical openings to form the shared vertically oriented digital line.

[0005] Another aspect of this disclosure provides a method for forming a vertically stacked memory cell array having horizontally oriented access devices and access lines, as well as shared vertically oriented digital lines. The method includes: forming a plurality of first vertical openings having a first horizontal axis and a second horizontal axis through repeated iterations of a vertical stack of a first dielectric material, a first semiconductor material, and a second dielectric material, the first vertical openings extending primarily along the second horizontal axis to form elongated vertical columns having first vertical sidewalls in the stack; filling the plurality of first vertical openings with a third dielectric material; forming a second vertical opening through the vertical stack and extending primarily along the first horizontal axis to expose a second vertical sidewall adjacent to a first region of the first semiconductor material; selectively etching the second dielectric material along the second horizontal axis to form vertically and horizontally separated columns in the stack. A plurality of first horizontal openings are horizontally separated by the third dielectric material; a portion of the third dielectric material filling the plurality of first vertical openings between the lateral sides of the first horizontal openings extending on the second horizontal direction axis is removed to form a continuous second horizontal opening extending on the first horizontal direction axis; a recessed conductive material is deposited on the gate dielectric material in the continuous second horizontal opening to form a horizontally oriented access line opposite to the channel region of the semiconductor material; a fourth dielectric material is deposited adjacent to the horizontally oriented access line to fill the plurality of first horizontal openings into the second vertical opening; a polysilicon material having a second type of dopant is deposited in the third vertical opening to form a shared vertically oriented digital line; and the polysilicon material is annealed to diffuse the second type of dopant outward into the first semiconductor material, thereby forming a first source / drain region of the horizontally oriented access device.

[0006] Another aspect of this disclosure provides a memory device comprising: a vertically stacked memory cell array having horizontally oriented access devices and access lines, and a shared vertically oriented digital line, the array comprising: a horizontally oriented access device having a first source / drain region and a second source / drain region separated by a channel region, and a gate opposite to the channel region and separated from the channel region by a gate dielectric; a horizontally oriented access line coupled to the gate and separated from the channel region by the gate dielectric; a horizontally oriented memory node electrically coupled to the second source / drain region of the horizontally oriented access device; and a vertically oriented digital line shared in two opposite directions between the two horizontally oriented access devices, electrically coupled to the first source / drain regions of the two horizontally oriented access devices. Attached Figure Description

[0007] Figure 1This is a schematic diagram of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0008] Figure 2 This is a perspective view showing a portion of a shared vertical digital line for a semiconductor device according to various embodiments of the present disclosure.

[0009] Figures 3A-3B A portion of a shared vertical digital line for a semiconductor device is shown according to several embodiments of the present disclosure.

[0010] Figure 4 This is a cross-sectional view of a vertically stacked memory cell array having shared vertical digital lines and horizontally oriented access lines for a semiconductor device, formed at multiple stages of a semiconductor manufacturing process for forming a vertically stacked memory cell array, according to several embodiments of the present disclosure.

[0011] Figures 5A-5B Examples of methods are shown for forming a vertically stacked memory cell array having shared vertical digital lines and horizontally oriented access lines for a semiconductor device at a stage of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0012] Figures 6A to 6E Examples of methods are shown for forming a vertically stacked memory cell array having shared vertical digital lines and horizontally oriented access lines for a semiconductor device at another stage of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0013] Figures 7A to 7E Examples of methods are shown for forming a vertically stacked memory cell array having shared vertical digital lines and horizontally oriented access lines for a semiconductor device at another stage of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0014] Figures 8A to 8E Examples of methods are shown for forming a vertically stacked memory cell array having shared vertical digital lines and horizontally oriented access lines for a semiconductor device at another stage of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0015] Figures 9A to 9E Examples of methods are shown for forming a vertically stacked memory cell array having shared vertical digital lines and horizontally oriented access lines for a semiconductor device at another stage of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0016] Figures 10A to 10E Examples of methods are shown for forming a vertically stacked memory cell array having shared vertical digital lines and horizontally oriented access lines for a semiconductor device at another stage of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0017] Figures 11A to 11E Examples of methods are shown for forming a vertically stacked memory cell array having shared vertical digital lines and horizontally oriented access lines for a semiconductor device at another stage of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0018] Figures 12A to 12E Examples of methods are shown for forming a vertically stacked memory cell array having shared vertical digital lines and horizontally oriented access lines for a semiconductor device at another stage of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0019] Figures 13A to 13E Examples of methods are shown for forming a vertically stacked memory cell array having shared vertical digital lines and horizontally oriented access lines for a semiconductor device at another stage of a semiconductor manufacturing process, according to several embodiments of the present disclosure.

[0020] Figure 14 These are examples of multiplexers for semiconductor devices according to various embodiments of the present disclosure.

[0021] Figure 15 Examples of multiplexers coupled to an example horizontally oriented access device and access line, and a shared vertically oriented digital line for a semiconductor device, according to various embodiments of the present disclosure.

[0022] Figure 16 This is a block diagram of a computing system in the form of a memory device 1693 according to several embodiments of the present disclosure. Detailed Implementation

[0023] Embodiments of this disclosure describe a shared vertical digital line for a semiconductor device. The shared vertical digital line comprises horizontally oriented access devices and access lines in a vertically stacked memory cell array. The horizontally oriented access devices are integrated with the horizontally oriented access lines and with the shared vertical digital line. The shared vertical digital line, shared between two horizontally oriented access devices, is coupled to a first source / drain region of the two horizontally oriented access devices. This further improves the array efficiency of the digital line.

[0024] Figure 1 This is a block diagram of an apparatus according to several embodiments of the present disclosure. Figure 1 A circuit diagram is shown, illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure. Figure 1A cell array with multiple sub-cell arrays 101-1, 101-2, ..., 101-N is shown. Sub-cell arrays 101-1, 101-2, ..., 101-N can be arranged along a second direction (D2) 105. Each of the sub-cell arrays, such as sub-cell array 101-2, can contain multiple access lines 107-1, 107-2, ..., 107-Q (which may also refer to word lines). Additionally, each of the sub-cell arrays, such as sub-cell array 101-2, can contain multiple shared digital lines 103-1, 103-2, ..., 103-Q (which may also be referred to as bit lines, data lines, or sensing lines). Figure 1 In this embodiment, access lines 107-1, 107-2, ..., 107-Q are shown extending in a first direction (D1) 109, and shared digital lines 103-1, 103-2, ..., 103-Q are shown extending in a third direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal (“XY”) plane. The third direction (D3) 111 can be considered to be in a vertical (“Z”) plane. Therefore, according to the embodiment described herein, shared digital lines 103-1, 103-2, ..., 103-Q extend in a vertical direction, for example, in a third direction (D3) 111.

[0025] A memory cell (e.g., 110) may include access means (e.g., access transistors) and memory nodes located at the intersections of each access line 107-1, 107-2, ..., 107-Q and each shared digital line 103-1, 103-2, ..., 103-Q. The memory cell can be written to or read from using the access lines 107-1, 107-2, ..., 107-Q and the shared digital lines 103-1, 103-2, ..., 103-Q. Access lines 107-1, 107-2, ..., 107-Q can electrically interconnect memory cells along the horizontal rows of each sub-cell array 101-1, 101-2, ..., 101-N, and digital lines 103-1, 103-2, ..., 103-Q can electrically interconnect memory cells along the vertical columns of each sub-cell array 101-1, 101-2, ..., 101-N. A memory cell (e.g., 110) can be located between an access line (e.g., 107-2) and a shared digital line (e.g., 103-2). Each memory cell can be uniquely addressed by a combination of access lines 107-1, 107-2, ..., 107-Q and shared digital lines 103-1, 103-2, ..., 103-Q.

[0026] Access lines 107-1, 107-2, ..., 107-P may be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Access lines 107-1, 107-2, ..., 107-Q may extend in a first direction (D1) 109. Access lines 107-1, 107-2, ..., 107-Q in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 111).

[0027] Shared digital lines 103-1, 103-2, ..., 103-Q may be or include conductive patterns (e.g., metal lines) extending in a vertical direction (e.g., on a third direction (D3) 111) relative to the substrate. Shared digital lines in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a first direction (D1) 109.

[0028] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line (e.g., 107-2), and a first conductive node (e.g., a first source / drain region) of an access means (e.g., a transistor) of memory cell 110 may be connected to a shared digital line (e.g., 103-2). Each of the memory cells (e.g., memory cell 110) may be connected to a storage node, such as a capacitor. A second conductive node (e.g., a second source / drain region) of an access means (e.g., a transistor) of memory cell 110 may be connected to a storage node, such as a capacitor. Although the references to first and second source / drain regions are used herein to denote two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as “first” and / or “second” have a single meaning. It is only contemplated that one of the source / drain regions is connected to a shared digital line (e.g., 103-2) and the other may be connected to a storage node.

[0029] Figure 2 Perspective views are shown according to some embodiments of the present disclosure, which depict three-dimensional (3D) semiconductor memory devices (e.g., Figure 1 The sub-cell array 101-2 shown is a vertically oriented stack of memory cells in the array. Figure 2 A perspective view is shown, which shows Figure 2 The unit cell of the 3D semiconductor memory device shown is, for example Figure 1 The memory unit 110 shown.

[0030] like Figure 2 As shown, a bonding can be formed on the substrate 200. Figure 1 One of the described arrays of sub-cells, such as 101-2. For example, substrate 200 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0031] like Figure 2 As shown in the example embodiment, memory cells extending in a vertical direction (e.g., third direction (D3)111) can be fabricated on the substrate 200. Figure 1 The memory cells 110 in the memory are vertically stacked. According to some embodiments, the vertical stacking of the memory cells can be manufactured such that each memory cell (e.g., Figure 1 The memory cells 110 are formed on multiple vertical levels (e.g., a first level (L1), a second level (L2), and a third level (L3)). Repeating vertical levels L1, L2, and L3 can be formed in the vertical direction (e.g., ...). Figure 1 The components are arranged, for example, "stacked", on the third direction (D3) 111. Each of the repeating vertical levels L1, L2, and L3 may contain multiple discrete components, such as zones, of horizontally oriented access devices 230 (e.g., transistors) and memory nodes (e.g., capacitors), including access lines 107-1, 107-2, ..., 107-Q connections and shared digital lines 103-1, 103-2, ..., 103-Q connections. Multiple components discrete with the horizontally oriented access devices 230 (e.g., transistors) may be formed in multiple iterations of the vertically repeating layers within each level, as described below. Figure 4 And as described in more detail in the following figures, these components can be found in similar... Figure 1 The second direction (D2)105 extends horizontally on the second direction (D2)205 shown.

[0032] A plurality of discrete components of a horizontally oriented access device 230 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223, separated by a channel region 225, extending laterally in a second direction (D2) 205 and formed in the body of the access device. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise an n-type dopant region formed in the p-type doped body of the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise a p-type dopant formed in the n-type doped body of the access device to form a p-type conductive transistor. By way of example and not limitation, the n-type dopant may comprise phosphorus (P) atoms and the p-type dopant may comprise boron (B) atoms formed in a relatively doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0033] Storage node 227 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 2As shown, storage node 227 (e.g., a capacitor) may be connected to the second source / drain region 223 of the access device. A storage node may be or contain a memory element capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistor body containing a phase change material, etc. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g. Figure 1 Each access device associated with a memory node in memory cell 110 can be similarly located in a memory node with a memory node ... Figure 1 It extends on the second direction (D2)205 as shown in the second direction (D2)105.

[0034] like Figure 2 As shown, multiple horizontally oriented access lines 207-1, 207-2, ..., 207-Q are in the first direction (D1) 209 (similar to...). Figure 1 Extending along the first direction (D1) 109). Multiple horizontally oriented access lines 207-1, 207-2, ..., 207-Q can be similar to... Figure 1 The access lines 107-1, 107-2, ..., 107-Q are shown. Multiple horizontally oriented access lines 207-1, 207-2, ..., 207-Q may be arranged (e.g., "stacked") along a third direction (D3) 211. The multiple horizontally oriented access lines 207-1, 207-2, ..., 207-Q may contain a conductive material. For example, the conductive material may contain one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0035] In the vertical hierarchies (L1)213-1, (L2)213-2, and (L3)213-P, the horizontally oriented memory cells (e.g., Figure 1 The memory cells 110 in the memory can be horizontally spaced apart from each other in the first direction (D1) 209. However, as described below... Figure 4As described in the figures below, a plurality of discrete components extending laterally in the second direction (D2) 205 to the horizontally oriented access device 230 (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225) and a plurality of horizontally oriented access lines 207-1, 207-2, ..., 207-Q extending laterally in the first direction (D1) 209 can be formed in different vertical layers within each level. For example, the plurality of horizontally oriented access lines 207-1, 207-2, ..., 207-Q extending in the first direction (D1) 209 can be formed on a top surface opposite to and electrically coupled to the channel region 225, separated therefrom by the gate dielectric, and orthogonal to the horizontally oriented access device 230 (e.g., a transistor) extending laterally in the second direction (D2) 205. In some embodiments, the plurality of horizontally oriented access lines 207-1, 207-2, ..., 207-Q extending in the first direction (D1) 209 are formed in a higher vertical layer (e.g., in layer (L1)) than the layer in which the discrete components forming the horizontally oriented access device (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225) are formed, and are farther from the substrate 200.

[0036] like Figure 2 As shown in the example embodiments, shared digital lines 203-1, 203-2, ..., 203-Q extend vertically relative to substrate 200 (e.g., on third-direction (D3) 211). Furthermore, as... Figure 2 As shown, a sub-cell array (e.g., Figure 1The shared digital lines 203-1, 203-2, ..., 203-Q in the sub-cell array 101-2 can be spaced apart from each other in the first direction (D1) 209. The shared digital lines 203-1, 203-2, ..., 203-Q can be provided, which extend vertically relative to the substrate 200 in the third direction (D3) 211, vertically aligned with the source / drain regions, to serve as the first source / drain regions 221. Alternatively, as shown, each of the horizontally oriented access devices 230 (e.g., transistors) extending laterally in the second direction (D2) 205 is vertically adjacent to the first source / drain region 221, but adjacent to each other in the layers (e.g., the first layer (L1)) on the first direction (D1) 209. Each of the shared digital lines 203-1, 203-2, ..., 203-Q may extend vertically in a third direction (D3) adjacent to the first source / drain region 221 of the corresponding horizontally oriented access device in a plurality of vertically stacked horizontally oriented access devices 230 (e.g., transistors). In some embodiments, the plurality of shared vertically oriented digital lines 203-1, 203-2, ..., 203-Q extending in the third direction (D3) 211 may be directly and / or connected to the side surface of the first source / drain region 221 via additional contacts including metal silicide.

[0037] For example, and such Figure 2 As shown in more detail, the first (e.g., 203-1) of the shared vertically extending digital line may be adjacent to the first source / drain region 221 of the first horizontally oriented access device 230 (e.g., transistor) in the first level (L1) 213-1, the first source / drain region 221 of the first horizontally oriented access device 230 (e.g., transistor) in the second level (L2) 213-2, and the first source / drain region 221 of the first horizontally oriented access device 230 (e.g., transistor) in the third level (L3) 213-P, etc. Similarly, the second (e.g., 203-2) in the shared vertically extended digital line may be adjacent to the first source / drain region 221 of the second horizontally oriented access device 230 (e.g., transistor) in the first level (L1) 213-1, and spaced apart from the first in the first direction (D1) 209. Furthermore, the second (e.g., 203-2) in the shared vertically extended digital line may be adjacent to the first source / drain region 221 of the second horizontally oriented access device 230 (e.g., transistor) in the second level (L2) 213-2, and the first source / drain region 221 of the second horizontally oriented access device 230 (e.g., transistor) in the third level (L3) 213-P, etc. The embodiments are not limited to a specific number of levels.

[0038] The shared vertically extending digital lines 203-1, 203-2, ..., 203-Q may contain conductive materials, such as one of doped semiconductor materials, conductive metal nitrides, metals, and / or metal-semiconductor compounds. The shared digital lines 203-1, 203-2, ..., 203-Q may correspond to a combination of... Figure 1 The shared digital line (DL) is described.

[0039] Figure 3A A more detailed illustration of a vertically stacked memory cell array according to some embodiments of the present disclosure (e.g.) Figure 1 Within the sub-cell array 101-2, the unit cell (e.g., Figure 1 (Memory unit 110 in the middle). For example Figure 3A As shown, the first source / drain region 321 and the second source / drain region 323 can be impurity-doped regions of the lateral access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be similar to... Figure 2 The first source / drain region 221 and the second source / drain region 223 are shown. The first source / drain region 221 and the second source / drain region 223 can be formed by n-type or p-type dopants doped in the host region. The embodiments are not limited thereto.

[0040] For example, in an n-type conductive transistor configuration, the body region of the horizontally oriented access device 330 (e.g., a transistor) can be formed of a lightly doped p-type (p-) semiconductor material. In one embodiment, the body region and the channel 325 separating the first source / drain region 321 and the second source / drain region 323 can comprise a lightly doped p-type (e.g., low dopant concentration (p-)) polysilicon material composed of boron (B) atoms as impurity dopants for polysilicon. The first source / drain region 321 and the second source / drain region 323 may also comprise metals and / or metal composites formed using atomic layer deposition processes, etc., containing: ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), highly doped degenerate semiconductor materials, and / or indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x At least one of O3). However, the embodiments are not limited to these examples. As used herein, degenerate semiconductor material means a semiconductor material, such as polycrystalline silicon, containing a high level of doping that utilizes significant interactions between dopants such as phosphorus (P), boron (B), etc. In contrast, non-degenerate semiconductors contain a moderate level of doping, wherein the dopant atoms are well separated from each other in the semiconductor main lattice with negligible interactions.

[0041] In this example, the first source / drain region 321 and the second source / drain region 323 may contain highly doped n-type conductive impurities (e.g., highly doped (n+)) doped into the first source / drain region 321 and the second source / drain region 323. In some embodiments, the highly doped n-type conductive first drain region 321 and the second drain region 323 may contain a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the horizontally oriented access device 330 (e.g., a transistor) may have a p-type conductive configuration, in which case the conductivity type of the impurity (e.g., the dopant) will be reversed.

[0042] The gate dielectric material 304 may comprise, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, or a combination thereof. The embodiments are not limited thereto. For example, in a high-k dielectric material example, the gate dielectric material 304 may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0043] like Figure 3A As shown in the example implementation, similar to Figure 2 The shared digital lines 203-1, 203-2, ..., 203-Q and Figure 1 The shared digital lines 103-1, 103-2, ..., 103-Q (e.g., 303-1) in the body may extend vertically in a third direction (D3) 311 adjacent to the first source / drain region 321 to a horizontally oriented access device 330 (e.g., a transistor), which is horizontally oriented between the first source / drain region 321 and the second source / drain region 323 along a second direction (D2) 305.

[0044] Figure 3B This illustrates a vertically stacked memory cell array with a dual-gate horizontal access device structure (e.g.) Figure 1 Within the sub-cell array 101-2, the unit cell (e.g., Figure 1 (Memory unit 110 in the memory). For example Figure 3B As shown, the first source / drain region 321 and the second source / drain region 323 can be impurity-doped regions of the horizontally oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be similar to... Figure 2 The first source / drain region 221 and the second source / drain region 223 shown are as follows: Figure 3AThe first source / drain region 321 and the second source / drain region 323 are shown. The first and second source / drain regions can be separated by a channel 325 formed in a semiconductor material body (e.g., a body region) of the horizontally oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be formed by an n-type or p-type dopant doped in the body region. Embodiments are not limited thereto.

[0045] like Figure 3B As shown in the example implementation, similar to Figure 2 The shared digital lines 203-1, 203-2, ..., 203-Q and Figure 1 The shared digital lines 103-1, 103-2, ..., 103-Q (e.g., 303-1) in the body may extend vertically in a third direction (D3) 311 adjacent to the first source / drain region 321 to a horizontally oriented access device 330 (e.g., a transistor), which is horizontally oriented between the first source / drain region 321 and the second source / drain region 323 along a second direction (D2) 305.

[0046] Figure 3B An example embodiment with a dual-gate structure is shown, wherein the horizontally oriented access device 330 is formed of a conductive gate material and has a top portion above a channel region 325 of semiconductor material and a bottom portion below a channel region 325. In one embodiment, the horizontally oriented access device 330 may be formed as a gate-all-around (GAA) horizontal access device, wherein the conductive gate material completely surrounds each surface of the channel region 325 formed in the semiconductor material body.

[0047] Figure 4 In the process of forming a shape with such Figure 1 A cross-sectional view of a stage of a semiconductor manufacturing process for a vertically stacked memory cell array with shared vertical digital lines and horizontally oriented access lines for a semiconductor device, as shown in Figures 3 and according to several embodiments of the present disclosure.

[0048] exist Figure 4In the example embodiment shown, the method includes iteratively depositing alternating layers of first dielectric material 430-1, 430-2, ..., 430-N (collectively referred to as first dielectric material 430), first semiconductor material 432-1, 432-2, ..., 432-N (collectively referred to as first semiconductor material 432) having a first type of dopant (e.g., p-type dopant, such as boron (B)), and second dielectric material 433-1, 433-2, ..., 433-N (collectively referred to as second dielectric 433) to form a vertical stack 401 on the working surface of a semiconductor substrate 400. In one embodiment, the first dielectric material 430 may be deposited to have a thickness in the range of twenty (20) nanometers (nm) to sixty (60) nm (e.g., vertical height in a third direction (D3)). In one embodiment, the first semiconductor material 432 may be deposited to have a thickness in the range of twenty (20) nm to one hundred (100) nm (e.g., vertical height). In one embodiment, the second dielectric material 433 may be deposited with a thickness (e.g., vertical height) in the range of ten (10) nm to thirty (30) nm. However, the embodiments are not limited to these examples. Figure 4 As shown, vertical direction 411 is shown as... Figure 1 The third direction (D3) shown in -3 is similar to the third direction (D3) in the first, second and third directions, such as the z direction in the xyz coordinate system.

[0049] In some embodiments, the first dielectric materials 430-1, 430-2, ..., 430-N may be interlayer dielectrics (ILDs). By way of example and not limitation, the first dielectric materials 430-1, 430-2, ..., 430-N may include oxide materials, such as SiO2. In another example, the first dielectric materials 430-1, 430-2, ..., 430-N may include silicon nitride (Si3N4) material (also referred to herein as “SiN”). In yet another example, the first dielectric materials 430-1, 430-2, ..., 430-N may include silicon oxycarbide (SiO2). x C y In another example, the first dielectric material 430-1, 430-2, ..., 430-N may comprise silicon oxynitride (SiO2). x N y Materials (also referred to herein as "SiON") and / or combinations thereof. Examples are not limited to these instances.

[0050] In some embodiments, the first semiconductor materials 432-1, 432-2, ..., 432-N may comprise silicon (Si) material in a polycrystalline and / or amorphous state. The first semiconductor materials 432-1, 432-2, ..., 432-N may be lightly doped p-type (p-) silicon materials. The first semiconductor materials 432-1, 432-2, ..., 432-N can be formed by vapor-phase doping with a first type of dopant. For example, the first semiconductor materials 432-1, 432-2, ..., 432-N can be formed by vapor-phase doping with boron atoms (B) at a low concentration as an impurity dopant to form lightly doped p-type (p-) silicon materials. The lightly doped p-type (p-) silicon material may be amorphous silicon material. However, the embodiments are not limited to these examples.

[0051] In some embodiments, the second dielectric materials 433-1, 433-2, ..., 433-N may be interlayer dielectrics (ILDs). By way of example and not limitation, the second dielectric materials 433-1, 433-2, ..., 433-N may include nitride materials. The nitride material may be silicon nitride (Si3N4) material (also referred to herein as “SiN”). In another example, the second dielectric materials 433-1, 433-2, ..., 433-N may include silicon oxycarbide (SiOC) material. In yet another example, the second dielectric materials 433-1, 433-2, ..., 433-N may include silicon oxynitride (SiON) and / or combinations thereof. Embodiments are not limited to these examples. However, according to embodiments, the second dielectric materials 433-1, 433-2, ..., 433-N are intentionally selected to be different from the first dielectric materials 430-1, 430-2, ..., 430-N in terms of material or composition, such that a selective etching process can be performed on one of the first and second dielectric layers. For example, a selective etching process can be performed on the first and second dielectric layers and / or on another of the first semiconductor materials 432 (e.g., the second SiN dielectric materials 433-1, 433-2, ..., 433-N) relative to the first semiconductor materials 432-1, 432-2, ..., 432-N and the first oxide dielectric materials 430-1, 430-2, ..., 430-N.

[0052] According to a semiconductor manufacturing process (e.g., chemical vapor deposition (CVD)), alternating layers of first dielectric material 430-1, 430-2, ..., 430-N, layers of first semiconductor material 432-1, 432-2, ..., 432-N, and layers of second dielectric material 433-1, 433-2, ..., 433-N can be deposited in a semiconductor fabrication apparatus in a repetitive iteration. However, the embodiments are not limited to this example and other suitable semiconductor fabrication techniques can be used to deposit alternating layers of first dielectric material, first semiconductor material, and second dielectric material in a repetitive iteration to form a vertical stack 401.

[0053] These layers can be iterated repeatedly in the vertical direction. Figure 4 In the example, three layers of repeated iterations are shown, numbered 1, 2, and 3. For example, the stack may include: a first layer having a first dielectric material 430-1, a first semiconductor material 432-1, and a second dielectric material 433-1; a second layer having a first dielectric material 430-2, a first semiconductor material 432-2, and a second dielectric material 433-2; and a third layer having a first dielectric material 430-3, a first semiconductor material 432-3, and a second dielectric material 433-3. Therefore, the stack may include: a first oxide material 430-1, a first first semiconductor material 432-1, a first nitride material 433-1, a second oxide material 430-2, a second first semiconductor material 432-2, a second nitride material 433-2, a third oxide material 430-3, a third first semiconductor material 432-3, and a third nitride material 433-3 in further repeated iterations. However, the embodiments are not limited to this example and may include more or fewer repeated iterations.

[0054] Figure 5A Shown in the formation of having as Figure 1 An example method of one stage of a semiconductor manufacturing process for a vertically stacked memory cell array with shared vertical digital lines and horizontally oriented access lines for a semiconductor device, as shown in Figures 3 and according to several embodiments of the present disclosure. Figure 5A This image shows a top-down view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 5A In the example embodiment shown, the method includes using an etching process through a vertically stacked substrate to form a plurality of first vertical openings 500 having a first horizontal axis (D1) 509 and a second horizontal axis (D2) 505. In one example, such as Figure 5A As shown, a plurality of first vertical openings 500 extend primarily along a second horizontal axis (D2) 505 and can form elongated vertical columns 513-1, 513-2, ..., 513-M (collectively and / or individually referred to as 513) with sidewalls 514 in the vertical stack. The plurality of first vertical openings 500 can be formed using photolithography to pattern a photomask 535 on the vertical stack, for example, to form a hard mask (HM), prior to etching the plurality of first vertical openings 500. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0055] The opening 500 can be filled with a third dielectric material 539. In one example, a spin dielectric process can be used to fill the opening 500. In one embodiment, the third dielectric material 539 can be an oxide material. However, the embodiments are not limited thereto. In some embodiments, the third dielectric material 539 can be formed of a material different from the first dielectric material 530. For example, the oxide material used to form the third dielectric material 539 can be different from the oxide material used to form the first dielectric material 530. In some embodiments, the dielectric material 539 can be formed of the same material as the first dielectric material 530 and / or the second dielectric material 533.

[0056] Figure 5B It is along Figure 5A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific time point in the semiconductor manufacturing process. Figure 5B The cross-sectional view shown illustrates alternating layers of first dielectric materials 530-1, 530-2, ..., 530-N, first semiconductor materials 532-1, 532-2, ..., 532-N, and second dielectric materials 533-1, 533-2, ..., 533-N repeatedly iteratively on a semiconductor substrate 500 to form a vertical stack, for example, as... Figure 4 401 shown.

[0057] like Figure 5B As shown, multiple first vertical openings can be formed through layers within a vertically stacked memory cell to expose the vertical sidewalls in the vertical stack and form elongated vertical columns 513, which are then filled with a third dielectric material 539. The first vertical openings can be formed through repeated iterations of oxide material 530, first semiconductor material 532, and nitride material 533. Therefore, the first vertical openings can be formed through first oxide material 530-1, first semiconductor material 532-1, first nitride material 533-1, second oxide material 530-2, second semiconductor material 532-2, second nitride material 533-2, third oxide material 530-3, third semiconductor material 532-3, and third nitride material 533-3. However, the embodiments are not limited to these. Figure 5B The vertical opening shown. Multiple vertical openings can be formed through the material layer. A first vertical opening can be formed to expose the vertical sidewalls in the vertical stack. The first vertical opening can extend along the second horizontal axis (D2) 505 to form an elongated column of vertical columns 513 with the first vertical sidewalls in the vertical stack, and then be filled with a third dielectric 539.

[0058] like Figure 5BAs shown, a third dielectric material 539 (e.g., an oxide or other suitable spin dielectric (SOD)) can be deposited in the first vertical opening using a process such as CVD to fill the first vertical opening. The third dielectric material 539 can also be formed from silicon nitride (Si3N4) material. In another example, the third dielectric material 539 may comprise silicon oxynitride (SiO2). x N y (and / or combinations thereof.) Embodiments are not limited to these examples. Multiple first vertical openings can be formed by patterning a photolithographic mask 535 on a vertically stacked structure using photolithography techniques (e.g., to form a hard mask (HM)) prior to etching multiple first vertical openings. In one embodiment, a hard mask 537 may be deposited on a third dielectric material 539. In some embodiments, subsequent photolithographic material 537 (e.g., the hard mask) may be deposited using CVD and planarized using CMP to cover and close the first vertical openings on the vertically stacked structure and the previous hard mask 537. Similar semiconductor process techniques may be used at other points in the semiconductor manufacturing process described herein.

[0059] Figure 6A Shown in the formation of having as Figure 1 Example method of another stage of semiconductor manufacturing process for a vertically stacked memory cell array with shared vertical digital lines and horizontally oriented access lines for a semiconductor device, as shown in Figures 3 and according to several embodiments of the present disclosure. Figure 6A This image shows a top-down view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 6A In the example embodiment shown, a plurality of first vertical openings 600 having a first horizontal axis (D1) 609 and a second horizontal axis (D2) 605 have been formed through a vertical stack to the substrate. In one example, as Figure 6A As shown, a plurality of first vertical openings 600 extend primarily along a second horizontal axis (D2) 605 and can form sidewalls 614 in an elongated column of vertical columns 613 in a vertical stack.

[0060] exist Figure 6A The method includes using photolithography to pattern a mask and using an etching process to form a continuous second opening 670 that extends across the first vertical opening 600 primarily along a first horizontal axis (D1) 609.

[0061] Figure 6B It is along Figure 6A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific time point in the semiconductor manufacturing process. Figure 6BThe cross-sectional view shown illustrates alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, first semiconductor materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N repeatedly iteratively on a semiconductor substrate 600 to form a vertical stack, for example, as... Figure 4 401 shown.

[0062] like Figure 6B As shown, multiple first vertical openings have been formed through the vertical stack, in which vertical stack memory cells will be formed to expose the vertical sidewalls in the vertical stack.

[0063] like Figure 6B As shown, a third dielectric material 639 (e.g., oxide or other suitable spin dielectric (SOD)) has been deposited in the first vertical opening using a process such as CVD to fill the first vertical opening. A photolithographic material 637 (e.g., a hard mask) can be deposited using CVD and planarized using chemical mechanical planarization (CMP) to cover and close the first vertical opening on the vertical stack. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0064] Figure 6C In the formation of such Figure 1 A cross-sectional view of another stage of a semiconductor manufacturing process for a semiconductor device with shared vertical digital lines, having horizontally oriented access means and horizontally oriented access lines, according to several embodiments of the present disclosure. Figure 6C Show along Figure 6A The cross-sectional view taken by the cutting line B-B' in the figure.

[0065] A continuous second vertical opening 670 may be formed in a vertical stack, wherein a first portion of the vertical stack is located on one side of the continuous second vertical opening 670 and a second portion of the vertical stack is located on the other side of the continuous second vertical opening 670. The continuous second vertical opening 670 may extend primarily along a first horizontal axis to expose a second vertical sidewall adjacent to a first region of the first semiconductor material 632.

[0066] Etching agent can be flowed into the second vertical opening 670 to selectively etch a portion of the second dielectric material 633, thereby forming a first horizontal opening 673 extending primarily along the second horizontal axis (D2) 605. For example, etching agent can be flowed into the second vertical opening 670 to selectively etch the nitride material 633. The etchant can be targeted at all iterations of the second dielectric material 633 within the stack. Thus, the etchant can be targeted at the first nitride material 633-1, the second nitride material 633-2, and the third nitride material 633-3 within the stack.

[0067] Selective etching processes may include one or more etching chemicals selected from aqueous etching chemicals, semi-aqueous etching chemicals, steam etching chemicals, or plasma etching chemicals, as well as other possible selective etching chemicals. For example, dry etching chemicals of oxygen (O2) or O2 and sulfur dioxide (SO2) may be used. As another example, dry etching chemicals of O2 or O2 and nitrogen (N2) may be used to selectively etch the second dielectric material 633. Alternatively or additionally, selective etching to remove the second dielectric material 633 may include selective etching chemicals of phosphoric acid (H3PO4) and / or the use of selective solvents to dissolve the second dielectric material 633.

[0068] A selective etching process can etch nitride material 633 to form a first horizontal opening 673. The selective etching process can also etch the second dielectric material 633 in two opposite directions along a second horizontal axis 605 to form a plurality of first horizontal openings 673 in opposite directions and to form two adjacent horizontal access devices sharing a vertically oriented digital line for direct electrical contact with the formed first source / drain regions. The selective etching process can be performed such that the first horizontal opening 673 has a length or depth (DIST 1) of a first distance 676 from the second vertical opening 670. The first distance (DIST 1) 676 can be a distance greater than the distance used to form the first source / drain regions. The second dielectric material 633 can be etched backward from the second vertical opening to a first distance (DIST 1) 676 in the range of approximately fifty (50) to two hundred and fifty (250) nanometers (nm). The first distance (DIST 1) 676 can be controlled by controlling the time, the composition of the etchant gas, and the etching rate (e.g., rate, concentration, temperature, pressure, and time parameters) of the reactive gas flowing into the second vertical opening 670. Therefore, the nitride material 633 can be etched from the vertical opening to the first distance 676. Selective etching can be isotropic but selective for the second dielectric material 633, thus stopping substantially on the first dielectric material 630 and the first semiconductor material. Thus, in one example embodiment, the selective etching process can remove substantially all of the nitride material 633 from the top surface of the first semiconductor material 632 to the bottom surface of the first dielectric material (e.g., oxide material) in an overlying layer, while horizontally etching the first distance (DIST 1) 676 adjacent to the first region of the first semiconductor material 632 through the second vertical opening 670. In this example, the horizontal opening 673 will have a height (H1) substantially equivalent to and controlled by the thickness of the deposited second dielectric layer 633 (e.g., nitride material). However, the embodiments are not limited to this example. As described herein, a selective etching process can etch the nitride material 633 to a first distance (DIST1) 676 and a height (H1).

[0069] Figure 6D Show along Figure 6A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 6D The cross-sectional view shown extends along a second horizontal axis (D2) 605 outside the area of ​​the horizontally oriented access device and the horizontally oriented storage node. A continuous second vertical opening 670 can be seen through the third dielectric material 639.

[0070] exist Figure 6E In this process, a third dielectric material 639, such as an oxide or other suitable spin dielectric (SOD), can be deposited in the first vertical opening using a process such as CVD. The third dielectric material 639 shown is spaced along a first direction (D1) of the three-dimensional array of vertically oriented memory cells, the first direction extending into and outward from the drawing plane. A hard mask 637, which can be deposited using CVD and planarized using chemical mechanical planarization (CMP), can be seen on the third dielectric material 639. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0071] Figure 6E Show along Figure 6A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 6E The cross-sectional diagram shown is a repeating iterative axis extending from right to left along the alternating layers of the first dielectric material 630-1, 630-2, ..., 630-N and the first semiconductor material 632-1, 632-2, ..., 632-N in the drawing plane, extending in the first direction (D1) 609, intersecting multiple third dielectric filling materials 639.

[0072] In this cross-sectional view, the etched second dielectric materials 633-1, 633-2, ..., 633-N can be seen, allowing the second dielectric materials 633-1, 633-2, ..., 633-N to be completely removed by selective etching to form the first horizontal opening 673. Figure 6E In the diagram, a third dielectric filler material 639 is shown to separate the space between first horizontal openings 673, which may be spaced apart along a first direction (D1) 609 and vertically stacked in an array extending along a third direction (D3) 611 in a three-dimensional (3D) memory. A hard mask 637 may be deposited using CVD and planarized using chemical mechanical planarization (CMP) to cover and close the first vertical openings on the vertical stack.

[0073] Figure 7AShown in the formation of having as Figure 1 Example method of another stage of semiconductor manufacturing process for a vertically stacked memory cell array with shared vertical digital lines and horizontally oriented access lines for a semiconductor device, as shown in Figures 3 and according to several embodiments of the present disclosure. Figure 7A This image shows a top-down view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 7A In the illustrated embodiment, the method includes using an etching process to etch a third dielectric material 739 through a plurality of first vertical openings 700 having a first horizontal axis (D1) 709 and a second horizontal axis (D2) 705, through a vertical stack to a substrate. The plurality of first vertical openings 700 and the continuous second openings 770 can be seen within a hard mask 737 within the working surface of the vertical semiconductor stack. The third dielectric material 739 can be etched to a certain height within the hard mask 737.

[0074] Figure 7B It is along Figure 7A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific time point in the semiconductor manufacturing process. Figure 7B The cross-sectional view shown illustrates the repeated iteration of alternating layers of first dielectric material 730-1, 730-2, ..., 730-N, first semiconductor material 732-1, 732-2, ..., 732-N, and second dielectric material 733-1, 733-2, ..., 733-N on semiconductor substrate 700.

[0075] like Figure 7B As shown, multiple first vertical openings can be formed through layers within a vertically stacked memory cell to expose the vertical sidewalls in the vertical stack. The first vertical openings can be formed through repeated iterations of oxide material 730, first semiconductor material 732, and nitride material 733. Therefore, the first vertical openings can be formed through first oxide material 730-1, first semiconductor material 732-1, first nitride material 733-1, second oxide material 730-2, second semiconductor material 732-2, second nitride material 733-2, third oxide material 730-3, third semiconductor material 732-3, and third nitride material 733-3. However, the embodiments are not limited to these. Figure 7B The vertical opening shown. Multiple vertical openings can be formed through the material layer. A first vertical opening can be formed to expose the vertical sidewalls in the vertical stack. The first vertical opening can extend on the second horizontal axis (D2) 705 to form an elongated column of vertical columns with the first vertical sidewalls in the vertical stack.

[0076] like Figure 7BAs shown, a third dielectric material 739, such as an oxide or other suitable spin dielectric (SOD), filling the first vertical opening can be seen within it. A hard mask 737 can be deposited to cover and close the first vertical opening on the vertical stack. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0077] Figure 7C In the formation of such Figure 1 A cross-sectional view of another stage of a semiconductor manufacturing process for a semiconductor device with shared vertical digital lines, having horizontally oriented access means and horizontally oriented access lines, according to several embodiments of the present disclosure. Figure 7C Show along Figure 7A The cross-sectional view taken by the cutting line B-B' in the figure.

[0078] The second dielectric material 733 can be selectively etched on the second horizontal axis (D2) 705 to form a plurality of first horizontal openings 773. An etchant can be flowed into the second vertical opening 770 to selectively etch a portion of the second dielectric material 733. Therefore, the etchant can target the first nitride material 733-1, the second nitride material 733-2, and the third nitride material 733-3 within the stack. The selective etching process can etch the nitride material 733 to form the first horizontal openings 773. The selective etching process can etch the nitride material 733 to a first distance (DIST 1) 776 and a height (H1).

[0079] like Figure 7C As shown, another etchant can be flowed into the second vertical opening 770 to penetrate the third dielectric material 739 in a lateral drilling manner, thereby forming a continuous second horizontal opening extending along the first horizontal axis (D1) 709. The etchant may be selective only towards the third dielectric material 739 and may not etch the first dielectric material 730. Therefore, the spin dielectric 739 can be formed of a material different from the oxide material 730.

[0080] A gate dielectric material 738 may be deposited in a plurality of first horizontal openings 773 formed by etching a second dielectric material 733. The gate dielectric material 738 may be conformally deposited on a first semiconductor material 732. The gate dielectric material 738 may be conformally deposited in the plurality of first horizontal openings 773 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first horizontal openings 773. In another embodiment, the gate dielectric material 738 may be thermally grown onto the surface of the first semiconductor material 732. By way of example and not limitation, the gate dielectric 738 may include silicon dioxide (SiO2) material, aluminum oxide (Al2O3) material, high dielectric constant (k) (e.g., high k) dielectric material, and / or combinations thereof.

[0081] Figure 7D Show along Figure 7A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 7D The cross-sectional diagram shown extends along a second horizontal axis (D2) 705 outside the area of ​​the horizontally oriented access device and the horizontally oriented storage node.

[0082] exist Figure 7D The diagram illustrates a three-dimensional array of vertically oriented memory cells, with a third dielectric material 739 filling the space along a first direction (D1) extending into and outward from the drawing plane. A portion of the third dielectric material 739 can be etched in a horizontal direction to reveal repeated iterations of alternating layers of first dielectric materials 730-1, 730-2, ..., 730-N and first semiconductor materials 732-1, 732-2, ..., 732-N. Lateral breakdown can be applied to the dielectric material 739 to etch through it. An etchant selectively applied only to the third dielectric material 739 can be flowed into a second vertical opening 770 to break down the third dielectric material 739. A hard mask 737 can be seen on the third dielectric material 739.

[0083] Figure 7E Show along Figure 7A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 7EThe cross-sectional diagram shown is a repeating iterative axis extending from right to left along the alternating layers of the first dielectric material 730-1, 730-2, ..., 730-N and the first semiconductor material 732-1, 732-2, ..., 732-N in the drawing plane, extending in the first direction (D1) 709, intersecting multiple third dielectric filling materials 739.

[0084] exist Figure 7E In the diagram, a third dielectric filler material 739 is shown as separating spaces between first horizontal openings 773, and can be spaced apart along a first direction (D1) 709 and vertically stacked in an array extending along a third direction (D3) 711 in a three-dimensional (3D) memory. A portion of the third dielectric material 739 can be vertically etched. A portion of the third dielectric filler material 739 within a plurality of first vertical openings can be removed. The openings formed by the etched third dielectric material 739 can be formed as continuous second horizontal openings 779 extending along the first horizontal direction axis 709. A hard mask 737 covering the first vertical openings on the vertical stack can be etched in the same manner as the third dielectric material 739.

[0085] Figure 8A Shown in the formation of having as Figure 1 Example method of another stage of semiconductor manufacturing process for a vertically stacked memory cell array with shared vertical digital lines and horizontally oriented access lines for a semiconductor device, as shown in Figures 3 and according to several embodiments of the present disclosure. Figure 8A This image shows a top-down view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 8A In the illustrated example embodiment, the method includes filling a series of second openings 870 having a horizontal orientation (D2) 805. A conductive gate material 877 may be deposited within the series of second openings 870.

[0086] Figure 8B It is along Figure 8A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific time point in the semiconductor manufacturing process. Figure 8B The cross-sectional view shown illustrates the repeated iteration of alternating layers of first dielectric material 830-1, 830-2, ..., 830-N, first semiconductor material 832-1, 832-2, ..., 832-N, and second dielectric material 833-1, 833-2, ..., 833-N on semiconductor substrate 800.

[0087] like Figure 8BAs shown, multiple first vertical openings have been formed through layers within the vertically stacked memory cells to expose the vertical sidewalls in the vertical stack. The first vertical openings have been filled with a third dielectric material 839. The first vertical openings have been formed through repeated iterations of oxide material 830, first semiconductor material 832, and nitride material 833.

[0088] Figure 8C In the formation of such Figure 1 A cross-sectional view of another stage of a semiconductor manufacturing process for a semiconductor device with shared vertical digital lines, having horizontally oriented access means and horizontally oriented access lines, according to several embodiments of the present disclosure. Figure 8C Show along Figure 8A The cross-sectional view taken by the cutting line B-B' in the figure.

[0089] Conductive gate materials 877-1, 877-2, ..., 877-N (collectively referred to as conductive gate materials 877) may be conformally deposited and filled with the second vertical opening 870 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes, such that the conductive gate materials 877 may also be deposited onto the first horizontal opening extending primarily in the second horizontal axis direction (D2) 805. Figure 7E In 736), and deposited into a continuous second horizontal opening extending primarily in the first horizontal axis direction (D1) 809 ( Figure 7C In 773), the conductive gate material 877 can be deposited on the gate dielectric material 838.

[0090] In some embodiments, the conductive gate materials 877-1, 877-2, ..., 877-N may include one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.) and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.) and / or some other combinations thereof also described in FIG. 3. The conductive gate material 877 formed on the gate dielectric material 838 may form horizontally oriented access lines, such as the access lines 103-1, 103-2, ..., 103-Q shown (also referred to as word lines).

[0091] Figure 8D Show along Figure 8A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 8DThe cross-sectional diagram shown extends along a second horizontal axis (D2) 805 outside the area of ​​the horizontally oriented access device and the horizontally oriented storage node.

[0092] exist Figure 8D The image shows a three-dimensional array of vertically oriented memory cells, in which a third dielectric material 839 fills the space along a first direction (D1) that extends into and outward from the drawing plane. Figure 8D The cross-sectional view shown extends from right to left along the second horizontal axis (D2) 805 in the drawing plane. The second continuous vertical opening 870 can be seen intersecting with the third dielectric material 839. Conductive gate materials 877-1, 877-2, ..., 877-N can fill the second vertical opening 870, the continuous second horizontal opening extending primarily along the first horizontal axis (D1) 809 (breaking down the third dielectric material 839), and the first horizontal opening extending primarily along the second horizontal axis (D2) 805. The conductive gate materials 877-1, 877-2, ..., 877-N can be conformally deposited using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0093] The hard mask 837 can be seen on the third dielectric material 839. The conductive gate materials 877-1, 877-2, ..., 877-N within the second continuous vertical opening 870 may intersect with the hard mask 837.

[0094] Figure 8E Show along Figure 8A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 8E The cross-sectional diagram shown is an iterative axis extending from right to left in the first direction (D1) 809 along the alternating layers of conductive gate materials 877-1, 877-2, ..., 877-N, first dielectric materials 830-1, 830-2, ..., 830-N, and first semiconductor materials 832-1, 832-2, ..., 832-N formed on the gate dielectric material 838, intersecting with multiple third dielectric filling materials 839.

[0095] exist Figure 8EIn the diagram, conductive gate materials 877-1, 877-2, ..., 877-N are shown as spaces in the second vertical opening 870 left by the etched portion of the second dielectric (shown as 533 in FIG. 5). A third dielectric filling material 839 is shown as spaced along a first direction (D1) 809 and vertically stacked in an array extending along a third direction (D3) 811 in a three-dimensional (3D) memory. The conductive gate materials 877-1, 877-2, ..., 877-N formed on the gate dielectric material 838 can fill the openings formed by the etched second dielectric material 833. A hard mask 837 covering the first vertical opening on the vertical stack can be etched in the same manner as the third dielectric material 839.

[0096] Figure 9A Shown in the formation of having as Figure 1 Example method of another stage of semiconductor manufacturing process for a vertically stacked memory cell array with shared vertical digital lines and horizontally oriented access lines for a semiconductor device, as shown in Figures 3 and according to several embodiments of the present disclosure. Figure 9A This image shows a top-down view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 9A In the example embodiment shown, the method includes etching conductive gate materials 977-1, 977-2, ..., 977-N formed in a second continuous vertical opening 970 having a first horizontal axis (D1) 909 using an etching process.

[0097] A fourth dielectric material 974 can fill the space left between the etched conductive gate material 977 and the second continuous vertical opening 970. For example, the dielectric material 974 can fill the first horizontal opening (as shown in 773 in FIG. 7). The fourth dielectric material 974, such as an oxide or other suitable spin dielectric material (SOD), can be deposited in the second continuous vertical opening 970 to fill the space between the etched conductive gate material 977 and the second continuous vertical opening 970. The fourth dielectric material 974 can be deposited using CVD and planarized using chemical mechanical planarization (CMP) to cover and close the first horizontal opening. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0098] Figure 9B It is along Figure 9A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific time point in the semiconductor manufacturing process. Figure 9BThe cross-sectional view shown illustrates the repeated iteration of alternating layers of first dielectric material 930-1, 930-2, ..., 930-N, first semiconductor material 932-1, 932-2, ..., 932-N, and second dielectric material 933-1, 933-2, ..., 933-N on semiconductor substrate 900.

[0099] Figure 9C In the formation of such Figure 1 A cross-sectional view of another stage of a semiconductor manufacturing process for a semiconductor device with shared vertical digital lines, having horizontally oriented access means and horizontally oriented access lines, according to several embodiments of the present disclosure. Figure 9C Show along Figure 9A The cross-sectional view taken by the cutting line B-B' in the figure.

[0100] Conductive gate materials 977-1, 977-2, ..., 977-N may be recessed back into the first horizontal opening, for example, etched away from the second vertical opening 970 using atomic layer etching (ALE) or other suitable techniques before deposition of the fourth dielectric material. In some instances, conductive gate material 977 may be etched back into the horizontal opening. Conductive gate material 977 may be etched back into the horizontal opening to a second distance (DIST 2) 983 in the range of twenty (20) to one hundred and fifty (150) nanometers (nm) from the second vertical opening 970. Conductive gate material 977 may be selectively etched, leaving oxide material 930, a portion of conductive gate material 977, and first semiconductor material 932 intact. In some embodiments, atomic layer etching (ALE) may be used to etch conductive gate material 977. In some embodiments, isotropic etching may be used to etch conductive gate material 977.

[0101] The conductive gate material 977 can be recessed into the first horizontal opening by a second distance (DIST 2) 983 to maintain direct contact with the remainder of the nitride material 933 and the top surface of the first semiconductor material 932. Therefore, the conductive gate material 977 formed on the gate dielectric material 938 can form a horizontally oriented access line.

[0102] A fourth dielectric material 974 can then be deposited to fill the first horizontal opening. For example, the dielectric material 974 can fill the space left between the etched conductive gate material 977 and the second continuous vertical opening 970. In some embodiments, the fourth dielectric material 974 can be below the first dielectric material 930 and above the lightly doped first semiconductor material 932. The fourth dielectric material 974 can be in direct contact with the conductive gate material 977 and the lightly doped first semiconductor material 932. However, the embodiments are not limited to this example. The fourth dielectric material 974, such as an oxide or other suitable spin dielectric (SOD), can be deposited in the second continuous vertical opening 970. The fourth dielectric material 974 can be the same as or different from the second dielectric material 33. For example, the second dielectric material 1033 can be Si3N4, and the fourth dielectric material 974 can also be Si3N4. In another example, the fourth dielectric material 974 can include silicon dioxide (SiO2) material. In another example, the fourth dielectric material 974 can include silicon carbide (SiO2). x C y In another example, the fourth dielectric material 1074 may comprise silicon oxynitride (SiO2). x N y (and / or combinations thereof.) Examples are not limited to these instances.

[0103] The fourth dielectric material 974 can be deposited using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover and close the first horizontal opening. Similar semiconductor process technologies can be used at other points in the semiconductor manufacturing process described herein.

[0104] Figure 9D Show along Figure 9A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 9D The cross-sectional diagram shown extends along a second horizontal axis (D2) 905 outside the area of ​​the horizontally oriented access device and the horizontally oriented storage node.

[0105] exist Figure 9D The image shows a three-dimensional array of vertically oriented memory cells, in which a third dielectric material 939 fills the space along a first direction (D1) that extends into and outward from the drawing plane. Figure 9DThe cross-sectional illustration shown represents a repeating iterative axis of alternating layers of etched portions of conductive gate materials 977-1, 977-2, ..., 977-N, extending from right to left on the drawing plane along a second horizontal axis (D2) 905. The conductive gate materials 977-1, 977-2, ..., 977-N may fill the openings formed by the etched second dielectric material 933. The conductive gate materials 977-1, 977-2, ..., 977-N may be recessed into the first horizontal opening, for example, etched away from the second vertical opening 970. A fourth dielectric material 974 may fill the spaces formed by the second consecutive vertical opening 970 and the recessed conductive gate materials 977 within the first horizontal opening and the consecutive second horizontal openings. A hard mask 937 can be seen on the third dielectric material 939.

[0106] Figure 9E Show along Figure 9A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 9E The cross-sectional diagram shown is an iterative axis extending from right to left in the drawing plane along the alternating layers of conductive gate materials 977-1, 977-2, ..., 977-N, first dielectric materials 930-1, 930-2, ..., 930-N, and first semiconductor materials 932-1, 932-2, ..., 932-N formed on the gate dielectric material 938 in the first direction (D1) 809, intersecting multiple third dielectric filling materials 939.

[0107] exist Figure 9E In the diagram, conductive gate materials 977-1, 977-2, ..., 977-N are shown filling the spaces within successive second horizontal openings in the third dielectric material 939, with the openings held in place by etched portions of the second dielectric. The third dielectric filling materials 939 are spaced apart along a first direction (D1) 909 and vertically stacked in an array extending along a third direction (D3) 911 in a three-dimensional (3D) memory. The conductive gate materials 977-1, 977-2, ..., 977-N may fill the openings formed by the etched second dielectric material 933.

[0108] Figure 10A Shown in the formation of having as Figure 1 As shown in Figure 3, and according to the formation of shared vertical digital lines (e.g., Figure 1 This is an example method of another stage of a semiconductor manufacturing process for a vertically stacked memory cell array with shared vertical digital lines and horizontally oriented access lines for a semiconductor device, according to several embodiments of the present disclosure (103). Figure 10A This image shows a top-down view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 10A In the illustrated embodiment, the method includes forming a plurality of third vertical openings 1072 to deposit a second semiconducting material 1041. The third vertical openings 1072, having a first horizontal axis (D1) 1009, are discontinuous and do not intersect with the third dielectric material 1039. It can be seen that the third dielectric material 1039 formed within the plurality of first vertical openings 1000 separates the worksheet of the vertical semiconductor stack.

[0109] Figure 10B It is along Figure 10A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific time point in the semiconductor manufacturing process. Figure 10B The cross-sectional view shown illustrates the repeated iteration of alternating layers of first dielectric material 1030-1, 1030-2, ..., 1030-N, first semiconductor material 1032-1, 1032-2, ..., 1032-N, and second dielectric material 1033-1, 1033-2, ..., 1033-N on the semiconductor substrate 1000 in the memory node region.

[0110] like Figure 10B As shown, multiple first vertical openings have been formed through layers within the vertically stacked memory cells to expose the vertical sidewalls in the vertical stack. The first vertical openings have been formed through repeated iterations of oxide material 1030, first semiconductor material 1032, and nitride material 1033.

[0111] Figure 10C In the formation of such Figure 1 A cross-sectional view of another stage of a semiconductor manufacturing process for a semiconductor device with shared vertical digital lines, having horizontally oriented access means and horizontally oriented access lines, according to several embodiments of the present disclosure. Figure 10C Show along Figure 10A The cross-sectional view taken by the cutting line B-B' in the figure.

[0112] The conductive gate material 1077 is shown adjacent to the second dielectric materials 1033-1, 1033-2, ..., 1033-N and the fourth dielectric materials 1074-1, 1074-2, ..., 1074-N, and is higher than the first semiconductor materials 1032-1, 1032-2, ..., 1032-N. It is separated from the gate dielectric 1038 and extends into and outwards from the drawing plane and orientation.

[0113] The conductive gate material 1077 can maintain direct electrical contact on the top surface of the first semiconductor materials 1032-1, 1032-2, ..., 1032-N. In some embodiments, the fourth dielectric material 1074 can be formed below the first dielectric material 1030, while maintaining direct contact with the conductive gate material 1077, the first source / drain region 1075, and the lightly doped first semiconductor material 1032.

[0114] A second semiconducting material 1041 with a second type of dopant (e.g., phosphorus (P)) may be formed within the third vertical opening 1072. The second semiconducting material 1041 may be formed as a shared vertical digital line adjacent to the conductive gate materials 1077-1, 1077-2, ..., 1077-N in the third vertical opening 1072 but separated from them by a fourth dielectric material 1074. The second semiconducting material 1041 may intersect with the first dielectric materials 1030-1, 1030-2, ..., 1030-N, the fourth dielectric materials 1074-1, 1074-2, ..., 1074-N, and the lightly doped first semiconductor materials 1032-1, 1032-2, ..., 1032-N. The second semiconducting material 1041 may form a shared vertically oriented digital line adjacent to the first source / drain region 1075 on the opposite side.

[0115] In some embodiments, the second semiconducting material 1041 may be formed of a silicide. In some embodiments, the second semiconducting material 1041 may include titanium. In some embodiments, the second semiconducting material 1041 may include titanium nitride (TiN). In some embodiments, the second semiconducting material 1041 may include ruthenium (Ru). In some embodiments, the second semiconducting material 1041 may be tungsten (W).

[0116] In one embodiment, before depositing the second semiconducting material 1041 in the third vertical opening 1072, a high-concentration n-type doped (n+) region is first formed by using a high-energy plasma (e.g., PECVD) vapor phase doping in the third vertical opening 1072 as an impurity dopant to form a first source / drain region 1075, which serves as the first source / drain region 1075 in the low-doped first semiconductor material 1032.

[0117] According to various embodiments, the dopant in the second semiconducting material 1041 having a second type of dopant can be a different dopant than that in the first semiconductor material 1032 having a first type of dopant. For example, the first semiconductor material 1032 may contain a first type of boron (B) dopant, while the second semiconducting material 1041 may contain a second type of phosphorus (P) dopant. Polycrystalline silicon material can be deposited into the third vertical opening 1072. For example, highly phosphorus (P)-doped (n+) polycrystalline silicon germanium (SiGe) material can be deposited into the third vertical opening 1072 to form the second semiconducting material 1041.

[0118] In an alternative embodiment, highly phosphorus (P)-doped (n+) polycrystalline silicon germanium (SiGe) material can first be deposited into the third vertical opening 1072 to form the second semiconducting material 1041, and the first source / drain region 1075 can be formed by diffusing an n-type (n+) dopant outward into the first semiconductor materials 1032-1, 1032-2, ..., 1032-N. The highly phosphorus (P)-doped (n+) polycrystalline silicon germanium (SiGe) material in the second semiconducting material 1041 can be annealed at a high temperature (e.g., above 600 degrees Celsius) to diffuse the n-type (n+) dopant (e.g., phosphorus (P)) outward into the first semiconductor material 1032 to form the first source / drain region 1075.

[0119] In one embodiment, a plurality of patterned third vertical openings are formed near the location where the first source / drain region 1075 will be formed, such that the first source / drain region 1075 will be adjacent to the second semiconducting material 1041 as highly phosphorus-doped atoms diffuse outward from the second semiconductor material. The first source / drain region 1075 may be formed within the lightly doped first semiconductor material 1032 on both sides of the vertically deposited second semiconducting material 1041. For example, the first source / drain region 1075 may be formed by annealing to diffuse n-type (n+) dopant outward into the lightly doped first semiconductor material 1032 on both sides of the vertically deposited second semiconducting material 1041. A fourth dielectric material 1074 may be located below the first dielectric material 1030 while maintaining direct contact with the conductive gate material 1077 and the first source / drain region 1075.

[0120] Figure 10D Show along Figure 10A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 10D The cross-sectional diagram shown extends along a second horizontal axis (D2) 1005 outside the area of ​​the horizontally oriented access device and the horizontally oriented storage node.

[0121] exist Figure 10DIn the middle, only the conductive gate material 1077 is visible through the third dielectric material 1039. The third vertical opening 1072 is filled with the second semiconducting material 1041. The hard mask 1037 can be seen on the third dielectric material 1039.

[0122] Figure 10E Show along Figure 10A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 10E The cross-sectional diagram shown is an iterative axis extending from right to left in the drawing plane along the alternating layers of conductive gate materials 1077-1, 1077-2, ..., 1077-N, first dielectric materials 1030-1, 1030-2, ..., 1030-N, and first semiconductor materials 1032-1, 1032-2, ..., 1032-N in the first direction (D1) 1009, intersecting multiple third dielectric filling materials 1039.

[0123] exist Figure 10E In the diagram, conductive gate materials 1077-1, 1077-2, ..., 1077-N formed on gate dielectric material 1038 are shown as spaces in the second vertical openings left by the etched portions of the second dielectric. Third dielectric filling material 1039 is shown as spaced apart along a first direction (D1) 1009 and vertically stacked in an array extending along a third direction (D3) 1011 in a three-dimensional (3D) memory. The conductive gate materials 1077-1, 1077-2, ..., 1077-N can fill the openings formed by the etched second dielectric material 1033 and the continuous second horizontal openings extending primarily along the first horizontal axis (D1) 1009 to form horizontal access lines, for example... Figure 1 101 in the middle.

[0124] Figure 11A Shown in the formation of having as Figure 1 As shown in Figure 3, and according to the formation of shared vertical digital lines (e.g., Figure 1 Example method of another stage of semiconductor manufacturing process for a vertically stacked memory cell array with shared vertical digital lines and horizontally oriented access lines for a semiconductor device, according to several embodiments of (103). Figure 11A This image shows a top-down view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 11AIn an example embodiment, the method includes forming a metallic material 1171 within a second semiconducting material 1141 formed within a plurality of third vertical openings 1172. The metallic material 1171 is deposited such that the second semiconducting material 1141 surrounds the metallic material 1171. The third vertical openings 1172 having a first horizontal axis (D1) 1109 are discontinuous and do not intersect with a third dielectric material 1139. The second semiconducting material 1141 may couple with the metallic material 1171 within the third vertical openings 1172.

[0125] Figure 11B It is along Figure 11A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 11B The cross-sectional view shown illustrates alternating layers of dielectric materials 1130-1, 1130-2, ..., 1130-(N+1), first semiconductor materials 1132-1, 1132-2, ..., 1132-N, and second dielectric materials 1133-1, 1133-2, ..., 1133-N, separated by openings filled with a third dielectric material 1139, repeatedly iterating on a semiconductor substrate 1100 to form a vertical stack. Figure 11B As shown, the vertical direction 1111 is shown as... Figure 1 The third direction (D3) 1111 shown in -3 is similar to the third direction (D3) in the first, second, and third directions, such as the z-direction in the xyz coordinate system. The left and right extended drawing plane is located in the first direction (D1) 1109. In Figure 11B In an example embodiment, the materials in the vertical stack—dielectric materials 1130-1, 1130-2, ..., 1130-(N+1), first semiconductor materials 1132-1, 1132-2, ..., 1132-N, and second dielectric materials 1133-1, 1133-2, ..., 1133-N—extend in the second direction (D2) along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory into the drawing plane and outward from the drawing plane.

[0126] Figure 11C Show along Figure 11A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 11CThe cross-sectional diagram shown is an extension of the second horizontal axis (D2) 1105 along the left-right direction of the drawing plane along the alternating layers of the first dielectric material 1130-1, 1130-2, ..., 1130-N and the first semiconductor material 1132-1, 1132-2, ..., 1132-N. The adjacent horizontal access line 1177 is shown as the adjacent second dielectric material 1133-1, 1133-2, ..., 1133-N.

[0127] In some embodiments, the fourth dielectric material 1174 may be below the first dielectric material 1130 while maintaining direct contact with the conductive gate material 1177. A first source / drain region 1175 may be formed in the lightly doped first semiconductor material 1132 adjacent to the vertical second semiconducting material 1141. In one embodiment, the second semiconducting material 1141 may be conformally deposited within the third vertical opening 1172, and the first source / drain region 1175 may be formed by diffusing an n-type (n+) dopant from the second semiconducting material 1141 outward into the first semiconductor material 1132. In another embodiment, the first source / drain region 1175 may be formed by vapor-phase doping a high-energy vapor dopant into the third vertical opening 1172 before depositing the second semiconducting material 1141 in the third vertical opening 1172 to form a high-concentration, n-type doped (n+) region in the lightly doped first semiconductor material 1132 as the first source / drain region 1175.

[0128] Metal material 1171 can be deposited in the third vertical opening 1172 to fill it. In this embodiment, for example using ALD, a second semiconducting material 1141 can be conformally deposited to a specific thickness (tpoly) on the vertically stacked exposed surfaces within the third vertical opening 1172, thereby leaving a vertical opening at the center of the third vertical opening 1172. Then, metal material 1171 can be deposited, for example using CVD, to fill the central opening within the third vertical opening 1172. For example, the second semiconducting material 1141 in contact with the first source / drain region 1175 can be seen outside the third vertical opening 1172, while the metal material 1171 is shown inside the third vertical opening 1172. In some embodiments, the metal material 1171 may include one or more of the following: conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.) and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.) and / or some other combinations thereof.

[0129] The second semiconducting material 1141 can be electrically coupled to the metal material 1171 within the third vertical opening 1172. The second semiconducting material 1141 coupled to the metal material 1171 can be formed vertically adjacent to the fourth dielectric material 1174-1, 1174-2, ..., 1174-N, the first dielectric material 1130, and the first source / drain region 1175, thereby filling the third vertical opening 1172 to form a shared vertical digital line on both sides.

[0130] Figure 11D Show along Figure 11A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 11D The cross-sectional diagram shown extends along the second horizontal axis (D2) 1105 outside the area of ​​the horizontally oriented access device and the horizontally oriented storage node in the left-right direction along the drawing plane.

[0131] exist Figure 11D Through the third dielectric material 1139, the conductive gate material 1177 forming the horizontal access line can be seen. The third vertical opening 1172 is filled with the second semiconducting material 1141 and the metal material 1171. The hard mask 1137 can be seen on the third dielectric material 1139.

[0132] Figure 11E Show along Figure 11A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 11E The cross-sectional diagram shown is an iterative axis extending from right to left on the drawing plane along the alternating layers of the first dielectric material 1130-1, 1130-2, ..., 1130-N, the first semiconductor material 1132-1, 1132-2, ..., 1132-N, and the second dielectric material 1133-1, 1133-2, ..., 1133-N, extending in the first direction (D1) 1109, crossing multiple independent horizontal access lines 1177-1, 1177-2, ..., 1177-N, and intersecting with them. The intersection regions of the first semiconductor materials 1132-1, 1132-2, ..., 1132-N are separated from the multiple independent horizontal access lines 1177-1, 1177-2, ..., 1177-N by the gate dielectric material 1138. Figure 11E In the diagram, the first dielectric filling material 1139 is shown as separating the space between adjacent horizontally oriented access devices, which can be configured to extend into and outward from the drawing plane, as in combination with... Figure 4As described in -9, and can be spaced apart along the first direction (D1) 1109 and vertically stacked in an array extending along the third direction (D3) 1111 in a three-dimensional (3D) memory.

[0133] Figure 12A Shown in the formation of having as Figure 1 Example method of another stage of semiconductor manufacturing process for a vertically stacked memory cell array with shared vertical digital lines and horizontally oriented access lines for a semiconductor device, as shown in Figures 3 and according to several embodiments of the present disclosure. Figure 12A A top-down view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments of a memory node is shown.

[0134] exist Figure 12A In an example embodiment, the method includes patterning a photomask 1237 using a photolithography process. Figure 12A The method further illustrates the use of one or more etching processes to form a fourth vertical opening 1251 in the storage node region 1250 through a vertical stack, the vertical opening extending primarily along the first horizontal axis (D1) 1209.

[0135] One or more etching processes form a fourth vertical opening 1251, exposing the third sidewall in the repeated iterations of alternating layers of the first dielectric material 1230-1, 1230-2, ..., 1230-N, the first semiconductor material 1232-1, 1232-2, ..., 1232-N, and the second dielectric material 1233-1, 1233-2, ..., 1233-N in a vertical stack, as shown. Figure 12B-12E As shown. A conductive gate material 1277 may be formed above the vertical opening 1251. A metallic material 1271 has been formed in a second semiconducting material 1241 within a plurality of third vertical openings 1272. The third vertical openings 1272 having a first horizontal axis (D1) 1209 are discontinuous and do not intersect with the third dielectric material 1239. The second semiconducting material 1241 may be coupled to the metallic material 1271 within the third vertical openings 1272.

[0136] according to Figure 12B-12E The illustrated example embodiment shows that the method includes vertical stacking ( Figure 4 In section 401), a second vertical opening 1251 is formed, and a second region of the first semiconductor material is selectively etched to form a second horizontal opening, the second horizontal opening being connected to the vertical stack ( Figure 4 The vertical opening 1251 in (401) maintains a third horizontal distance. According to an embodiment, selective etching of the second region of the first semiconductor material may include using an atomic layer etching (ALE) process. (As will be combined with...) Figure 12CTo explain in more detail, a second source / drain region can be formed in the first semiconductor material at the distance from the second horizontal opening to the far end of the vertical opening.

[0137] Figure 12B Show along Figure 12A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 12B The cross-sectional view shown illustrates the repeated iterations of alternating layers of dielectric materials 1230-1, 1230-2, ..., 1230-(N+1), separated by openings filled with a third dielectric material 1239, on a semiconductor substrate 1200 to form a vertical stack. Figure 12B In an example embodiment, the horizontal opening 1279 is shown as other materials within the vertical stack—dielectric materials 1230-1, 1230-2, ..., 1230-(N+1) and second dielectric materials 1233-1, 1233-2, ..., 1233-N—extending in the drawing plane and outward from the drawing plane in a second direction (D2) and along the orientation axis of the horizontal access devices and horizontal memory nodes of the vertically stacked memory cell array of the three-dimensional (3D) memory. In one example, an atomic layer etching (ALE) process is used to selectively etch a portion of the first semiconductor material, and the second horizontal opening 1279 is visible. In the view shown, only the second horizontal opening 1279 is visible; the first semiconductor material is not visible in the vertical stack.

[0138] Figure 12C Show along Figure 12A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 12C The cross-sectional diagram shown is an iterative axis along the left-right direction of the drawing plane, extending on the second horizontal axis (D2) 1205 along the alternating layers of the first dielectric material 1230-1, 1230-2, ..., 1230-N, the second horizontal opening 1279, and the second dielectric material 1233-1, 1233-2, ..., 1233-N.

[0139] exist Figure 12C In an example embodiment, the vertical opening 1251 is shown as being formed by combining Figure 12A The masking, patterning, and etching processes described are formed. For example... Figure 12CAs shown, the first semiconductor materials 1232-1, 1232-2, ..., 1232-N in the second region 1244 have been selectively removed to form the second horizontal opening 1279. In one example, an atomic layer etching (ALE) process is used to selectively etch the first semiconductor materials 1232-1, 1232-2, ..., 1232-N. Horizontally oriented memory nodes, such as capacitor cells, can be formed in the second horizontal opening 1279.

[0140] In the center of the page, a shared vertical digital line is formed by a second semiconducting material 1241 surrounded by a metal material 1271 within a third vertical opening 1272. On either side of the shared vertical digital line are a first dielectric material 1230, a fourth dielectric material 1274 adjacent to the conductive gate material 1277 and the second dielectric material 1233, and a first source / drain region 1275 adjacent to the lightly doped first semiconductor material 1232.

[0141] In some embodiments, vapor-phase doping can be used to achieve high isotropy (e.g., non-directional doping) to form the second source / drain region 1278 to the horizontally oriented access device through the fourth vertical opening 1251 and the second horizontal opening 1279. In another example, thermal annealing using a dopant gas (e.g., phosphorus) can be used in conjunction with high-energy plasma-assisted methods to break the bond. However, the embodiments are not limited thereto, and other suitable semiconductor fabrication techniques can be used.

[0142] According to an example implementation, such as Figure 12C As shown, a second source / drain region 1278 can be formed by introducing a high-energy vapor dopant (e.g., phosphorus (P) for n-type transistors) into the second horizontal opening 1279 at the distal end of the fourth vertical opening 1251 to dope the first semiconductor materials 1232-1, 1232-2, ..., 1232-N. The fourth vertical opening 1251 can be formed to expose the third vertical sidewall in the vertical stack. The first semiconductor materials 1232-1, 1232-2, ..., 1232-N can be selectively etched on the second horizontal axis (D2) 1205 to form a plurality of third horizontal openings in the second region. The dopant can be doped into the side surface of the first semiconductor material from the second horizontal opening 1279 to horizontally form the second source / drain region 1278. A horizontally oriented capacitor cell with a bottom electrode (1361 as shown in Figure 13) can be deposited into a second horizontal opening 1279 to make electrical contact with a second source / drain region 1278.

[0143] Figure 12D Show along Figure 12AThe cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 12D The cross-sectional diagram shown is along the left-right direction of the drawing plane at the point where... Figure 12D The area of ​​the horizontally oriented access device and horizontally oriented storage node (e.g., capacitor cell) extends along a second horizontal axis (D2) 1205, beyond which the conductive gate material 1277 can be seen through the third dielectric material 1239. A fourth vertical opening 1251 is shown at both ends of the drawing. A hard mask 1237 can be seen on the third dielectric material 1239.

[0144] Figure 12E Show along Figure 12A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 12E The cross-sectional diagram shown is an iterative axis extending in the first direction (D1) 1209 from right to left on the drawing plane, along the alternating layers of the first dielectric material 1230-1, 1230-2, ..., 1230-N, the first semiconductor material 1232-1, 1232-2, ..., 1232-N, and the second dielectric material 1233-1, 1233-2, ..., 1233-N. This axis crosses multiple independent horizontal access lines 1277-1, 1277-2, ..., 1277-N, and the intersection regions of the first semiconductor materials 1232-1, 1232-2, ..., 1232-N are separated from the multiple independent horizontal access lines 1277-1, 1277-2, ..., 1277-N by the gate dielectric material 1238. Figure 12E In the diagram, the first dielectric filling material 1239 is shown as a space separating adjacent horizontally oriented access devices and horizontally oriented storage nodes. It can be formed to extend into and outward from the drawing plane, as described in more detail below, and can be spaced along a first direction (D1) 1209 and vertically stacked in an array extending along a third direction (D3) 1211 in a three-dimensional (3D) memory.

[0145] Figure 13A An example method is shown for another stage of a semiconductor manufacturing process for forming a vertically stacked memory cell array having shared vertical digital lines and horizontally oriented access lines for a semiconductor device according to several embodiments of the present disclosure. Figure 13A A top-down view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments is shown.

[0146] exist Figure 13A In an example embodiment, the method includes patterning a photomask 1337 using a photolithography process. Figure 13A The method further illustrates the use of one or more etchant processes to form a fourth vertical opening 1351 through a vertical stack, the fourth vertical opening extending primarily along a first horizontal axis (D1) 1309. One or more etch processes form the vertical opening 1351 to expose a third sidewall adjacent to a second region of the first semiconductor material in repeated iterations of alternating layers of the first dielectric material 1330-1, 1330-2, ..., 1330-N, the first semiconductor material 1332-1, 1332-2, ..., 1332-N, and the second dielectric material 1333-1, 1333-2, ..., 1333-N, as shown in the image. Figure 13B-13E As shown. Metallic material 1371 has been formed in a second semiconducting material 1341 within a plurality of third vertical openings 1372. The metallic material 1371 is deposited such that the second semiconducting material 1341 surrounds the metallic material 1371.

[0147] In some embodiments, such as Figure 13B-13E As shown, the method includes forming a capacitor cell as a storage node in a second horizontal opening. By way of example, and not limitation, forming the capacitor includes sequentially depositing a first electrode 1361 and a second electrode 1356 in the second horizontal opening using an atomic layer deposition (ALD) process, the electrodes being separated by a cell dielectric 1363 within a fourth vertical opening 1351. Other suitable semiconductor manufacturing techniques and / or storage node structures may be used.

[0148] Figure 13B Show along Figure 13A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 13B The cross-sectional view shown is away from multiple independent horizontal access lines 1377-1, 1377-2, ..., 1377-N, 1377-(N+1), ..., 1377-(Z-1), and illustrates the repeated iteration of alternating layers of dielectric materials 1330-1, 1330-2, ..., 1330-(N+1) on a semiconductor substrate 1300 to form a vertical stack. These dielectric materials are separated by horizontally oriented capacitor cells having a first electrode 1361 (e.g., a bottom cell contact electrode), a cell dielectric 1363, and a second electrode 1356 (e.g., a top common node electrode). Figure 13B As shown, vertical direction 1311 is shown as... Figure 1 The third direction (D3) 1311 shown in Figure -3 is similar to the third direction (D3) in the first, second, and third directions, such as the z-direction in the xyz coordinate system. The left-right extending drawing plane lies on the first direction (D1) 1309. Figure 13BIn an example embodiment, the first electrode 1361 (e.g., the bottom electrode coupled to the source / drain region of the horizontal access device) and the second electrode 1356 are shown separated by a cell dielectric material 1363 that extends in the second direction (D2) and along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory into and out of the drawing plane.

[0149] Figure 13C Show along Figure 13A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 13C The cross-sectional diagram shown is an iterative axis extending along the second horizontal axis (D2) 1305 along the alternating layers of the first dielectric material 1330-1, 1330-2, ..., 1330-N, the first semiconductor material 1332-1, 1332-2, ..., 1332-N, and the second dielectric material 1333-1, 1333-2, ..., 1333-N in the left-right direction along the drawing plane. Horizontally oriented access devices and horizontally oriented storage nodes, such as capacitor cells, can be formed within the layers with second horizontal openings. Figure 13C In the example embodiment, a first electrode 1361 (e.g., a bottom electrode coupled to the source / drain region of a horizontal access device) and a second electrode 1356 (e.g., a top electrode coupled to a common electrode plane (e.g., a ground plane) separated by a cell dielectric 1363) are shown. However, the embodiments are not limited to this example.

[0150] exist Figure 13C In an example embodiment, a horizontally oriented memory node is shown formed in a second horizontal opening extending along a second direction (D2) along the left-right direction of the drawing plane, having a first electrode 1361 (e.g., a bottom electrode coupled to the source / drain region of the horizontal access device) and a second electrode 1356 (e.g., a top electrode coupled to a common electrode plane (e.g., a ground plane)). The second electrode 1356, separated by a cell dielectric 1363, is also shown filling a fourth vertical opening (1251 as shown in FIG. 12) and extending along the orientation axis of the horizontal access device and the horizontal memory node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0151] Figure 13D Show along Figure 13A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 13DThe cross-sectional diagram shown extends along a second horizontal axis (D2) 1305, outside the area of ​​the horizontally oriented access device and the horizontally oriented storage node (e.g., capacitor cell), in the left-right direction along the drawing plane. Figure 13C The diagram illustrates a three-dimensional array of vertically oriented memory cells. A third dielectric material 1339 fills the space between horizontally oriented access devices spaced along a first direction (D1) that extends into and outwards from the drawing plane. A conductive gate material 1377 is visible through the third dielectric material 1339. At both ends of the drawing, second electrodes 1356, separated by cell dielectrics 1362, are visible, such as the top common electrode of a capacitor cell structure. A hard mask 1237 is visible on the third dielectric material 1339.

[0152] Figure 13E Show along Figure 13A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 13E The cross-sectional diagram shown is an iterative axis extending in the first direction (D1) 1309 from right to left on the drawing plane, along the alternating layers of the first dielectric material 1330-1, 1330-2, ..., 1330-N, the first semiconductor material 1332-1, 1332-2, ..., 1332-N, and the second dielectric material 1333-1, 1333-2, ..., 1333-N, crossing multiple independent horizontal access lines 1377-1, 1377-2, ..., 1377-N, and intersecting therein. The intersection regions of the first semiconductor materials 1332-1, 1332-2, ..., 1332-N, where channel regions can be formed, are separated from the multiple independent horizontal access lines 1377-1, 1377-2, ..., 1377-N by the gate dielectric material 1338. Figure 13E In the diagram, the first dielectric filling material 1339 is shown as a space separating adjacent horizontally oriented access devices and horizontally oriented storage nodes. It can be formed to extend into and outward from the drawing plane, as described in more detail below, and can be spaced along a first direction (D1) 1309 and vertically stacked in an array extending along a third direction (D3) 1311 in a three-dimensional (3D) memory.

[0153] Figure 14 These are examples of multiplexers for semiconductor devices according to various embodiments of the present disclosure. Figure 14 The vertical 3D memory shown is Figure 1Similar to that shown in -3, but presented from a different angle and at a different level of detail. A portion of multiple vertically stacked layers 1430-1, 1430-2, ..., 1430-P of memory cells in the array is shown. Layers 1430 are vertically stacked along a third direction 1411(D3). Multiple vertical sensing lines, such as vertical sensing lines 1403-1 to 1403-8, also pass through layers 1430 along the third direction 1411(D3). Each vertical sensing line 1403 is coupled to a memory cell 1410 in each layer 1430.

[0154] Each level 1430-1, 1430-2, ..., 1430-P may contain memory cells coupled to corresponding horizontal access lines, each horizontal access line extending parallel to each other along the first direction 1409(D1). For example, as Figure 14As shown, layer 1430-1 includes memory cells 1410-1 and 1410-5 (coupled to horizontal access line 1407-1 and vertical sensing lines 1403-1 and 1403-5, respectively), memory cells 1410-2 and 1410-6 (coupled to horizontal access line 1407-2 and vertical sensing lines 1403-2 and 1403-6, respectively), memory cells 1410-3 and 1410-7 (coupled to horizontal access line 1407-3 and vertical sensing lines 1403-3 and 1403-7, respectively), and memory cells 1410-4 and 1410-8 (coupled to horizontal access line 1407-4 and vertical sensing lines 1403-4 and 1403-8, respectively). Similarly, layer 1430-2 may include memory cells 1410-9 and 1410-13 (coupled to the same horizontal access line and vertical sensing line 1403-1 and 1403-5, respectively), 1410-10 and 1410-14 (coupled to the same horizontal access line and vertical sensing line 1403-2 and 1403-6, respectively), 1410-11 and 1410-15 (coupled to the same horizontal access line and vertical sensing line 1403-3 and 1403-7, respectively), and 1410-12 and 1410-16 (coupled to the same horizontal access line and vertical sensing line 1403-4 and 1403-8, respectively). Similarly, layer 1430-P may include 1410-Q and 1410-(Q+4) (coupled to the same horizontal access line and vertical sensing line 1403-1 and 1403-5, respectively), 1410-(Q+1) and 1410-(Q+5) (coupled to the same horizontal access line and vertical sensing line 1403-2 and 1403-6, respectively), 1410-(Q+2) and 1410-(Q+6) (coupled to the same horizontal access line and vertical sensing line 1403-3 and 1403-7, respectively), and 1410-(Q+3) and 1410-(Q+7) (coupled to the same horizontal access line and vertical sensing line 1403-4 and 1403-8, respectively), as follows. Figure 14 As shown. In addition, each layer 1430 intersects with a plurality of vertical sensing lines 1403 extending along a third direction 1411 (D3).

[0155] like Figure 14 As further shown, vertical sensing lines 1403-1 to 1403-4 are coupled to one of a pair of horizontal sensing lines 1422-1 and 1422-2 via corresponding multiplexers 1432-1 to 1432-4 formed under a vertically stacked memory cell array. For example, as Figure 14As shown, vertical sensing lines 1403-1 and 1403-3 are coupled to horizontal sensing line 1422-1 via multiplexers 1432-1 and 1432-3, respectively, and vertical sensing lines 1403-2 and 1403-4 are coupled to horizontal sensing line 1422-2 via multiplexers 1432-2 and 1432-4, respectively. (As shown in the diagram...) Figure 14 As shown, the vertical sensing line 1403 includes alternating vertical sensing lines along a pair of horizontal sensing lines 1422.

[0156] Multiplexer 1432-1 is operable to electrically couple / decouple vertical sensing line 1403-1 from horizontal sensing line 1422-1 (making one of memory cells 1410-1, 1410-9, and 1410-Q accessible); multiplexer 1432-2 is operable to electrically couple / decouple vertical sensing line 1403-2 from horizontal sensing line 1422-2 (making one of memory cells 1410-2, 1410-10, and 1410-(Q+1) accessible); multiplexing Device 1432-3 can be operated to electrically couple / decouple vertical sensing line 1403-3 from horizontal sensing line 1422-1 (so that one of memory cells 1410-3, 1410-11 and 1410-(Q+2) can be accessed); and multiplexer 1432-4 can be operated to electrically couple / decouple vertical sensing line 1403-4 from horizontal sensing line 1422-2 (so that one of memory cells 1410-4, 1410-12 and 1410-(Q+3) can be accessed).

[0157] As described in this article, each multiplexer is operable to electrically couple / decouple the vertical sensing line from the corresponding horizontal sensing line. Although Figure 14Not shown, but a pair of horizontal sensing lines 1422-1 and 1422-2 can be coupled to a sensing amplifier. To sense a memory cell, the control circuitry can cause two multiplexers adjacent to each other and coupled to the pair of horizontal sensing lines 1422 to electrically couple one vertical sensing line (to which the memory cell to be sensed is coupled) to one of the pair of horizontal sensing lines, and another vertical sensing line to the other of the pair of horizontal sensing lines. For example, to sense memory cell 1410-1, the control circuit can cause multiplexer 1432-1 to electrically couple vertical sensing line 1403-1 to horizontal sensing line 1422-1, and multiplexer 1432-2 to electrically couple vertical sensing line 1403-2 to horizontal sensing line 1422-1, while the remaining multiplexers 1432-3 and 1432-4 decouple the remaining vertical sensing lines (e.g., vertical sensing lines 1403-3 and 1403-4) from the corresponding horizontal sensing lines 1422-1 and 1422-2. The control circuit can further activate the access line driver to provide a positive power supply to horizontal access line 1407-1, which will further provide a differential voltage (e.g., the voltage difference between vertical sensing lines 1403-1 and 1403-2) to the sensing amplifier via horizontal sensing lines 1422-1 and 1422-2.

[0158] Figure 15 Examples of multiplexers coupled to instance horizontally oriented access devices and access lines, and shared vertically oriented digital lines for semiconductor devices, according to various embodiments of this disclosure. Figure 15As shown, the vertical stack 1502 may comprise repeating alternating layers of a first dielectric material 1512-1, 1512-2, 1512-3, 1512-4, ..., 1512-N, a semiconductor material 1514-1, 1514-2, 1514-3, 1514-4, ..., 1514-N, and a second dielectric material 1516-1, 1516-2, 1516-3, 1516-4, ..., 1516-N. In some embodiments, at least two (2) repeating iterations of the alternating layers may be formed to form the vertical stack 1502 to a height ranging from twenty (20) nanometers (nm) to three hundred (300) nm. The semiconductor material layer 1514 may also be referred to as channel 1514. In some embodiments, the first dielectric material 1512, the semiconductor material 1514, and the second dielectric material 1516 may be formed using a chemical vapor deposition (CVD) process. In one embodiment, a first dielectric material 1512 may be deposited to a thickness (e.g., vertical height) in the third direction (D3) ranging from 20 nm to 60 nm. In one embodiment, a semiconductor material 1514 may be deposited to a thickness (e.g., vertical height) ranging from 10 nm to 30 nm. In one embodiment, a second dielectric material 1516 may be deposited to a thickness (e.g., vertical height) ranging from 20 nm to 150 nm. However, the embodiments are not limited to these examples. Figure 15 As shown, vertical direction 1511 is shown as... Figure 1 The third direction (D3) shown in Figure -3 is similar to the third direction (D3) in the first, second, and third directions, such as the z direction in the xyz coordinate system. The vertical stack 1502 may also include a dielectric cover 1522.

[0159] In some embodiments, the first dielectric material 1512 may be an interlayer dielectric (ILD). By way of example and not limitation, the first dielectric material 1512 may include an oxide material, such as SiO2. In another example, the first dielectric material 1512 may include a silicon nitride (Si3N4) material (also referred to herein as “SiN”). In another example, the first dielectric material 1512 may include a silicon oxycarbide (SiOxCy) material. In yet another example, the first dielectric material 1512 may comprise a silicon oxynitride (SiOxNy) material (also referred to herein as “SiON”) and / or combinations thereof. Embodiments are not limited to these examples.

[0160] In some embodiments, the second dielectric material 1516 may be an interlayer dielectric (ILD). By way of example and not limitation, the second dielectric material 1516 may include a nitride material. The nitride material may be silicon nitride (Si3N4) material. In another example, the second dielectric material 1516 may include silicon oxycarbide (SiOC) material. In yet another example, the second dielectric material 1516 may comprise silicon oxynitride (SiON) and / or combinations thereof. Embodiments are not limited to these examples. However, according to embodiments, the second dielectric material 1516 is intentionally selected to be different in material or composition from the first dielectric material 1512, such that a selective etching process can be performed on the other of the first and second dielectric layers with selectivity relative to one of the first and second dielectric layers (e.g., the second SiN dielectric material 1516 may be selectively etched relative to the semiconductor material 1514 and the first oxide dielectric material 1512).

[0161] In some embodiments, semiconductor material 1514 may comprise silicon (Si) material in a polycrystalline and / or amorphous state. Semiconductor material 1514 may be a lightly doped p-type (p-) silicon material. Semiconductor material 1514 may be formed by vapor-phase doping with boron atoms (B) at a low concentration as an impurity dopant to form a lightly doped p-type (p-) silicon material. In some embodiments, semiconductor material 1516 may be formed by in-situ vapor-phase doping with boron atoms (B). Lightly doped p-type (p-) silicon material may be amorphous silicon material. However, embodiments are not limited to these examples.

[0162] The vertical stack 1502 may also include sensing lines 1503 and a plurality of access lines 1507-1, 1507-2, ..., 1507-Q. In some embodiments, the sensing line 1503 may be a vertical sensing line that intersects and contacts each layer of the vertical stack 1502. In some embodiments, the access line 1507 may be a horizontal access line 1507 and may be formed in the semiconductor material 1516 layer of the vertical stack 1502. The vertical stack 1502 may also include a dielectric material 1524 for isolating the plurality of vertical stacks 1502, horizontally oriented memory nodes 1537 (e.g., capacitor cells), and vertical portions of memory nodes 1518-1.

[0163] The vertical stack 1502 may also include a multiplexer 1520. As used herein, the term "multiplexer" refers to a circuit that selects one of a plurality of vertical and / or horizontal sensing lines. Figure 15As shown, in some embodiments, multiplexer 1520 may be the bottom portion of a vertical stack 1502. In some embodiments, multiplexer 1520 may be coupled to a digital line (e.g., a shared vertically oriented digital line described herein) to select between two adjacent horizontal access devices. In some embodiments, multiplexer 1520 may include a first dielectric material 1512, a semiconductor material 1514, a second dielectric material 1516, and a sensing line 1503 (e.g., a local sensing line) of the vertical stack 1502. However, instead of access lines (e.g., access line 1507), a first multiplexer switch 1506-1 and a second multiplexer switch 1506-2 are formed in the semiconductor material 1516. In some embodiments, multiplexer switch 1506 may be formed in a region of semiconductor material 1516 corresponding to the region of semiconductor material 1516 forming access line 1507, such that multiplexer switch 1506 is vertically aligned with access line 1507. The first multiplexer switch 1506-1 includes a first gate, and the second multiplexer switch 1506-2 includes a second gate. In some embodiments, the first gate and the second gate are parallel to and vertically aligned with the corresponding horizontal access line 1507 in each of the plurality of layers. Figure 15 As shown, multiplexer switch 1506 can be located below access line 1507. A first layer of semiconductor material 1514-1 can be used as the channel for the first multiplexer switch 1506-1, and a second layer of semiconductor material 1514-2 can be used as the channel for the second multiplexer switch 1506-2. Subsequent layers of semiconductor material (e.g., semiconductor materials 1514-3, 1514-4, ..., 1514-N) can be used as memory cells (e.g., ...). Figure 1 The channel of memory cell 110 in the memory.

[0164] First multiplexer switch 1506-1 and second multiplexer switch 1506-2 can be selectively coupled to the same vertical sensing line (e.g., sensing line 1503) as access line 1507 in the vertical stack 1502. A first terminal (e.g., source / drain region) of the first multiplexer switch 1506-1 can be coupled to sensing line 1503, and a second terminal of the first multiplexer switch 1506-1 can be coupled to horizontal (e.g., global) sensing line 1513. The first multiplexer switch 1506-1 can be coupled to horizontal sensing line 1513 via a first metal filler 1531 coupled to the second terminal of the first multiplexer switch 1506-1 and a metal line (e.g., horizontal sensing line contact) 1533 coupled to horizontal sensing line 1513. The area where the first metal filler 1531 is deposited can be filled with a "fat" metal (e.g., filled with a metal thicker than the second metal filler 1508 discussed below). Applying a voltage to the gate of the first multiplexer switch 1506-1 can electronically couple the local sensing line 1503 to the horizontal sensing line 1513. The first multiplexer gate (mux1 gate) can be configured for high performance.

[0165] A first terminal of the second multiplexer switch 1506-2 may be coupled to a sensing line 1503, and a second terminal of the second multiplexer switch may include a second metal filler 1508. In some embodiments, the second metal filler 1508 may be deposited in a horizontal opening parallel to and substantially similar to the horizontal opening of the deposited capacitor material. Due to the thickness that the second metal filler 1508 can be deposited, the second metal filler 1508 can act as a resistor and limit the current through the second terminal of the second multiplexer switch 1506-2. When no voltage is applied to the capacitor, the second metal filler 1508 can be used to discharge the voltage stored in the capacitor. In some embodiments, the second metal filler 1508 may be coupled to a capacitor 1537. Applying a voltage to the gate of the second multiplexer switch 1506-2 may couple the second metal filler 1508 to the capacitor 1537 to discharge any charge stored in the capacitor 1537. Applying a voltage to the gate of the second multiplexer switch 1506-2 may also precharge the vertical sensing line 1503.

[0166] In some embodiments, the second terminal of the first multiplexer switch 1506-1 may have a first vertical thickness and be coupled to a corresponding horizontal sensing line 1513. Furthermore, the second terminal of the second multiplexer switch 1506-2 may have a second vertical thickness less than the first vertical thickness. This difference in vertical thickness may result in the second terminal of the first multiplexer switch 1506-1 having a higher resistance than the second terminal of the second multiplexer switch 1506-2. In some embodiments, the second terminals of the first multiplexer switch 1506-1 and the second terminals of the second multiplexer switch 1506-2 are parallel to and vertically aligned with a plurality of memory nodes in a specific vertical stack of memory cells.

[0167] Figure 16 This is a block diagram of a device in the form of a computing system including a memory device 1693 according to several embodiments of the present disclosure. As used herein, for example, the memory device 1693, the memory array 1680, and / or the host (not depicted) may also be individually considered as a “device”.

[0168] In this example, system 1690 includes a host (not depicted) coupled to memory device 1693 via an interface. The computing system can be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device, as well as various other types of systems. The host may include multiple processing resources (e.g., one or more processors, microprocessors, or other types of control circuitry) capable of accessing memory device 1693. The system may include a separate integrated circuit, or the host and memory device 1693 may be on the same integrated circuit. For example, the host may be a system controller for a memory system including multiple memory devices 1693, wherein the system controller (not depicted) provides access to the respective memory devices 1693 by another processing resource, such as a central processing unit (CPU).

[0169] exist Figure 16 In the illustrated example, the host is responsible for executing the operating system (OS) and / or various applications (e.g., processes), which can be loaded onto the host (e.g., via a controller from memory device 1693). The OS and / or various applications can be loaded from memory device 1693 by providing access commands from the host to memory device 1693 for accessing data including the OS and / or various applications. The host can also access the data used by the OS and / or various applications by providing access commands to memory device 1693 for retrieving data used in the execution of the OS and / or various applications.

[0170] For clarity, the system has been simplified to focus on features particularly relevant to this disclosure. Memory array 1680 may be a DRAM array comprising at least one memory cell 1610 having sensing lines and shared digital lines formed according to the techniques described herein. For example, memory array 1680 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Memory array 1680 may include memory cells 1610 arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sensing lines (which may be referred to herein as digital lines or data lines), a sense amplifier 1634, and a transmission gate 1689 that can be used as a switch. The sense amplifier 1634 may be provided for a corresponding sense line and connected to at least one corresponding local input / output (I / O) line pair (LIOT / B), which may in turn be coupled via transmission gate 1689 to at least one corresponding main I / O line pair (MIOT / B). Memory device 1693 may comprise a plurality of arrays 1680 (e.g., a plurality of DRAM cell groups).

[0171] Address signals are received and decoded by address decoder 1671, row decoder 1698, and column control circuitry 1682 to access memory array 1680. Data can be read from memory array 1680 by sensing voltage and / or current changes on a sensing line using sensing circuitry (not depicted). The sensing circuitry may include, for example, a sensing amplifier 1634, which can read and latch a page (e.g., a row) of data from memory array 1680. I / O circuitry 1697 can be used for bidirectional data communication with the host via a first voltage bus 1679, a first data bus 1681, and a second data bus 1684. Read / write circuitry (read / write amplifier) ​​1683 is used to write data to or read data from memory array 1680. For example, read / write circuitry 1683 may include various drivers, latching circuits, etc.

[0172] Command control circuitry 1675 includes registers and decodes signals provided by the host. These signals can be commands provided by the host. Command address input circuitry 1673 receives commands via command bus 1672, and these commands can be decoded by command decoder circuitry (not depicted). Although address input circuitry 1696 and command address input circuitry 1673 are shown as separate circuits, they can be combined into a single circuit. These signals may include chip enable signals, write enable signals, and address latch signals, which control operations performed on memory array 1680, including data read operations, data write operations, and data erase operations. Memory device 1693 may also include refresh control circuitry 1677 for refreshing data in memory device 1693. In various embodiments, control circuitry is responsible for executing instructions from the host. Control circuitry may include a state machine, sequencer, and / or some other type of control circuitry, which may be implemented in hardware, firmware, or software, or any combination thereof. In some instances, the host may be a controller external to memory device 1693. For example, the host can be a memory controller coupled to the processing resources of a computing device.

[0173] The memory device 1693 may also include a clock input circuit 1685 for receiving external clock signals via a clock bus 1674. The memory device 1693 may also include an internal clock generator 1686 for generating internal clock signals. Furthermore, the memory device 1693 may include an internal voltage generator 1687 for generating various internal voltage potentials based on supply potentials VDD and VSS, and a second voltage bus 1688 for transmitting and receiving voltages.

[0174] For example, the term semiconductor can refer to a material, wafer, or substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a substrate semiconductor structure, and other semiconductor structures. Furthermore, when referenced to semiconductor in the foregoing description, prior processing steps may have been used to form regions / junctions in the substrate semiconductor structure, and the term semiconductor may include an underlying material containing these regions / junctions.

[0175] As used herein, “multiple” or “a number” of something can refer to one or more of such things. For example, multiple or a number of memory cells can refer to one or more memory cells. “Multiple” something means two or more. As used herein, multiple actions performed simultaneously refer to actions that overlap at least partially within a specific time period. As used herein, the term “coupling” can include electrical coupling, direct coupling and / or direct connection (e.g., by direct physical contact) without intermediate elements, or indirect coupling and / or connection with intermediate elements, or wireless coupling. The term coupling can further include two or more elements that cooperate or interact with each other (e.g., as in a causal relationship). An element coupled between two elements can be between and coupled to each of the two elements.

[0176] It should be recognized that the term "vertical" refers to variations in verticality due to routine manufacturing, measurement, and / or assembly changes, and those skilled in the art should understand the meaning of the term "vertical." For example, vertical may correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, may be above or laterally to the other element, and / or may be in direct physical contact with the other element. For example, laterally to may refer to a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0177] While specific embodiments have been shown and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of various embodiments of this disclosure. It should be understood that the above description has been carried out illustratively and not restrictively. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the above description. The scope of the various embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and the full scope of the equivalents granted therein.

Claims

1. A method for forming a vertically stacked memory cell array, the vertically stacked memory cell array having horizontally oriented access means and access lines and shared vertically oriented digital lines, the method comprising: Passing through a first dielectric material (430, 530, 630, 730, 830, 930, 1030, 1130, 1230, 1330), a first semiconductor material with a first type of dopant (432, 532, 632, 732, 832, 932, 1032, 1132, 1232, 1332), and a second dielectric material (433, 533, 633, 733, 833, 933, 1033, 1133, 1233, 1333). Repeated iterative vertical stacking forms a plurality of first vertical openings having a first horizontal axis (509, 609, 709, 809, 909, 1009, 1109, 1209, 1309) and a second horizontal axis (505, 605, 705, 805, 905, 1005, 1105, 1205, 1305), the first vertical openings extending primarily on the second horizontal axis to form an elongated vertical column having a first vertical sidewall in the stack; A third dielectric material (539, 639, 739, 839, 939, 1039, 1139, 1239) is deposited in the plurality of first vertical openings; A second vertical opening (670, 770, 870, 970) is formed, which extends through the vertical stack and primarily along the first horizontal axis to expose the second vertical sidewall of the first region adjacent to the first semiconductor material. The second dielectric material is selectively etched on the second horizontal axis to form a plurality of first horizontal openings (673, 773, 873, 973); A portion of the third dielectric material filling the plurality of first vertical openings between the first horizontal openings is removed to form a continuous second horizontal opening extending along the first horizontal axis. In the consecutive second horizontal openings, conductive gate materials (677, 738, 838, 938, 1038, 1138, 1238, 1338) recessed in the plurality of first horizontal openings are deposited on the gate dielectric materials (304, 738, 838, 938, 1038, 1138, 1238, 1377) to form horizontally oriented access lines (107, 207, 307) opposite to the channel regions (225, 325) of the semiconductor material; and Multiple third vertical openings (1072, 1172, 1272, 1372) are formed to deposit a second semiconducting material (1041, 1141, 1241, 1341) having a second type of dopant within the second vertical openings to form the shared vertically oriented digital line.

2. The method of claim 1, further comprising selectively etching the second dielectric material in two opposite directions in parallel along the second horizontal axis to form a plurality of first horizontal openings in opposite directions and to form two adjacent horizontal access devices sharing a vertically oriented digital line to directly electrically contact the formed first source / drain regions (221, 321, 1075, 1175, 1275).

3. The method of claim 2, further comprising coupling a multiplexer to the shared vertically oriented digital line to select between the two adjacent horizontal access devices.

4. The method of claim 1, further comprising depositing tungsten (W) material as the second semiconductive material to form vertically oriented digital lines.

5. The method of claim 1, further comprising: A vapor-phase dopant is applied to the top surface of the first semiconductor material to form a first source / drain region horizontally adjacent to the channel region; as well as A fourth dielectric material (974, 1074, 1174, 1274) is deposited adjacent to the conductive gate material and the gate dielectric material in the continuous second horizontal opening.

6. The method of claim 1, further comprising: A fourth vertical opening (1251, 1351) is formed in the second region adjacent to the first semiconductor material to expose the third vertical sidewall in the vertical stack; The first semiconductor material is selectively etched along the second horizontal axis to form a plurality of third horizontal openings in the second region; Vapor dopant is applied to the side surface of the first semiconductor material from the third horizontal opening to form a second source / drain region (223, 323, 1278) horizontally adjacent to the channel region; as well as A horizontally oriented capacitor cell is deposited, having a bottom electrode (1361) formed in electrical contact with the second source / drain region.

7. The method of claim 1, wherein selective etching of the second dielectric material comprises removing the second dielectric material backward from the second vertical opening by a first distance (DIST 1) (676, 776) in the range of approximately fifty to one hundred and fifty nanometers.

8. The method of claim 1, further comprising using an atomic layer etching (ALE) process to selectively recess the conductive gate material and the gate dielectric material a second distance (DIST 2) back into the continuous second horizontal opening extending along the first horizontal direction axis.

9. The method of claim 1, further comprising depositing an oxide material layer as the first dielectric material, a lightly doped p-type (p-) polycrystalline silicon layer as the first semiconductor material, and a silicon nitride (SiN) material layer as the second dielectric material in a vertically repeating iterative manner to form the vertical stack.

10. A method for forming a vertically stacked memory cell array, the vertically stacked memory cell array having horizontally oriented access means and access lines and shared vertically oriented digital lines, the method comprising: Repeated iterations through the first dielectric material (430, 530, 630, 730, 830, 930, 1030, 1130, 1230, 1330), the first semiconductor material (432, 532, 632, 732, 832, 932, 1032, 1132, 1232, 1332), and the second dielectric material (433, 533, 633, 733, 833, 933, 1033, 1133, 1233, 1333). The vertical stacking forms a plurality of first vertical openings having a first horizontal axis (509, 609, 709, 809, 909, 1009, 1109, 1209, 1309) and a second horizontal axis (505, 605, 705, 805, 905, 1005, 1105, 1205, 1305), the first vertical openings extending primarily along the second horizontal axis to form an elongated vertical column having a first vertical sidewall in the stack; The plurality of first vertical openings are filled with a third dielectric material (539, 639, 739, 839, 939, 1039, 1139, 1239); A second vertical opening (670, 770, 870, 970) is formed, which extends through the vertical stack and primarily along the first horizontal axis to expose the second vertical sidewall of the first region adjacent to the first semiconductor material. The second dielectric material is selectively etched on the second horizontal axis to form a plurality of first horizontal openings (673, 773, 873, 973) that are vertically and horizontally separated in the stack and horizontally separated by the third dielectric material; A portion of the third dielectric material filling the plurality of first vertical openings is removed between the lateral sides of the first horizontal openings extending on the second horizontal axis to form a continuous second horizontal opening extending on the first horizontal axis. In the continuous second horizontal opening, recessed conductive materials (677, 777, 877, 977, 1077, 1177, 1277, 1377) are deposited on the gate dielectric materials (304, 738, 838, 938, 1038, 1138, 1238, 1338) to form horizontally oriented access lines (107, 207, 307) opposite to the channel regions (225, 325) of the semiconductor material; A fourth dielectric material (974, 1074, 1174, 1274) is deposited adjacent to the horizontally oriented access line to fill the plurality of first horizontal openings into the second vertical opening; Polycrystalline silicon material (1041, 1141, 1241, 1341) with second-type dopants is deposited in the third vertical opening to form a shared vertically oriented digital line; as well as The polycrystalline silicon material is annealed to allow the second type of dopant to diffuse outward into the first semiconductor material, thereby forming the first source / drain region of the horizontally oriented access device.

11. The method of claim 10, wherein forming the shared vertically oriented digital line comprises forming two adjacent horizontal access devices that share the vertically oriented digital line to make direct electrical contact with the first source / drain region, thereby improving the array efficiency of the digital line.

12. The method of claim 10, further comprising depositing a titanium / titanium nitride (TiN) conductive material on the polycrystalline silicon material via the third vertical opening to form a titanium silicide as part of the shared vertically oriented digital line coupled to the first source / drain region of the horizontally oriented access device.

13. The method of claim 10, further comprising depositing a ruthenium (Ru) composition as the conductive material to form a horizontally oriented access line opposite to the channel region of the semiconductor material.

14. A memory device comprising: A vertically stacked memory cell array, the array comprising: A horizontally oriented access device having a first source / drain region (221, 321, 1075, 1175, 1275) and a second source / drain region (223, 323, 1278) separated by a channel region, and a gate opposite to the channel region (225, 325) and separated from the channel region by a gate dielectric (304, 738, 838, 938, 1038, 1138, 1238, 1338); wherein each horizontally oriented access device comprises a vertically stacked, iterative arrangement of a first dielectric material, a semiconductor material including the channel region, and a second dielectric material; Horizontal oriented access lines (107, 207, 307) form the gate and are separated from the channel region by the gate dielectric; A horizontally oriented memory node electrically coupled to the second source / drain region of the horizontally oriented access device; A third dielectric material, which is adjacent to the horizontally oriented storage node in the vertical opening through the vertical stack; The second dielectric material is formed between the gate and the channel region connected to the gate dielectric; and A vertically oriented digital line, which is shared between the two horizontally oriented access devices in two opposite directions, is electrically coupled to the first source / drain regions of the two horizontally oriented access devices.

15. The memory device of claim 14, wherein the vertically oriented digital line comprises one of the following: High phosphorus (P) doped (n+) polycrystalline silicon-germanium (SiGe) materials; or Tungsten (W) material formed on titanium / titanium nitride (TiN) material, wherein the TiN material forms titanium silicide with the first source / drain region of the horizontally oriented access device.

16. The memory device of claim 14, wherein the horizontally oriented access device is a gate-all-around (GAA) horizontally oriented access device having a conductive gate material that completely surrounds each surface of the channel region.

17. The memory device of claim 14, wherein the horizontal access device is a dual-gate horizontal access device.

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