Semiconductor device

Abstract

The device includes a source electrode, a drain electrode, and a gate that controls the current flowing between the source electrode and the drain electrode. Furthermore, if the capacitance between the gate and the drain electrode is defined as a first capacitor Cgd, the capacitance between the gate and the source electrode as a second capacitor Cgs, the sum of the first capacitor Cgd and the second capacitor Cgs as a third capacitor Ciss, and the sum of a first switching loss Et(dI / dt) defined by the current change rate dI / dt and a second switching loss Et(dV / dt) defined by the voltage change rate dV / dt is defined as the total switching loss Esum, then the capacitance ratio of the first capacitor Cgd to the third capacitor Ciss, Cgd / Ciss, is set as the ratio where the total switching loss Esum is below a predetermined threshold.

Description

[0001] Cross-references to related applications

[0002] This application is based on Japanese Patent Application No. 2019-168543, filed on September 17, 2019, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device having a gate. Background Technology

[0004] As switching elements used in inverters, DC / DC converters, etc., semiconductor devices with gates have been proposed in the past (see, for example, Non-Patent Document 1). Specifically, the semiconductor device is configured to have a gate, a source, and a drain. Furthermore, in this semiconductor device, it is configured to reduce switching losses by reducing Miller charge Qgd.

[0005] Existing technical documents

[0006] Non-patent literature

[0007] Non-Patent Literature 1: Syotaro Ono, Yoshihiro Yamaguchi, Yusuke Kawaguchi, Akio Nakagawa, 30V Sub-micron Shallow Junction Planar-MOSFET for DC-DC Converters, Proceedings of 2004 International Symposium on Power Semiconductor Devices & ICs, Kitakyushu, pp.401-404 (Reference translation: Syotaro Ono, Yoshihiro Yamaguchi, Yusuke Kawaguchi, Akio Nakagawa, 30V Sub-micron Shallow Junction Planar-MOSFET for DC-DC Converters, Proceedings of 2004 International Symposium on Power Semiconductor Devices & ICs, Kitakyushu, pp.401-404) Summary of the Invention

[0008] However, in the aforementioned semiconductor device, by reducing the Miller charge Qgd, the Miller time becomes shorter, and therefore the drain voltage change time also becomes shorter. Furthermore, in the aforementioned semiconductor device, as the drain voltage change time shortens, the dV / dt surge becomes larger. Therefore, when the aforementioned semiconductor device is assembled into a system constituting an inverter or the like, there are concerns about system damage caused by noise or surges.

[0009] The purpose of this disclosure is to provide a semiconductor device that can reduce switching losses while suppressing damage.

[0010] According to one aspect of this disclosure, a semiconductor device includes: a source electrode; a drain electrode; and a gate, the gate controlling the current flowing between the source electrode and the drain electrode; if the capacitance between the gate and the drain electrode is defined as a first capacitance, the capacitance between the gate and the source electrode is defined as a second capacitance, the sum of the first capacitance and the second capacitance is defined as a third capacitance, and the sum of a first switching loss defined by the rate of change of current and a second switching loss defined by the rate of change of voltage is defined as the total switching loss, then the capacitance ratio of the first capacitance to the third capacitance is defined as the ratio at which the total switching loss is lower than a predetermined threshold.

[0011] Therefore, since the total switching loss is configured to be below a specified amount, the switching loss can be reduced, and the system damage can be suppressed when it is assembled into a system constituting an inverter, etc.

[0012] Furthermore, the bracketed reference numerals used to indicate each constituent element, etc., represent an example of the correspondence between the constituent element, etc., and the specific constituent elements, etc., described in the embodiments described later. Attached Figure Description

[0013] Figure 1 This is a top view of the semiconductor device according to the first embodiment.

[0014] Figure 2 It is along Figure 1 A sectional view along line II-II.

[0015] Figure 3 It is along Figure 1 A sectional view along line III-III.

[0016] Figure 4 These are simulation results representing the relationship between the depth of the separation layer and the capacitance ratio.

[0017] Figure 5 This is a graph showing the relationship between capacitance ratio and switching losses.

[0018] Figure 6 This is a cross-sectional view of the semiconductor device according to the second embodiment. Detailed Implementation

[0019] Hereinafter, embodiments of the present disclosure will be described based on the accompanying drawings. Furthermore, the same reference numerals will be used to describe the parts that are identical or equivalent to each other in the following embodiments.

[0020] (First Implementation)

[0021] The semiconductor device of the first embodiment will be described with reference to the accompanying drawings. Furthermore, the semiconductor device of this embodiment is preferably used as a power switching element in a power supply circuit, such as an inverter or a DC / DC converter.

[0022] Hereinafter, a semiconductor device having a JFET formed thereon will be described in this embodiment. First, referring to... Figures 1-3 The structure of the semiconductor device in this embodiment will be described. Furthermore, Figure 1 This is a top view showing one cell of a JFET. Semiconductor devices are constructed by... Figure 1 The shown units are arranged in a contiguous manner. Additionally, in Figure 1 In this text, the interlayer insulating film 23, gate electrode 24, source electrode 25, etc., which will be described later, are omitted.

[0023] The semiconductor device includes a semiconductor substrate 10, the semiconductor substrate 10 having N ++ The drain layer 11 is made of a silicon carbide (hereinafter also referred to as SiC) substrate. Furthermore, an N-type impurity layer with a lower impurity concentration than the drain layer 11 is disposed on the drain layer 11. + A type of buffer layer 12, on which an N2 impurity concentration lower than that of the buffer layer 12 is disposed. － The type of drift layer 13. In addition, the buffer layer 12 and the drift layer 13 are formed, for example, by growing an epitaxial film of SiC on the SiC substrate constituting the drain layer 11.

[0024] An N-type channel layer 14 with a higher impurity concentration than the drift layer 13 is disposed on the drift layer 13. Furthermore, the channel layer 14 is formed, for example, by growing a SiC epitaxial film. In this embodiment, one side 10a of the semiconductor substrate 10 is configured as a surface containing the channel layer 14.

[0025] P with a higher impurity concentration than channel layer 14 is formed on channel layer 14. + Type 15 gate layer and P + The body layer 16 is of the form of a square frame. In this embodiment, when viewed from above as a unit region, the body layer 16 is formed as a four-sided frame with one direction as its long side. Furthermore, in... Figure 1 In the middle, it is formed into a four-sided border shape with the vertical direction of the paper as its long side. When viewed from above, the gate layer 15 is set into a rectangular shape with the long side of the body layer 16 as its long side, and is formed in a manner that is located within the body layer 16 and separated from the body layer 16. In this embodiment, the gate layer 15 is equivalent to a gate.

[0026] Furthermore, if the thickness direction of the semiconductor substrate 10 is taken as the depth direction, the gate layer 15 and the body layer 16 are formed from one side 10a of the semiconductor substrate 10 (i.e., the surface of the channel layer 14) along the depth direction, and the body layer 16 is formed deeper than the gate layer 15. In addition, the depth direction of the semiconductor substrate 10 can also be described as the stacking direction of the drain layer 11, the drift layer 13, and the channel layer 14.

[0027] On the surface of the channel layer 14, an N layer with a higher impurity concentration than the channel layer 14 is formed in a manner that connects it to the body layer 16. + Type 17 source layer.

[0028] Furthermore, in the channel layer 14, at a depth deeper than the gate layer 15, a shielding layer 18 is formed in a manner separate from and opposite to the gate layer 15. That is, in the channel layer 14, in the portion located between the gate layer 15 and the drift layer 13, a shielding layer 18 opposite to the gate layer 15 is formed.

[0029] In this embodiment, the shielding layer 18 is configured to have the same impurity concentration as the body layer 16 (P). + The shielding layer 18, when viewed from above, is rectangular in shape along the long side of the gate layer 15. Furthermore, the shielding layer 18 is longer than the gate layer 15 along its long side, and is electrically connected to the body layer 16 by connecting its two ends along its long side to the body layer 16. In other words, the shielding layer 18 in this embodiment is set to be at the same potential as the body layer 16. In this embodiment, the shielding layer 18 is maintained at a different potential from the gate layer 15 in this manner.

[0030] Additionally, N is formed in the channel layer 14, in the portion between the gate layer 15 and the shielding layer 18. + The separation layer 19 is a type of separation layer. This separation layer 19 is a layer that electrically separates the gate layer 15 from the shielding layer 18, and has a higher impurity concentration than the channel layer 14.

[0031] Furthermore, in this embodiment, on the surface portion of the channel layer 14, such as Figure 1 and Figure 3 As shown, an STI (Shallow Trench Isolation) separation section 20 is formed to electrically separate the gate layer 15 from the body layer 16. Specifically, the STI separation section 20 is formed at both ends of the gate layer 15 in the long side direction between the gate layer 15 and the body layer 16. In addition, the STI separation section 20 in this embodiment is constructed by burying the insulating film 22 in a trench 21 at a predetermined depth.

[0032] An interlayer insulating film 23 is formed on one side 10a of the semiconductor substrate 10. A first contact hole 23a is formed on the interlayer insulating film 23, exposing the gate layer 15, and a second contact hole 23b is formed on the interlayer insulating film 23, exposing the body layer 16 and the source layer 17. A gate electrode 24 is disposed on the interlayer insulating film 23 such that it passes through the first contact hole 23a and is electrically connected to the gate layer 15. An active electrode 25 is formed on the interlayer insulating film 23 such that it passes through the second contact hole 23b and is electrically connected to the body layer 16 and the source layer 17.

[0033] Furthermore, a drain electrode 26 electrically connected to the drain layer 11 is formed on the other side 10b of the semiconductor substrate 10.

[0034] The above describes the structure of the semiconductor device according to this embodiment. Furthermore, in this embodiment, N... － Type, N-type, N + Type, N ++ Type P is equivalent to the first conductivity type. + This type corresponds to the second conductivity type. Furthermore, in this embodiment, as described above, the semiconductor substrate 10 comprises a drain layer 11, a buffer layer 12, a drift layer 13, a channel layer 14, a gate layer 15, a body layer 16, a source layer 17, and a shielding layer 18. Moreover, in this embodiment, as described above, the drain layer 11 is made of a SiC substrate, and the buffer layer 12, drift layer 13, channel layer 14, etc., are formed by growing an epitaxial film of SiC. Therefore, the semiconductor device of this embodiment can also be referred to as a SiC semiconductor device.

[0035] Next, the relationship between the gate layer 15 and the shielding layer 18 in this embodiment will be explained. Hereinafter, the capacitance between the gate layer and the drain electrode will be designated as the first capacitor Cgd, the capacitance between the gate layer and the source electrode will be designated as the second capacitor Cgs, and the sum of the first capacitor Cgd and the second capacitor Cgs (i.e., Cgd + Cgs) will be designated as the third capacitor Ciss. Furthermore, the first capacitor is equivalent to a Miller capacitor, and the third capacitor is equivalent to an input capacitor.

[0036] Furthermore, the ratio expressed in terms of the first capacitor Cgd relative to the third capacitor Ciss is defined as the capacitance ratio Cgd / Ciss (hereinafter also simply referred to as the capacitance ratio). In this case, if the length from one side 10a of the semiconductor substrate 10 to the bottom surface of the shielding layer 18 and the spacing between the gate layer 15 and the shielding layer 18 are set to a constant, then as follows... Figure 4 As shown, the capacitance ratio changes by varying the depth of the separator layer 19. Specifically, it can be confirmed that the deeper the separator layer 19 is formed, the greater the capacitance ratio. That is, it can be confirmed that the deeper the gate layer 15 is formed, the greater the capacitance ratio. In other words, in this semiconductor device, the capacitance ratio can be easily varied, for example, by varying the depth of the gate layer 15.

[0037] Furthermore, the inventors conducted in-depth research on the relationship between capacitance ratio and switching losses, and obtained... Figure 5 The results are shown. Specifically, the inventors investigated the relationship between the capacitance ratio and the switching loss Et(dI / dt) defined by the rate of change of current dI / dt (hereinafter also simply dI / dt). Furthermore, the inventors investigated the relationship between the capacitance ratio and the switching loss Et(dV / dt) defined by the rate of change of voltage dV / dt (hereinafter also simply dV / dt). Moreover, the inventors investigated the total switching loss Esum (i.e., Et(dI / dt) + Et(dV / dt)) which is the sum of the capacitance ratio and the switching loss Et(dI / dt) and the switching loss Et(dV / dt).

[0038] Furthermore, dI / dt corresponds to self-surge, and dV / dt corresponds to system surges such as motor surges that may occur when a system such as an inverter circuit is constructed. In this embodiment, the switching loss Et(dI / dt) defined by dI / dt corresponds to the first switching loss. Similarly, the switching loss Et(dV / dt) defined by dV / dt corresponds to the second switching loss.

[0039] The switching losses will be explained in detail below. Furthermore, the semiconductor device described above controls the current flowing between the source electrode 25 and the drain electrode 26 by applying a voltage to the gate layer 15. The action of cutting off the current from a state where it is flowing through the semiconductor device will be referred to as "cut-off," and the action of setting the state where the current is not flowing through the semiconductor device to a state where it is flowing will be referred to as "on-off." The power supply voltage will be set to Vd, the operating current to Id, the cut-off time totoff, the gate resistance to Rg, the gate Miller potential to Vm, the gate threshold voltage to Vth, the on-time toton, and the gate drive voltage to Vg.

[0040] First, the dI / dt when the semiconductor device is cut off is shown in the following mathematical formula 1.

[0041] [Mathematical Expression 1]

[0042] dI / dt=Id / toff

[0043] In addition, the toff in mathematical formula 1 is shown in mathematical formula 2 below.

[0044] [Mathematical Expression 2]

[0045] toff = Rg × Ciss × In(Vm / Vth)

[0046] Similarly, dV / dt when the semiconductor device is cut off is shown in Equation 3 below.

[0047] [Mathematical Expression 3]

[0048] dV / dt=Vd / tm

[0049] In addition, tm in mathematical formula 3 is shown in mathematical formula 4 below.

[0050] [Mathematical Expression 4]

[0051] tm=(Rg×Cgd×Vd) / Vm

[0052] In addition, the dI / dt when the semiconductor device is turned on is shown in the following mathematical formula 5.

[0053] [Mathematical Expression 5]

[0054] dI / dt=Id / ton

[0055] In addition, ton in mathematical formula 5 is shown in mathematical formula 6 below.

[0056] [Mathematical Expression 6]

[0057] ton=Rg×Ciss×ln{(Vg-Vth) / (Vg-Vm)}

[0058] Similarly, dV / dt when the semiconductor device is turned on is shown in the following mathematical formula 7.

[0059] [Mathematical Expression 7]

[0060] dV / dt=Vd / tm

[0061] In addition, tm in mathematical formula 7 is as shown in mathematical formula 8 below.

[0062] [Mathematical Expression 8]

[0063] tm=(Vd×Rg×Cgd) / (Vg-Vm)

[0064] Furthermore, the switching loss when the semiconductor device is turned off is defined as Eon, the switching loss when the semiconductor device is turned on is defined as Eoff, and the recovery loss is defined as Err. In this case, the switching loss Et(dI / dt) specified by dI / dt is shown in the following mathematical formula 9.

[0065] [Mathematical Expression 9]

[0066] Et(dI / dt)=Eon+Eoff+Err

[0067] Furthermore, Eon and Eoff in the switching loss Et(dI / dt) are shown in Equations 10 and 11 below.

[0068] [Mathematical Expression 10]

[0069] Eoff=Vd×Id 2 ×{0.5+(Cgd×Vd) / (2×Vm×Ciss) / In(Vm / Vth)} / (dI / dt)

[0070] [Mathematical Expression 11]

[0071] Eon=Vd×Id 2 ×[0.5+(Vd×Cgd) / {2(Vg-Vm)×Ciss} / In{(Vg-Vth) / (Vg-Vm)] / (dI / dt)

[0072] Furthermore, the recovery loss Err is usually small enough relative to Eon and Eoff to be negligible. Similarly, the switching loss Et(dV / dt), specified in dV / dt, is shown in Equation 12 below.

[0073] [Mathematical Expression 12]

[0074] Et(dV / dt)=Eon+Eoff+Err

[0075] In this case, Eon and Eoff in the switching loss Et(dV / dt) are shown in Equations 13 and 14 below.

[0076] [Mathematical Expression 13]

[0077] Eoff=Vd×Id×{(Vm / 2 / Cgd)×Ciss×ln(Vm / Vth)+Vd / 2}(dV / dt)

[0078] [Mathematical Expression 14]

[0079] Eon=Vd×Id×[(Ciss / 2)×ln{(Vg-Vth) / (Vg-Vm)}×(Vg-Vm) / Cgd+Vd / 2] / (dV / dt)

[0080] And, as Figure 5 As shown, it can be confirmed that a larger capacitance ratio results in a smaller switching loss Et(dV / dt), and a larger capacitance ratio results in a larger switching loss Et(dI / dt). In other words, the relationship between switching loss Et(dV / dt) and switching loss (dI / dt) and capacitance ratio is inverse. Furthermore, the semiconductor device is preferably configured to have both small switching losses Et(dV / dt) and Et(dI / dt). That is, the semiconductor device is preferably configured to have a small total switching loss Esum. Therefore, the semiconductor device of this embodiment is configured such that Esum is below a predetermined threshold. Specifically, the semiconductor device of this embodiment is configured to satisfy the following values.

[0081] First, based on the above mathematical formulas 1 to 14, the capacitance at the intersection point x1 of the two tangents SI1 and SI2 of the switching loss Et (dI / dt) and the intersection point x1 of the two tangents SV1 and SV2 of the switching loss Et (dV / dt) is shown in the following mathematical formula 15.

[0082] [Mathematical Expression 15]

[0083] Cgd / Ciss=x1=Id / (gm×Vd)

[0084] Furthermore, in Equation 15, gm is Id / (Vm-Vth), and the same applies in the following formulas. Tangent SI1 is the tangent with the smallest absolute value of the slope of the switching loss Et(dI / dt), and tangent SI2 is the tangent with the largest absolute value of the slope of the switching loss Et(dI / dt). Tangent SV1 is the tangent with the largest absolute value of the slope of the switching loss Et(dV / dt), and tangent SV2 is the tangent with the smallest absolute value of the slope of the switching loss Et(dV / dt).

[0085] Furthermore, the intersection point x2 of the switching loss Et(dI / dt) and the switching loss Et(dV / dt) is Et(dI / dt) = Et(dV / dt). Therefore, based on the above mathematical equations 1 to 14, the capacitance at this intersection point x2 is as shown in the following mathematical equation 16.

[0086] [Mathematical Expression 16]

[0087] Cgd / Ciss=x2=dI / dt / (gm×dV / dt)

[0088] Furthermore, the semiconductor device of this embodiment is configured such that the capacitance ratio is 15 or higher and 16 or lower than the aforementioned mathematical formula. For example, as described above... Figure 4 As explained, the semiconductor device is configured such that, by changing the depth relationship between the gate layer 15 and the shielding layer 18, the capacitance ratio is greater than or equal to the aforementioned mathematical formula 14 and less than or equal to the aforementioned mathematical formula 15. This results in a semiconductor device with reduced switching losses Et(dI / dt) and Et(dV / dt).

[0089] In this case, based on the above mathematical formulas 1 to 14, the minimum value x3 in the total switching loss Esum is shown in the following mathematical formula 17.

[0090] [Mathematical Expression 17]

[0091] Cgd / Ciss=×3=1 / gm×{(Id / Vd)×(dI / dt) / (dV / dt)} 1 / 2

[0092] Therefore, by configuring the semiconductor device to achieve the capacitance ratio described in Equation 17 above, the total switching loss Esum can be minimized. Additionally, x3 2 It is also x1×x2.

[0093] As explained above, in this embodiment, the capacitance ratio is set to 15 or higher and 16 or lower. Therefore, the total switching loss Esum can be reduced, and damage to the system can be suppressed when it is assembled into a system constituting an inverter or similar device.

[0094] (Second Implementation)

[0095] The second embodiment will be described. Compared to the first embodiment described above, this embodiment is a semiconductor device having a MOSFET formed therein. Other aspects are the same as in the first embodiment described above, and therefore will not be described here.

[0096] like Figure 6 As shown, the semiconductor device of this embodiment includes a semiconductor substrate 110, which has N... + A drain layer 111 is formed on a substrate of the type described above. Furthermore, an N-type impurity layer with a lower concentration than that of the drain layer 111 is disposed on the drain layer 111. - A drift layer 112 of type 112. A P-type channel layer 113 with a higher impurity concentration than the drift layer 112 is disposed on the drift layer 112.

[0097] Furthermore, a plurality of trenches 114 are formed on the semiconductor substrate 110 in such a manner that they penetrate the channel layer 113 and reach the drift layer 112, and the channel layer 113 is separated into a plurality of trenches 114. In this embodiment, the plurality of trenches 114 are along one of the surface directions of one side 110a of the semiconductor substrate 110 (i.e., Figure 6 The grooves 114 are formed into strips at equal intervals (in the direction of the paper's depth). Alternatively, the multiple grooves 114 can also be formed into a ring structure by wrapping around the front ends.

[0098] Furthermore, each trench 114 is filled with a gate insulating film 115 and a gate electrode 116. The gate insulating film 115 is formed in such a way as to cover the walls of each trench 114, and the gate electrode 116 is made of polysilicon or the like formed on the gate insulating film 115. Thus, a trench gate structure is formed.

[0099] Furthermore, N is formed in channel layer 113. + Type 117 source layer and P sandwiched by source layer 117 + The contact layer 118 is of the type 118. The source layer 117 is formed with a higher impurity concentration than the drift layer 112 and is formed in a manner that it is in contact with the side of the trench 114. The contact layer 118 is formed with a higher impurity concentration than the channel layer 113.

[0100] More specifically, the source layer 117 is configured such that it extends in a rod-like shape along the long side of the trench 114 in the region between the trenches 114, connecting with the side of the trench 114, and terminates at a point inward from the front end of the trench 114. Furthermore, the contact layer 118 is sandwiched between two source layers 117 and extends in a rod-like shape along the long side of the trench 114 (i.e., the source layers 117). The contact layer 118 is formed to approximately the same depth as the trench 114.

[0101] An interlayer insulating film 119 is formed on the channel layer 113 (i.e., one side 110a of the semiconductor substrate 110). A contact hole 119a is formed on the interlayer insulating film 119, exposing a portion of the source layer 117 and the contact layer 118. A source electrode 120 is formed on the interlayer insulating film 119, passing through the contact hole 119a and electrically connected to the source layer 117 and the contact layer 118.

[0102] On the other side 110b of the semiconductor substrate 110, a drain electrode 121 electrically connected to the drain layer 111 is formed.

[0103] The above describes the structure of the semiconductor device according to this embodiment. Furthermore, the semiconductor device is configured such that the capacitance between the gate electrode 116 and the drain electrode 121 is set as the first capacitance Cgd, and the capacitance between the gate electrode 116 and the source electrode 120 is set as the second capacitance Cgs, thereby satisfying the aforementioned capacitance ratio. The semiconductor device of this embodiment is configured such that by making the depth of the contact layer 118 approximately the same as the depth of the trench 114, the capacitance ratio is greater than or equal to formula 15 and less than formula 16.

[0104] As explained above, in a semiconductor device in which a MOSFET is formed, the same effect as described in the first embodiment can be obtained by configuring the capacitance ratio to satisfy the first embodiment.

[0105] (Other implementation methods)

[0106] This disclosure is based on embodiments, but it should be understood that this disclosure is not limited to these embodiments and structures. This disclosure also includes various modifications and equivalent variations. In addition, various combinations and methods, as well as other combinations or methods that contain only one element, more or fewer elements, are also within the scope or spirit of this disclosure.

[0107] For example, in the above embodiments, examples of setting the first conductivity type to N type and the second conductivity type to P type have been described, but it is also possible to set the first conductivity type to P type and the second conductivity type to N type.

[0108] Furthermore, in the first embodiment described above, the semiconductor device can be configured to use either a silicon substrate or another compound semiconductor substrate. Similarly, in the second embodiment described above, the semiconductor device can be configured to use either a SiC substrate or another compound semiconductor substrate.

[0109] Furthermore, in the first embodiment described above, an example of adjusting the depth relationship between the gate layer 15 and the shielding layer 18 was given as a method for changing the capacitance ratio. However, as long as the capacitance ratio is changed, other methods can also be used to change the capacitance ratio. For example, the capacitance ratio can also be changed by adjusting the impurity concentration of the body layer 16 and the shielding layer 18.

[0110] Similarly, in the second embodiment described above, an example of increasing the depth of the contact layer 118 was given as a method for changing the capacitance ratio. However, as long as the capacitance ratio is changed, other methods can also be used to change the capacitance ratio. For example, the capacitance ratio can also be changed by forming a p-type impurity layer between the gate electrode 116 and the drain electrode 121.

[0111] Furthermore, in the second embodiment described above, a trench gate type semiconductor device was described, but the semiconductor device may also be a planar gate type in which the gate electrode 116 is disposed on one side 110a of the semiconductor substrate 110.

Claims

1. A semiconductor device having a gate electrode (15, 116), characterized by comprising: Possessing: a source electrode (25, 120); a drain electrode (26, 121); and a gate electrode that controls current flowing between the source electrode and the drain electrode; if a capacitance between the gate electrode and the drain electrode is set as a first capacitance (Cgd), a capacitance between the gate electrode and the source electrode is set as a second capacitance (Cgs), a sum of the first capacitance and the second capacitance is set as a third capacitance (Ciss), and a sum of a first switching loss (Et(dI / dt)) defined by a current change rate (dI / dt) and a second switching loss (Et(dV / dt)) defined by a voltage change rate (dV / dt) is set as a total switching loss (Esum), then a capacitance ratio (Cgd / Ciss) of the first capacitance with respect to the third capacitance is set as a ratio at which the total switching loss is lower than a prescribed threshold value, if Vd is set as a power supply voltage, Id is set as an operation current, Vm is set as a gate Miller potential, Vth is set as a threshold voltage of a gate, and gm is set as Id / (Vm-Vth), then the capacitance ratio is set as the following Mathematical Expression 1 or more and the following Mathematical Expression 2 or less: [Mathematical Expression 1] Cgd / Ciss = Id / (gm x Vd) [Mathematical Expression 2] Cgd / Ciss = dI / dt / (gm x dV / dt).

2. The semiconductor device according to claim 1, wherein the capacitance ratio is set as the following Mathematical Expression 3: [Mathematical Expression 3] Cgd / Ciss = 1 / gm x {(Id / Vd) x (dI / dt) / (dV / dt)} 1 / 2 .

3. The semiconductor device according to claim 1 or 2, wherein Possessing: a drift layer (13) of a first conductivity type; a channel layer (14) of the first conductivity type that is disposed on the drift layer; a source layer (17) of the first conductivity type that is formed in a surface layer portion of the channel layer and has a higher impurity concentration than the channel layer; a gate layer (15) of a second conductivity type that is the gate and is formed deeper in the channel layer than the source layer; a drain layer (11) of the first conductivity type that is disposed on a side opposite the source layer with the drift layer interposed therebetween; the source electrode that is electrically connected to the source layer; the drain electrode that is electrically connected to the drain layer; and a shield layer (18) that is disposed between the gate layer and the drain electrode and is electrically connected to the source electrode; the gate layer and the shield layer are configured to satisfy the capacitance ratio. Possessing:

4. The semiconductor device according to claim 1 or 2, wherein a drift layer (112) of a first conductivity type; a channel layer (113) of a second conductivity type that is disposed on the drift layer; a source layer (117) of the first conductivity type that is formed in a surface layer portion of the channel layer and has a higher impurity concentration than the drift layer; a gate insulating film (115) that is disposed on a surface of the channel layer interposed between the source layer and the drift layer; a gate electrode (116) that is the gate and is disposed on the gate insulating film; and the gate electrode and the gate insulating film are configured to satisfy the capacitance ratio. A drain layer (111) of a first conductivity type is disposed on the side opposite to the channel layer with the drift layer interposed therebetween; The source electrode is electrically connected to the channel layer and the source layer; And The drain electrode is connected to the drain layer. In the channel layer, a contact layer (118) of a second conductivity type is formed in the surface layer portion and is electrically connected to the source electrode, The gate electrode and the contact layer are configured to satisfy the capacitance ratio.

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