Low power mode management

Abstract

Various embodiments of the present disclosure relate to the management of low power modes. In one embodiment, a method for managing the low power mode of an electronic device includes storing the value of a first counter and the value of a second counter of the electronic device at a first edge of a first clock upon a first request for transitioning the electronic device to the low power mode; and calculating the number of cycles of a second clock between a second edge of the first clock and the first edge upon a second request for transitioning the electronic device out of the low power mode, the second edge being later than the first edge; and updating the value of the second counter using the calculated value, wherein the first clock drives the first counter and the second clock drives the second counter, the second clock being faster than the first clock.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French Application No. 2011958, filed on November 20, 2020, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic circuits and devices, and more particularly to the management of different power consumption modes in electronic devices or systems. Background Art

[0004] Current electronic systems and devices have multiple power consumption levels. In particular, low power modes are now commonly provided to reduce power consumption. Summary of the invention

[0005] Embodiments provide improved mechanisms for managing low power modes of electronic systems and devices.

[0006] Embodiments overcome the shortcomings of known mechanisms of low power mode management, in particular the shortcomings of time base management mechanisms in low power mode.

[0007] One embodiment provides a method for managing a low power mode of an electronic device, the electronic device comprising a first clock for rating a first counter and a second clock for rating a second counter that is faster than the first counter, the method comprising the following steps: upon a first request for entering the low power mode, saving the value of the first counter and the value of the second counter at a first edge of the first clock; and upon a second request for leaving the low power mode: calculating the number of cycles of the second clock included between the second edge of the first clock and the first edge after the above-mentioned second request; and using the calculated value to update the value of the second counter.

[0008] One embodiment provides an electronic device, which includes a first clock for rating a first counter and a second clock for rating a second counter that is faster than the first counter, and the electronic device is configured to: upon a first request for entering a low power mode, save the value of the first counter and the value of the second counter at a first edge of the first clock; upon a second request for leaving the low power mode: calculate the number of cycles of the second clock included between the second edge of the first clock after the above-mentioned second request and the first edge; and use the calculated value to update the value of the second counter.

[0009] One embodiment provides a computer program product comprising instructions which, when implemented by an electronic device comprising a first clock for rating a first counter and a second clock for rating a second counter faster than the first counter, cause: upon a first request for entering a low power mode, saving the value of the first counter and the value of the second counter at a first edge of the first clock; and upon a second request for leaving the low power mode: calculating the number of cycles of the second clock included between the second edge of the first clock and the first edge after the above-mentioned second request; and updating the value of the second counter using the calculated value.

[0010] According to one embodiment, the updating of the value of the second counter is performed at an edge of the first clock.

[0011] According to one embodiment, the first counter represents a real time clock.

[0012] According to one embodiment, the second counter represents system time used by the processor that is active outside of the low power mode.

[0013] According to one embodiment, the first clock maintaining activity includes being in a low power mode, and the second clock is disabled in the low power mode.

[0014] According to one embodiment, an operation of saving or restoring the value of the second counter is implemented.

[0015] According to one embodiment, the low power mode controller is active, including in a low power mode.

[0016] According to one embodiment, the calculation of the number of cycles of the second clock comprised between said second edge and said first edge takes into account the time of processing the values ​​of the counters for their saving and restoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above features and advantages and other features and advantages will be described in detail in the following description of specific embodiments given by way of example and not limitation, with reference to the accompanying drawings, in which:

[0018] Figure 1 shows a functional block diagram according to an embodiment;

[0019] Figure 2 A low power mode management method according to an embodiment is shown; and

[0020] Figure 3 A timing diagram according to an embodiment is shown.

[0021] In different figures, similar features are designated by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, dimensions and material properties. DETAILED DESCRIPTION

[0022] For the sake of clarity, only the steps and elements useful for understanding the embodiments described herein are explained and described in detail. In particular, except for the needs of this specification, the components of the electronic system or device suitable for the implementation of the described solution have not been explained in detail, and the described embodiments are compatible with any electronic system or device with a standby or low power mode.

[0023] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0024] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers such as terms "front", "back", "top", "bottom", "left", "right", or relative position qualifiers such as terms "above", "below", "upper", "lower", or orientation qualifiers such as "horizontal", "vertical", etc., reference is made to the orientation shown in the figure.

[0025] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "on the order of" mean within 10%, preferably within 5%.

[0026] Figure 1 A functional block diagram of an electronic device according to an embodiment is shown.

[0027] An electronic device of the type to which the described implementation and embodiments are applicable comprises at least one processor 1 (CPU) adapted to implement at least one operating system to handle various FCT functions depending on the application of the device. For its rated value or timing, the processor 1 uses a clock between several hundred MHz and several GHz, usually derived from a system or high-speed clock HSC (usually via a phase-locked loop PLL). The high-speed clock HSC supplies a clock, count or rate for a register or counter 3 (ST system time) providing a system time or system time base. The clock HSC is usually supplied by an oscillator 5 (OSC) from a quartz 7.

[0028] In an embodiment of the present disclosure, a clock LSC (low speed clock) which is slower than the clock HSC provides a clock, count or rate for increments of a register or counter 9 (RTC real time clock) and supplies a time base or real time clock which is slower than the system time. The low speed clock is also based on an oscillator (OSC) 11 including a quartz 13. The real time clock RTC generally has the function of supplying a count of time in human units (hours, minutes, seconds, etc.), and is therefore different from the system time used to rate the operations performed by the device or system.

[0029] To simplify, Figure 1 Only the system clock and the real-time clock are shown, and the circuits for generating clock signals for rating the different circuits (especially the processor) are not shown, nor are these clock signals.

[0030] The LSC clock is much slower than the HSC clock (the ratio is at least 100, and usually in the order of 1,000). For example, the period of the real-time clock RTC rated by the LSC clock is in the order of tens of microseconds, while the period of the system time rated by the HSC clock is in the order of hundreds of nanoseconds.

[0031] In order to reduce power consumption, the circuit of the device is set to standby or stop power supply in low power consumption or low power consumption mode. To this end, the device usually includes a controller 15 (LPC low power controller) dedicated to low power mode. The controller has the following functions: maintaining operation in low power mode, and controlling the execution of tasks that maintain activity in low power mode at the rate of the real-time clock.

[0032] In an embodiment of the present disclosure, circuits are powered by one or the other of two different domains depending on whether they should maintain activity in low-power mode. Therefore, in a simplified manner, it can be understood that, among the above-mentioned elements, the oscillator 11, the real-time clock counter RTC and the controller 15 are powered by a voltage PVcc that is considered permanent, while the oscillator 5, the system clock counter 3, and the main processing unit 1 are powered by a controllable voltage CVcc. Of course, in reality, the voltage PVcc is also controllable because it is provided by the power supply circuit. However, for the needs of the present disclosure, it is considered permanent because it continues to exist in low-power mode. Other circuits not shown (memory, sensor, actuator, interface, transceiver, peripheral device, etc.) exist in the device or system according to their application and are powered by one and / or the other of the voltages PVcc and CVcc according to their operating mode.

[0033] In most current systems, as long as the system is equipped with an operating system that requires an accurate system time, the oscillator 5 and the clock HSC remain powered to maintain the value of the system time (the value of the counter 3) and more precisely to restore its value upon wake-up (exiting the low power mode), as if the system had not been in the low power mode. To this end, all non-essential functions of the device are switched off, but the active system time is preserved, including during standby. However, in order to further reduce power consumption, it may be advantageous to be able to switch off the oscillator 5 and therefore also the processor 1 in the low power mode.

[0034] For this purpose, a mechanism is provided for the device to be provided for saving and restoring the system time (block 20, system time saving and restoring). Thus, upon entry into low power mode triggered by the operating system and therefore by the system time, the value of counter 3 is saved in a memory associated with the controller 15 (included therein or external thereto). This memory may be a volatile or non-volatile memory. However, in the case of a volatile memory, it is maintained powered by the PVcc domain. The date of entry into low power mode (the value of counter 9) is also saved. Then, upon waking up (exiting low power mode), the difference between the current date and the stored date is calculated and the obtained number is multiplied by the ratio between the clocks HSC and LSC. The obtained value is then added to the saved value of counter 3 to restore the system time as if it had not been stopped.

[0035] If the entry to the low power mode is not too frequent, such as once every hour or every few minutes, or if the system is reset regularly, this mechanism can operate acceptably. In fact, during the reset, the system time is also reset (not the real-time clock, even if the voltage PVcc disappears, the oscillator 11, counter 9 and quartz 13 of the real-time clock are usually powered by a battery). However, in recent systems, it is hoped that the device is placed in low power mode as often as possible to minimize power consumption. For example, it is hoped that the system can be placed in low power mode up to hundreds of times per second. Then, the above mechanism becomes incompatible with the preservation of system time. In fact, the update of the system time when exiting the low power mode can only be performed by multiple cycles of the low-speed clock (only the real-time counter maintains an active state). This will cause the system time to be inaccurate, and each time the low power mode is left, the system time may reach several cycles of the clock HSC. When entering the low power mode is not too frequent, this tolerance or inaccuracy can be considered negligible, but it is no longer the case for frequent entry into the low power mode.

[0036] However, according to one embodiment, it is provided that the high-speed clock HSC is stopped in low-power mode, but the recovery of the system time is synchronized at the edge of the low-speed or real-time clock. Usually, the entry into low-power mode is triggered by the operating system and therefore by the system time. Therefore, not only the recovery of the system time is synchronized on the real-time clock, but also the stop of the system time (the storage value of the counter 3) is synchronized on the real-time clock (at the edge of the clock LSC). Then, the interval between the stop and restart time corresponds to an integer multiple of the real-time counter 9, so that the accuracy of the system time can be maintained.

[0037] What might be considered detrimental is delaying the storage of the system time and thereby delaying the stopping of the high-speed clock and delaying the recovery of the system time until the next or subsequent edge of the low-speed clock. However, this appears to be a negligible effect compared to the gains in power consumption and system time keeping accuracy.

[0038] According to the described embodiment, block 20 is configured by processor 1 to:

[0039] Get and set the system time (read from and write to counter 3);

[0040] Get the real time clock (the value of counter 9);

[0041] is triggered by the controller 15; and

[0042] Receives low speed clock LSC for synchronous operation.

[0043] Figure 1 Some functional links and power supply links between modules and circuits are shown. Thus, circuits 1, 3, 5 and 7 are powered by voltage CVcc, while circuits and blocks 9, 11, 13, 15 and 20 are powered by voltage PVcc. A low speed clock LSC supplied by oscillator 11 sequences circuits and blocks 9, 15 and 20, while a high speed clock HSC supplied by oscillator 5 sequences circuits 1 and 3. The real time clock (the value of counter 9) can be accessed by processor 1, controller 15 and clock management unit / block 20. The system time (the value of counter 3) can be accessed by processor 1 and block 20.

[0044] The system time saving and restoring functions are implemented in software, for example by a program executed by the controller 15. As a variant, a hardware implementation may be provided, for example by a state machine in the wired logic.

[0045] Figure 2 A low power mode management method according to an embodiment is shown. More specifically, Figure 2 Steps implemented by a device during transitions to and from a low power mode are shown.

[0046] FIG. 1 shows a timing diagram according to an embodiment. More precisely, Figure 3 Examples are shown of the shape of the high-speed clock signal HSC, the shape of the system time value ST, the shape of the low-speed clock signal LSC, the value of the real-time clock counter RTC, and the shape of the signal LPR (low power request) for requesting entry into and exiting a low power mode.

[0047] Arbitrarily, it is considered that the counters ST and RTC are incremented on the rising edge of their respective nominal signals HSC and LSC. However, this is a pure convention, and the opposite is of course possible, either on the character of increasing or decreasing, or on the increment / decrement on the rising or falling edge. Similarly, it is arbitrarily assumed that a request to enter a low power mode corresponds to a high state (1) of the entry signal LPR and a request to leave a low power mode corresponds to a low state (0) of the entry signal LPR.

[0048] Assume that at time t1( Figure 3 ), processor 1 requests to enter low power mode (block 31, LPM request, Figure 2 ). This results in a rising edge of the signal LPR and activation of the function 20. The function 20 results in the storage of the values ​​of the counters ST and RTC. However, this storage (block 33, storage of RTC and ST, Figure 2 ) is not immediate, but delayed to the next rising edge of the clock LSC (time t2, Figure 3 ). Therefore, in the example shown, it is assumed that the stored values ​​of counters 3 and 9 are "4" and "2".

[0049] For simplicity, the counter value is relatively small, but in reality, the counter value exceeds several dozen digits and the number represented is much higher. Figure 3 An example is shown where the ratio between the clocks HSC and LSC is relatively small, whereas in reality the ratio is in the hundreds or even thousands. In particular, Figure 3 The representation of the signals HSC and LSC is not proportional to the ratio between these two signals.

[0050] At time t2, when the value is saved, the updating of the system time counter stops due to the stopping of the clock HSC. This corresponds to setting the low power mode of the device (block 35, LPM on, Figure 2 ). From time t2 onwards, only the low power functions are powered and only the real time clock RTC is updated.

[0051] Assume that at time t3( Figure 3 ), the controller 15 receives a request to wake up or leave the low power mode (block 37, wake up request, Figure 2). Time t3 is not synchronous with clock LSC and occurs at any time within its cycle. At time t3, controller 15 causes restart of high speed clock HSC. Starting from time t3, function 20 reads the stored values ​​of counters 3 and 9 and calculates the difference between the saved value of the real time clock and the next expected value ( Figure 3 Function 20 is implemented, for example, by controller 15, which then calculates the interval between two values ​​of the real-time clock to deduce therefrom the number of cycles of clock HSC and, from this, the number of increments of system time that have elapsed since time t2 (block 39, ST calculation, Figure 2 ). At the next rising edge of the clock LSC (time t4, Figure 3 ), function 20 resumes (block 41, resumes ST, Figure 2 ) or force the value of counter 3, and thereby restore or force the value of the system time. In the example shown, it is assumed that the ratio between the clocks HSC and LSC is 4, so the restored value of the system time is "20". From time t4, the device has restarted and maintains this state until the next time it enters low power mode.

[0052] According to one embodiment, the clocks HSC and LSC are not synchronized. If the clock HSC is not stopped, there may be a slight offset between the value of the recovered system time and the value it should have. However, this offset is negligible compared to the offset that would exist without such synchronization.

[0053] According to another embodiment, a hardware mechanism (circuitry) synchronizes the clocks HSC and LSC so that they have zero offset.

[0054] According to one embodiment, function 20 has a software implementation. In this case, the executed program saves the exact values ​​of counters 3 and 9 (time t2) taking into account the clock HSC to enter the low power mode and performs the restoration of the counters of the high speed clock HSC when exiting the low power sequence.

[0055] According to another implementation, a hardware implementation (full or partial) of the clocks LSC and HSC programmed in software and hardware synchronization are provided. For example, the program issues a command to trigger the acquisition of the value of counter 3 at the next edge of the clock LSC, and the acquisition of the counter state is confirmed by the status bit. The saved value is used in software to calculate the interval and store counter 3 at the edge of the clock LSC.

[0056] Whatever implementation mode is chosen, the storage access and reading times of the different counters are preferably taken into account to recover the system time.

[0057] According to a preferred embodiment, the calculation path time is further considered to determine the period of the clock LSC that triggers the restart of the system time and to estimate the system time value to be restored. Therefore, the accuracy is optimized taking into account the different calculation times, that is, it can be reduced to less than one clock HSC period, which is completely negligible in system operation.

[0058] Therefore, the edges entering and exiting the low power mode (times t2 and t4) may not correspond to the edges immediately following times t1 and t3, but may occur later depending on the processing time considered. However, it is easy to estimate this processing time, whether it is limited to the access time between the counter and the memory, or also taking into account the calculation path. In fact, this processing time remains unchanged because it is the same every time.

[0059] An advantage of the described embodiments is that they further reduce power consumption in low power mode relative to conventional devices and systems.

[0060] Another advantage of the described embodiments is that they improve the accuracy with which system time can be recovered at the output of a low power mode.

[0061] A further advantage of the described embodiments is that their implementation in software in existing devices is possible.

[0062] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will be able to conceive of other variations.

[0063] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, the choice between pure software, hybrid or pure hardware implementation depends on the application and the available resources therein.

Claims

1. A method for managing a low power mode of an electronic device, the electronic device comprising a processor, a first counter and a second counter, the method comprising: The first counter is driven by a first oscillator using a first clock; The second counter is driven by a second oscillator using a second clock, wherein the second clock is faster than the first clock; Upon a first request to transition the electronic device to the low power mode: storing the value of the first counter and the value of the second counter at a first edge of the first clock; De-energizing the second counter; as well as deactivating the second oscillator; as well as Upon a second request to transition the electronic device out of the low power mode: activating the second oscillator; energizing the second counter; Calculating the number of cycles of the second clock between a second edge of the first clock and the first edge, the second edge being later than the first edge; as well as Using the calculated value to update the value of the second counter, Wherein entry into the low power mode is triggered by a system time, stopping of the system time is synchronized on the first clock, and restoration of the system time is synchronized on the first clock upon exiting the low power mode. 2 . The method of claim 1 , wherein updating the value of the second counter comprises updating the value of the second counter at an edge of the first clock.

3. The method of claim 1, wherein the first counter is a real-time counter, and wherein the second counter is a system time counter. 4 . The method of claim 3 , wherein the system time counter is used by the processor when the electronic device is not in the low power mode. The method of claim 1 , wherein the first clock is activated in the low power mode, and wherein the second clock is deactivated in the low power mode. The method according to claim 1 , wherein the value of the second counter is updated by a clock management unit. 7 . The method of claim 1 , wherein the processor is disabled in the low power mode while a low power mode controller of the electronic device is activated.

8. The method of claim 1 , wherein calculating the number of cycles of the second clock between the first edge and the second edge of the first clock comprises: Reading a stored value from memory; calculating an interval between the second edge and the first edge based on the number of cycles of the first clock; deriving from the interval a number of cycles of the second clock that have elapsed since the value of the second counter was stored; as well as The value of the second counter is calculated.

9. An electronic device, comprising: processor; Low power controller; a memory associated with the low power controller; a first oscillator configured to drive a first counter using a first clock; a second oscillator configured to drive a second counter using a second clock, wherein the second clock is faster than the first clock; as well as The clock management unit is configured as: Upon a first request for transitioning, by the processor, the electronic device to a low power mode: storing a value of the first counter and a value of the second counter at the memory at a first edge of the first clock; De-energizing the second counter; as well as deactivating the second oscillator; as well as Upon a second request for the low power controller to transition the electronic device out of the low power mode: activating the second oscillator; energizing the second counter; Calculating the number of cycles of the second clock between a second edge of the first clock and the first edge, the second edge being later than the first edge; as well as Using the calculated value to update the value of the second counter, Wherein entry into the low power mode is triggered by a system time, stopping of the system time is synchronized on the first clock, and restoration of the system time is synchronized on the first clock upon exiting the low power mode. 10 . The electronic device of claim 9 , wherein the value of the second counter is updated at an edge of the first clock.

11. The electronic device of claim 9, wherein the first counter is a real-time counter, and wherein the second counter is a system time counter. 12 . The electronic device of claim 11 , wherein the processor is configured to execute based on the system time counter when the electronic device is not in the low power mode. 13 . The electronic device of claim 9 , wherein the first clock is activated in the low power mode, and wherein the second clock is deactivated in the low power mode.

14. The electronic device of claim 9, wherein the processor is deactivated in the low power mode while the low power controller is activated.

15. The electronic device according to claim 9, wherein the clock management unit is configured to: reading a stored value from the memory; calculating an interval between the second edge and the first edge based on the number of cycles of the first clock; deriving from the interval the number of cycles of the second clock that have elapsed since the value of the second counter was stored; and The value of the second counter is calculated.

16. A non-transitory computer-readable storage medium storing a program to be executed by a processor, the program comprising instructions for: The first counter is driven by the first oscillator using the first clock; A second oscillator drives a second counter with a second clock, wherein the second clock is faster than the first clock; Upon a first request to transition an electronic device to a low power mode: storing the value of the first counter and the value of the second counter of the electronic device at a first edge of the first clock; De-energizing the second counter; as well as deactivating the second oscillator; as well as Upon a second request to transition the electronic device out of the low power mode: activating the second oscillator; energizing the second counter; Calculating the number of cycles of the second clock between a second edge of the first clock and the first edge, the second edge being later than the first edge; as well as Using the calculated value to update the value of the second counter, Wherein entry into the low power mode is triggered by a system time, stopping of the system time is synchronized on the first clock, and restoration of the system time is synchronized on the first clock upon exiting the low power mode. 17 . The non-transitory computer-readable storage medium of claim 16 , wherein the first clock is activated in the low power mode, and wherein the second clock is deactivated in the low power mode. 18 . The non-transitory computer-readable storage medium of claim 16 , wherein the processor is deactivated in the low power mode while a low power mode controller of the electronic device is activated.

19. The non-transitory computer-readable storage medium of claim 16, wherein the instructions for calculating the number of cycles of the second clock between the first edge and the second edge of the first clock comprise instructions for: Reading a stored value from memory; calculating an interval between the second edge and the first edge based on the number of cycles of the first clock; deriving from the interval the number of cycles of the second clock that have elapsed since the value of the second counter was stored; and The value of the second counter is calculated.

20. The non-transitory computer-readable storage medium of claim 16, wherein the instructions for updating the value of the second counter include instructions for updating the value of the second counter at an edge of the first clock.

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