A hafnium-based ferroelectric field-effect transistor and its fabrication method

Abstract

This invention relates to a hafnium-based ferroelectric field-effect transistor and its fabrication method. A hafnium-based ferroelectric field-effect transistor includes a silicon substrate; and a gate disposed on the silicon substrate, the gate being separated from the silicon substrate by an interface layer. A source and a drain are respectively disposed on opposite sides of the gate; wherein the interface layer is aluminum oxynitride, and the gate includes a bottom-to-top stacked HZO layer and a titanium nitride layer. This invention solves the problem of poor durability in existing ferroelectric transistors and further enhances the trap density and pyrolysis performance (Pr) by incorporating an HPA process.

Description

Technical Field

[0001] This invention relates to the field of transistors, and in particular to a hafnium-based ferroelectric field-effect transistor and its fabrication method. Background Technology

[0002] Ferroelectric field-effect transistors (FeFETs) offer numerous advantages, such as low power consumption, high speed, and non-destructive readout, making them a promising candidate for next-generation memory devices. Hafnium oxide-based FeFETs, in particular, have attracted significant attention due to their high scalability and CMOS compatibility. However, existing FeFETs suffer from poor durability; for example, Vth and subthreshold swing deteriorate rapidly with increasing program / erase pulse voltage cycles. One contributing factor to this problem is severe degradation of the gate-substrate interface layer (IL).

[0003] Therefore, this invention is proposed. Summary of the Invention

[0004] The main objective of this invention is to provide a hafnium-based ferroelectric field-effect transistor and its fabrication method, which solves the problem of poor durability of existing ferroelectric transistors.

[0005] To achieve the above objectives, the present invention provides the following technical solutions.

[0006] A first aspect of the present invention provides a hafnium-based ferroelectric field-effect transistor, comprising a silicon substrate; and a gate disposed on the silicon substrate, wherein the gate is separated from the silicon substrate by an interface layer, and a source and a drain are respectively disposed on both sides of the gate;

[0007] The interface layer is made of aluminum oxynitride, and the gate comprises an HZO layer and a titanium nitride layer stacked from bottom to top.

[0008] This invention optimizes the material combination for FeFETs, significantly improving device performance, particularly durability. Aluminum oxynitride (ANO) serves as the interface layer, possessing a higher k-value (approximately 9) and a larger ΔEv, thus allowing for a smaller voltage drop and suppressing hole trapping. Furthermore, the nitrogen in ANO enhances thermal stability and inhibits the formation of a sub-interface layer by suppressing the reaction of residual hydroxyl groups with the silicon substrate. Additionally, the combination of the silicon substrate, ANO interface layer, HZO ferroelectric layer, and titanium nitride electrode layer allows for a thinner ferroelectric layer, thereby increasing durability by suppressing bulk charge and promoting device miniaturization.

[0009] A second aspect of the present invention provides one method for fabricating the above-mentioned hafnium-based ferroelectric field-effect transistor, comprising the following steps:

[0010] Provide silicon substrates;

[0011] A stacked structure of aluminum oxynitride layer, HZO layer and titanium nitride layer is sequentially formed on the silicon substrate;

[0012] The stacked structure is patterned to form a gate;

[0013] The silicon substrates on both sides of the gate are doped and annealed to form source and drain regions.

[0014] As described above, this invention utilizes the optimized combination of silicon, aluminum oxynitride layer, HZO layer and titanium nitride layer to improve device durability and promote device miniaturization. Attached Figure Description

[0015] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0016] Figure 1 A schematic diagram of the structure of the hafnium-based ferroelectric field-effect transistor provided by the present invention;

[0017] Figures 2 to 8 The diagram shows the structures obtained in each step of the preparation method provided by this invention. Detailed Implementation

[0018] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0019] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0020] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0021] As described in the background section, existing ferroelectric transistors suffer from poor durability. This invention discovers that by changing the material of the ferroelectric layer and its optimized combination with other layers, this problem can be effectively solved, as detailed below.

[0022] like Figure 1 The hafnium-based ferroelectric field-effect transistor shown includes a silicon substrate and a gate disposed on the silicon substrate. The gate is separated from the silicon substrate by an interface layer 4, and a source 3a and a drain 3b are respectively disposed on both sides of the gate.

[0023] The interface layer 4 is made of aluminum oxynitride, and the gate includes an HZO layer 5 and a titanium nitride layer stacked from bottom to top. The HZO layer 5 (i.e., hafnium oxide-zirconia) is a ferroelectric layer, and the titanium nitride layer is an electrode layer.

[0024] Traditional ferroelectric transistors use silicon oxide as the interface layer. However, due to the low k-value of the parasitic silicon oxide in the silicon channel, a strong electric field exists in the silicon oxide interface layer at the relatively high gate voltage required to achieve ferroelectric polarization switching. This strong electric field induces charge trapping and entrapment, exacerbating silicon oxide degradation and ultimately reducing device durability. The transistor of this invention replaces the traditional silicon oxide interface layer with aluminum oxynitride (Aoxynitride), combining it with a silicon substrate, an HZO layer, and a titanium nitride layer to suppress the aforementioned strong electric field problem. This is because Aoxynitride has a higher k-value (approximately 9) and a larger ΔEv, thus allowing for a smaller voltage drop and suppressing hole trapping. Furthermore, the nitrogen in Aoxynitride enhances thermal stability and can suppress the formation of a sub-interface layer by inhibiting the reaction of residual hydroxyl groups with the silicon substrate. In practical applications, the thickness of the interface layer can be 1.2 nm to 1.5 nm.

[0025] Furthermore, in this invention, the combination of silicon substrate, aluminum oxynitride layer, HZO layer and titanium nitride layer can employ a thinner ferroelectric layer, thereby increasing durability by suppressing bulk charge and promoting device miniaturization.

[0026] In the aforementioned transistor, the structure of the gate electrode—the titanium nitride layer—can be further optimized, consisting of two layers formed using different processes. From bottom to top, these layers comprise a first titanium nitride layer 6 and a second titanium nitride layer 7. The first titanium nitride layer 6 is formed using ALD (Alternating Discharge Machining), while the second titanium nitride layer 7 is formed by sputtering. The first titanium nitride layer 6, formed by ALD, acts as a barrier layer to prevent sputtering damage to the HZO layer and the interface layer (damage reduces durability). Furthermore, the thickness of the first titanium nitride layer 6 can be 3 nm to 5 nm, and the thickness of the second titanium nitride layer 7 can be 80 to 100 nm.

[0027] The silicon substrate used in this invention can be bulk silicon or silicon-on-insulator (SOI), preferably the latter, which includes a backing 1, an insulating layer 2, and a top silicon layer 3. The thickness of the top silicon layer 3 is preferably 30-40 nm to achieve miniaturization.

[0028] In addition, the present invention optimizes the metal contact structure 8 of the source and drain electrodes, which includes a titanium nitride layer 801, a titanium layer 802 and an aluminum layer 803 stacked from bottom to top, which has lower resistance and lower leakage current problem.

[0029] In the above structure, the isolation of each conductive layer is usually achieved using silicon oxide, a typical interlayer dielectric material, but this invention does not impose any particular limitation on this.

[0030] There are many methods for fabricating the transistors provided by this invention. This invention provides one method with a simpler process that can reduce trap density and enhance Pr, specifically including the following steps.

[0031] First, in step S1, taking an SOI substrate as an example, active regions are etched on the top silicon layer 3, such as... Figure 2 As shown.

[0032] Then, depending on the device size requirements, step S2 can be selected to thin the top silicon layer to a thickness of 30nm–40nm, such as… Figure 3 As shown.

[0033] Step S3: An aluminum oxynitride (AlON) layer is formed on the top silicon layer 3 as an interface layer 4, such as... Figure 4 As shown, the formation methods include, but are not limited to, CVD, ALD, LPCVD, RTCVD, or PECVD. The present invention preferably employs the ALD method, for example, using TMA (trimethylaluminum) as the Al precursor and NH3 plasma as the reactant, the thickness of which can be controlled between 1.2 nm and 1.5 nm.

[0034] Step S4, continue forming HZO layer 5 as a ferroelectric layer, such as Figure 5 As shown, the formation methods include, but are not limited to, CVD, ALD, LPCVD, RTCVD, or PECVD. This invention preferably uses the ALD method, for example, through cyclic deposition of HfO2 and ZrO2. This step and step S3 can be deposited in the same ALD chamber, thus simplifying the process. The ferroelectric layer can be controlled to be 4nm–5nm, which is thinner and lighter than existing ferroelectric layers, promoting device miniaturization.

[0035] Step S5: Continue forming a titanium nitride layer as an electrode layer. Typically, the electrode layer is quite thick, and existing technologies generally use sputtering to form it in one step. However, this method has the drawback of sputtering damaging the ferroelectric layer. Therefore, this invention preferably uses the following method to complete the process in two steps.

[0036] In step S501, a first titanium nitride layer is first formed using the ALD method. This layer acts as a barrier, preventing subsequent sputtering from damaging the underlying layer and thus reducing durability. The thickness of the first titanium nitride layer can be controlled between 3 nm and 5 nm.

[0037] In step S502, the remaining electrode, i.e., the second titanium nitride layer, is formed by sputtering. The thickness of this step can be controlled to be 80-100 nm, resulting in the following: Figure 6 The structure shown includes a first titanium nitride layer 6 and a second titanium nitride layer 7.

[0038] Continuing with step S6, the multilayer stacked structure formed on the substrate in step S5 is patterned to form a gate, such as... Figure 7 As shown. This invention does not impose specific limitations on patterning methods, including but not limited to typical electron beam lithography (EBL) and reactive ion etching (RIE).

[0039] Step S7 involves doping the silicon substrates on both sides of the gate. The doping type depends on the substrate doping type and the transistor type. If the substrate is p-doped, then n-type ions (e.g., arsenic) are doped into the source and drain. This step typically uses self-aligned ion implantation.

[0040] Step S8, perform rapid annealing (RTA) to obtain the following result: Figure 8 The structure is shown. This step can simultaneously achieve annealing activation of the source and drain electrodes and induce ferroelectricity in the HZO layer. The preferred annealing conditions are rapid annealing at 450–550°C for 20–40 seconds, for example, rapid annealing at 500–550°C for 30 seconds. In actual processes, targeted optimization can be performed according to actual process conditions and specific performance requirements.

[0041] At this point, the gate and source / drain electrodes are fabricated. Subsequent steps include depositing interlayer dielectric material, etching contact holes, and establishing metal contacts for each electrode. To further improve device performance, this invention proposes a preferred metal contact structure fabrication process, as detailed below.

[0042] Step S9: After annealing in step S8, an interlayer dielectric material such as silicon oxide can be deposited, contact holes can be etched, and metal contact material can be filled into the contact holes. Alternatively, a metal contact structure can be formed first, followed by filling with the interlayer dielectric. This invention does not impose any particular restriction on the order of these steps. However, the preferred method is the metal contact structure 8, which employs a multi-layer stack as shown in the figure, comprising, from bottom to top, a titanium nitride layer 801, a titanium layer 802, and an aluminum layer 803, as shown. Figure 1 As shown (interlayer medium is not shown in the figure).

[0043] In step S10, after forming the metal contact structure 8, high-pressure annealing (HPA) is performed in a mixed atmosphere of argon and hydrogen. This reduces the trap density and enhances Pr. The high-pressure annealing process can be adjusted according to actual conditions, including pressure, annealing temperature, and annealing time. Preferred process conditions are: temperature 400–500°C, pressure 18–22 atm, time 25–35 min, and the preferred volume ratio of argon to hydrogen is 95–97%. More preferred process conditions are: temperature 450°C, pressure 20 atm, time 30 min, and the preferred volume ratio of argon to hydrogen is 96%.

[0044] In summary, this invention improves the device's durability and electrical performance through multiple aspects, including optimization of the interface layer material, optimization of the combination of other layer materials, optimization of the gate electrode layer structure, and optimization of the HPA process, so as to ensure that the device has good read and write capabilities and a low bit error rate during cycling.

[0045] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A hafnium-based ferroelectric field-effect transistor, characterized in that, It includes a silicon substrate; and a gate disposed on the silicon substrate, wherein the gate is separated from the silicon substrate by an interface layer, and a source and a drain are respectively disposed on both sides of the gate; The interface layer is made of aluminum oxynitride, and the gate comprises an HZO layer and a titanium nitride layer stacked from bottom to top. From bottom to top, the titanium nitride layer includes a first titanium nitride layer and a second titanium nitride layer, wherein the first titanium nitride layer is formed by ALD and the second titanium nitride layer is formed by sputtering; And / or, From bottom to top, the titanium nitride layer includes a first titanium nitride layer and a second titanium nitride layer. The thickness of the first titanium nitride layer is 3nm to 5nm, and the thickness of the second titanium nitride layer is 80 to 100nm.

2. The hafnium-based ferroelectric field-effect transistor according to claim 1, characterized in that, The silicon substrate comprises a backing, an insulating layer, and a top silicon layer stacked from bottom to top, wherein the thickness of the top silicon layer is 30–40 nm.

3. The hafnium-based ferroelectric field-effect transistor according to claim 1, characterized in that, The thickness of the interface layer is 1.2 nm to 1.5 nm.

4. The hafnium-based ferroelectric field-effect transistor according to claim 1, characterized in that, The thickness of the HZO layer is 4nm to 5nm.

5. The hafnium-based ferroelectric field-effect transistor according to claim 1, characterized in that, Both the source and drain electrodes are connected to a metal contact structure, which includes a titanium nitride layer, a titanium layer, and an aluminum layer stacked from bottom to top.

6. A method for fabricating a hafnium-based ferroelectric field-effect transistor, characterized in that, Includes the following steps: Provide silicon substrates; A stacked structure of aluminum oxynitride layer, HZO layer and titanium nitride layer is sequentially formed on the silicon substrate; The stacked structure is patterned to form a gate; The silicon substrates on both sides of the gate are doped and annealed to form source and drain regions; From bottom to top, the titanium nitride layer includes a first titanium nitride layer and a second titanium nitride layer. The titanium nitride layer is formed using the following method: First, the first titanium nitride layer is formed using the ALD method, and then the second titanium nitride layer is formed using the sputtering method. And / or, From bottom to top, the titanium nitride layer includes a first titanium nitride layer and a second titanium nitride layer. The thickness of the first titanium nitride layer is 3nm to 5nm, and the thickness of the second titanium nitride layer is 80 to 100nm.

7. The preparation method according to claim 6, characterized in that, The annealing conditions are: rapid annealing at 450-550℃ for 20-40 seconds.

8. The preparation method according to claim 6, characterized in that, The aluminum oxynitride layer is formed using the ALD method; And / or, the HZO layer is formed using the ALD method, and is formed in the same chamber as the aluminum oxynitride layer.

9. The preparation method according to claim 6, characterized in that, The aluminum oxynitride layer was formed using the ALD method, with trimethylaluminum as the aluminum precursor and ammonia as the reactant gas.

10. The preparation method according to claim 6, characterized in that, Also includes: The metal contact structure of the source and drain regions is introduced; The metal contact structure comprises, from bottom to top, a titanium nitride layer, a titanium layer, and an aluminum layer.

11. The preparation method according to claim 10, characterized in that, Following the introduction of the aforementioned metal contact structure, it also includes: High-pressure annealing is carried out in a mixed atmosphere of argon and hydrogen at a temperature of 400–500°C, a pressure of 18–22 atm, and a time of 25–35 min.

12. The preparation method according to claim 11, characterized in that, The volume ratio of argon to hydrogen is 95-97%.

Images