Method for eliminating defects generated during patterning of amorphous silicon mask layer

Abstract

The invention provides a method for eliminating defects generated during patterning of an amorphous silicon mask layer, and the method comprises the steps: 1, providing a substrate, and sequentially forming a titanium nitride mask layer, an oxide mask layer and an amorphous silicon mask layer on the substrate; step 2, forming a mask layer for limiting an ion implantation window on the amorphous silicon mask layer; and step 3, after ion implantation is carried out on the amorphous silicon mask layer, removing the mask layer formed in the step 2 and the part, which is not subjected to ion implantation, of the amorphous silicon mask layer to form a patterned amorphous silicon mask layer. According to the invention, the particle defect problem can be effectively solved, and the product yield is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a method for eliminating defects generated in the process of patterning amorphous silicon mask layer. BACKGROUND

[0002] The prior art adjusts the etching rate of amorphous silicon by wet etching through boron implantation in the amorphous silicon mask layer to complete the patterning of the amorphous silicon mask layer. Before forming the amorphous silicon mask layer on the substrate, a titanium nitride mask layer, a first oxide layer and a second oxide layer are sequentially deposited, wherein the first oxide layer is deposited by atomic layer deposition process. Due to the heavy bombardment of plasma in the atomic layer deposition process, a large number of particles are formed on the surface of the titanium nitride mask layer, and defects such as those shown in Figure 1 are generated in the subsequent process, resulting in yield loss. SUMMARY

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for eliminating defects generated in the process of patterning amorphous silicon mask layer, which solves the problem of the prior art.

[0004] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for eliminating defects generated in the process of patterning amorphous silicon mask layer, comprising:

[0005] Step one, providing a substrate, and sequentially forming a titanium nitride mask layer, an oxide mask layer and an amorphous silicon mask layer on the substrate;

[0006] Step two, forming a mask layer for defining ion implantation window on the amorphous silicon mask layer;

[0007] Step three, after ion implantation on the amorphous silicon mask layer, removing the mask layer formed in step two and the part of the amorphous silicon mask layer which is not implanted by ions, to form a patterned amorphous silicon mask layer.

[0008] Preferably, the oxide mask layer is formed by plasma enhanced chemical vapor deposition process.

[0009] Preferably, the mask layer formed in step two comprises a spin-on dielectric layer, an anti-reflective coating layer and a photoresist layer stacked from bottom to top.

[0010] Preferably, boron is doped in the amorphous silicon mask layer exposed under the ion implantation window by ion implantation.

[0011] Preferably, the mask layer formed in step two and the part of the amorphous silicon mask layer which is not implanted by ions are removed by wet etching.

[0012] Preferably, the etching solution used for removing the mask layer formed in step two by wet etching is SPM solution.

[0013] Preferably, the etching solution used for removing the un-ion implanted part of the amorphous silicon mask layer by wet etching is ammonium hydroxide.

[0014] As described above, the method for eliminating defects generated when patterning the amorphous silicon mask layer provided by the present application has the following beneficial effects: effectively solves the problem of particle defects, and improves product yield. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0016] Figure 1 An electron photo showing the defects generated when patterning the amorphous silicon mask layer by the prior art;

[0017] Figure 2 A flow chart showing the method for eliminating defects generated when patterning the amorphous silicon mask layer provided by the embodiments of the present application;

[0018] Figures 3A-3C A device cross-sectional structure schematic diagram formed after each step in the method for eliminating defects generated when patterning the amorphous silicon mask layer provided by the embodiments of the present application. DETAILED DESCRIPTION

[0019] The embodiments of the present application will be described in detail below through specific, concrete examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the present specification. The present application can also be implemented or applied through other different specific embodiments, and each detail in the present specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0020] The technical solutions in the present application will be described in detail below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0021] In the description of the present application, it should be explained that the orientation or position relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description and cannot be understood as indicating or implying relative importance.

[0022] In the description of the present application, it should be explained that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0023] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict between them.

[0024] Please refer to Figure 2 , which shows the flowchart of the method for eliminating defects generated when the patterned amorphous silicon mask layer is removed.

[0025] As Figure 2 shown, the method for eliminating defects generated when the patterned amorphous silicon mask layer is removed comprises:

[0026] Step one, providing a substrate, sequentially forming a titanium nitride mask layer, an oxide mask layer and an amorphous silicon mask layer on the substrate;

[0027] Step two, forming a mask layer for defining an ion implantation window on the amorphous silicon mask layer;

[0028] Step three, after ion implantation on the amorphous silicon mask layer, removing the mask layer formed in step two and the part of the amorphous silicon mask layer which is not ion implanted, to form a patterned amorphous silicon mask layer.

[0029] In step one, as Figure 3A shown, the substrate 300 can be any suitable substrate material known to those skilled in the art, for example, it can be monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium silicide, etc. III-V compound.

[0030] Different regions of the substrate 300 are formed with various semiconductor devices, such as MOS transistors, diodes, etc., which are not shown in the figure for simplicity.

[0031] An interlayer dielectric layer is formed on the substrate 300, which is not shown in the figure for simplicity. The material of the interlayer dielectric layer is, for example but not limited to, silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxide (i.e., organosilicate) including silicon (Si), carbon (C), oxygen (O), and / or hydrogen (H) atoms, thermoset polyarylene ether, or other low dielectric constant (<3.9) materials.

[0032] As an example, the titanium nitride mask layer 301 and the amorphous silicon mask layer 303 are formed by a deposition process, and the oxide mask layer 302 is formed by a plasma enhanced chemical vapor deposition process. The oxide mask layer 302 is the sum of the thicknesses of the first oxide layer and the second oxide layer in the prior art, which are formed by an atomic layer deposition process and a plasma enhanced chemical vapor deposition process, respectively.

[0033] In step two, as shown in FIG. 3B, a mask layer 306 for defining ion implantation windows 305 is formed on the amorphous silicon mask layer 303. The mask layer 306 includes, from bottom to top, a spin-on dielectric layer (SOC) 306a, an anti-reflective coating layer 306b, and a photoresist layer 306c. Figure 3B

[0034] In step three, as shown in FIG. 3C, boron is implanted into the amorphous silicon mask layer 303 exposed under the ion implantation windows 305 by ion implantation. Then, the mask layer 306 and the un-implanted portion of the amorphous silicon mask layer 303 are removed by wet etching, forming a patterned amorphous silicon mask layer 307. Figure 3C

[0035] As an example, the etchant solution used for removing the mask layer 306 by wet etching is SPM solution (a mixture of sulfuric acid and hydrogen peroxide), and the etchant solution used for removing the un-implanted portion of the amorphous silicon mask layer 303 is ammonium hydroxide.

[0036] ​​The oxide mask layer 302 formed in step one by the plasma enhanced chemical vapor deposition process can avoid the formation of particles on the surface of the titanium nitride mask layer 301. For the prior art, the atomic layer deposition process implemented in step one to form the oxide mask layer 302 causes the titanium nitride mask layer 301 to form a large number of particles on the surface due to heavy bombardment of the plasma; in step two, the formation of the ion implantation window 305 causes over-etching of the amorphous silicon mask layer 303 above the area where the particles are formed, and thus exposes the oxide mask layer 302 below; in step three, the wet etching process corrodes the exposed oxide mask layer 302, causing damage to the titanium nitride mask layer 301, and thus forms the defect as shown in Figure 1

[0037] In summary, the method for eliminating defects generated when the patterned amorphous silicon mask layer is removed can effectively solve the particle defect problem and improve product yield. Therefore, the present application effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0038] It should be noted that the diagrams provided in the present embodiment only schematically illustrate the basic concept of the present application, and thus only the components related to the present application are shown in the diagrams, rather than the number, shape and size of the components when actually implemented. The actual implementation of each component can be arbitrarily changed in terms of shape, number and proportion, and the layout pattern of the components can be more complex.

[0039] The above embodiments only illustratively explain the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea of the present application should be covered by the claims of the present application.​

Claims

1. A method for eliminating defects generated during the patterning of amorphous silicon mask layers, characterized in that, The method includes: Step 1: Provide a substrate, and sequentially form a titanium nitride mask layer, an oxide mask layer, and an amorphous silicon mask layer on the substrate; Step 2: Form a mask layer on the amorphous silicon mask layer to define the ion implantation window; Step 3: After ion implantation of the amorphous silicon mask layer, remove the mask layer formed in step 2 and the un-ion-implanted portion of the amorphous silicon mask layer to form a patterned amorphous silicon mask layer.

2. The method according to claim 1, characterized in that, An oxide mask layer is formed using a plasma-enhanced chemical vapor deposition process.

3. The method according to claim 1, characterized in that, The mask layer formed in step two includes a spin-coated dielectric layer, an anti-reflective coating layer, and a photoresist layer stacked from bottom to top.

4. The method according to claim 1, characterized in that, Boron is doped into the amorphous silicon mask layer exposed under the ion implantation window by ion implantation.

5. The method according to claim 1, characterized in that, The un-ion-implanted portions of the mask layer and amorphous silicon mask layer formed in step two are removed by wet etching.

6. The method according to claim 5, characterized in that, The etching solution used in the wet etching process to remove the mask layer formed in step two is an SPM solution.

7. The method according to claim 5, characterized in that, Ammonium hydroxide is used as the etching solution to remove the un-ion-implanted portions of the amorphous silicon mask layer using wet etching.

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