Processing core circuits and computing chips

Abstract

This disclosure relates to a computational core circuit and a computing chip. One computational core circuit includes an input module configured to receive data blocks, a computational module configured to perform hash operations on the received data blocks, and a clock module. The computational module includes: a first hash engine including a first plurality of computational stages arranged in a pipelined structure such that data signals based on data blocks are sequentially transmitted along the first plurality of computational stages; and a second hash engine including a second plurality of computational stages arranged in a pipelined structure such that data signals received from the first hash engine are sequentially transmitted along the second plurality of computational stages. The clock module is configured to provide clock signals to the first and second hash engines, wherein the transmission direction of the clock signal in the first hash engine is opposite to the transmission direction of the clock signal in the second hash engine.

Description

Technical Field

[0001] This disclosure relates to a computational core circuit for performing hash operations, and more specifically, to a computational core circuit and a computing chip. Background Technology

[0002] The SHA (Secure Hash Algorithm) series of algorithms were released by the National Institute of Standards and Technology (NIST). Among them, the SHA-256 algorithm is a secure hash algorithm with a hash length of 256 bits. Summary of the Invention

[0003] According to a first aspect of this disclosure, a computational core circuit is provided, comprising: an input module configured to receive a data block; a computation module configured to perform a hash operation on the received data block, the computation module including a first hash engine and a second hash engine, the first hash engine including a first plurality of computation stages arranged in a pipelined structure such that a data signal based on the data block is sequentially transmitted along the first plurality of computation stages, the second hash engine including a second plurality of computation stages arranged in a pipelined structure such that a data signal received from the first hash engine is sequentially transmitted along the second plurality of computation stages, wherein each of the first plurality of computation stages and the second plurality of computation stages performs a computation on the data signal received from the preceding computation stage and provides the computationally processed data signal to the following computation stage; and a clock module configured to provide a clock signal to the first hash engine and the second hash engine, wherein the transmission direction of the clock signal in the first hash engine is opposite to the transmission direction of the clock signal in the second hash engine.

[0004] According to a second aspect of this disclosure, a computing chip is provided, including one or more computing core circuits as described above.

[0005] According to a third aspect of this disclosure, a computing chip is provided, including a plurality of computing core circuits as described above, the plurality of computing core circuits being arranged in a plurality of columns, wherein the clock module of each column of computing core circuits receives a clock signal via a common clock channel.

[0006] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0007] The accompanying drawings are for illustrative purposes and are intended only to provide examples of possible structures and arrangements of the inventive apparatus disclosed herein and methods of applying it to computing devices. These drawings are in no way intended to limit any changes in form and detail that may be made to the embodiments by those skilled in the art without departing from the spirit and scope of the embodiments. The embodiments will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings, wherein similar reference numerals denote similar structural elements.

[0008] Figures 1 to 4 This is a schematic diagram of a computational core circuit according to some embodiments of the present disclosure.

[0009] Figures 5A to 5C This is a schematic diagram of a computational core circuit according to some other embodiments of the present disclosure.

[0010] Figures 6A to 6D This is a schematic diagram of an operational core circuit with a vertical structure according to some embodiments of the present disclosure.

[0011] Figure 7 This is a schematic diagram of a computing chip according to some embodiments of the present disclosure.

[0012] Figure 8A This is a schematic diagram of a computing chip according to other embodiments of the present disclosure.

[0013] Figure 8B This is a schematic diagram of a computing chip including an arithmetic core circuit with a vertical structure, according to other embodiments of the present disclosure.

[0014] Figure 8C It is used to Figure 8B The diagram shows a schematic layout of the clock signal distribution for the vertically structured arithmetic core circuit in a computing chip.

[0015] Figures 9A to 9C This is a schematic diagram of a computing chip according to other embodiments of the present disclosure.

[0016] Figure 9D It is used to Figure 9C The diagram shows a schematic layout of the clock signal distribution for the arithmetic core circuit in the computing chip.

[0017] Figure 9E This is a schematic diagram of a computing chip including an arithmetic core circuit with a vertical structure, according to other embodiments of the present disclosure.

[0018] Figure 9F It is used to... Figure 9E The diagram shows a schematic layout of the clock signal distribution for the vertically structured arithmetic core circuit in a computing chip.

[0019] Figure 9GThis is a schematic arrangement diagram for distributing clock signals to the arithmetic core circuitry in a computing chip according to other embodiments of the present disclosure.

[0020] Figure 10 This is a schematic diagram of an exemplary pipeline structure for executing the SHA-256 algorithm.

[0021] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0022] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0023] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0024] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. That is, the hash engines described herein are shown in an exemplary manner to illustrate different embodiments of the circuitry in this disclosure and are not intended to be limiting. Those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement the invention, and not exhaustive ways.

[0025] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0026] Computing chips typically include a top-level module and a computational core circuit. The top-level module performs communication, control, input / output (I / O), and clock / PLL functions. The computational core circuit performs the core computational operations. The computational core circuit receives the computational tasks from the top-level module and feeds the results back to it. For double hashing, a complete computation typically requires two rounds of 64 iterations (executing the SHA-256 algorithm twice), or 128 computation cycles. Some optimization methods can reduce this by a few cycles (e.g., 6 cycles). In the embodiments according to this disclosure, the example of the computational core circuit performing two SHA-256 algorithm operations (i.e., 128 cycles) is used for illustration; however, those skilled in the art will understand that this disclosure is not limited to this and can be applied to computations with any number of cycles. The SHA-256 algorithm mentioned herein includes any known version of the SHA-256 algorithm and its variations and modifications.

[0027] In this disclosure, in order to improve computational throughput, the computational core circuit can be configured to have multiple computational stages arranged in a pipelined structure. Figure 10 The diagram illustrates an exemplary pipeline structure for executing the SHA-256 algorithm. This pipeline includes 64 operation stages, each with eight compressed registers (AH) and 16 extended registers (0-15). The first operation stage receives an input data block, divides it into eight 32-bit data segments, stores each segment in a compressed register (AH), processes the data, and provides the result to the second operation stage. Each operation stage then processes the result received from the previous stage and provides its result to the next stage. Finally, after processing through 64 operation stages, the core circuit outputs the hash result of the SHA-256 algorithm applied to the input data block. Thus, when all operation stages in the pipeline are fully loaded (i.e., all operation stages are receiving and processing data), the core circuit can output a result per clock cycle, significantly improving throughput.

[0028] As a non-limiting example, a computing chip core circuit that needs to perform the SHA-256 algorithm twice would require a total of 128 operation stages. The core circuit could include two hash engines, each with 64 operation stages configured to perform the SHA-256 algorithm. Each hash engine could, for example, have... Figure 10 The configuration shown is as described. It is understood that this disclosure does not impose any particular restrictions on the hash algorithm executed by the hash engine. The hash engine of the computing core circuit can actually be used to execute any hash algorithm now known or developed in the future (not limited to the SHA series of algorithms), and may accordingly include a corresponding number of computing stages.

[0029] When designing an arithmetic core circuit according to a pipelined architecture, a clock signal needs to be provided to each arithmetic stage in the pipeline. In one case, the clock signal propagation direction in the arithmetic core circuit can be the same as the data signal propagation direction in the pipeline (forward clock structure), i.e., from the first arithmetic stage to the last. In this case, the clock cycle can be shorter, and the chip frequency can be faster, achieving higher performance. However, in this case, the hold time of the registers at each arithmetic stage in the pipeline is not easily met, and the chip may not function properly. In another case, the clock signal propagation direction in the arithmetic core circuit can be opposite to the data signal propagation direction in the pipeline (reverse clock structure), i.e., from the last arithmetic stage to the first. In this case, it is easier to meet the hold time of the registers at each arithmetic stage in the pipeline, allowing data to be stably written to the registers. However, in this case, the chip frequency is sacrificed, leading to a decrease in chip performance. Furthermore, in both cases, the clock signal needs to traverse every operational stage in the pipeline of the arithmetic core circuit, typically reaching up to 128 stages. However, the further the clock signal propagates, the greater the distortion of its rising and / or falling edges, leading to a deterioration in the clock signal's shape and a worse duty cycle. When the clock signal propagates downstream of the pipeline (e.g., stage 128) or upstream (e.g., stage 1) in the opposite direction to the data signal propagation, the clock signal level may no longer meet the minimum pulse requirement of the registers in the current operational stage, severely degrading performance.

[0030] In the arithmetic core circuit according to embodiments of the present disclosure, one hash engine is configured as a forward clock structure and the other hash engine is configured as a reverse clock structure, resulting in a hybrid clock structure for the entire arithmetic core circuit, where the clock signals in the two hash engines of the arithmetic core circuit propagate in different directions. This configuration not only combines the advantages of forward and reverse clock structures, seeking to maintain a balance between time and chip frequency, but also significantly reduces the number of arithmetic stages through which the clock signal needs to be transmitted. This significantly improves the shape of the clock signal at each arithmetic stage, thereby advantageously enhancing the performance of the arithmetic core circuit and thus the entire computing chip.

[0031] The operational core circuit according to embodiments of the present disclosure is described in detail below with reference to the accompanying drawings. In these drawings, dashed arrows indicate the direction of data signal transmission, and solid arrows indicate the direction of clock signal transmission. It should be noted that the actual operational core circuit may also include additional components, but to avoid obscuring the key points of the present disclosure, these additional components are not shown in the drawings and are not discussed in this disclosure.

[0032] Figure 1 A computational core circuit 100A according to an embodiment of the present disclosure is schematically illustrated. The computational core circuit 100A may include an input module 110, a computation module 120, and a clock module 140. The input module 110 may be configured to receive data blocks. The computation module 120 may be configured to perform hash operations on the received data blocks. The clock module 140 may be configured to provide the required clock signal to the computation module 120.

[0033] like Figure 1 As shown, the computation module 120 includes a first hash engine 121 and a second hash engine 122. The first hash engine 121 includes a first plurality of computation stages 121-1, ..., 121-i, ..., 121-64. The computation stages 121-1, ..., 121-i, ..., 121-64 are arranged in a pipelined structure, such that data signals based on received data blocks are sequentially transmitted along the computation stages 121-1, ..., 121-i, ..., 121-64. The second hash engine 122 includes a second plurality of computation stages 122-1, ..., 122-i, ..., 122-64. The computation stages 122-1, ..., 122-i, ..., 122-64 are arranged in a pipelined structure, such that data signals received from the first hash engine 121 are sequentially transmitted along the computation stages 122-1, ..., 122-i, ..., 122-64. Each operation level in operation levels 121-1, ..., 121-i, ..., 121-64, 122-1, ..., 122-i, ..., 122-64 performs operations on the data signals received from the previous operation level and provides the data signals processed by that operation level to the next operation level. In some examples, refer to... Figure 10 The exemplary pipelined structure configured the operation stages in the hash engine can also be configured according to other pipelined structures known in the art or developed hereafter. It should be understood that although the first hash engine 121 and the second hash engine 122 are depicted in the figures as each comprising 64 operation stages, as mentioned above, this document merely uses a hash engine for performing the SHA-256 algorithm as a non-limiting example. The operation core circuitry and hash engine according to this disclosure can actually be applied to perform any hash algorithm now known or developed hereafter (not limited to the SHA family of algorithms), and accordingly may include a suitable number of operation stages.

[0034] Clock module 140 is configured to provide clock signals to the first hash engine 121 and the second hash engine 122, such that the propagation direction of the clock signal in the first hash engine 121 is opposite to the propagation direction of the clock signal in the second hash engine 122. Thus, the clock signal does not need to traverse the first hash engine 121 and then the second hash engine 122 (forward clock structure) or traverse the second hash engine 122 and then the first hash engine 121 (reverse clock structure), but only needs to traverse the first hash engine 121 and the second hash engine 122 respectively, halving the number of computation stages required for the clock signal compared to the forward or reverse clock structure. Since the data signal propagates in the first hash engine 121 and the second hash engine 122 in the same direction, while the clock signal propagates in opposite directions, the clock structure of the computation core circuit according to this disclosure can be called a hybrid clock structure.

[0035] In some embodiments, the transmission direction of the clock signal in the first hash engine 121 may be opposite to the transmission direction of the data signal, and the transmission direction of the clock signal in the second hash engine 122 may be the same as the transmission direction of the data signal.

[0036] For example, such as Figure 1 As shown, in the arithmetic core circuit 100A, the clock signal provided by the clock module 140 to the first hash engine 121 is transmitted from arithmetic stage 121-64 to arithmetic stage 121-1, while the clock signal provided by the clock module 140 to the second hash engine 122 is transmitted from arithmetic stage 122-1 to arithmetic stage 122-64. Thus, the clock signal propagates from the center of the arithmetic core circuit outwards to both sides, reaching a maximum distance of only 64 arithmetic stages, greatly improving the worst-case clock shape.

[0037] In some embodiments, the arithmetic core circuit according to this disclosure may also be provided with a synchronous first-in-first-out (FIFO) module in the first hash engine 121 and the second hash engine 122 for transmitting data signals between arithmetic stages 121-64 and 122-1. A synchronous FIFO is a FIFO design in which read and write operations on the FIFO buffer are performed within the same clock domain; that is, data values ​​are written to the FIFO buffer from one clock domain and read from the same FIFO buffer from the same clock domain.

[0038] Figure 2A computational core circuit 100B with a synchronous FIFO module according to the present disclosure is shown. Compared to the computational core circuit 100A, the computational core circuit 100B further includes a synchronous FIFO module 150 disposed between the last computational stage 121-64 of the first hash engine 121 and the first computational stage 122-1 of the second hash engine 122. The synchronous FIFO module 150 is configured to receive data signals output from the last computational stage 121-64 of the first hash engine 121 using a clock signal provided by a clock module 140, and to output the received data signals to the first computational stage 122-1 of the second hash engine 122 using the clock signal provided by the clock module 140. The clock module 140 is also configured to provide a clock signal to the synchronous FIFO module 150. In the arithmetic core circuit 100B, the clock signal provided by the clock module 140 to the first hash engine 121 is transmitted from arithmetic stage 121-64 to arithmetic stage 121-1, while the clock signal provided by the clock module 140 to the second hash engine 122 is transmitted from arithmetic stage 122-1 to arithmetic stage 122-64. The clock signal is transmitted a maximum of 64 arithmetic stages. The introduction of the synchronous FIFO module 150 does not affect the processing speed and throughput of the entire arithmetic core circuit, because the transmission time of the data signal between the synchronous FIFO module 150 and the arithmetic stage will not exceed the transmission time between arithmetic stages.

[0039] The introduction of the synchronous FIFO module also brings additional benefits. Typically, the arithmetic core circuitry can be implemented on a semiconductor chip (e.g., a silicon chip). All arithmetic stages of the pipeline structure are usually arranged in the same row, with the first hash engine and the second hash engine adjacent to each other in the horizontal direction. The horizontal direction referred to here can be the direction of extension of the pipeline structure, i.e., the direction of data signal transmission. In some embodiments, the first hash engine and the second hash engine can also be arranged in two different rows along the surface of the semiconductor chip, thus being adjacent to each other in the vertical direction perpendicular to the horizontal direction. An arithmetic core circuitry with such an arrangement of first and second hash engines can be referred to herein as an arithmetic core circuitry with a vertical structure. An arithmetic core circuitry with a vertical structure can have a more suitable (e.g., closer to a square) aspect ratio, thus facilitating the flexible arrangement of such arithmetic core circuitry on a computing chip. In such cases, it is more convenient to cut more typically rectangular chips from the typically circular silicon wafer. However, for vertically structured arithmetic core circuits, the distance the data signal needs to travel between the last operation stage of the first hash engine and the first operation stage of the second hash engine is greater than the distance traveled between two adjacent operation stages within the hash engine. This results in a longer data signal transmission time between these two operation stages compared to the time between adjacent operation stages within the hash engine, potentially limiting the processing speed and throughput of the arithmetic core circuit. However, the synchronous FIFO module has a relaxed timing, which can help shorten the data signal transmission time from the last operation stage of the first hash engine to the first operation stage of the second hash engine in a vertical structure. This improves the performance of vertically structured arithmetic core circuits, allowing them to offer advantages without degrading processing speed and throughput.

[0040] Figure 6A and Figure 6B This is a schematic diagram of a circuit including a synchronous FIFO module and a first hash engine and a second hash engine that are vertically adjacent to each other, according to an embodiment of the present disclosure. Figure 6A As shown, the first hash engine 221 and the second hash engine 222 of the arithmetic core circuit 200A are vertically adjacent to each other. The data signal travels from the first hash engine 221 to the second hash engine 222 via the synchronous FIFO module 250. The clock signal in the first hash engine 221 travels in the opposite direction to the data signal, while the clock signal in the second hash engine 222 travels in the same direction as the data signal. Figure 6BAs shown, the first hash engine 221 and the second hash engine 222 of the arithmetic core circuit 200B are vertically adjacent to each other. Data signals travel from the first hash engine 221 to the second hash engine 222 via the synchronization FIFO module 250. The clock signal in the second hash engine 222 travels in the opposite direction to the data signal, while the clock signal in the first hash engine 221 travels in the same direction as the data signal. The relative vertical positions of the first hash engine 221 and the second hash engine 222 depicted in the figures are merely exemplary and not limiting; their relative vertical positions can be reversed as needed.

[0041] In other embodiments, the arithmetic core circuit according to this disclosure may also include asynchronous first-in-first-out (FIFO) modules in the first hash engine 121 and the second hash engine 122 for transmitting data signals between arithmetic stages 121-64 and 122-1. An asynchronous FIFO is a FIFO design in which data values ​​are written to a FIFO buffer from one clock domain and read from the same FIFO buffer from another clock domain, with the two clock domains being asynchronous to each other. An asynchronous FIFO can be used to safely transfer data from one clock domain to another.

[0042] Figure 3 A computational core circuit 100C with an asynchronous FIFO module according to the present disclosure is shown. Compared to the computational core circuit 100A, the computational core circuit 100C further includes an asynchronous FIFO module 130 disposed between the last computational stage 121-64 of the first hash engine 121 and the first computational stage 122-1 of the second hash engine 122. The asynchronous FIFO module 130 is configured to receive a data signal output from the last computational stage 121-64 of the first hash engine 121 using a first clock signal and to output the received data signal to the first computational stage 122-1 of the second hash engine 122 using a second clock signal different from the first clock signal. The computational core circuit 100C includes a first clock module 141 and a second clock module 142. The first clock module 141 is configured to provide a first clock signal to the first hash engine 121 and the asynchronous FIFO module 130, and the second clock module 142 is configured to provide a second clock signal to the second hash engine 122 and the asynchronous FIFO module 130, wherein the first clock signal and the second clock signal have the same frequency. The introduction of the asynchronous FIFO module 130 will not affect the processing speed and throughput of the entire arithmetic core circuit, because the transmission time of the data signal between the asynchronous FIFO module 130 and the arithmetic stage will not exceed the transmission time between the arithmetic stages.

[0043] In some embodiments, the first clock signal and the data signal may be transmitted in the same direction, and the second clock signal and the data signal may be transmitted in opposite directions. For example... Figure 3 As shown, the data signal propagates from left to right through all the operation stages of the operation module 120, while the first clock signal propagates from left to right within the first hash engine 121 (from operation stage 121-1 to 121-64), and the second clock signal propagates from right to left within the second hash engine 122 (from operation stage 122-64 to 122-1).

[0044] In other embodiments, the transmission directions of the first clock signal and the data signal may be opposite, and the transmission directions of the second clock signal and the data signal may be the same. For example... Figure 4 As shown, compared to the arithmetic core circuit 100C, the data signal in the arithmetic core circuit 100D still propagates from left to right through all arithmetic stages of the arithmetic module 120, but the first clock signal propagates from right to left within the first hash engine 121 (from arithmetic stage 121-64 to 121-1), and the second clock signal propagates from left to right within the second hash engine 122 (from arithmetic stage 122-1 to 122-64).

[0045] In some embodiments, the first clock module 141 and the second clock module 142 can be configured to receive clock signals from the same clock source located outside the arithmetic core circuitry. The clock source can be used to provide a basic clock signal. That is, the first clock signal and the second clock signal can be from the same source, but they travel different paths from the clock source to reach the respective clock modules.

[0046] The introduction of asynchronous FIFO modules also brings additional benefits. Similar to synchronous FIFO modules, asynchronous FIFO modules can also help shorten the transmission time of data signals from the last operation stage of the first hash engine to the first operation stage of the second hash engine in a vertical structure, thereby improving the performance of the operation core circuit with a vertical structure. Figure 6C and Figure 6D This is a schematic diagram of a circuit comprising an asynchronous FIFO module and a first hash engine and a second hash engine that are vertically adjacent to each other, according to an embodiment of the present disclosure. Figure 6C As shown, the first hash engine 221 and the second hash engine 222 of the arithmetic core circuit 200C are vertically adjacent to each other. The data signal travels from the first hash engine 221 to the second hash engine 222 via the asynchronous FIFO module 230. The first clock signal and the data signal are transmitted in the same direction, while the second clock signal and the data signal are transmitted in opposite directions. Figure 6DAs shown, the first hash engine 221 and the second hash engine 222 of the computing core circuit 200D are vertically adjacent to each other. The data signal travels from the first hash engine 221 to the second hash engine 222 via the asynchronous FIFO module 230. The second clock signal and the data signal are transmitted in the same direction, while the first clock signal and the data signal are transmitted in opposite directions. The relative vertical positions of the first hash engine 221 and the second hash engine 222 depicted in the figure are merely exemplary and not limiting.

[0047] In some embodiments, the first hash engine 121 or the second hash engine 122 may further include one or more asynchronous FIFO modules, which may be inserted between the operation stages. This further reduces the number of operation stages that each clock signal needs to pass through. The insertion of these asynchronous FIFO modules allows the operation stages in each hash engine to be divided into multiple groups; in some embodiments, each group may contain the same number of operation stages. Figures 5A to 5C An example of a computational core circuit with an additional asynchronous FIFO module set in the first hash engine 121 and the second hash engine 122 is shown.

[0048] like Figure 5A As shown, the arithmetic core circuit 100A' further includes a second asynchronous FIFO module 132 compared to the arithmetic core circuit 100A. The second asynchronous FIFO module 132 is disposed between adjacent first arithmetic stages 121-a and 121-b in the first plurality of arithmetic stages of the first hash engine 121, with the first arithmetic stage 121-a preceding the second arithmetic stage 121-b. The second asynchronous FIFO module 132 is configured to receive the data signal output from the first arithmetic stage 121-a using a third clock signal different from the clock signal provided by the clock module 140, and to output the received data signal to the second arithmetic stage 121-b using the clock signal provided by the clock module 140. The arithmetic core circuit 100A' also includes a third clock module 143, which is configured to provide a third clock signal to the second asynchronous FIFO module 132 and to the first arithmetic stage 121-a and the arithmetic stages preceding the first arithmetic stage 121-a in the first plurality of arithmetic stages of the first hash engine 121. Clock module 140 is also configured to provide clock signals to the second asynchronous FIFO module 132 and to the first plurality of operational stages following the second operational stage 121-b and the first hash engine 121.

[0049] Additionally or alternatively, the arithmetic core circuit 100A' further includes a third asynchronous FIFO module 133. The third asynchronous FIFO module 133 is disposed between adjacent third operational stage 122-c and fourth operational stage 122-d in the second plurality of operational stages of the second hash engine 122, with third operational stage 122-c preceding fourth operational stage 122-d. The third asynchronous FIFO module 133 is configured to receive a data signal output from third operational stage 122-c using a clock signal provided by clock module 140 and to output the received data signal to fourth operational stage 122-d using a fourth clock signal different from the clock signal provided by clock module 140. The arithmetic core circuit 100A' further includes a fourth clock module 144, which is configured to provide a fourth clock signal to the third asynchronous FIFO module 133 and to the fourth operational stage 122-d and the operational stages following fourth operational stage 122-d in the second plurality of operational stages of the second hash engine 122. Clock module 140 is also configured to provide clock signals to the third asynchronous FIFO module 133 and to the third operation level 122-c and the second hash engine 122, in the second plurality of operation levels preceding the third operation level 122-c.

[0050] like Figure 5B As shown, similarly, the operation core circuit 100B' may also include a second asynchronous FIFO module 132, a third clock module 143 and / or a third asynchronous FIFO module 133 and a fourth clock module 144 compared to the operation core circuit 100B.

[0051] like Figure 5CAs shown, the arithmetic core circuit 100C' may further include a second asynchronous FIFO module 132 compared to the arithmetic core circuit 100C. The second asynchronous FIFO module 132 is disposed between adjacent first arithmetic stages 121-a and second arithmetic stages 121-b in the first plurality of arithmetic stages of the first hash engine 121, with the first arithmetic stage 121-a preceding the second arithmetic stage 121-b. The second asynchronous FIFO module 132 is configured to receive data signals output from the first arithmetic stage 121-a using a third clock signal different from the first clock signal provided by the first clock module 141, and to output the received data signals to the second arithmetic stage 121-b using the first clock signal provided by the first clock module 141. The arithmetic core circuit 100C' also includes a third clock module 143, which is configured to provide a third clock signal to the second asynchronous FIFO module 132 and to the first arithmetic stage 121-a and the arithmetic stages preceding the first arithmetic stage 121-a in the first plurality of arithmetic stages of the first hash engine 121. The first clock module 141 is configured to provide a first clock signal to the first asynchronous FIFO module 130 and the second asynchronous FIFO module 132, and to the first plurality of operational stages of the second operational stage 121-b and the first hash engine 121, in the operational stage following the second operational stage 121-b.

[0052] Additionally or alternatively, the arithmetic core circuit 100C' may further include a third asynchronous FIFO module 133. The third asynchronous FIFO module 133 is disposed between adjacent third operational stage 122-c and fourth operational stage 122-d in the second plurality of operational stages of the second hash engine 122, with third operational stage 122-c preceding fourth operational stage 122-d. The third asynchronous FIFO module 133 is configured to receive a data signal output from the third operational stage 122-c using a second clock signal provided by the second clock module 142, and to output the received data signal to the fourth operational stage 122-d using a fourth clock signal different from the second clock signal provided by the second clock module 142. The arithmetic core circuit 100C' may further include a fourth clock module 144, which is configured to provide a fourth clock signal to the third asynchronous FIFO module 133 and to the fourth operational stage 122-d and the operational stages following the fourth operational stage 122-d in the second plurality of operational stages of the second hash engine 122. The second clock module 142 is configured to provide a second clock signal to the first asynchronous FIFO module 130 and the third asynchronous FIFO module 133, and to the third operation level 122-c and the second hash engine 122, in the second plurality of operation levels preceding the third operation level 122-c.

[0053] For example, the second asynchronous FIFO module 132 can be set between the 32nd and 33rd operation stages of the first hash engine 121, and the third asynchronous FIFO module 133 can be set between the 32nd and 33rd operation stages of the second hash engine 122, so that each clock signal is transmitted to a maximum of 32 operation stages, thereby further optimizing the shape of the clock signal at each operation stage.

[0054] Those skilled in the art will understand that, although Figures 5A to 5C The example shown includes an asynchronous FIFO module within each hash engine; however, this is merely a non-limiting example, and the number and location of asynchronous FIFO modules within the hash engine can be reasonably configured according to actual needs. It should also be understood that, based on the number and location of synchronous and asynchronous FIFO modules within the hash engine, appropriate clock modules can be configured to provide clock signals to each computational stage and each FIFO module within the hash engine. This is as long as the clock signal direction within each hash engine is consistent, but the clock signal directions of different hash engines are opposite, and the same clock signal is provided to the synchronous FIFO module while different clock signals are provided to the asynchronous FIFO module. Figures 5A to 5C The examples shown are merely a few and are not intended to limit this disclosure.

[0055] This disclosure also provides a computing chip that includes one or more computing core circuits as described in any of the above embodiments.

[0056] The following is combined Figure 7 A computing chip 700 according to some embodiments of the present disclosure is described. The computing chip 700 may include a top-level module 710 and a plurality of arithmetic core circuits 720 having a hybrid clock structure as described above. As a non-limiting example, in Figure 7 In the depicted embodiment, the arithmetic core circuit 720 is shown as having Figure 1 The structure shown.

[0057] like Figure 7 As shown, the top-level module 710 includes a clock source 711. The clock source 711 is configured to provide a clock signal to the arithmetic core circuitry 720 of the computing chip 700. The arithmetic core circuitry 720 is arranged in multiple columns 720-1, 720-2, 720-3, and 720-4, with the clock module of each column receiving the clock signal via a common clock channel. For example, the clock modules of the arithmetic core circuitry in columns 720-1, 720-2, 720-3, and 720-4 receive clock signals via clock channels 731, 732, 733, and 734, respectively. Figure 7 In the illustrated arithmetic core circuit, the two hash engines are depicted arranged in the same row. When the arithmetic core circuit has a vertical structure, the clock channel can also be shared between arithmetic core circuits in adjacent columns.

[0058] Although not specifically illustrated, it is understood that when the hash engine of the arithmetic core circuit 720 has the additional asynchronous FIFO module as described above, an additional clock channel can also be set so that the corresponding clock modules of the arithmetic core circuits 720 in the same column, which are added due to the addition of the asynchronous FIFO module, can also receive clock signals through a common clock channel.

[0059] It should be understood that although the computing chip in the illustrated example includes four columns and four rows of arithmetic core circuits, this is merely exemplary and not restrictive, and any suitable number of arithmetic core circuits can be arranged in any suitable number of columns as appropriate.

[0060] Figure 8A The computing chip 800A compared to Figure 7 The difference between the computing chip 700 and the computing chip 800A is that the computing core circuit 820 also has a synchronous FIFO module (illustrated by the rectangle filled with a left diagonal line in the figure), for example, it can have such Figure 2 The structure shown. In such an embodiment, the clock modules of the arithmetic core circuits in each column 820-1, 820-2, 820-3, and 820-4 can still receive clock signals via clock channels 731, 732, 733, and 734, respectively.

[0061] When the arithmetic core circuit has a vertical structure, clock channels can be shared between adjacent columns of arithmetic core circuits. For example... Figure 8B As shown, the difference between computing chip 800B and computing chip 800A lies in that the computing core circuit 820' of computing chip 800B has a first hash engine and a second hash engine that are vertically adjacent to each other. In the accompanying drawings of this disclosure, SF represents a synchronous FIFO module, ASF represents an asynchronous FIFO module, H1 represents the first hash engine, and H2 represents the second hash engine.

[0062] The multiple columns of arithmetic core circuits may include first and second columns of arithmetic core circuits (e.g., 820-1′ and 820-2′) arranged adjacent to each other in the stated order. In some embodiments, the clock modules of the first column of arithmetic core circuits 820-1′ and the clock modules of the second column of arithmetic core circuits 820-2′ receive clock signals via a common clock channel 831. The computing chip may also include multiple pairs of such first and second column arithmetic core circuits, each pair of which can receive clock signals via a common clock channel. For example, columns 820-3′ and 820-4′ of computing chip 800B also receive clock signals via a common clock channel 832.

[0063] It should be understood that, although in Figure 8BThe synchronous FIFO module is positioned to the left of hash engines H1 and H2, but this is merely exemplary and not restrictive; for example, Figure 8C As shown, the synchronous FIFO module of the arithmetic core circuit can be arranged on either side of the hash engine H1 and H2. Furthermore, regardless of whether the arrangement of the corresponding arithmetic core circuits in adjacent columns of arithmetic core circuits with respect to the synchronous FIFO module is the same or opposite, the hybrid clock structure of this disclosure can be achieved. In practice, the position of the synchronous FIFO module in each arithmetic core circuit relative to the hash engine can be reasonably set according to the actual situation, and it is not necessarily required that the arrangement of each arithmetic core circuit or each column of arithmetic core circuits in the computing chip be the same.

[0064] It should also be understood that, although in Figure 8B H1 is depicted as being above H2, but the vertical relative positions of hash engines H1 and H2 are not particularly restricted, and the hybrid clock structure of this disclosure can be implemented regardless of whether H1 is above H2 or H2 is above H1. In practice, the vertical relative positions of hash engines H1 and H2 in each arithmetic core circuit can be reasonably set according to the actual situation, and it is not necessarily required that the arrangement of each arithmetic core circuit or each column of arithmetic core circuits in the computing chip be the same.

[0065] Figure 9A The computing chip 900A compared to Figure 7 The difference between the computing chip 700 and the computing chip 900A is that the computing core circuit 920A also has an asynchronous FIFO module (illustrated by the rectangle filled with a right diagonal line in the figure), for example, it can have... Figure 4 The structure is shown. In such an embodiment, the first clock module of the arithmetic core circuit in each column 920A-1, 920A-2, 920A-3, and 920A-4 receives a first clock signal via a common clock channel, and the second clock module receives a second clock signal via a common clock channel. For example, in column 920A-1, one of the first clock module and the second clock module of the arithmetic core circuit receives the first clock signal via a common clock channel 931, and the other receives the second clock signal via a common clock channel 932.

[0066] Figure 9B The difference between the computing chip 900B and the computing chip 900A lies in the fact that the computing core circuit of the computing chip 900A, 920B, can have, for example, such as Figure 3The structure is shown. In such an embodiment, the first clock module of the arithmetic core circuit in each column 920B-1, 920B-2, 920B-3, and 920B-4 receives a first clock signal via a common clock channel, and the second clock module receives a second clock signal via a common clock channel. For example, in column 920B-1, one of the first clock module and the second clock module of the arithmetic core circuit receives the first clock signal via a common clock channel 931', and the other receives the second clock signal via a common clock channel 932'.

[0067] for Figure 9B The illustrated embodiment can be further modified to share a clock channel between adjacent columns. Multiple columns 920B-1, 920B-2, 920B-3, and 920B-4 include first and second column arithmetic core circuits (e.g., 920B-1, 920B-2) arranged adjacent to each other in the stated order. In some embodiments, one of the first and second clock modules of the first column arithmetic core circuit and one of the first and second clock modules of the second column arithmetic core circuit can receive clock signals via a common clock channel. In some embodiments, in addition to the first and second column arithmetic core circuits, the multiple columns also include a third column arithmetic core circuit (e.g., 920B-3) adjacent to the second column arithmetic core circuit relative to the first column arithmetic core circuit. Another of the first and second clock modules of the second column arithmetic core circuit and one of the first and second clock modules of the third column arithmetic core circuit can receive clock signals via a common clock channel.

[0068] For example, Figure 9C The difference between the 900B' computing chip and the 900B chip lies in the fact that adjacent columns of arithmetic core circuits share a clock channel. For example... Figure 9C As shown, column 920B-1 and column 920B-2 share clock channel 934, column 920B-2 and column 920B-3 share clock channel 935, and column 920B-3 and column 920B-4 share clock channel 936. In addition, column 920B-1 also has a separate clock channel 933, and column 920B-4 also has a separate clock channel 937. Figure 9C The document does not specify how the 920B arithmetic core circuitry is arranged within the computing chip. In fact, the reference... Figure 9D It can be seen that regardless of the arrangement of the 920B arithmetic core circuits (first hash engine on the left and second hash engine on the right, or second hash engine on the left and first hash engine on the right), clock channel sharing between adjacent columns of arithmetic core circuits can be achieved. Therefore, each arithmetic core circuit in the computing chip 900B' can be arranged reasonably according to the actual situation. It should be noted that, as... Figure 9DAs shown, the direction of data signal transmission is always from the first hash engine to the second hash engine. In other words, whether the first hash engine or the second hash engine is on the left in the diagram is only relative to the perspective of the diagram and does not change their upstream and downstream data transmission relationship.

[0069] Furthermore, when the arithmetic core circuit has a vertical structure, adjacent columns of arithmetic core circuits can also share a clock channel. The following section combines... Figures 9E to 9G Detailed description. Figures 9E to 9G In the diagram, for clarity, dashed lines are also used to represent clock signals. Multiple columns of arithmetic core circuits may include a first column of arithmetic core circuits and a second column of arithmetic core circuits arranged adjacent to each other in the stated order. In some embodiments, one of the first and second clock modules of the first column of arithmetic core circuits receives clock signals via a common clock channel as well as one of the first and second clock modules of the second column of arithmetic core circuits; additionally or alternatively, the other of the first and second clock modules of the first column of arithmetic core circuits receives clock signals via a common clock channel as well as the other of the first and second clock modules of the second column of arithmetic core circuits.

[0070] like Figure 9E As shown, the difference between computing chip 900C and computing chip 900B' is that computing chip 900C's arithmetic core circuit 920' has a first hash engine and a second hash engine that are vertically adjacent to each other. Multiple columns 920-1', 920-2', 920-3', and 920-4' include first and second column arithmetic core circuits (e.g., 920-1', 920-2') arranged adjacent to each other in the stated order. In some embodiments, the first clock module of the first column arithmetic core circuit (e.g., 920-1') and the first clock module of the second column arithmetic core circuit (e.g., 920-2') receive clock signals via a common clock channel (e.g., 991) as their respective first clock signals. In some embodiments, additionally or alternatively, the second clock module of the first column arithmetic core circuit (e.g., 920-1') and the second clock module of the second column arithmetic core circuit (e.g., 920-2') receive clock signals via a common clock channel (e.g., 993) as their respective second clock signals. The computing chip 900C may include multiple pairs of such first column arithmetic core circuits and second column arithmetic core circuits. For example, the first clock modules of the arithmetic core circuits in columns 920-3′ and 920-4′ can receive clock signals via a common clock channel 992 as their respective first clock signals, and the second clock modules can receive clock signals via a common clock channel 994 as their respective second clock signals.

[0071] It should be understood Figure 9EThe arrangement of the asynchronous FIFO module relative to hash engines H1 and H2 is merely exemplary and not restrictive, for example... Figure 9F As shown, the asynchronous FIFO module of the arithmetic core circuit can be arranged on either side of the hash engine H1 and H2. Furthermore, regardless of whether the arrangement of the corresponding arithmetic core circuits in adjacent columns of arithmetic core circuits with respect to the asynchronous FIFO module is the same or opposite, the hybrid clock structure of this disclosure can be implemented. In practice, the position of the asynchronous FIFO module in each arithmetic core circuit relative to the hash engine can be reasonably set according to the actual situation, and it is not necessarily required that the arrangement of each arithmetic core circuit or each column of arithmetic core circuits in the computing chip be the same.

[0072] It should also be understood Figure 9E The arrangement of hash engine H1 above hash engine H2 is merely exemplary and not restrictive. The relative vertical positions of hash engines H1 and H2 are not particularly limited, and the hybrid clock structure of this disclosure can be implemented regardless of whether H1 is above H2 or H2 is above H1. For example, as... Figure 9G As shown, in the second column of the computational core circuit, hash engine H2 is located above hash engine H1. In... Figure 9G In the illustrated embodiment, the first clock module of the first column of arithmetic core circuits and the second clock module of the second column of arithmetic core circuits receive clock signals via a common clock channel, which are used as their respective first and second clock signals. Alternatively, the second clock module of the first column of arithmetic core circuits and the first clock module of the second column of arithmetic core circuits receive clock signals via a common clock channel, which are used as their respective second and first clock signals. In practice, the relative vertical positions of hash engines H1 and H2 in each arithmetic core circuit can be reasonably set according to actual conditions, and it is not necessarily required that the arrangement of each arithmetic core circuit or each column of arithmetic core circuits in the computing chip be identical.

[0073] Because the aspect ratio of the arithmetic core circuits in conventional computing chips is typically very large (due to the need to accommodate up to 128 arithmetic stages), the arrangement of these arithmetic core circuits on computing chips (generally based on silicon wafers) is very limited. The vertically structured arithmetic core circuits provided in this disclosure can have a significantly reduced aspect ratio, allowing for more flexible and rational arrangement on the computing chip. Including synchronous or asynchronous FIFO modules can further improve the performance of the vertically structured arithmetic core circuits. Furthermore, by sharing clock channels between adjacent columns of the arithmetic core circuits, chip area can be further saved, and a larger number of arithmetic core circuits can be arranged on a chip of the same size to efficiently handle complex computational tasks.

[0074] It is understood that although the above embodiments describe sharing a clock channel between adjacent columns of the computing core circuit, it is also feasible to share a clock channel between adjacent rows of the computing core circuit in a similar manner, and this is also covered within the scope of this disclosure.

[0075] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “up,” “down,” “high,” “low,” etc., used in the specification and claims, if present, are for descriptive purposes and not necessarily for describing unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, so that embodiments of this disclosure described herein can, for example, operate in orientations different from those shown or otherwise described herein. For example, when the device in the drawings is reversed, a feature previously described as “above” other features may now be described as “below” other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), in which case the relative spatial relationships will be interpreted accordingly.

[0076] In the specification and claims, when an element is described as being "on top of," "attached" to, "connected" to, "coupled" to, or "in contact with" another element, the element may be directly on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" on top of, "directly attached" to, "directly connected" to, "directly coupled" to, or "directly in contact with" another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping the adjacent feature or a portion located above or below the adjacent feature.

[0077] As used herein, the term "exemplary" means "used as an example, instance, or illustration" and not as a "model" to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, this disclosure is not limited to any theory expressed or implied as given in the field of art, background art, summary of invention, or detailed description.

[0078] As used herein, the word "substantially" means any minor variation caused by defects in design or manufacture, tolerances of devices or components, environmental influences, and / or other factors. The word "substantially" also allows for differences from the perfect or ideal situation caused by parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0079] Additionally, terms such as “first,” “second,” etc., may be used in this document for reference purposes only and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence.

[0080] It should also be understood that when the term "includes / contains" is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0081] In this disclosure, the term "provide" is used broadly to cover all ways of obtaining an object, and therefore "provide an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting up", "installing / assembling", and / or "ordering" an object.

[0082] As used herein, the terms "and / or" include any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms "-", "a", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0083] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0084] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. An operational core circuit, comprising: The input module is configured to receive data blocks; A computation module is configured to perform hash operations on received data blocks, the computation module comprising: A first hash engine includes a plurality of processing stages arranged in a pipelined structure such that data signals based on the data block are sequentially transmitted along the plurality of processing stages; and The second hash engine includes a second plurality of processing stages, which are arranged in a pipelined structure such that data signals received from the first hash engine are sequentially transmitted along the second plurality of processing stages. Each of the first plurality of operation levels and the second plurality of operation levels performs operations on the data signal received from the previous operation level and provides the data signal processed by the operation level to the next operation level; A clock module is configured to provide clock signals to the first hash engine and the second hash engine, wherein the transmission direction of the clock signal in the first hash engine is opposite to the transmission direction of the clock signal in the second hash engine; and A first-in-first-out (FIFO) module is located between two adjacent computation stages in the direction of data signal transmission within the computation module and includes a FIFO buffer. One of the two computation stages precedes the other. The FIFO module is configured to receive data signals output from one computation stage and write them into the FIFO buffer, and to read the received data signals from the FIFO buffer and output them to the other computation stage.

2. The operational core circuit according to claim 1, wherein, The clock signal in the first hash engine is transmitted in the opposite direction to the data signal, while the clock signal in the second hash engine is transmitted in the same direction as the data signal.

3. The operational core circuit according to claim 1, wherein, The FIFO module includes: A synchronous FIFO module is disposed between the last operation stage in the first plurality of operation stages of the first hash engine and the first operation stage in the second plurality of operation stages of the second hash engine. The synchronous FIFO module is configured to receive a data signal output from the last operation stage of the first hash engine using a clock signal provided by the clock module, and to output the received data signal to the first operation stage of the second hash engine using the clock signal provided by the clock module. The clock module is configured to provide the clock signal to the first hash engine, the second hash engine, and the synchronous FIFO module.

4. The operational core circuit according to claim 1, wherein, The FIFO module includes: An asynchronous FIFO module is disposed between the last operation stage in the first plurality of operation stages of the first hash engine and the first operation stage in the second plurality of operation stages of the second hash engine. The asynchronous FIFO module is configured to receive a data signal output from the last operation stage of the first hash engine using a first clock signal provided by the clock module, and to output the received data signal to the first operation stage of the second hash engine using a second clock signal provided by the clock module, which is different from the first clock signal. The clock module includes a first clock module and a second clock module. The first clock module is configured to provide the first clock signal to the first hash engine and the asynchronous FIFO module, and the second clock module is configured to provide the second clock signal to the second hash engine and the asynchronous FIFO module. The first clock signal and the second clock signal have the same frequency.

5. The operational core circuit according to claim 4, wherein, The first clock signal and the data signal are transmitted in the same direction, and the second clock signal is transmitted in the opposite direction to the data signal.

6. The operational core circuit according to claim 4, wherein, The first clock signal is transmitted in the opposite direction to the data signal, and the second clock signal is transmitted in the same direction as the data signal.

7. The operational core circuit according to any one of claims 1-6, wherein, The computing core circuit is implemented on a semiconductor chip, and the first hash engine and the second hash engine are arranged to be adjacent to each other in a vertical direction perpendicular to the transmission direction of the data signal along the surface of the semiconductor chip.

8. The operational core circuit according to any one of claims 1-3, wherein, The FIFO module includes: A second asynchronous FIFO module is disposed between adjacent first and second operational stages in the plurality of operational stages, wherein the first operational stage precedes the second operational stage. The second asynchronous FIFO module is configured to receive data signals output from the first operational stage using a third clock signal different from the stated clock signal, and to output the received data signals to the second operational stage using the stated clock signal. The computational core circuit further includes a third clock module, which is configured to provide the third clock signal to the second asynchronous FIFO module and to the first computational level and the computational levels preceding the first computational level among the first plurality of computational levels. The clock module is further configured to provide the clock signal to the second asynchronous FIFO module and to the second operation level and the operation level after the second operation level among the first plurality of operation levels.

9. The operational core circuit according to any one of claims 1-3, wherein, The FIFO module includes: A third asynchronous FIFO module is disposed between adjacent third and fourth operational stages in the second plurality of operational stages, wherein the third operational stage precedes the fourth operational stage. The third asynchronous FIFO module is configured to receive data signals output from the third operational stage using the clock signal and to output the received data signals to the fourth operational stage using a fourth clock signal different from the clock signal. The arithmetic core circuit further includes a fourth clock module, which is configured to provide the fourth clock signal to the third asynchronous FIFO module and to the fourth arithmetic stage and the arithmetic stages following the fourth arithmetic stage in the second plurality of arithmetic stages. The clock module is further configured to provide the clock signal to the third asynchronous FIFO module and to the third operation level and the operation level preceding the third operation level in the second plurality of operation levels.

10. The operational core circuit according to any one of claims 4-6, wherein, The asynchronous FIFO module is a first asynchronous FIFO module, and the FIFO module further includes: A second asynchronous FIFO module is disposed between adjacent first and second operational stages in the plurality of operational stages, wherein the first operational stage precedes the second operational stage. The second asynchronous FIFO module is configured to receive data signals output from the first operational stage using a third clock signal different from the first clock signal, and to output the received data signals to the second operational stage using the first clock signal. The computational core circuit further includes a third clock module, which is configured to send a third clock signal to the second asynchronous FIFO module and to the first computational level and the computational levels preceding the first computational level among the first plurality of computational levels. The first clock module is configured to provide the first clock signal to the first asynchronous FIFO module and the second asynchronous FIFO module, and to the second operation level and the operation level after the second operation level among the first plurality of operation levels.

11. The operational core circuit according to any one of claims 4-6, wherein, The asynchronous FIFO module is a first asynchronous FIFO module, and the FIFO module further includes: A third asynchronous FIFO module is disposed between adjacent third and fourth operational stages in the second plurality of operational stages, wherein the third operational stage precedes the fourth operational stage. The third asynchronous FIFO module is configured to receive data signals output from the third operational stage using a second clock signal and to output the received data signals to the fourth operational stage using a fourth clock signal different from the second clock signal. The arithmetic core circuit further includes a fourth clock module, which is configured to provide the fourth clock signal to the third asynchronous FIFO module and to the fourth arithmetic stage and the arithmetic stages following the fourth arithmetic stage in the second plurality of arithmetic stages. The second clock module is configured to provide the second clock signal to the first asynchronous FIFO module and the third asynchronous FIFO module, and to the third operation level and the operation level preceding the third operation level in the second plurality of operation levels.

12. A computing chip comprising one or more arithmetic core circuits as described in any one of claims 1-11.

13. A computing chip comprising a plurality of arithmetic core circuits according to any one of claims 1-3, 8-9, wherein the plurality of arithmetic core circuits are arranged in a plurality of columns, and the clock module of each column of arithmetic core circuits receives a clock signal via a common clock channel.

14. The computing chip according to claim 13, in, The computational core circuit is the computational core circuit according to claim 3, the computational core circuit is implemented on a semiconductor chip, and the first hash engine and the second hash engine are arranged adjacent to each other along the surface of the semiconductor chip in a vertical direction perpendicular to the transmission direction of the data signal. Furthermore, the plurality of columns include a first column of arithmetic core circuits and a second column of arithmetic core circuits arranged adjacent to each other in the stated order, and wherein the clock modules of the first column of arithmetic core circuits and the clock modules of the second column of arithmetic core circuits receive clock signals via a common clock channel.

15. A computing chip comprising a plurality of arithmetic core circuits according to any one of claims 4-6, 10-11, wherein the plurality of arithmetic core circuits are arranged in a plurality of columns, wherein a first clock module of each column of arithmetic core circuits receives a first clock signal via a common clock channel, and a second clock module of each column of arithmetic core circuits receives a second clock signal via a common clock channel.

16. The computing chip according to claim 15, in, The computational core circuit is the computational core circuit according to claim 5. The plurality of columns include a first column of operational core circuits and a second column of operational core circuits arranged adjacent to each other in the stated order. Furthermore, one of the first clock module and the second clock module of the first column arithmetic core circuit receives clock signals through a common clock channel with one of the first clock module and the second clock module of the second column arithmetic core circuit.

17. The computing chip according to claim 16, in, The plurality of columns include a first column of operational core circuits, a second column of operational core circuits, and a third column of operational core circuits arranged adjacent to each other in the stated order. Furthermore, in this circuit, one of the first clock module and the second clock module of the second column arithmetic core circuit receives clock signals via a common clock channel with one of the first clock module and the second clock module of the third column arithmetic core circuit.

18. The computing chip according to claim 15, in, The computing core circuit is implemented on a semiconductor chip, and the first hash engine and the second hash engine are arranged adjacent to each other along the surface of the semiconductor chip in a vertical direction perpendicular to the transmission direction of the data signal. The plurality of columns include a first column of operational core circuits and a second column of operational core circuits arranged adjacent to each other in the stated order. And among them: One of the first clock module and the second clock module of the first column of arithmetic core circuits receives clock signals via a common clock channel as one of the first clock module and the second clock module of the second column of arithmetic core circuits; and / or The other of the first clock module and the second clock module of the first column arithmetic core circuit receives clock signals through a common clock channel with the other of the first clock module and the second clock module of the second column arithmetic core circuit.

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