Pulse neuron reinforcement circuit and reinforcement method

Abstract

A spiking neuron reinforcement circuit and method address the existing flaw in spiking neurons, which are susceptible to computational errors due to single-particle effects, and effectively improve the spatial adaptability of spiking neurons. This method utilizes configuration information and model parameters to achieve the spiking neurons and neuron discharge pulse signals required by spiking neural networks. Furthermore, the method uses an ECC codec module to perform error correction and fault tolerance on the configuration information and model parameters. Furthermore, the method uses a shadow memory (or register bank) to back up and fault-tolerant the configuration information and model parameters.

Description

Technical Field

[0001] The present invention relates to a pulse neuron reinforcement circuit and a reinforcement method, and relates to the technical field of pulse neural networks. Background Art

[0002] Spiking neural networks, as the third generation of neural networks, are widely used in the field of brain-like neuromorphic computing due to their biomimetic neurodynamic characteristics and event-driven advantages. Spiking neurons are the basic computational units of spiking neural networks. They simulate the working mode of biological neurons, integrating and calculating input pulse signals and outputting new pulse signals to subsequent neurons, thereby completing information transmission between neurons. Spiking neurons output pulse signals that excite or inhibit neuronal discharges by calculating neuronal model parameters. Commonly used spiking neuron models include the LIF model proposed by Lapicque in 1907, the Izhikevich model proposed by Ezhikevich in 2003, and the Hodgkin-Huxley model proposed by Hodgkin and Huxley in 1952. The Izhikevich model can simulate the 20 most prominent pulse signals of excitatory or inhibitory neuronal discharges in biological neurons.

[0003] Spiking neurons are extremely susceptible to single-particle effects when used in space. If the neuron model parameters cause single-bit errors or multi-bit errors due to single-particle upsets or single-particle transients, it will cause abnormal neuron discharge behavior and output erroneous pulse signals. In severe cases, it will lead to erroneous output results of brain-like neuromorphic computing chips. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the shortcomings of the existing technology and provide a spiking neuron reinforcement circuit and reinforcement method, which solves the defect of spiking neurons in the existing technology that are prone to calculation errors due to single-particle effects, and effectively improves the spatial environment adaptability of spiking neurons. This method can realize the spiking neurons and neuron discharge pulse signals required by spiking neural networks through configuration information and model parameters; further, this method uses an ECC codec module to perform error correction and fault tolerance on the configuration information and model parameters; further, this method uses a shadow memory (or register group) to back up the configuration information and model parameters for fault tolerance.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] A pulse neuron reinforcement circuit includes a first register group, a second register group, a third register group, an encoding module, a decoding module, a logic module, and a configurable pulse neuron computing unit;

[0007] The encoding module is used to encode the first data and / or the second data input from the external or logical module;

[0008] The first register group is used to store the encoded first data;

[0009] The second register group is used to store the encoded second data;

[0010] The third register group is used to directly store the first data and / or the second data;

[0011] The decoding module is used to perform error correction and detection decoding on the encoded first data and / or second data, and record the decoding result; the encoding method of the encoding module corresponds to the decoding method of the decoding module;

[0012] The logic module selects the decoded first data and / or second data to be output to the configurable pulse neuron computing unit according to the decoding result, or selects the first data and / or second data in the third register group to be output to the configurable pulse neuron computing unit and the encoding module;

[0013] The configurable pulse neuron computing unit is configured using the input first data and / or second data.

[0014] In one embodiment of the present invention, the first data is configuration information, and the second data is model parameters.

[0015] In one embodiment of the present invention, the configurable spiking neuron computing unit generates LIF neurons, Izhikevich neurons, or Hodgkin-Huxley neurons using configuration information.

[0016] In one embodiment of the present invention, the configurable pulse neuron calculation unit uses the model parameters to generate corresponding pulse signals for exciting or inhibiting neuron discharges.

[0017] In one embodiment of the present invention, the third register group is spatially isolated from the first register group and the second register group, or the third register group is independently reinforced to reduce the impact of spatial single event effects.

[0018] In one embodiment of the present invention, the third register is spatially isolated from the first register group and the second register group using a cross layout, and the spatial distance between the third register group and the first register group and the second register group is determined based on the spatial environment in which the configurable pulse neuron computing unit operates; the spatial environment includes the space orbit altitude, the space radiation environment, and the spatial layout of the three register groups.

[0019] In one embodiment of the present invention, the encoding module adopts an ECC encoding method.

[0020] In one embodiment of the present invention, when the decoding module performs error correction and detection decoding, it performs single-bit error correction and multi-bit error detection on the input data.

[0021] In one embodiment of the present invention, when the decoding result is a multiple-bit error, the logic module selects the first data and the second data in the third register group and outputs them to the configurable pulse neuron computing unit and the encoding module.

[0022] In one embodiment of the present invention, the encoding module includes a first encoding module and a second encoding module. The first encoding module is used to encode first data input from an external or logical module; the second encoding module is used to encode second data input from an external or logical module.

[0023] In one embodiment of the present invention, the decoding module includes a first decoding module and a second decoding module. The first decoding module is used to perform error correction and detection decoding on first data input from an external or logical module; the second decoding module is used to perform error correction and detection decoding on second data input from an external or logical module.

[0024] In one embodiment of the present invention, the encoding mode of the encoding module and the decoding mode of the decoding module use different encoding and decoding bit numbers according to different neuron models to perform multi-bit error correction and multi-bit error detection on input data.

[0025] A pulse neuron reinforcement method comprises the following steps:

[0026] Originally storing first data and / or second data input from the outside, and encoding the input first data and / or second data;

[0027] The encoded first data and second data are stored separately;

[0028] performing error correction and detection decoding on the encoded first data and / or second data;

[0029] When there are fewer erroneous data during decoding, the erroneous data are corrected and used to configure pulse neurons; when there are more erroneous data during decoding, the original stored data are used to configure pulse neurons, and the corresponding erroneous data before encoding are replaced with the original stored data.

[0030] In one embodiment of the present invention, the first data is configuration information, which can configure the spiking neuron to generate a LIF neuron, an Izhikevich neuron, or a Hodgkin-Huxley neuron.

[0031] In one embodiment of the present invention, the second data is a model parameter, which can configure the spiking neuron to generate a corresponding pulse signal for exciting or inhibiting neuronal discharge.

[0032] In one embodiment of the present invention, the original storage is isolated from the encoded storage space, or the original storage is independently reinforced to reduce the impact of spatial single-particle effects.

[0033] In one embodiment of the present invention, the original storage is isolated from the encoded storage space using a cross layout, and the spatial isolation distance is determined according to the spatial environment in which the pulse neuron works; the spatial environment includes the space orbit height, the space radiation environment, and the spatial isolation layout.

[0034] In one embodiment of the present invention, an ECC encoding method and an ECC decoding method are adopted.

[0035] In one embodiment of the present invention, during error correction and detection decoding, single-bit error correction and multi-bit error detection are performed on input data.

[0036] In one embodiment of the present invention, when multiple bit errors occur during decoding, the spiking neurons are configured using the original stored data.

[0037] In one embodiment of the present invention, the encoding method matches the decoding method, and different encoding and decoding bit numbers are used according to different neuron models to perform multi-bit error correction and multi-bit error detection on input data.

[0038] In one embodiment of the present invention, two encoding circuits are used, one of which encodes the first data and the other encodes the second data.

[0039] In one embodiment of the present invention, two decoding circuits are used, one of which performs error correction and detection decoding on the first data, and the other performs error correction and detection decoding on the second data.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] (1) The present invention can generate a variety of neurons and their discharge pulse signals through configuration information and model parameter information, thereby improving the adaptability of the pulse neural network. At the same time, when a neuron is damaged by space particles, it can be configured into another type of neuron through configuration information, thereby improving the reliability of the neuron.

[0042] (2) When one or more errors occur in the neuron configuration information, the present invention automatically corrects the error through the ECC error correction mechanism, thereby improving the reliability of the neuron.

[0043] (3) When multiple errors occur in the neuron configuration information, the present invention controls the shadow memory (or register group) to output the correct configuration information data through the arbitration correction control logic module, and corrects the erroneous configuration information at the same time, thereby improving the reliability of the neuron.

[0044] (4) When one or more errors occur in the neuron model parameters, the present invention automatically corrects the errors through the ECC error correction mechanism, thereby improving the reliability of the neuron.

[0045] (5) When multiple errors occur in the neuron model parameters, the present invention controls the shadow memory (or register group) to output the correct model parameter data through the arbitration correction control logic module, and corrects the erroneous model parameters at the same time, thereby improving the reliability of the neuron. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a structural diagram of a high-reliability neuron in an embodiment of the present invention;

[0047] Figure 2 Schematic diagram of the logic of the arbitration correction control logic module in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0049] Example 1:

[0050] A pulse neuron reinforcement circuit and reinforcement method, comprising a configuration information memory (or register group), a model parameter memory (or register group), an ECC encoding module, an ECC decoding module, a configurable neuron computing unit, a shadow memory (or register group), and an arbitration correction control logic module;

[0051] The configuration information memory (or register group) stores configuration information of multiple neuron models, and the configurable neuron computing unit can generate required pulse neurons, such as LIF neurons, Izhikevich neurons, or Hodgkin-Huxley neurons, according to the configuration information;

[0052] The model parameter memory (or register group) stores parameter information corresponding to a plurality of neuron models, and the configurable neuron calculation unit can realize the corresponding pulse signal of exciting or inhibiting neuron discharge according to the model parameter information. For example, the 20 groups of Izhikevich model parameters stored correspond to 20 types of neuron discharge behaviors such as tonic pulse discharge and type 1 excitation, respectively;

[0053] The ECC encoding module is composed of a logic circuit for error correction and detection coding, which can perform single-bit error correction and multi-bit error detection coding on the input data;

[0054] The ECC decoding module is composed of error correction and detection decoding logic circuits, which can decode the input data to correct single-bit errors and detect multiple-bit errors. If there is no error or a single-bit error occurs, the correct result is output to the arbitration correction control logic module. If multiple bit errors occur, an error flag is output to the arbitration correction control logic module.

[0055] The configurable neuron computing unit is composed of a configurable digital logic circuit (such as an adder, a multiplier, etc.) or a configurable resistor and other new devices, and can generate corresponding pulse neurons through configuration information;

[0056] The shadow memory (or register group) stores the configuration information of the spiking neurons and a backup of the model parameters;

[0057] The arbitration correction control logic module controls the shadow memory (or register group) to output the backed-up correct data to the configurable neuron computing unit according to the error identifier output by the ECC decoding module, and corrects the errors in the configuration information memory and the model parameter memory.

[0058] Preferably, the above-mentioned high-reliability pulse neuron, the input configuration information data is subjected to error correction and detection encoding by the ECC encoding module and then output to the configuration information memory (or register group). When a bit error occurs in the configuration information data output by the configuration information memory (or register group) to the ECC decoding module, the ECC decoding module corrects the erroneous data through error correction and detection decoding logic and then outputs the correct configuration information data to the configurable neuron computing unit.

[0059] Preferably, the configuration information input to the above-mentioned high-reliability pulse neuron is subjected to error correction encoding by the ECC encoding module and then output to the configuration information memory (or register group). When multiple-bit errors occur in the configuration information data output by the configuration information memory (or register group), the ECC decoding module outputs the configuration information error identifier to the arbitration correction control logic module through error correction decoding.

[0060] Preferably, for the above-mentioned high-reliability pulse neuron, after the arbitration correction control logic module receives the configuration information error identifier, it controls the shadow memory (or register group) to output the backed-up correct configuration information data to the configurable neuron computing unit, and at the same time outputs the correct configuration information data to the ECC encoding module. After the ECC encoding module re-corrects the error encoding of the configuration information data, it outputs the correct encoded data to the configuration information memory, thereby completing the error information correction of the configuration information memory.

[0061] Preferably, the above-mentioned high-reliability pulse neuron, the input model parameter data is error-corrected and encoded by the ECC encoding module and then output to the model parameter memory (or register group). When a bit error occurs in the model parameter data output by the model parameter memory (or register group) to the ECC decoding module, the ECC decoding module corrects the erroneous data through the error-correction decoding logic and then outputs the correct model parameter data to the configurable neuron computing unit.

[0062] Preferably, the above-mentioned high-reliability pulse neuron, the input model parameter data is error-corrected and encoded by the ECC encoding module and then output to the model parameter memory (or register group). When multiple-bit errors occur in the model parameter data output by the model parameter memory (or register group), the ECC decoding module outputs the model parameter error identifier to the arbitration correction control logic module through error-correction decoding.

[0063] Preferably, the above-mentioned high-reliability pulse neuron, after the arbitration correction control logic module receives the model parameter error identifier, controls the shadow memory (or register group) to output the backed-up correct model parameter data to the configurable neuron computing unit, and at the same time outputs the correct model parameter data to the ECC encoding module. After the ECC encoding module re-corrects the error encoding of the model parameters, it outputs the correct encoded data to the model parameter memory, thereby completing the error information correction of the model parameter memory.

[0064] Preferably, the shadow memory, configuration information memory, and model parameter memory are physically implemented in a cross-shaped layout, i.e., they are spatially isolated with a spacing of no less than a preset value, which is in the range of 2-10 μm, to achieve the goal of high-reliability operation of the spiking neuron in the full range of LEO, MEO, and GEO orbits. More specifically:

[0065] Through heavy particle Monte Carlo model simulation and comparative analysis with NASA data and irradiation test data, the following layout conditions were determined:

[0066] 1) When the single event upset threshold exceeds 37 MeV·cm 2 / mg or when working in MEO orbit, the memory interval is not less than the first preset value, and the value range of the first preset value is 8-10um.

[0067] 2) When the single event upset threshold exceeds 15 MeV·cm 2 / mg or when working in GEO orbit, the memory interval is not less than a second preset value, and the value range of the second preset value is 5-7um.

[0068] 3) When the single event upset error rate is no greater than 1E-10 / device·day or when operating in a LEO orbit, the memory spacing is no less than a third preset value, and the third preset value ranges from 2 μm to 4 μm.

[0069] Example 2:

[0070] A pulse neuron reinforcement circuit and reinforcement method may specifically include a configuration information memory, a model parameter memory, an ECC encoding module, an ECC decoding module, a configurable neuron computing unit, a shadow memory, and an arbitration correction control logic module.

[0071] The output of the ECC encoding module is connected to the configuration information memory and the model parameter memory.

[0072] The outputs of the configuration information memory and the model parameter memory are connected to the ECC decoding module.

[0073] The outputs of the ECC decoding module and the shadow memory are connected to the arbitration correction control logic module.

[0074] The output of the arbitration correction control logic module is connected to the configurable neuron computing unit and the ECC encoding module.

[0075] In an embodiment of the present invention, for the sake of low power consumption and resource saving, only one ECC encoding module and ECC decoding module are used, and the error correction and detection encoding and decoding of configuration information and model parameters are completed through the selection switch time-sharing multiplexing module; two ECC encoding modules and two ECC decoding modules can also be used, corresponding to the configuration information memory and the model parameter memory respectively, to complete the error correction and detection encoding and decoding of the configuration information and the error correction and detection encoding and decoding of the model parameters respectively.

[0076] In an embodiment of the present invention, the configuration information memory stores configuration information of multiple neuron models, and the configurable neuron computing unit can generate the required pulse neurons and neuron working states based on the configuration information. The pulse neurons can be LIF neurons, Izhikevich neurons, or Hodgkin-Huxley neurons, and the neuron working states can be leakage mode, threshold discharge mode, or reset mode, etc.

[0077] In an embodiment of the present invention, the model parameter memory stores parameter information corresponding to a plurality of neuron models, and the configurable neuron computing unit can realize the corresponding pulse signal of excitatory or inhibitory neuron discharge based on the model parameter information. For example, the 20 groups of Izhikevich model parameters stored correspond to 20 types of neuron discharge behaviors such as tonic pulse discharge and type 1 excitation; the 6 groups of Hodgkin-Huxley model parameters stored correspond to 6 types of excitatory or inhibitory neuron discharge behaviors such as RS neuron discharge, IB neuron discharge, and FS neuron discharge; the 3 groups of LIF model parameters stored correspond to 3 types of neuron discharge behaviors such as integrator discharge.

[0078] In the first embodiment of the present invention, the ECC encoding module comprises a logic circuit for error correction and detection encoding, capable of encoding input data to correct single-bit errors and detect multiple-bit errors, specifically employing Hamming code for error correction and detection encoding. The ECC decoding module comprises a logic circuit for error correction and detection decoding, capable of decoding input data to correct single-bit errors and detect multiple-bit errors, specifically employing Hamming code for error correction and detection decoding. If there is no error or a single-bit error occurs, a correct result (i.e., an error flag of 0) is output to the arbitration correction control logic module. If multiple-bit errors occur, an error flag (i.e., an error flag of 1) is output to the arbitration correction control logic module.

[0079] In the second embodiment of the present invention, the ECC encoding and decoding module adopts a corresponding reinforcement encoding and decoding strategy according to the complexity of the input neuron model:

[0080] a. For a simple neuron model, such as the LIF neuron model that supports three types of neuron discharge behaviors, when the total number of configuration parameters and model parameters is no more than 39 bits, a 4-check-4 encoding is used, which requires 24 check bits. The encoding length overhead is 63 bits (39 data bits, 24 check bits).

[0081] b. For moderately complex neuron models, such as the Hodgkin-Huxley neuron model that supports six types of neuron firing behaviors, when the total number of configuration parameters and model parameters is no more than 64 bits, they are divided into four groups. Each group of 16 bits of data uses 1-correction-2-check encoding. Each group requires 6 check bits, which can achieve 4-correction-8-check encoding. The corresponding encoding length overhead is 88 bits (64 data bits, 24 check bits).

[0082] c. For complex neuron models, such as the Izhikevich neuron model that supports 20 types of neuron discharge behaviors, when the total configuration parameters and model parameters are greater than 64 bits, they are divided into groups of 32-bit data. Each group uses 1-correction-2-check encoding, and each group requires 7 check bits. This can achieve the effect of correcting multiple bit errors. For example, 128-bit neuron data is divided into 4 groups, each with 32 bits of data. 1-correction-2-check encoding is used, and each group requires 7 check bits. This can achieve 4-correction-8-check encoding, corresponding to a coding code length overhead of 156 bits (128 data bits, 28 check bits).

[0083] When the reinforced coding and decoding strategy in the above-mentioned embodiment 2 is adopted; if there is no error, or the number of bit errors does not exceed 4 and has been corrected, the correct result (that is, the error mark is 0) is output to the arbitration correction control logic module; otherwise, the error mark (that is, the error mark is 1) is output to the arbitration correction control logic module.

[0084] In an embodiment of the present invention, the configurable neuron computing unit can generate corresponding pulse neurons through configuration information. The specific implementation may include: realizing LIF neurons, Izhikevich neurons, or Hodgkin-Huxley neurons by configurable digital logic circuits such as adders and multipliers or by new devices such as configurable resistors.

[0085] In an embodiment of the present invention, a shadow memory stores configuration information of the pulse neuron and a backup of the model parameters; the arbitration correction control logic module controls the shadow memory to output the correct backup data to the configurable neuron computing unit based on the error identifier output by the ECC decoding module, and corrects errors that occur in the configuration information memory and the model parameter memory.

[0086] The working process of the arbitration correction control logic module is as follows Figure 2 As shown: if the configuration information error flag output by the ECC decoding module is 0, it means that the configuration information is correct, and the configuration information data output by the ECC decoding module is selected to be given to the configurable neuron computing unit; if the configuration information error flag output by the ECC decoding module is 1, it means that the configuration information is wrong, and the correct configuration information data is taken out from the shadow memory and given to the configurable neuron computing unit, and the correct configuration information data is sent to the ECC encoding module to correct and replace the erroneous configuration information data; if the model parameter error flag output by the ECC decoding module is 0, it means that the model parameters are correct, and the model parameter data output by the ECC decoding module is selected to be given to the configurable neuron computing unit; if the model parameter error flag output by the ECC decoding module is 1, it means that the model parameters are wrong, and the correct model parameter data is taken out from the shadow memory and given to the configurable neuron computing unit, and the correct model parameter data is sent to the ECC encoding module to correct and replace the erroneous model parameter data.

[0087] In an embodiment of the present invention, the shadow memory, the configuration information memory, and the model parameter memory are physically implemented in a cross-layout, i.e., they are spatially isolated with a spacing of no less than a preset value, the preset value ranging from 2 to 10 μm, so as to achieve the goal of high-reliability operation of the pulse neuron in the full orbit range of LEO, MEO, and GEO. Preferably, there are three types of cross-layouts: the first is that the shadow memory, the configuration information memory, and the model parameter memory are perpendicular to each other; the second is that the configuration information memory and the model parameter memory are parallel, and the shadow memory is perpendicular to both the configuration information memory and the model parameter memory; the third is that the configuration information memory and the model parameter memory are parallel, and the angle between the shadow memory, the configuration information memory, and the model parameter memory is greater than 60°. In each layout, in order to facilitate the description of the relationship between the three, each memory can be equivalent to a sheet structure.

[0088] In the case of the second spatial layout or the third spatial layout, more specifically:

[0089] Through heavy particle Monte Carlo model simulation and comparative analysis with NASA data and irradiation test data, the following layout conditions were determined:

[0090] 1) When the single event upset threshold exceeds 37 MeV·cm 2 / mg or when working in MEO orbit, the memory interval is not less than the first preset value, and the value range of the first preset value is 8-10um.

[0091] 2) When the single event upset threshold exceeds 15 MeV·cm 2 / mg or when working in GEO orbit, the memory interval is not less than a second preset value, and the value range of the second preset value is 5-7um.

[0092] 3) When the single event upset error rate is no greater than 1E-10 / device·day or when operating in a LEO orbit, the memory spacing is no less than a third preset value, and the third preset value ranges from 2 μm to 4 μm.

[0093] Example 3:

[0094] A pulse neuron reinforcement circuit includes a first register group, a second register group, a third register group, an encoding module, a decoding module, a logic module, and a configurable pulse neuron computing unit;

[0095] The encoding module is used to encode the first data and / or the second data input from the external or logical module;

[0096] The first register group is used to store the encoded first data;

[0097] The second register group is used to store the encoded second data;

[0098] The third register group is used to directly store the first data and / or the second data;

[0099] The decoding module is used to perform error correction and detection decoding on the encoded first data and / or second data, and record the decoding result; the encoding method of the encoding module corresponds to the decoding method of the decoding module;

[0100] The logic module selects the decoded first data and / or second data to be output to the configurable pulse neuron computing unit according to the decoding result, or selects the first data and / or second data in the third register group to be output to the configurable pulse neuron computing unit and the encoding module;

[0101] The configurable pulse neuron computing unit is configured using the input first data and / or second data.

[0102] In one embodiment of the present invention, the first data is configuration information, and the second data is model parameters.

[0103] In one embodiment of the present invention, the configurable spiking neuron computing unit generates LIF neurons, Izhikevich neurons, or Hodgkin-Huxley neurons using configuration information.

[0104] In one embodiment of the present invention, the configurable pulse neuron calculation unit uses the model parameters to generate corresponding pulse signals for exciting or inhibiting neuron discharges.

[0105] In one embodiment of the present invention, the third register group is spatially isolated from the first register group and the second register group, or the third register group is independently reinforced to reduce the impact of spatial single event effects.

[0106] In one embodiment of the present invention, the third register is spatially isolated from the first register group and the second register group using a cross layout, and the spatial distance between the third register group and the first register group and the second register group is determined based on the spatial environment in which the configurable pulse neuron computing unit operates; the spatial environment includes the space orbit altitude, the space radiation environment, and the spatial layout of the three register groups.

[0107] In one embodiment of the present invention, the encoding module adopts an ECC encoding method.

[0108] In one embodiment of the present invention, when the decoding module performs error correction and detection decoding, it performs single-bit error correction and multi-bit error detection on the input data.

[0109] In one embodiment of the present invention, when the decoding result is a multiple-bit error, the logic module selects the first data and the second data in the third register group and outputs them to the configurable pulse neuron computing unit and the encoding module.

[0110] In one embodiment of the present invention, the encoding module includes a first encoding module and a second encoding module. The first encoding module is used to encode first data input from an external or logical module; the second encoding module is used to encode second data input from an external or logical module.

[0111] In one embodiment of the present invention, the decoding module includes a first decoding module and a second decoding module. The first decoding module is used to perform error correction and detection decoding on the first data input from the external or logic module; the second decoding module is used to perform error correction and detection decoding on the second data input from the external or logic module.

[0112] In one embodiment of the present invention, the encoding mode of the encoding module and the decoding mode of the decoding module adopt different encoding and decoding bit numbers according to different neuron models to perform multi-bit error correction and multi-bit error detection on input data.

[0113] Example 4:

[0114] A pulse neuron reinforcement method comprises the following steps:

[0115] Originally storing first data and / or second data input from the outside, and encoding the input first data and / or second data;

[0116] The encoded first data and second data are stored separately;

[0117] performing error correction and detection decoding on the encoded first data and / or second data;

[0118] When there are fewer erroneous data during decoding, the erroneous data are corrected and used to configure pulse neurons; when there are more erroneous data during decoding, the original stored data are used to configure pulse neurons, and the corresponding erroneous data before encoding are replaced with the original stored data.

[0119] In one embodiment of the present invention, the first data is configuration information, which can configure the spiking neuron to generate a LIF neuron, an Izhikevich neuron, or a Hodgkin-Huxley neuron.

[0120] In one embodiment of the present invention, the second data is a model parameter, which can configure the spiking neuron to generate a corresponding pulse signal for exciting or inhibiting neuronal discharge.

[0121] In one embodiment of the present invention, the original storage is isolated from the encoded storage space, or the original storage is independently reinforced to reduce the impact of spatial single-particle effects.

[0122] In one embodiment of the present invention, the original storage is isolated from the encoded storage space using a cross layout, and the spatial isolation distance is determined according to the spatial environment in which the pulse neuron works; wherein the spatial environment includes the space orbit height, the space radiation environment, and the spatial isolation layout.

[0123] In one embodiment of the present invention, an ECC encoding method and an ECC decoding method are adopted.

[0124] In one embodiment of the present invention, during error correction and detection decoding, single-bit error correction and multi-bit error detection are performed on input data.

[0125] In one embodiment of the present invention, when multiple bit errors occur during decoding, the spiking neurons are configured using the original stored data.

[0126] In one embodiment of the present invention, the encoding method matches the decoding method, and different encoding and decoding bit numbers are used according to different neuron models to perform multi-bit error correction and multi-bit error detection on input data.

[0127] In one embodiment of the present invention, two encoding circuits are used, one of which encodes the first data and the other encodes the second data.

[0128] In one embodiment of the present invention, two decoding circuits are used, one of which performs error correction and detection decoding on the first data, and the other performs error correction and detection decoding on the second data.

[0129] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

[0130] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention.

Claims

1. A pulse neuron reinforcement circuit, characterized in that: It includes a first register group, a second register group, a third register group, an encoding module, a decoding module, a logic module, and a configurable pulse neuron computing unit; The encoding module is used to encode the first data and / or the second data input from the external or logical module; The encoding module adopts ECC encoding method; The first register group is used to store the encoded first data; The second register group is used to store the encoded second data; The third register group is used to directly store the first data and / or the second data; The third register group is spatially isolated from the first register group and the second register group in a cross layout manner, and the spatial distance between the third register group and the first register group and the second register group is determined according to the spatial environment in which the configurable pulse neuron computing unit operates; The decoding module is used to perform error correction and detection decoding on the encoded first data and / or second data, and record the decoding result; the encoding method of the encoding module corresponds to the decoding method of the decoding module; The logic module selects the decoded first data and / or second data to output to the configurable pulse neuron calculation unit according to the decoding result, or selects the first data and / or second data in the third register group to output to the configurable pulse neuron calculation unit and the encoding module; The configurable pulse neuron computing unit is configured using the input first data and / or second data.

2. The pulse neuron reinforcement circuit according to claim 1, characterized in that: The first data is configuration information, and the second data is model parameters.

3. The pulse neuron reinforcement circuit according to claim 2, characterized in that: The configurable pulse neuron computing unit generates LIF neurons, Izhikevich neurons, or Hodgkin-Huxley neurons using configuration information.

4. The pulse neuron reinforcement circuit according to claim 2, characterized in that: The configurable pulse neuron calculation unit generates a corresponding pulse signal of excited or inhibited neuron discharge using the model parameters.

5. The pulse neuron reinforcement circuit according to any one of claims 1 to 4, characterized in that: The third register group is independently reinforced to reduce the impact of spatial single event effects.

6. The pulse neuron reinforcement circuit according to claim 1, characterized in that: The space environment includes the space orbit altitude, space radiation environment, and the spatial layout of the three register groups.

7. The pulse neuron reinforcement circuit according to any one of claims 1 to 4, characterized in that: When the decoding module performs error correction and detection decoding, it corrects single-bit errors and detects multiple-bit errors on the input data.

8. The pulse neuron reinforcement circuit according to any one of claims 1 to 4, characterized in that: When the decoding result is a multi-bit error, the logic module selects the first data and the second data in the third register group, and outputs them to the configurable pulse neuron calculation unit and the encoding module.

9. The pulse neuron reinforcement circuit according to any one of claims 1 to 4, characterized in that: The encoding module includes a first encoding module and a second encoding module. The first encoding module is used to encode first data input from an external or logical module; the second encoding module is used to encode second data input from an external or logical module.

10. The pulse neuron reinforcement circuit according to any one of claims 1 to 4, characterized in that: The decoding module includes a first decoding module and a second decoding module. The first decoding module is used to perform error correction decoding on first data input from an external or logic module; the second decoding module is used to perform error correction decoding on second data input from an external or logic module.

11. The pulse neuron reinforcement circuit according to any one of claims 1 to 4, characterized in that: The encoding method of the encoding module and the decoding method of the decoding module use different encoding and decoding bit numbers according to different neuron models to perform multi-bit error correction and multi-bit error detection on the input data.

12. A pulse neuron reinforcement method, characterized in that: The steps include: Originally storing the first data and / or the second data input from the outside, and encoding the input first data and / or the second data; The encoded first data and second data are stored separately; performing error correction and detection decoding on the encoded first data and / or second data; When there are fewer erroneous data during decoding, the erroneous data is corrected and then used to configure the spiking neurons; When there are many erroneous data during decoding, the original stored data is used to configure the pulse neurons, and the corresponding erroneous data before encoding is replaced by the original stored data; The original storage is isolated from the encoded storage space using a cross layout, and the spatial isolation distance is determined according to the spatial environment in which the spiking neurons work; Adopt ECC encoding and ECC decoding methods.

13. The pulse neuron reinforcement method according to claim 12, characterized in that: The first data is configuration information, which can configure the pulse neuron to generate a LIF neuron, an Izhikevich neuron, or a Hodgkin-Huxley neuron.

14. The pulse neuron reinforcement method according to claim 12, characterized in that: The second data is a model parameter, which can configure the pulse neuron to generate a corresponding pulse signal for exciting or inhibiting neuronal discharge.

15. The pulse neuron reinforcement method according to any one of claims 12 to 14, characterized in that: The original storage is independently reinforced to reduce the impact of spatial single-particle effects.

16. The pulse neuron reinforcement method according to claim 14, characterized in that: The space environment includes the space orbit altitude, space radiation environment, and space isolation layout.

17. The pulse neuron reinforcement method according to any one of claims 12 to 14, characterized in that: During error correction and detection decoding, single-bit error correction and multi-bit error detection are performed on the input data.

18. The pulse neuron reinforcement method according to any one of claims 12 to 14, characterized in that: When multiple bit errors occur during decoding, the spiking neurons are configured using the original stored data.

19. The pulse neuron reinforcement method according to any one of claims 12 to 14, characterized in that: The encoding method matches the decoding method, and different encoding and decoding bit numbers are used according to different neuron models to perform multi-bit error correction and multi-bit error detection on the input data.

20. The pulse neuron reinforcement method according to any one of claims 12 to 14, characterized in that: Two encoding circuits are used, one of which encodes the first data and the other encodes the second data.

21. The pulse neuron reinforcement method according to any one of claims 12 to 14, characterized in that: Two decoding circuits are used, one of which performs error correction and detection decoding on the first data, and the other performs error correction and detection decoding on the second data.

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