GOA circuit and display panel
By introducing multi-stage cascaded GOA units and high-resistance wire connections into the GOA circuit, the leakage current problem in the pull-up stage is solved, ensuring the stable output of the gate drive signal and the normal operation of the pull-down stage.
Patent Information
- Application Number
- CN202210167275.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-02-23
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2042-02-23
Smart Images
Figure CN114530113B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of display technology, and in particular to a GOA circuit and a display panel. Background Art
[0002] GOA (Gate Driver On Array) technology refers to integrating the gate drive circuit of the display panel on the glass substrate to scan the display panel line by line. Since GOA technology can reduce the binding process of external ICs and reduce product costs, it is now widely used.
[0003] like Figure 1 As shown, in the pull-up stage of the GOA circuit, the pull-up node Q is at a high potential, and the pull-up node Q has several leakage current paths, such as Figure 1 In the GOA circuit shown, the pull-up node Q is connected to NT1, NT2, NT5 and NT7. In the pull-up stage, the pull-up node Q is at a high potential, NT1 and NT7 are in an open state, NT2 and NT5 are in a closed state, and the path of the leakage circuit of the pull-up node Q is NT2 and NT5. It should be noted that during the forward scan, NT2 is in a closed state for a long time, so that NT2 is negatively biased, and the threshold voltage of NT2 will shift negatively, resulting in a decrease in the off-state leakage current of NT2; while NT5 is in an open state for a long time, so that NT5 is forward biased, and the threshold voltage of NT5 will shift positively, resulting in an increase in the off-state leakage current of NT5, that is, the off-state leakage current of NT5 is large in the pull-up stage, resulting in a decrease in the potential of the pull-up node Q, so that NT9 is not fully opened, affecting the output stability of the gate drive signal G(N).
[0004] Therefore, it is necessary to Figure 1 The leakage path of NT5 in the conventional GOA circuit shown is improved so that the pull-up node Q can stably maintain a high potential during the pull-up stage, so that the GOA circuit can normally output a gate driving signal. Summary of the invention
[0005] In order to solve the above problems, an embodiment of the present invention provides a GOA circuit, including multiple cascaded GOA units, each level of GOA unit includes: a forward and reverse scanning module, a pull-up module and a first node pull-down module;
[0006] The forward and reverse scanning module is connected to the N-2-th level gate driving signal terminal, the N+2-th level gate driving signal terminal, the forward scanning terminal, the reverse scanning terminal and the first node, and is used to pull up the potential of the first node through the forward scanning terminal or the reverse scanning terminal under the control of the N-2-th level gate driving signal terminal and the N+2-th level gate driving signal terminal;
[0007] The pull-up module is connected to the first node, the Nth level clock signal terminal and the Nth level gate driving signal terminal, and is used to output the Nth level gate driving signal through the Nth level clock signal terminal under the control of the first node;
[0008] The first node pull-down module is connected to the second node, and the first node and the constant voltage low potential end are used to maintain the potential of the first node at a constant voltage low potential through the constant voltage low potential end under the control of the second node; wherein the first node pull-down module is respectively connected to the first node and the constant voltage low potential end through a high-resistance wire.
[0009] In some embodiments, the high-resistance wire is made of a conductive polymer material or a conductive high molecular material.
[0010] In some embodiments, the resistance value of the high-resistance wire is 1-18KΩ.
[0011] In some embodiments, the forward and reverse scanning module includes a first transistor and a second transistor;
[0012] The gate of the first transistor is connected to the N-2th stage gate driving signal terminal, the source of the first transistor is connected to the forward scanning terminal, and the drain of the first transistor is connected to the first node;
[0013] The gate of the second transistor is connected to the N+2th stage gate driving signal terminal, the source of the second transistor is connected to the reverse scanning terminal, and the drain of the second transistor is connected to the first node.
[0014] In some embodiments, the pull-up module includes a ninth transistor, the gate of the ninth transistor is connected to the third node, the source of the ninth transistor is connected to the Nth level clock signal terminal, and the drain of the ninth transistor is connected to the Nth level gate drive signal terminal.
[0015] In some embodiments, the first node pull-down module includes a fifth transistor, a gate of the fifth transistor is connected to the second node, a source of the fifth transistor is connected to the constant voltage low potential end, and a drain of the fifth transistor is connected to the first node.
[0016] In some embodiments, each level of the GOA unit further includes a second node pull-up module, wherein the second node pull-up module includes a third transistor, a fourth transistor, and an eighth transistor.
[0017] The gate of the third transistor is connected to the forward scanning end, the source of the third transistor is connected to the N+2th level clock signal end, and the drain of the third transistor and the drain of the fourth transistor are connected to the gate of the eighth transistor;
[0018] The gate of the fourth transistor is connected to the reverse scanning terminal, and the source of the fourth transistor is connected to the N-2th level clock signal terminal;
[0019] The source of the eighth transistor is connected to the constant voltage high potential end, and the drain of the eighth transistor is connected to the second node.
[0020] In some embodiments, each level of GOA unit also includes a second node pull-down module, the second node pull-down module includes a sixth transistor, the gate of the sixth transistor is connected to the drain of the second transistor and the first node, the source of the sixth transistor is connected to the constant voltage low potential end, and the drain of the sixth transistor is connected to the second node.
[0021] In some embodiments, each level of GOA unit also includes a gate drive signal pull-down module, the gate drive signal pull-down module includes a tenth transistor, the gate of the tenth transistor is connected to the second node, the source of the tenth transistor is connected to the Nth level gate drive signal terminal, and the drain of the tenth transistor is connected to the constant voltage low potential terminal.
[0022] In some embodiments, each level of GOA unit also includes a first voltage stabilizing module, the first voltage stabilizing module includes a seventh transistor and a first capacitor, the gate of the seventh transistor is connected to the constant voltage high potential end, the source of the seventh transistor is connected to the first node, and the drain of the seventh transistor is connected to the third node; the first capacitor is coupled between the first node and the constant voltage low potential end.
[0023] In some embodiments, each level of the GOA unit further includes a second voltage stabilizing module, the second voltage stabilizing module includes a second capacitor, and the second capacitor is coupled between the second node and the constant voltage low potential end.
[0024] In some embodiments, each level of the GOA unit further includes a gate drive signal fully-on module, wherein the gate drive signal fully-on module includes an eleventh transistor and a twelfth transistor;
[0025] The gate of the eleventh transistor, the drain of the eleventh transistor and the gate of the twelfth transistor are connected to the full-on control signal terminal, and the source of the eleventh transistor is connected to the Nth stage gate drive signal terminal;
[0026] The source of the twelfth transistor is connected to the constant voltage low potential end, and the drain of the twelfth transistor is connected to the second node.
[0027] In some embodiments, each level of GOA unit also includes a gate drive signal full-off module, and the gate drive signal full-off module includes a thirteenth transistor, the gate of the thirteenth transistor is connected to the full-off control signal terminal, the source of the thirteenth transistor is connected to the constant voltage low potential terminal, and the drain of the thirteenth transistor is connected to the second node.
[0028] In addition, an embodiment of the present invention further provides a display panel, comprising the GOA circuit as described above.
[0029] In the GOA circuit and display panel provided by the embodiments of the present invention, each level of GOA unit includes a forward and reverse scanning module, a pull-up module and a first node pull-down module connected to the first node. Since the first node of each level of GOA unit is pulled up when the GOA unit of this level outputs a gate drive signal, the first node pull-down module of the GOA unit of this level is in a non-working state during the pre-charging stage and the pull-up stage of the GOA unit of this level, so that the first node of the GOA unit of this level maintains a high potential, wherein the first node pull-down module is respectively connected to the first node and the constant voltage low potential end through a high-resistance wire, which can make the off-state leakage current of the first node pull-down module in the pre-charging stage and the pull-up stage smaller, thereby helping the first node to maintain a stable high potential, so that the pull-up module enables the GOA unit of this level to smoothly output the gate drive signal during the pull-up stage. At the same time, during forward scanning, the reverse scanning module can pull down the first node in the pull-down stage, and the first node pull-down module is in a working state in the pull-down stage and the pull-down maintaining stage, so that the first node can continue to maintain a low potential. Therefore, the first node pull-down module is connected to the first node and the constant voltage low potential end respectively through a high-resistance wire, which will not affect the normal output of the gate drive signal by the next-level GOA unit. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.
[0031] Figure 1 It is a structural schematic diagram of a GOA circuit of the prior art;
[0032] Figure 2 A schematic diagram of the structure of a GOA circuit provided in an embodiment of the present invention;
[0033] Figure 3 A timing diagram of a GOA circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0034] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
[0035] All embodiments of the present invention distinguish the two poles of the thin film transistor except the gate, and one of the poles is called the source and the other is called the drain. Since the source and drain of the thin film transistor are symmetrical, the source and drain are interchangeable. According to the form in the accompanying drawings, the middle end of the thin film transistor is defined as the gate, the signal input end is the source, and the signal output end is the drain. In addition, the thin film transistors used in all embodiments of the present invention may include P-type and / or N-type transistors, wherein the P-type thin film transistor is turned on when the gate is at a low potential and is turned off when the gate is at a high potential; the N-type thin film transistor is turned on when the gate is at a high potential and is turned off when the gate is at a low potential.
[0036] like Figure 2 As shown, an embodiment of the present invention provides a GOA circuit, including multiple stages of cascaded GOA units, each stage of the GOA unit includes: a forward and reverse scanning module 100, a pull-up module 200 and a first node pull-down module 300;
[0037] The forward and reverse scanning module 100 is connected to the N-2-stage gate driving signal terminal G(N-2), the N+2-stage gate driving signal terminal G(N+2), the forward scanning terminal U2D, the reverse scanning terminal D2U and the first node Q1, and is used to pull up the potential of the first node Q1 through the forward scanning terminal U2D or the reverse scanning terminal D2U under the control of the N-2-stage gate driving signal terminal G(N-2) and the N+2-stage gate driving signal terminal G(N+2);
[0038] The pull-up module 200 is connected to the first node Q1, the N-th clock signal terminal CK(N) and the N-th gate drive signal terminal G(N), and is used to output the N-th gate drive signal G(N) through the N-th clock signal terminal CK(N) under the control of the first node Q1;
[0039] The first-node pull-down module 300 is connected to the second node Q2, the first node Q1 and the constant-voltage low-potential end VGL, and is used to maintain the potential of the first node Q1 as a constant-voltage low-potential through the constant-voltage low-potential end VGL under the control of the second node Q2; wherein the first-node pull-down module 300 is connected to the first node Q1 and the constant-voltage low-potential end VGL respectively through high-resistance wires R1 and R2.
[0040] In the GOA circuit provided by the embodiment of the present invention, each level of GOA unit includes a forward and reverse scanning module 100, a pull-up module 200 and a first node pull-down module 300 connected to the first node Q1. Since the first node Q1 of each level of GOA unit is pulled up when the GOA unit of this level outputs the gate drive signal G(N), the first node pull-down module 300 of the GOA unit of this level is in a non-working state during the pre-charging stage and the pull-up stage of the GOA unit of this level, so that the first node Q1 of the GOA unit of this level is maintained at a high potential, wherein the first node pull-down module 300 is respectively connected to the first node Q1 and the constant voltage low potential end VGL through a high-resistance wire, which can make the off-state leakage current of the first node pull-down module 300 in the pre-charging stage and the pull-up stage smaller, thereby helping the first node Q1 to maintain a stable high potential, so that the pull-up module 200 enables the GOA unit of this level to smoothly output the gate drive signal during the pull-up stage. At the same time, during forward scanning, the reverse scanning module can pull down the first node Q1 in the pull-down stage, and the first node pull-down module 300 is in a working state in the pull-down stage and the pull-down maintaining stage, so that the first node Q1 can continue to maintain a low potential. Therefore, the first node pull-down module 300 is connected to the first node Q1 and the constant voltage low potential terminal VGL respectively through a high-resistance wire, which will not affect the normal output of the gate drive signal by the next-level GOA unit.
[0041] Figure 2 In the embodiment, the first node pull-down module 300 is connected to the first node Q1 through the high resistance wire R1, and is connected to the constant voltage low potential end VGL through the high resistance wire R2.
[0042] Wherein, the high-resistance wire is made of conductive polymer material or conductive high molecular material; the resistance value of the high-resistance wire is 1-18KΩ.
[0043] Specifically, conductive polymers generally refer to conductive macromolecules, which are polymer materials with a conjugated main electron system in the main chain, which can be made conductive by doping, and have a conductivity of more than 1000S / cm. Conductive polymer materials are a type of polymer material with conductivity, which can be a polymer material that has a conductive function itself or has a conductive function after being doped with other materials, or can be filled with composite materials, or surface mixed or laminated with ordinary polymer materials and various conductive materials to obtain conductivity. High-resistance wires are made of conductive polymer materials or conductive macromolecular materials, and their resistance is relatively large, generally in the order of kilo-ohms. The resistance value of the high-resistance wire in the embodiment of the present invention is 1-18KΩ.
[0044] In some embodiments, the forward and reverse scanning module 100 includes a first transistor T1 and a second transistor T2; the gate of the first transistor T1 is connected to the N-2 level gate drive signal terminal G(N-2), the source of the first transistor T1 is connected to the forward scanning terminal U2D, and the drain of the first transistor T1 is connected to the first node Q1; the gate of the second transistor T2 is connected to the N+2 level gate drive signal terminal G(N+2), the source of the second transistor T2 is connected to the reverse scanning terminal D2U, and the drain of the second transistor T2 is connected to the first node Q1.
[0045] In some embodiments, the pull-up module 200 includes a ninth transistor T9, the gate of the ninth transistor T9 is connected to the third node Q3, the source of the ninth transistor T9 is connected to the Nth level clock signal terminal CK(N), and the drain of the ninth transistor T9 is connected to the Nth level gate drive signal terminal G(N).
[0046] In some embodiments, the first node pull-down module 300 includes a fifth transistor T5, a gate of the fifth transistor T5 is connected to the second node Q2, a source of the fifth transistor T5 is connected to the constant voltage low potential terminal VGL, and a drain of the fifth transistor T5 is connected to the first node Q1.
[0047] In some embodiments, each level of GOA unit also includes a second node pull-up module 400, and the second node pull-up module 400 includes a third transistor T3, a fourth transistor T4 and an eighth transistor T8, the gate of the third transistor T3 is connected to the forward scan terminal U2D, the source of the third transistor T3 is connected to the N+2-level clock signal terminal CK(N+2), the drain of the third transistor T3 and the drain of the fourth transistor T4 are connected to the gate of the eighth transistor T8; the gate of the fourth transistor T4 is connected to the reverse scan terminal D2U, and the source of the fourth transistor T4 is connected to the N-2-level clock signal terminal CK(N-2); the source of the eighth transistor T8 is connected to the constant voltage high potential terminal VGH, and the drain of the eighth transistor T8 is connected to the second node Q2.
[0048] In some embodiments, each level of GOA unit also includes a second node pull-down module 500, the second node pull-down module 500 includes a sixth transistor T6, the gate of the sixth transistor T6 is connected to the drain of the second transistor T2 and the first node Q1, the source of the sixth transistor T6 is connected to the constant voltage low potential terminal VGL, and the drain of the sixth transistor T6 is connected to the second node Q2.
[0049] In some embodiments, each level of GOA unit also includes a gate drive signal pull-down module 1000, the gate drive signal pull-down module 1000 includes a tenth transistor T10, the gate of the tenth transistor T10 is connected to the second node Q2, the source of the tenth transistor T10 is connected to the Nth level gate drive signal terminal G(N), and the drain of the tenth transistor T10 is connected to the constant voltage low potential terminal VGL.
[0050] In some embodiments, each level of GOA unit also includes a first voltage stabilizing module 600, the first voltage stabilizing module 600 includes a seventh transistor T7 and a first capacitor C1, the gate of the seventh transistor T7 is connected to the constant voltage high potential end VGH, the source of the seventh transistor T7 is connected to the first node Q1, and the drain of the seventh transistor T7 is connected to the third node Q3; the first capacitor C1 is coupled between the first node Q1 and the constant voltage low potential end VGL.
[0051] In some embodiments, each stage of the GOA unit further includes a second voltage stabilizing module 700 , wherein the second voltage stabilizing module 700 includes a second capacitor C2 , and the second capacitor C2 is coupled between the second node Q2 and the constant voltage low potential terminal VGL.
[0052] Based on the above embodiments, combined with Figure 2 and Figure 3 As shown, if the transistors in the GOA circuit are all N-type thin film transistors, the specific work flow of each level of the GOA unit of the GOA circuit includes a pre-charge stage t0, a pull-up stage t1, a pull-down stage t2 and a pull-down maintenance stage t3, wherein:
[0053] In the pre-charge stage t0: CK(N-2) and G(N-2) are at high potential, T1 is turned on, U2D pulls Q1 up to high potential through T1, T7 is normally open, making Q3 also at high potential, making T9 turned on, and C1 is charged at the same time. In addition, Q1 turns on T6, making Q2 at low potential.
[0054] In the pull-up stage t1: CK(N-2) and G(N-2) are at low potential, T1 is closed, and C1 keeps Q1 at high potential. CK(N) is at high potential, so that G(N) outputs high potential, and due to the coupling effect of the gate-source parasitic capacitance of T9, the potential of Q3 further increases with CK(N), which can make T9 open more thoroughly, wherein T7 is in a normally open state, which is used to make the potential of Q1 not higher than the potential of Q3, so as to ensure that when the potential of Q3 further increases to higher than Q1, the potential of Q3 can remain stable. It should be noted that at this time, T2 and T5 are both in a closed state, and T5 is connected to Q1 through a high-resistance wire R1, and is connected to VGL through a high-resistance wire R2. The resistance of the high-resistance wire R1 and the high-resistance wire R2 is large, thereby reducing the leakage current of Q1 through T5, which can keep Q1 at a stable high potential, so that Q3 can maintain a stable high potential.
[0055] In the pull-down stage t2: CK(N+2) and G(N+2) are at high potential, so that T3 and T2 are turned on, D2U pulls down the potential of Q1 through T2, and at the same time U2D turns on T8 through T3, VGH pulls up the potential of Q2, so that T5 and T10 are turned on, and C2 is charged, T5 keeps Q1 at a low potential, and T10 makes G(N) at a low potential.
[0056] In the pull-down maintenance phase t3: C2 keeps Q2 at a high potential, so that T5 and T10 remain turned on, T5 keeps Q1 at a low potential, and T10 keeps G(N) at a low potential.
[0057] It should be noted that, from the waveform simulation diagram of the potential and drive signal of the above-mentioned key nodes obtained through experiments, it can be seen that when the resistance value of the high-resistance wire used by T5 varies in the range of 1-18KΩ, the waveform of the potential of the key node and the drive signal almost overlaps together. It can be seen that the use of a high-resistance wire by T5 will not affect the actual changes of the key nodes and the drive signal, and can enable the GOA circuit to output the gate drive signal normally.
[0058] In some embodiments, each level of GOA unit also includes a gate drive signal fully-on module 800, and the gate drive signal fully-on module 800 includes an eleventh transistor T11 and a twelfth transistor T12; the gate of the eleventh transistor T11, the drain of the eleventh transistor T11 and the gate of the twelfth transistor T12 are connected to the fully-on control signal terminal Gas1, and the source of the eleventh transistor T11 is connected to the N-th level gate drive signal terminal G(N); the source of the twelfth transistor T12 is connected to the constant voltage low potential terminal VGL, and the drain of the twelfth transistor T12 is connected to the second node Q2.
[0059] It should be noted that before the display panel wakes up from a black screen, it is usually necessary to open all the output ends of the GOA units at all levels within a period of time, so that the gate drive signals all output high potentials, turn on the thin film transistors in all pixels in the display panel, and apply black voltage to all pixels through data signals to clear the residual leakage charge in the display panel, thereby realizing the all gate on function to prevent the display panel from having residual images. Therefore, the gate drive signal full-on module of each level of the GOA unit in the embodiment of the present invention is used to realize this function.
[0060] Specifically, before the display panel wakes up from a black screen, Gas1 is set to a high potential to turn on T11 and T12 of each level of GOA unit. T11 makes G(N) a high potential, and T12 makes Q2 a low potential, thereby turning off T5 and T10 and preventing T10 from pulling down G(N).
[0061] In some embodiments, each level of GOA unit also includes a gate drive signal full-off module 900, and the gate drive signal full-off module 900 includes a thirteenth transistor T13, the gate of the thirteenth transistor T13 is connected to the full-off control signal terminal Gas2, the source of the thirteenth transistor T13 is connected to the constant voltage low potential terminal VGL, and the drain of the thirteenth transistor T13 is connected to the second node Q2.
[0062] It should be noted that when the display panel is a touch screen, before the touch signal arrives, the gate drive signal needs to be turned off to prevent the gate drive signal and the touch signal from affecting each other. Therefore, the gate drive signal full-on module of each GOA unit in the embodiment of the present invention is used to achieve this function.
[0063] Specifically, before the touch signal arrives, Gas2 is set to a high potential, so that T13 of each level of GOA unit is turned on, thereby pulling down G(N).
[0064] Based on the above embodiments, an embodiment of the present invention further provides a display panel, which includes the GOA circuit as described above. The display panel has the same structure and beneficial effects as the GOA circuit. Since the above embodiments have already described the GOA circuit in detail, it will not be repeated here.
[0065] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0066] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A GOA circuit, It is characterized in that It includes a multi-stage cascaded GOA unit, each stage of the GOA unit includes: a forward and reverse scanning module, a pull-up module and a first node pull-down module; The forward and reverse scanning module is connected to the N-2-th level gate driving signal terminal, the N+2-th level gate driving signal terminal, the forward scanning terminal, the reverse scanning terminal and the first node, and is used to pull up the potential of the first node through the forward scanning terminal or the reverse scanning terminal under the control of the N-2-th level gate driving signal terminal and the N+2-th level gate driving signal terminal; The pull-up module is connected to the first node, the Nth level clock signal terminal and the Nth level gate driving signal terminal, and is used to output the Nth level gate driving signal through the Nth level clock signal terminal under the control of the first node; The first node pull-down module is connected to the second node, and the first node and the constant voltage low potential end are used to maintain the potential of the first node at a constant voltage low potential through the constant voltage low potential end under the control of the second node; wherein the first node pull-down module is respectively connected to the first node and the constant voltage low potential end through a high-resistance wire; The first node pull-down module comprises a fifth transistor, the gate of the fifth transistor is connected to the second node, the source of the fifth transistor is connected to the constant voltage low potential end, and the drain of the fifth transistor is connected to the first node; The high-resistance wire is made of conductive polymer material or conductive high molecular material.
2. The GOA circuit according to claim 1, It is characterized in that The resistance value of the high-resistance wire is 1-18KΩ.
3. The GOA circuit as claimed in claim 1, It is characterized in that The forward and reverse scanning module includes a first transistor and a second transistor; The gate of the first transistor is connected to the N-2th stage gate driving signal terminal, the source of the first transistor is connected to the forward scanning terminal, and the drain of the first transistor is connected to the first node; The gate of the second transistor is connected to the N+2th stage gate driving signal terminal, the source of the second transistor is connected to the reverse scanning terminal, and the drain of the second transistor is connected to the first node.
4. The GOA circuit according to claim 1, It is characterized in that The pull-up module includes a ninth transistor, a gate of the ninth transistor is connected to the third node, a source of the ninth transistor is connected to the Nth stage clock signal terminal, and a drain of the ninth transistor is connected to the Nth stage gate drive signal terminal.
5. The GOA circuit as claimed in claim 1, It is characterized in that Each level of GOA unit also includes a second node pull-up module, wherein the second node pull-up module includes a third transistor, a fourth transistor and an eighth transistor. The gate of the third transistor is connected to the forward scanning end, the source of the third transistor is connected to the N+2th level clock signal end, and the drain of the third transistor and the drain of the fourth transistor are connected to the gate of the eighth transistor; The gate of the fourth transistor is connected to the reverse scanning terminal, and the source of the fourth transistor is connected to the N-2th level clock signal terminal; The source of the eighth transistor is connected to the constant voltage high potential end, and the drain of the eighth transistor is connected to the second node.
6. The GOA circuit as claimed in claim 3, It is characterized in that Each level of GOA unit also includes a second node pull-down module, the second node pull-down module includes a sixth transistor, the gate of the sixth transistor is connected to the drain of the second transistor and the first node, the source of the sixth transistor is connected to the constant voltage low potential end, and the drain of the sixth transistor is connected to the second node.
7. The GOA circuit according to claim 1, It is characterized in that Each level of GOA unit also includes a gate drive signal pull-down module, the gate drive signal pull-down module includes a tenth transistor, the gate of the tenth transistor is connected to the second node, the source of the tenth transistor is connected to the Nth level gate drive signal terminal, and the drain of the tenth transistor is connected to the constant voltage low potential terminal.
8. The GOA circuit as claimed in claim 4, It is characterized in that Each level of the GOA unit also includes a first voltage stabilizing module, wherein the first voltage stabilizing module includes a seventh transistor and a first capacitor; The gate of the seventh transistor is connected to the constant voltage high potential terminal, the source of the seventh transistor is connected to the first node, and the drain of the seventh transistor is connected to the third node; The first capacitor is coupled between the first node and the constant voltage low potential terminal.
9. The GOA circuit according to claim 1, It is characterized in that Each level of the GOA unit further includes a second voltage stabilizing module, the second voltage stabilizing module includes a second capacitor, and the second capacitor is coupled between the second node and the constant voltage low potential end.
10. The GOA circuit according to claim 1, It is characterized in that Each level of the GOA unit also includes a gate drive signal full-on module, and the gate drive signal full-on module includes an eleventh transistor and a twelfth transistor; The gate of the eleventh transistor, the drain of the eleventh transistor and the gate of the twelfth transistor are connected to the full-on control signal terminal, and the source of the eleventh transistor is connected to the Nth stage gate drive signal terminal; The source of the twelfth transistor is connected to the constant voltage low potential end, and the drain of the twelfth transistor is connected to the second node.
11. The GOA circuit according to claim 1, It is characterized in that Each level of GOA unit also includes a gate drive signal full-off module, and the gate drive signal full-off module includes a thirteenth transistor, the gate of the thirteenth transistor is connected to the full-off control signal terminal, the source of the thirteenth transistor is connected to the constant voltage low potential terminal, and the drain of the thirteenth transistor is connected to the second node.
12. A display panel, It is characterized in that The GOA circuit comprises the GOA circuit described in any one of claims 1-11.
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