Pixel circuit, driving method and display device

Abstract

The invention provides a pixel circuit, a driving method and a display device. The pixel circuit comprises a light-emitting element, a driving circuit, an on-off control circuit, a first energy storage circuit and a data write-in circuit. The on-off control circuit controls the connection or disconnection between the first node and the second node under the control of the on-off control signal; the first energy storage circuit is electrically connected with the second node and the write-in node; the data write circuit provides a data voltage to a write node under the control of a scan signal. According to the invention, the first node and the second node can be controlled to be disconnected through the on-off control circuit under the control of the on-off control signal in the light emitting stage, so that the potential of the first node is not influenced by the floating write-in node, the potential of the first node is stable, and the display uniformity is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a driving method and a display device. Background Art

[0002] In the relevant pixel circuit, during the light-emitting stage, the potential of the first node is affected by the floating write node, making the potential of the first node unstable. The first node is electrically connected to the gate of the driving transistor included in the driving circuit in the pixel circuit, thereby affecting display uniformity. Summary of the invention

[0003] The main purpose of the present invention is to provide a pixel circuit, a driving method and a display device to solve the problem in the prior art that during the light-emitting stage, the potential of the first node is affected by the floating write node, making the potential of the first node unstable, thereby affecting the display uniformity.

[0004] In one aspect, an embodiment of the present invention provides a pixel circuit, including a light-emitting element, a driving circuit, an on-off control circuit, a first energy storage circuit, and a data writing circuit;

[0005] The control end of the driving circuit is electrically connected to the first node, and the driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node;

[0006] The on-off control circuit is electrically connected to the on-off control terminal, the first node and the second node respectively, and is used to control the connection or disconnection between the first node and the second node under the control of the on-off control signal provided by the on-off control terminal;

[0007] The first energy storage circuit is electrically connected to the second node and the write node respectively;

[0008] The data writing circuit is electrically connected to the scanning end, the data line and the writing node respectively, and is used to provide the data voltage provided by the data line to the writing node under the control of the scanning signal provided by the scanning end.

[0009] The pixel circuit described in at least one embodiment of the present invention further includes a second energy storage circuit and a bias control circuit;

[0010] The first end of the second energy storage circuit is electrically connected to the first node, and the second end of the second energy storage circuit is electrically connected to the third node;

[0011] The bias control circuit is electrically connected to the bias control terminal, the bias voltage terminal and the third node respectively, and is used to write the bias voltage provided by the bias voltage terminal into the third node under the control of the bias control signal provided by the bias control terminal.

[0012] The pixel circuit described in at least one embodiment of the present invention further includes a first control circuit;

[0013] The first control circuit is electrically connected to the first control terminal, the first voltage terminal and the third node respectively, and is used to control the connection or disconnection between the first voltage terminal and the third node under the control of a first control signal provided by the first control terminal.

[0014] The pixel circuit described in at least one embodiment of the present invention further includes a second energy storage circuit;

[0015] The second energy storage circuit is electrically connected to the first node, and is used to maintain the potential of the first node.

[0016] The pixel circuit described in at least one embodiment of the present invention further includes a first initialization circuit, a second initialization circuit and a compensation control circuit;

[0017] The first terminal of the driving circuit is electrically connected to the first voltage terminal, and the second terminal of the driving circuit is electrically connected to the fourth node;

[0018] The first initialization circuit is electrically connected to the first reset control terminal and the first initial voltage terminal respectively, and is also electrically connected to the first node or the fourth node. The first initialization circuit is used to write the first initial voltage provided by the first initial voltage terminal into the first node or the fourth node under the control of the first reset control signal provided by the first reset control terminal;

[0019] The second initialization circuit is electrically connected to the second reset control terminal, the reference voltage terminal and the write node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the write node under the control of the second reset control signal provided by the second reset control terminal;

[0020] The compensation control circuit is electrically connected to the compensation control terminal, the first node and the fourth node respectively, and is used to control the connection or disconnection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal.

[0021] The pixel circuit described in at least one embodiment of the present invention further includes a light emitting control circuit and a third initialization circuit; the first end of the driving circuit is electrically connected to the first voltage end, and the second end of the driving circuit is electrically connected to the fourth node;

[0022] The light emitting control circuit is electrically connected to the light emitting control terminal, the fourth node and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the fourth node and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal;

[0023] The third initialization circuit is electrically connected to the third reset control terminal, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal;

[0024] The second electrode of the light emitting element is electrically connected to the second voltage terminal.

[0025] Optionally, the on-off control circuit includes a first transistor; the first energy storage circuit includes a first capacitor, and the data writing circuit includes a second transistor;

[0026] The gate of the first transistor is electrically connected to the on / off control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second node;

[0027] A first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the write node;

[0028] A gate of the second transistor is electrically connected to the scan end, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the write node.

[0029] Optionally, the second energy storage circuit includes a second capacitor, and the bias control circuit includes a third transistor;

[0030] A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to a third node;

[0031] The gate of the third transistor is electrically connected to the bias control terminal, the first electrode of the third transistor is electrically connected to the bias voltage terminal, and the second electrode of the third transistor is electrically connected to the third node.

[0032] Optionally, the first control circuit includes a fourth transistor;

[0033] The gate of the fourth transistor is electrically connected to the first control terminal, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the third node.

[0034] In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above-mentioned pixel circuit, wherein the display cycle of the pixel circuit includes a light-emitting phase; the driving method includes:

[0035] In the light-emitting stage, the on-off control circuit controls the first node and the second node to be disconnected under the control of the on-off control signal.

[0036] Optionally, the pixel circuit further includes a second energy storage circuit and a bias control circuit; the display cycle further includes a bias phase arranged before the light emitting phase; and the driving method further includes:

[0037] In the bias phase, the bias control circuit writes a bias voltage into the third node under the control of a bias control signal.

[0038] Optionally, the pixel circuit further includes a first control circuit; and the driving method further includes:

[0039] In the bias phase, the first control circuit controls the first voltage terminal and the third node to be disconnected under the control of the first control signal.

[0040] Optionally, the display cycle includes a data writing phase arranged in the bias phase; and the driving method further includes:

[0041] In the data writing stage, the data writing circuit provides the data voltage provided by the data line to the writing node under the control of the scanning signal provided by the scanning end, and the on-off control circuit controls the connection between the first node and the third node under the control of the on-off control signal.

[0042] Optionally, the display cycle further includes a compensation phase; the compensation phase is independent of the data writing phase; the pixel circuit further includes a second initialization circuit and a compensation control circuit; the driving method further includes:

[0043] In the compensation stage, the on-off control circuit controls the connection between the first node and the third node under the control of the on-off control signal, the second initialization circuit provides the reference voltage provided by the reference voltage terminal to the write node under the control of the second reset control signal, and the compensation control circuit controls the connection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal.

[0044] In a third aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned pixel circuit.

[0045] The pixel circuit, driving method and display device described in the embodiments of the present invention can control the disconnection between the first node and the second node through the on-off control circuit under the control of the on-off control signal during the light-emitting stage, so that the potential of the first node is not affected by the floating write node, thereby stabilizing the potential of the first node and improving display uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1A is a circuit diagram of at least one embodiment of a pixel circuit;

[0047] Figure 1B yes Figure 1A An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0048] Figure 1C is a circuit diagram of at least one embodiment of a pixel circuit;

[0049] Figure 1D is a circuit diagram of at least one embodiment of a pixel circuit;

[0050] Figure 1E yes Figure 1D An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0051] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0052] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0053] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0054] Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0055] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0056] Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0057] Figure 8 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0058] Fig. 9 yes Figure 8 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0059] Fig.10 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0060] Fig.11 yes Fig.10 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0061] Fig.12 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0062] Fig.13 yes Fig.12An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0063] Fig.14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0064] Fig.15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0067] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0068] like Figure 1A As shown, at least one embodiment of the pixel circuit may include an organic light emitting diode O1, a driving transistor T0, a second transistor T2, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1 and a second capacitor C2;

[0069] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the power supply voltage terminal VDD, and the drain of T0 is electrically connected to the fourth node N4;

[0070] The gate of T2 is electrically connected to the scanning terminal GT, the source of T2 is electrically connected to the data line DL, the drain of T2 is electrically connected to the second end of C1; the first end of C1 is electrically connected to the first node N1; the second end of C1 is electrically connected to the write node NX;

[0071] A first end of C2 is electrically connected to the first node N1, and a second end of C2 is electrically connected to the power supply voltage terminal VDD;

[0072] The gate of T5 is electrically connected to the first reset control terminal RST1, the source of T5 is electrically connected to the first initial voltage terminal I1, and the drain of T5 is electrically connected to the fourth node N4;

[0073] The gate of T6 is electrically connected to the second reset control terminal RST2, the source of T6 is electrically connected to the reference voltage terminal REF, and the drain of T6 is electrically connected to the second terminal of C1;

[0074] The gate of T7 is electrically connected to the light emitting control terminal EM, the source of T7 is electrically connected to the fourth node N4, the drain of T7 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS;

[0075] The gate of T8 is electrically connected to the first reset control terminal RST1, the source of T8 is electrically connected to the second initial voltage terminal I2, and the drain of T8 is electrically connected to the anode of O1;

[0076] The gate of T9 is electrically connected to the second reset control terminal RST2 , the source of T9 is electrically connected to the first node N1 , and the drain of T9 is electrically connected to the fourth node N4 .

[0077] exist Figure 1A In at least one embodiment shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0078] Figure 1B yes Figure 1A An operating timing diagram of at least one embodiment of the pixel circuit shown.

[0079] Figure 1A When working, at least one embodiment of the pixel circuit shown can separate data voltage writing and threshold voltage compensation, so that the threshold voltage compensation time is not limited by the row cycle, and the threshold voltage compensation time can be increased to fully compensate the threshold voltage and power supply voltage of the driving transistor.

[0080] like Figure 1B As shown, Figure 1A When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a reset phase S1, a compensation phase S2, a data writing phase S3 and a light emitting phase S4 which are arranged in sequence;

[0081] In the reset phase S1, EM provides a high voltage signal, RST1 provides a low voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, T7 is turned off, T2 is turned off, T5 and T9 are turned on, I1 provides a first initial voltage Vinit1 to N1 and N4, T6 is turned on, REF provides a reference voltage Vref to NX, T8 is turned on, and I2 provides a second initial voltage Vinit2 to clear the residual charge on the anode of O1;

[0082] In the compensation stage S2, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, T6 is turned on, and T9 is turned on;

[0083] At the beginning of the compensation stage S2, T0 is turned on, Vref is charged through C1, T9 and the turned-on T0, and the potential of N1 is changed until the potential of N1 becomes Vdd+Vth, and T0 is turned off to complete the threshold voltage compensation; wherein Vdd is the voltage value of the power supply voltage provided by VDD, and Vth is the threshold voltage of T0;

[0084] In the data writing phase S3, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a low voltage signal, T2 is turned on, DL provides a data voltage Vdata to NX, and through the coupling effect of C1, the potential of N1 changes from Vdd+Vth to Vdd+Vth-Vref+Vdata;

[0085] In the light-emitting stage S4, EM provides a low voltage signal, RST1, RST2 and GT all provide high voltage signals, T2 and T6 are turned off, NX is in a floating state, preventing the potential of N1 from being affected by the potential of NX and keeping the potential of N1 stable; T7 is turned on, T0 drives O1 to emit light, at this time, the current value of the driving current generated by T0 to drive O1 is K×(Vdd+Vth-Vref+Vdata-Vdd-Vth) 2 =K×(Vdata-Vref) 2 ; Wherein, K is the current coefficient of T0. It can be seen that Id is independent of Vdd and Vth, and can compensate for the uneven display problem caused by the uneven driving current caused by Vdd and Vth.

[0086] Figure 1C At least one embodiment of the pixel circuit shown is Figure 1A The difference of at least one embodiment of the pixel circuit shown is as follows: the drain of T5 is electrically connected to N1.

[0087] Figure 1D At least one embodiment of the pixel circuit shown is Figure 1A The differences of at least one embodiment of the pixel circuit shown are as follows:

[0088] It also includes a bias control circuit and a first control circuit; the bias control circuit includes a third transistor T3; the first control circuit includes a fourth transistor T4;

[0089] The second end of the second capacitor C2 is electrically connected to the third node N3;

[0090] The gate of the third transistor T3 is electrically connected to the bias control terminal SP, the source of the third transistor T3 is electrically connected to the bias voltage terminal VB, and the drain of the third transistor T3 is electrically connected to the third node N3;

[0091] The gate of the fourth transistor T4 is electrically connected to the first control terminal SC, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal VDD, and the drain of the fourth transistor T4 is electrically connected to the third node N3;

[0092] T3 and T4 are p-type transistors.

[0093] like Figure 1E As shown, the present invention Figure 1D When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a reset phase S1, a compensation phase S2, a writing phase S3, a bias phase S0 and a light emitting phase S4 which are arranged in sequence;

[0094] In the reset phase S1, EM provides a high voltage signal, RST1 provides a low voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is turned off, T4 is turned on, VDD is connected to N3, T7 is turned off, T2 is turned off, T5 and T9 are turned on, I1 provides a first initial voltage Vinit1 to N1 and N4, T6 is turned on, REF provides a reference voltage Vref to NX, T8 is turned on, and I2 provides a second initial voltage Vinit2 to clear the residual charge on the anode of O1;

[0095] In the compensation stage S2, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is turned off, T4 is turned on, VDD is connected to N3, T6 is turned on, and T9 is turned on;

[0096] At the beginning of the compensation stage S2, T0 is turned on, Vref is charged through C1, T9 and the turned-on T0, and the potential of N1 is changed until the potential of N1 becomes Vdd+Vth, and T0 is turned off to complete the threshold voltage compensation; wherein Vdd is the voltage value of the power supply voltage provided by VDD, and Vth is the threshold voltage of T0;

[0097] In the data writing phase S3, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a low voltage signal, ST provides a low voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is turned off, T4 is turned on, VDD is connected to N3, T2 is turned on, DL provides a data voltage Vdata to NX, and through the coupling effect of C1, the potential of N1 changes from Vdd+Vth to Vdd+Vth-Vref+Vdata;

[0098] In the bias stage S0, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a high voltage signal, SP provides a low voltage signal, SC provides a high voltage signal, T4 is turned off, T4 is turned on, VB provides a bias voltage Vbias to N3, and the potential of N3 changes from Vdd to Vbias. Due to the coupling effect of C2, the potential of N1 changes from Vdd+Vth-Vref+Vdata to Vdd+Vth-Vref+Vdata+Vbias-Vdd, that is, to Vth-Vref+Vdata+Vbias, so as to improve the hysteresis phenomenon of T0; the bias effect on T0 can be adjusted by adjusting the voltage value of Vbias and the number of effective pulses of the bias control signal provided by SP;

[0099] In the light-emitting stage S4, EM provides a low voltage signal, RST1, RST2 and GT all provide high voltage signals, ST provides a high voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is turned off, T4 is turned on, N3 is connected to VDD, the potential of N3 changes from Vbias to Vdd, due to the coupling effect of C2, the potential of N1 changes back to Vdd+Vth-Vref+Vdata, T2 and T6 are turned off, NX is in a floating state, preventing the potential of N1 from being affected by the potential of NX and keeping the potential of N1 stable; T7 is turned on, T0 drives O1 to emit light, at this time, the current value of the driving current generated by T0 to drive O1 is K×(Vdd+Vth-Vref+Vdata-Vdd-Vth) 2 =K×(Vdata-Vref) 2 ; Wherein, K is the current coefficient of T0. It can be seen that Id is independent of Vdd and Vth, and can compensate for the uneven display problem caused by the uneven driving current caused by Vdd and Vth.

[0100] Figure 1A , Figure 1C , Figure 1D When at least one embodiment of the pixel circuit is in operation, during the light emitting stage, the potential of the first node is unstable due to the influence of the floating write node.

[0101] like Figure 2 As shown, the pixel circuit according to at least one embodiment of the present invention includes a light emitting element E1, a driving circuit 10, an on-off control circuit 11, a first energy storage circuit 12 and a data writing circuit 13;

[0102] The control end of the driving circuit 10 is electrically connected to the first node N1, and the driving circuit 10 is used to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1;

[0103] The on-off control circuit 11 is electrically connected to the on-off control terminal ST, the first node N1 and the second node N2 respectively, and is used to control the connection or disconnection between the first node N1 and the second node N2 under the control of the on-off control signal provided by the on-off control terminal ST;

[0104] The first energy storage circuit 12 is electrically connected to the second node N2 and the write node NX respectively; the first energy storage circuit 12 is used to store electrical energy;

[0105] The data writing circuit 13 is electrically connected to the scanning terminal GT, the data line DL and the writing node NX respectively, and is used to provide the data voltage provided by the data line DL to the writing node NX under the control of the scanning signal provided by the scanning terminal GT.

[0106] The present invention Figure 2 When at least one embodiment of the pixel circuit shown is in operation, a display cycle of the pixel circuit includes a light emitting phase;

[0107] In the light emitting stage, the on-off control circuit 11 controls the disconnection between the first node N1 and the second node N2 under the control of the on-off control signal, so that the potential of the first node N1 is not affected by the floating write node NX, so that the potential of the first node N1 is stable.

[0108] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a second energy storage circuit 21 and a bias control circuit 22;

[0109] The first end of the second energy storage circuit 21 is electrically connected to the first node N1, the second end of the second energy storage circuit 21 is electrically connected to the third node N3, and the second energy storage circuit 21 is used to store electrical energy;

[0110] The bias control circuit 22 is electrically connected to the bias control terminal SP, the bias voltage terminal VB and the third node N3 respectively, and is used to write the bias voltage Vbias provided by the bias voltage terminal VB into the third node N3 under the control of the bias control signal provided by the bias control terminal SP.

[0111] The present invention Figure 3 When at least one embodiment of the pixel circuit shown is in operation, a display cycle includes a data writing phase and a biasing phase which are arranged before the light emitting phase and are arranged successively;

[0112] In the data writing stage, the data writing circuit 13 provides the data voltage Vdata provided by the data line DL to the writing node NX under the control of the scanning signal provided by the scanning terminal GT;

[0113] In the bias stage, the bias control circuit 22, under the control of the bias control signal provided by the bias control terminal SP, writes the bias voltage Vbias provided by the bias voltage terminal VB into the third node N3, so that the driving transistor included in the driving circuit 10 is in a biased state, which can improve the hysteresis phenomenon of the driving transistor.

[0114] In at least one embodiment of the present invention, when the driving transistor is a p-type transistor, in the bias phase, Vbias is provided to N3 to correspondingly change the potential of N1 so that the gate-source voltage of the driving transistor is less than or greater than the gate-source voltage of the driving transistor in the data writing phase, so as to improve the hysteresis phenomenon of the driving transistor;

[0115] In a preferred case, when the driving transistor is a p-type transistor, in the bias phase, Vbias is provided to N3 to correspondingly change the potential of N1 so that the gate-source voltage of the driving transistor is smaller than the gate-source voltage of the driving transistor in the data writing phase.

[0116] In at least one embodiment of the present invention, when the driving transistor is an n-type transistor, in the bias stage, by providing Vbias to N3 to correspondingly change the potential of N1, the gate-source voltage of the driving transistor is made less than or greater than the gate-source voltage of the driving transistor in the data writing stage, so as to improve the hysteresis phenomenon of the driving transistor.

[0117] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a first control circuit 31;

[0118] The first control circuit 31 is electrically connected to the first control terminal SC, the first voltage terminal V1 and the third node N3 respectively, and is used to control the connection or disconnection between the first voltage terminal V1 and the third node N3 under the control of a first control signal provided by the first control terminal SC.

[0119] Optionally, the first voltage terminal may be a power supply voltage terminal, but is not limited thereto.

[0120] The present invention Figure 4 When at least one embodiment of the pixel circuit shown is in operation, in the bias phase, the first control circuit 31 controls the first voltage terminal V1 to be disconnected from the third node N3 under the control of the first control signal;

[0121] During a time period other than the bias phase included in the display cycle, the first control circuit 31 may control the first voltage terminal V1 to be connected to the third node N3 under the control of the first control signal.

[0122] The pixel circuit described in at least one embodiment of the present invention further includes a second energy storage circuit;

[0123] The second energy storage circuit is electrically connected to the first node, and is used to maintain the potential of the first node.

[0124] like Figure 5 As shown, in Figure 2 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a second energy storage circuit 21;

[0125] The second energy storage circuit 21 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1.

[0126] The pixel circuit described in at least one embodiment of the present invention further includes a first initialization circuit, a second initialization circuit and a compensation control circuit;

[0127] The first terminal of the driving circuit is electrically connected to the first voltage terminal, and the second terminal of the driving circuit is electrically connected to the fourth node;

[0128] The first initialization circuit is electrically connected to the first reset control terminal and the first initial voltage terminal respectively, and is also electrically connected to the first node or the fourth node. The first initialization circuit is used to write the first initial voltage provided by the first initial voltage terminal into the first node or the fourth node under the control of the first reset control signal provided by the first reset control terminal;

[0129] The second initialization circuit is electrically connected to the second reset control terminal, the reference voltage terminal and the write node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the write node under the control of the second reset control signal provided by the second reset control terminal;

[0130] The compensation control circuit is electrically connected to the compensation control terminal, the first node and the fourth node respectively, and is used to control the connection or disconnection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal.

[0131] In a specific implementation, the pixel circuit may further include a first initialization circuit, a second initialization circuit and a compensation control circuit; the first initialization circuit writes a first initial voltage to the first node or the fourth node under the control of a first reset control signal; the second initialization circuit writes a reference voltage to the write node under the control of the second reset control signal; the compensation control circuit controls the connection or disconnection between the first node and the fourth node under the control of the compensation control signal.

[0132] The pixel circuit described in at least one embodiment of the present invention further includes a light emitting control circuit and a third initialization circuit; the first end of the driving circuit is electrically connected to the first voltage end, and the second end of the driving circuit is electrically connected to the fourth node;

[0133] The light emitting control circuit is electrically connected to the light emitting control terminal, the fourth node and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the fourth node and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal;

[0134] The third initialization circuit is electrically connected to the third reset control terminal, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal;

[0135] The second electrode of the light emitting element is electrically connected to the second voltage terminal.

[0136] Optionally, the second voltage terminal may be a low voltage terminal.

[0137] In a specific implementation, the pixel circuit may further include a light-emitting control circuit and a third initialization circuit; the light-emitting control circuit, under the control of the light-emitting control signal, controls the connection or disconnection between the fourth node and the first pole of the light-emitting element to perform light-emitting control; the third initialization circuit, under the control of the third reset control signal, writes the second initial voltage into the first pole of the light-emitting element to clear the residual charge in the first pole of the light-emitting element.

[0138] like Figure 6 As shown, in Figure 4 Based on at least one embodiment of the pixel circuit shown in the figure, the pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit 51, a second initialization circuit 52 and a compensation control circuit 53;

[0139] The first terminal of the driving circuit 10 is electrically connected to the first voltage terminal V1, and the second terminal of the driving circuit 10 is electrically connected to the fourth node N4;

[0140] The first initialization circuit 51 is electrically connected to the first reset control terminal RST1 and the first initial voltage terminal I1 respectively, and the first initialization circuit 51 is also electrically connected to the fourth node N4. The first initialization circuit 51 is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the fourth node N4 under the control of the first reset control signal provided by the first reset control terminal RST1;

[0141] The second initialization circuit 52 is electrically connected to the second reset control terminal RST2, the reference voltage terminal REF and the write node NX respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the write node NX under the control of the second reset control signal provided by the second reset control terminal RST2;

[0142] The compensation control circuit 53 is electrically connected to the compensation control terminal SK, the first node N1 and the fourth node N4 respectively, and is used to control the connection or disconnection between the first node N1 and the fourth node N4 under the control of the compensation control signal provided by the compensation control terminal SK;

[0143] The pixel circuit according to at least one embodiment of the present invention further includes a light emitting control circuit 54 and a third initialization circuit 55; the first terminal V1 of the driving circuit 10 is electrically connected to the first voltage terminal, and the second terminal of the driving circuit 10 is electrically connected to the fourth node N4;

[0144] The light emitting control circuit 54 is electrically connected to the light emitting control terminal EM, the fourth node N4 and the first electrode of the light emitting element E1 respectively, and is used to control the connection or disconnection between the fourth node N4 and the first electrode of the light emitting element E1 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0145] The third initialization circuit 55 is electrically connected to the third reset control terminal RST3, the second initial voltage terminal I2 and the first electrode of the light emitting element E1 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first electrode of the light emitting element E1 under the control of the third reset control signal provided by the third reset control terminal RST3;

[0146] The second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2.

[0147] like Figure 7 As shown, in Figure 5 Based on at least one embodiment of the pixel circuit shown in the figure, the pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit 51, a second initialization circuit 52 and a compensation control circuit 53;

[0148] The first terminal of the driving circuit 10 is electrically connected to the first voltage terminal V1, and the second terminal of the driving circuit 10 is electrically connected to the fourth node N4;

[0149] The first initialization circuit 51 is electrically connected to the first reset control terminal RST1 and the first initial voltage terminal I1 respectively, and the first initialization circuit 51 is also electrically connected to the fourth node N4. The first initialization circuit 51 is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the fourth node N4 under the control of the first reset control signal provided by the first reset control terminal RST1;

[0150] The second initialization circuit 52 is electrically connected to the second reset control terminal RST2, the reference voltage terminal REF and the write node NX respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the write node NX under the control of the second reset control signal provided by the second reset control terminal RST2;

[0151] The compensation control circuit 53 is electrically connected to the compensation control terminal SK, the first node N1 and the fourth node N4 respectively, and is used to control the connection or disconnection between the first node N1 and the fourth node N4 under the control of the compensation control signal provided by the compensation control terminal SK;

[0152] The pixel circuit according to at least one embodiment of the present invention further includes a light emitting control circuit 54 and a third initialization circuit 55; the first terminal V1 of the driving circuit 10 is electrically connected to the first voltage terminal, and the second terminal of the driving circuit 10 is electrically connected to the fourth node N4;

[0153] The light emitting control circuit 54 is electrically connected to the light emitting control terminal EM, the fourth node N4 and the first electrode of the light emitting element E1 respectively, and is used to control the connection or disconnection between the fourth node N4 and the first electrode of the light emitting element E1 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0154] The third initialization circuit 55 is electrically connected to the third reset control terminal RST3, the second initial voltage terminal I2 and the first electrode of the light emitting element E1 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first electrode of the light emitting element E1 under the control of the third reset control signal provided by the third reset control terminal RST3;

[0155] The second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2.

[0156] Optionally, the on-off control circuit includes a first transistor; the first energy storage circuit includes a first capacitor, and the data writing circuit includes a second transistor;

[0157] The gate of the first transistor is electrically connected to the on / off control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second node;

[0158] A first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the write node;

[0159] A gate of the second transistor is electrically connected to the scan end, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the write node.

[0160] Optionally, the second energy storage circuit includes a second capacitor, and the bias control circuit includes a third transistor;

[0161] A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to a third node;

[0162] The gate of the third transistor is electrically connected to the bias control terminal, the first electrode of the third transistor is electrically connected to the bias voltage terminal, and the second electrode of the third transistor is electrically connected to the third node.

[0163] Optionally, the first control circuit includes a fourth transistor;

[0164] The gate of the fourth transistor is electrically connected to the first control terminal, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the third node.

[0165] like Figure 8 As shown, in Figure 7 Based on at least one embodiment of the pixel circuit shown, the on-off control circuit includes a first transistor T1; the first energy storage circuit includes a first capacitor C1, the data writing circuit includes a second transistor T2; the driving circuit includes a driving transistor T0;

[0166] The gate of T0 is electrically connected to the first node N1, the source of T1 is electrically connected to the power supply voltage terminal VDD, and the drain of T1 is electrically connected to the fourth node N4;

[0167] The gate of the first transistor T1 is electrically connected to the light emitting control terminal EM, the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor is electrically connected to the second node N2;

[0168] A first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the write node NX;

[0169] The gate of the second transistor T2 is electrically connected to the scanning terminal GT, the source of the second transistor T2 is electrically connected to the data line DL, and the drain of the second transistor T2 is electrically connected to the writing node NX;

[0170] The second energy storage circuit includes a second capacitor C2;

[0171] A first end of the second capacitor C2 is electrically connected to the first node N1, and a second end of the second capacitor C2 is electrically connected to a power supply voltage terminal VDD;

[0172] The first initialization circuit includes a fifth transistor T5, the second initialization circuit includes a sixth transistor T6, the light emitting control circuit includes a seventh transistor T7, the third initialization circuit includes an eighth transistor T8, the compensation control circuit includes a ninth transistor T9, the light emitting element is an organic light emitting diode O1,

[0173] The gate of T5 is electrically connected to the first reset control terminal RST1, the source of T5 is electrically connected to the first initial voltage terminal I1, and the drain of T5 is electrically connected to the fourth node N4;

[0174] The gate of T6 is electrically connected to the second reset control terminal RST2, the source of T6 is electrically connected to the reference voltage terminal REF, and the drain of T6 is electrically connected to the write node NX;

[0175] The gate of T7 is electrically connected to the light emitting control terminal EM, the source of T7 is electrically connected to the fourth node N4, and the drain of T7 is electrically connected to the anode of O1;

[0176] The gate of T8 is electrically connected to the first reset control terminal RST1, the source of T8 is electrically connected to the second initial voltage terminal I2, the drain of T8 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low voltage terminal VSS;

[0177] The gate of T9 is electrically connected to the second reset control terminal RST2 , the source of T9 is electrically connected to the first node N1 , and the drain of T9 is electrically connected to the fourth node N4 .

[0178] exist Figure 8 In at least one embodiment shown, the first reset control terminal and the third reset control terminal can be the same reset control terminal, the on-off control terminal and the light-emitting control terminal are the same control terminal, and the compensation control terminal and the second reset control terminal are the same control terminal to reduce the number of control terminals used.

[0179] exist Figure 8In at least one embodiment shown, T1 is an n-type transistor, and T0, T2, T5, T6, T7, T8, and T9 are all p-type transistors.

[0180] like Fig. 9 As shown, the present invention Figure 8 When at least one embodiment of the pixel circuit shown is in operation, the display cycle of the pixel circuit includes a reset phase S1, a compensation phase S2, a data writing phase S3 and a light emitting phase S4 which are arranged in sequence;

[0181] In the reset phase S1, EM provides a high voltage signal, RST1 provides a low voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, T7 is turned off, T2 is turned off, T1 is turned on, so that N1 and N2 are connected, T5 and T9 are turned on, I1 provides a first initial voltage Vinit1 to N1 and N4, T6 is turned on, REF provides a reference voltage Vref to NX, T8 is turned on, and I2 provides a second initial voltage Vinit2 to clear the residual charge of the anode of O1;

[0182] In the compensation stage S2, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, T1 is turned on, T6 is turned on, and T9 is turned on;

[0183] At the beginning of the compensation stage S2, T0 is turned on, Vref is charged through C1, T1, T9 and the turned-on T0, and the potential of N1 is changed until the potential of N1 becomes Vdd+Vth, and T0 is turned off to complete the threshold voltage compensation; wherein Vdd is the voltage value of the power supply voltage provided by VDD, and Vth is the threshold voltage of T0;

[0184] In the data writing phase S3, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a low voltage signal, T1 is turned on, T2 is turned on, DL provides a data voltage Vdata to NX, and through the coupling effect of C1, the potential of N1 changes from Vdd+Vth to Vdd+Vth-Vref+Vdata;

[0185] In the light-emitting stage S4, EM provides a low voltage signal, RST1, RST2 and GT all provide high voltage signals, T1 is turned off to control the disconnection between N1 and N2, T2 and T6 are turned off, NX is in a floating state to prevent the potential of N1 from being affected by the potential of NX and keep the potential of N1 stable; T7 is turned on, T0 drives O1 to emit light, at this time, the current value of the driving current generated by T0 to drive O1 is K×(Vdd+Vth-Vref+Vdata-Vdd-Vth) 2 =K×(Vdata-Vref) 2; Wherein, K is the current coefficient of T0. It can be seen that Id is independent of Vdd and Vth, and can compensate for the uneven display problem caused by the uneven driving current caused by Vdd and Vth.

[0186] In the related art, the threshold voltage of the driving transistor is uneven due to process fluctuations, resulting in uneven display quality. In addition, the power supply voltage received by the pixel circuit in the remote display area of ​​the display panel has a voltage drop, which also causes uneven display. At least one embodiment of the present invention can compensate for the threshold voltage and power supply voltage of the driving transistor to improve the uneven display phenomenon.

[0187] Furthermore, when the pixel circuit described in at least one embodiment of the present invention is in operation, data voltage writing and threshold voltage compensation can be separated, so that the threshold voltage compensation time is not limited by the row cycle, and the threshold voltage compensation time can be increased to fully compensate for the threshold voltage and power supply voltage of the driving transistor.

[0188] The present invention Fig.10 At least one embodiment of the pixel circuit shown in the figure is consistent with the present invention Figure 8 The difference of at least one embodiment of the pixel circuit shown is that:

[0189] T1 is a p-type transistor, and a gate of T1 is electrically connected to an on-off control terminal ST.

[0190] exist Fig.10 In at least one embodiment shown, the drain of T5 may also be electrically connected to N1 instead.

[0191] like Fig.11 As shown, the present invention Fig.10 When at least one embodiment of the pixel circuit shown is in operation, the display cycle of the pixel circuit includes a reset phase S1, a compensation phase S2, a data writing phase S3 and a light emitting phase S4 which are arranged in sequence;

[0192] In the reset phase S1, EM provides a high voltage signal, RST1 provides a low voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, ST provides a low voltage signal, T7 is turned off, T2 is turned off, T1 is turned on, so that N1 and N2 are connected, T5 and T9 are turned on, I1 provides a first initial voltage Vinit1 to N1 and N4, T6 is turned on, REF provides a reference voltage Vref to NX, T8 is turned on, and I2 provides a second initial voltage Vinit2 to clear the residual charge of the anode of O1;

[0193] In the compensation stage S2, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, ST provides a low voltage signal, T1 is turned on, T6 is turned on, and T9 is turned on;

[0194] At the beginning of the compensation stage S2, T0 is turned on, Vref is charged through C1, T1, T9 and the turned-on T0, and the potential of N1 is changed until the potential of N1 becomes Vdd+Vth, and T0 is turned off to complete the threshold voltage compensation; wherein Vdd is the voltage value of the power supply voltage provided by VDD, and Vth is the threshold voltage of T0;

[0195] In the data writing phase S3, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a low voltage signal, ST provides a low voltage signal, T1 is turned on, T2 is turned on, DL provides a data voltage Vdata to NX, and through the coupling effect of C1, the potential of N1 changes from Vdd+Vth to Vdd+Vth-Vref+Vdata;

[0196] In the light-emitting stage S4, EM provides a low voltage signal, RST1, RST2 and GT all provide high voltage signals, ST provides a high voltage signal, T1 is turned off to control the disconnection between N1 and N2, T2 and T6 are turned off, NX is in a floating state to prevent the potential of N1 from being affected by the potential of NX and keep the potential of N1 stable; T7 is turned on, T0 drives O1 to emit light, at this time, the current value of the driving current generated by T0 to drive O1 is K×(Vdd+Vth-Vref+Vdata-Vdd-Vth) 2 =K×(Vdata-Vref) 2 ; Wherein, K is the current coefficient of T0. It can be seen that Id is independent of Vdd and Vth, and can compensate for the uneven display problem caused by the uneven driving current caused by Vdd and Vth.

[0197] The present invention Fig.12 At least one embodiment of the pixel circuit shown in the figure is consistent with the present invention Figure 8 The difference of at least one embodiment of the pixel circuit shown is as follows: it also includes a bias control circuit and a first control circuit; the bias control circuit includes a third transistor T3; the first control circuit includes a fourth transistor T4;

[0198] The second end of the second capacitor C2 is electrically connected to the third node N3;

[0199] The gate of the third transistor T3 is electrically connected to the bias control terminal SP, the source of the third transistor T3 is electrically connected to the bias voltage terminal VB, and the drain of the third transistor T3 is electrically connected to the third node N3;

[0200] The gate of the fourth transistor T4 is electrically connected to the first control terminal SC, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal VDD, and the drain of the fourth transistor T4 is electrically connected to the third node N3;

[0201] T3 and T4 are p-type transistors.

[0202] like Fig.13 As shown, the present invention Fig.12 When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a reset phase S1, a compensation phase S2, a writing phase S3, a bias phase S0 and a light emitting phase S4 which are arranged in sequence;

[0203] In the reset phase S1, EM provides a high voltage signal, RST1 provides a low voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is turned off, T4 is turned on, VDD is connected to N3, T7 is turned off, T2 is turned off, T1 is turned on, so that N1 is connected to N2, T5 and T9 are turned on, I1 provides a first initial voltage Vinit1 to N1 and N4, T6 is turned on, REF provides a reference voltage Vref to NX, T8 is turned on, I2 provides a second initial voltage Vinit2 to clear the residual charge of the anode of O1;

[0204] In the compensation stage S2, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a low voltage signal, GT provides a high voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is turned off, T4 is turned on, VDD is connected to N3, T1 is turned on, T6 is turned on, and T9 is turned on;

[0205] At the beginning of the compensation stage S2, T0 is turned on, Vref is charged through C1, T1, T9 and the turned-on T0, and the potential of N1 is changed until the potential of N1 becomes Vdd+Vth, and T0 is turned off to complete the threshold voltage compensation; wherein Vdd is the voltage value of the power supply voltage provided by VDD, and Vth is the threshold voltage of T0;

[0206] In the data writing phase S3, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a low voltage signal, ST provides a low voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is turned off, T4 is turned on, VDD is connected to N3, T1 is turned on, T2 is turned on, DL provides a data voltage Vdata to NX, and through the coupling effect of C1, the potential of N1 changes from Vdd+Vth to Vdd+Vth-Vref+Vdata;

[0207] In the bias stage S0, EM provides a high voltage signal, RST1 provides a high voltage signal, RST2 provides a high voltage signal, GT provides a high voltage signal, SP provides a low voltage signal, SC provides a high voltage signal, T4 is turned off, T4 is turned on, VB provides a bias voltage Vbias to N3, and the potential of N3 changes from Vdd to Vbias. Due to the coupling effect of C2, the potential of N1 changes from Vdd+Vth-Vref+Vdata to Vdd+Vth-Vref+Vdata+Vbias-Vdd, that is, to Vth-Vref+Vdata+Vbias, so as to improve the hysteresis phenomenon of T0; the bias effect on T0 can be adjusted by adjusting the voltage value of Vbias and the number of effective pulses of the bias control signal provided by SP;

[0208] In the light-emitting stage S4, EM provides a low voltage signal, RST1, RST2 and GT all provide high voltage signals, ST provides a high voltage signal, SP provides a high voltage signal, SC provides a low voltage signal, T3 is turned off, T4 is turned on, N3 is connected to VDD, the potential of N3 changes from Vbias to Vdd, due to the coupling effect of C2, the potential of N1 changes back to Vdd+Vth-Vref+Vdata, T1 is turned off to control the disconnection between N1 and N2, T2 and T6 are turned off, NX is in a floating state to prevent the potential of N1 from being affected by the potential of NX and keep the potential of N1 stable; T7 is turned on, T0 drives O1 to emit light, at this time, the current value of the driving current generated by T0 to drive O1 is K×(Vdd+Vth-Vref+Vdata-Vdd-Vth) 2 =K×(Vdata-Vref) 2 ; Wherein, K is the current coefficient of T0. It can be seen that Id is independent of Vdd and Vth, and can compensate for the uneven display problem caused by the uneven driving current caused by Vdd and Vth.

[0209] The present invention Fig.14 At least one embodiment of the pixel circuit shown in the figure is consistent with the present invention Figure 8 The differences of at least one embodiment of the pixel circuit shown are as follows:

[0210] The drain of T5 is electrically connected to the first node N1.

[0211] The present invention Fig.14 When at least one embodiment of the pixel circuit shown is in operation, in the reset phase, RST1 provides a low voltage signal, T5 is turned on, and I1 can directly provide the first initial voltage Vinit1 to N1, so that T0 can be turned on at the beginning of the compensation phase.

[0212] The present invention Fig.15 At least one embodiment of the pixel circuit shown in the figure is consistent with the present invention Fig.12 The differences of at least one embodiment of the pixel circuit shown are as follows:

[0213] The drain of T5 is electrically connected to the first node N1.

[0214] The present invention Fig.15 When at least one embodiment of the pixel circuit shown is in operation, in the reset phase, RST1 provides a low voltage signal, T5 is turned on, and I1 can directly provide the first initial voltage Vinit1 to N1, so that T0 can be turned on at the beginning of the compensation phase.

[0215] The driving method described in the embodiment of the present invention is applied to the above-mentioned pixel circuit, wherein the display cycle of the pixel circuit includes a light-emitting phase; the driving method includes:

[0216] In the light emitting stage, the on-off control circuit controls the disconnection between the first node and the second node under the control of the on-off control signal, so that the potential of the first node is not affected by the floating write node, and the potential of the first node is stable.

[0217] In at least one embodiment of the present invention, in the bias stage before the light emitting stage, the driving method further includes:

[0218] In the bias phase, the bias control circuit writes a bias voltage into the third node under the control of a bias control signal to improve the hysteresis phenomenon of the driving transistor included in the driving circuit.

[0219] In at least one embodiment of the present invention, the pixel circuit further includes a first control circuit; and the driving method further includes:

[0220] In the bias phase, the first control circuit controls the first voltage terminal and the third node to be disconnected under the control of the first control signal.

[0221] In at least one embodiment of the present invention, the display period includes a data writing phase arranged in the bias phase; and the driving method further includes:

[0222] In the data writing stage, the data writing circuit provides the data voltage provided by the data line to the writing node under the control of the scanning signal provided by the scanning end, and the on-off control circuit controls the connection between the first node and the third node under the control of the on-off control signal to write the data voltage.

[0223] In at least one embodiment of the present invention, the display cycle further includes a compensation phase; the compensation phase is independent of the data writing phase; the pixel circuit further includes a second initialization circuit and a compensation control circuit; the driving method further includes:

[0224] In the compensation stage, the on-off control circuit controls the connection between the first node and the third node under the control of the on-off control signal, the second initialization circuit provides the reference voltage provided by the reference voltage terminal to the write node under the control of the second reset control signal, and the compensation control circuit controls the connection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal to perform threshold voltage compensation.

[0225] The display device described in the embodiment of the present invention includes the above-mentioned pixel circuit.

[0226] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: It includes a light-emitting element, a driving circuit, an on-off control circuit, a first energy storage circuit and a data writing circuit; The control end of the driving circuit is electrically connected to the first node, and the driving circuit is used to generate a driving current to drive the light emitting element under the control of the potential of the first node; The on-off control circuit is electrically connected to the on-off control terminal, the first node and the second node respectively, and is used to control the connection or disconnection between the first node and the second node under the control of the on-off control signal provided by the on-off control terminal; The first energy storage circuit is electrically connected to the second node and the write node respectively; The data writing circuit is electrically connected to the scanning end, the data line and the writing node respectively, and is used to provide the data voltage provided by the data line to the writing node under the control of the scanning signal provided by the scanning end.

2. The pixel circuit according to claim 1, wherein: Also includes a second energy storage circuit and a bias control circuit; The first end of the second energy storage circuit is electrically connected to the first node, and the second end of the second energy storage circuit is electrically connected to the third node; The bias control circuit is electrically connected to the bias control terminal, the bias voltage terminal and the third node respectively, and is used to write the bias voltage provided by the bias voltage terminal into the third node under the control of the bias control signal provided by the bias control terminal.

3. The pixel circuit according to claim 2, characterized in that: Also includes a first control circuit; The first control circuit is electrically connected to the first control terminal, the first voltage terminal and the third node respectively, and is used to control the connection or disconnection between the first voltage terminal and the third node under the control of a first control signal provided by the first control terminal.

4. The pixel circuit according to claim 1, wherein: Also included is a second tank circuit; The second energy storage circuit is electrically connected to the first node, and is used to maintain the potential of the first node.

5. The pixel circuit according to any one of claims 1 to 4, characterized in that: Also includes a first initialization circuit, a second initialization circuit and a compensation control circuit; The first terminal of the driving circuit is electrically connected to the first voltage terminal, and the second terminal of the driving circuit is electrically connected to the fourth node; The first initialization circuit is electrically connected to the first reset control terminal and the first initial voltage terminal respectively, and is also electrically connected to the first node or the fourth node. The first initialization circuit is used to write the first initial voltage provided by the first initial voltage terminal into the first node or the fourth node under the control of the first reset control signal provided by the first reset control terminal; The second initialization circuit is electrically connected to the second reset control terminal, the reference voltage terminal and the write node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the write node under the control of the second reset control signal provided by the second reset control terminal; The compensation control circuit is electrically connected to the compensation control terminal, the first node and the fourth node respectively, and is used to control the connection or disconnection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal.

6. The pixel circuit according to any one of claims 1 to 4, characterized in that: It also includes a light emitting control circuit and a third initialization circuit; the first end of the driving circuit is electrically connected to the first voltage end, and the second end of the driving circuit is electrically connected to the fourth node; The light emitting control circuit is electrically connected to the light emitting control terminal, the fourth node and the first electrode of the light emitting element respectively, and is used to control the connection or disconnection between the fourth node and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal; The third initialization circuit is electrically connected to the third reset control terminal, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal; The second electrode of the light emitting element is electrically connected to the second voltage terminal.

7. The pixel circuit according to any one of claims 1 to 4, characterized in that: The on-off control circuit includes a first transistor; the first energy storage circuit includes a first capacitor, and the data writing circuit includes a second transistor; The gate of the first transistor is electrically connected to the on / off control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second node; A first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the write node; A gate of the second transistor is electrically connected to the scan end, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the write node.

8. The pixel circuit according to claim 2, characterized in that: The second energy storage circuit includes a second capacitor, and the bias control circuit includes a third transistor; A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to a third node; The gate of the third transistor is electrically connected to the bias control terminal, the first electrode of the third transistor is electrically connected to the bias voltage terminal, and the second electrode of the third transistor is electrically connected to the third node.

9. The pixel circuit according to claim 8, characterized in that: The first control circuit includes a fourth transistor; The gate of the fourth transistor is electrically connected to the first control terminal, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the third node.

10. A driving method, applied to the pixel circuit according to any one of claims 1 to 9, characterized in that: The display cycle of the pixel circuit includes a light emitting phase; the driving method includes: In the light-emitting stage, the on-off control circuit controls the first node and the second node to be disconnected under the control of the on-off control signal.

11. The driving method according to claim 10, characterized in that: The pixel circuit further includes a second energy storage circuit and a bias control circuit; the display cycle further includes a bias phase arranged before the light emitting phase; the driving method further includes: In the bias phase, the bias control circuit writes a bias voltage into the third node under the control of a bias control signal.

12. The driving method according to claim 11, characterized in that: The pixel circuit further includes a first control circuit; and the driving method further includes: In the bias phase, the first control circuit controls the first voltage terminal and the third node to be disconnected under the control of the first control signal.

13. The driving method according to claim 11 or 12, characterized in that: The display cycle includes a data writing phase arranged in the bias phase; the driving method further includes: In the data writing stage, the data writing circuit provides the data voltage provided by the data line to the writing node under the control of the scanning signal provided by the scanning end, and the on-off control circuit controls the connection between the first node and the third node under the control of the on-off control signal.

14. The driving method according to claim 13, characterized in that: The display cycle further includes a compensation phase; the compensation phase is independent of the data writing phase; the pixel circuit further includes a second initialization circuit and a compensation control circuit; the driving method further includes: In the compensation stage, the on-off control circuit controls the connection between the first node and the third node under the control of the on-off control signal, the second initialization circuit provides the reference voltage provided by the reference voltage terminal to the write node under the control of the second reset control signal, and the compensation control circuit controls the connection between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal.

15. A display device, characterized in that: The method comprises a pixel circuit as claimed in any one of claims 1 to 9.

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