Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: injecting a first ion into the bottom of the first opening to form a first modified region in the first anti-reflection material layer exposed by the first opening, and forming a second modified region in the first anti-reflection material layer on the second region and the residual layer; etching the first modified region and the second modified region until the first modified region is removed, so that the first anti-reflection material layer forms a first anti-reflection layer. The first anti-reflection material layer in the second modified region has a lower density than that in the first modified region. In the process of etching the first modified region and the second modified region, very little residue remains on the surface of the first pattern material layer located on the second region, which does not affect the subsequent etching process, thereby improving the accuracy of pattern definition and thus improving the performance of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and particularly to a method for forming a semiconductor structure. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, in order to achieve faster computing speeds, larger data storage capacities, and more functions, integrated circuit chips are developing towards higher device densities and higher integration levels.

[0003] As the integration level of semiconductor chips continues to increase, the feature size of transistors continues to shrink, posing an increasingly great challenge to the lithography process. Controlling the critical dimension of the pattern linewidth has become an important direction for semiconductor development. In order to form more refined patterns and achieve higher fidelity during the process, self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), etc. are introduced to realize smaller-sized patterns.

[0004] However, existing lithography technologies need to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing an etch layer, where the etch layer includes a first region and a second region surrounding the first region; forming a first pattern material layer on the surface of the etch layer, a first anti-reflection material layer on the surface of the first pattern material layer, and a second anti-reflection material layer on the surface of the first anti-reflection material layer; patterning the second anti-reflection material layer to form a second anti-reflection layer and a first opening in the second anti-reflection layer, and exposing the surface of the first anti-reflection material layer at the bottom of the first opening on the first region, and the remaining part of the second anti-reflection material layer on the second region forms a residual layer; injecting a first ion into the bottom of the first opening to form a first modified region on the first anti-reflection material layer exposed by the first opening, and forming a second modified region on the first anti-reflection material layer and the residual layer on the second region; etching the first modified region and the second modified region until the first modified region is removed, and forming a first anti-reflection layer from the first anti-reflection material layer.

[0007] Optionally, a second opening is formed in the first anti-reflection layer, and the surface of the first pattern material layer on the first region is exposed at the bottom of the second opening.

[0008] Optionally, it further includes: injecting a second ion into the bottom of the second opening, so that the first graphic material layer located at the bottom of the second opening forms a third modified region, and the first graphic material layer located at the bottom of the first anti-reflection layer forms a first graphic layer; removing the third modified region.

[0009] Optionally, it further includes: forming sidewalls on the sidewalls of the first graphic layer; before forming the sidewalls, removing the first anti-reflection layer and the second anti-reflection layer; after forming the sidewalls, removing the first graphic layer.

[0010] Optionally, the material of the sidewalls includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon silicon nitride, and carbon oxynitride.

[0011] Optionally, before forming the first graphic material layer, it further includes: forming a second graphic material layer on the surface of the layer to be etched, and the second graphic material layer is located between the first graphic material layer and the layer to be etched.

[0012] Optionally, the material of the second graphic material layer includes one or more of titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon silicon nitride, and carbon oxynitride.

[0013] Optionally, the first graphic layer exposes a partial surface of the second graphic material layer.

[0014] Optionally, it further includes: using the sidewalls as a mask to etch the second graphic material layer until the surface of the layer to be etched is exposed, forming a second graphic layer.

[0015] Optionally, the method for patterning the second anti-reflection material layer includes: forming a patterned photoresist layer on the second anti-reflection material layer, and the photoresist layer exposes the second anti-reflection material layer on the second region and a part of the second anti-reflection material layer on the first region; using the photoresist layer as a mask to etch the second anti-reflection material layer.

[0016] Optionally, it further includes: removing the photoresist layer after injecting the first ion into the bottom of the first opening.

[0017] Optionally, the process parameters for injecting the first ion include: the first ion includes P-type ions or N-type ions, and the energy range is 5 keV to 20 keV.

[0018] Optionally, the selectivity range of the process for etching the first modified region and the second modified region with respect to the first modified region and the second modified region is greater than or equal to 1.2:1.

[0019] Optionally, the process of etching the first modified region and the second modified region includes one or a combination of a dry etching process and a wet etching process.

[0020] Optionally, the process of etching the first modified region and the second modified region includes a dry etching process, and the process parameters of the dry etching process include: the etching gas includes one or a combination of CF4 and CHF3, and the power range is 300 watts to 1000 watts.

[0021] Optionally, it includes: the material of the second anti-reflection material layer includes an organic polymer.

[0022] Optionally, it includes: the material of the first anti-reflection material layer includes a carbon-containing polymer.

[0023] Optionally, it includes: the material of the first pattern material layer includes silicon.

[0024] Optionally, the thickness range of the residual layer is less than or equal to 200 angstroms.

[0025] Optionally, after removing the first modified region, the thickness of the second modified region remaining on the surface of the first pattern material layer located on the second region is less than or equal to 200 angstroms.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0027] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first ion is implanted into the bottom of the first opening. The first ion implantation will increase the density of the film in the implanted region, increasing the density of the first modified region. Since the second anti-reflection material layer remaining on its surface cannot be implanted with the first ion, the first anti-reflection material layer in the second modified region has a lower density. The increase in film density will lead to a decrease in the etching rate. The first anti-reflection material layer in the second modified region has a relatively lower density compared to the first modified region. In the process of etching the first modified region and the second modified region, the first anti-reflection material layer in the second modified region has a relatively higher etching rate. Therefore, while removing the first modified region, the removal amount of the second modified region on the second region can be increased, or even completely removed, leaving very little residue on the surface of the first pattern material layer located on the second region, which does not affect the subsequent etching process, enabling the subsequent formation of a uniform first pattern layer on the surface of the layer to be etched, reducing the situation of missing the first pattern layer on the second region, thereby improving the accuracy of pattern definition, reducing the influence of the relatively thick second anti-reflection material layer on the wafer edge on the etching process, and thus improving the performance of the device.

[0028] Further, the selectivity of the first etching process for the first modified region and the second modified region ranges from greater than or equal to 1.2:1. The thickness of the second modified region is greater than that of the first modified region, but they can be removed simultaneously, or after the first modified region is removed, the residue amount of the second modified region is small enough not to affect the subsequent etching process, improving the accuracy of pattern definition and thus enhancing the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 5 is a cross-sectional schematic diagram of a semiconductor structure formation process.

[0030] Figures 6 to 16 is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] It should be noted that the "surface" and "upper" in this specification are used to describe the relative spatial position relationship and do not limit whether there is direct contact.

[0032] As described in the background art, the performance of semiconductor structures formed by existing lithography technologies urgently needs to be improved. Now, a method for forming a semiconductor structure is used for illustration and analysis.

[0033] Figures 1 to 5 is a cross-sectional schematic diagram of a semiconductor structure formation process.

[0034] Please refer to Figure 1 , a substrate is provided, the substrate includes a first region Ⅰ and a second region Ⅱ, and an etch layer 101 located on the top surface of the substrate; a pattern material layer 102 is formed on the etch layer 101, a sacrificial layer 103 is formed on the pattern material layer 102, a first anti-reflection material layer 104 is formed on the surface of the sacrificial layer 103, a second anti-reflection material layer 105 is formed on the surface of the first anti-reflection material layer 104, and a photoresist material layer 106 is formed on the second anti-reflection material layer 105.

[0035] Please refer to Figure 2 , through development, the photoresist material layer 106 is formed into a patterned photoresist layer 107, and the photoresist layer 107 exposes a part of the second anti-reflection material layer 105 on the first region Ⅰ and the second anti-reflection material layer 105 on the second region (as Figure 1 shown); using the photoresist layer 107 as a mask, the second anti-reflection material layer 105 and the first anti-reflection material layer 104 are etched until the sacrificial layer 103 is exposed to form an anti-reflection layer 108 and an opening 109 located in the anti-reflection layer 108.

[0036] Please refer to Figure 3, remove the photoresist layer 107; after removing the photoresist layer 107, inject modified ions to the bottom of the opening 109, so that the sacrificial layer 103 (as shown in Figure 2 ) exposed by the opening 109 forms a modified region 110, and the sacrificial layer 103 located at the bottom of the anti-reflection layer 108 forms a core layer 111.

[0037] Please refer to Figure 4 , remove the modified region 110 and the anti-reflection layer 108; after removing the modified region 110 and the anti-reflection layer 108, form a sidewall 112 on the sidewall of the core layer 111.

[0038] Please refer to Figure 5 , after forming the sidewall 112, remove the core layer 111.

[0039] In the above method, the sidewall 112 is used as a mask for pattern definition. The second anti-reflection material layer 105 serves as a bottom anti-reflection material layer, and its material is a fluid organic polymer, which is usually formed by spin coating. The second region II is located at the edge of the wafer. Due to the easy aggregation of liquid at the wafer edge under the action of centrifugal force, the thickness of the second anti-reflection material layer 105 on the second region II is relatively thick, forming an abnormal region A (as shown in Figure 1 ). The etching process for forming the opening 109 has a selectivity ratio of 1:6 for the second anti-reflection material layer 105 and the first anti-reflection material layer 104. When the second anti-reflection material layer 105 and the first anti-reflection material layer 104 on the first region I are completely etched, there is still residue of the second anti-reflection material layer 105 on the second region II, so that a complete opening 109 cannot be formed at the abnormal region A (as shown in Figure 2 ). Whether ions are injected into the sacrificial layer 103 will result in different etching rates. For the sacrificial layer 103 located on the second region II, due to the blocking of ion implantation by the remaining second anti-reflection material layer 105, a modified region cannot be formed. Therefore, in the process of removing the modified region 110, the sacrificial layer 103 on the second region II cannot be completely removed (as shown in Figure 3 ), which further leads to the inability to form a sidewall on the surface of the pattern material layer 102 in the second region, resulting in the absence of sidewalls at corresponding positions, and making the sidewall 112 unable to be used to accurately define the pattern subsequently. When the sidewall 112 is used as a mask pattern to form metal interconnections, the positions of the metal interconnections cannot be accurately defined, which may cause bridging between the metal interconnections, resulting in leakage and affecting the yield of the device, etc.

[0040] To solve the above problems, in one embodiment, over-etching is used to remove the residual bottom anti-reflection coating on the second region II, but it is likely to cause over-etching of the bottom anti-reflection coating 105 and the carbon coating 104 that do not need to be etched, thus affecting problems such as the size of the subsequent defined pattern.

[0041] To solve the above problems, in a method for forming a semiconductor structure provided by the present invention, first ions are implanted into the bottom of the first opening. The first ion implantation will increase the density of the film in the implanted area, increasing the density of the first modified region. Since the first anti-reflection material layer in the second modified region cannot be implanted with the first ions due to the residual second anti-reflection material layer on its surface, it has a lower density. The increase in film density will lead to a decrease in the etching rate. The first anti-reflection material layer in the second modified region has a relatively lower density compared to the first modified region. In the process of etching the first modified region and the second modified region, the first anti-reflection material layer in the second modified region has a relatively higher etching rate. Therefore, while removing the first modified region, the removal amount of the second modified region on the second region can be increased, or even completely removed, so that there is very little residue on the surface of the first pattern material layer located on the second region, without affecting the subsequent etching process, enabling the subsequent formation of a uniform first pattern layer on the surface of the layer to be etched, reducing the situation of missing the first pattern layer on the second region, thereby improving the accuracy of the mask for pattern definition and reducing the influence of the relatively thick second anti-reflection material layer on the wafer edge on the etching process, thus improving the performance of the device.

[0042] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0043] Figures 6 to 16 It is a schematic structural diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0044] Please refer to Figure 6 and Figure 7 , Figure 7 is a top view, Figure 6 is Figure 7 a cross-sectional view of region A in Figure 6 along the XX direction ( Figure 7 and

[0045] are schematic diagrams, and the two are not in the same proportion), providing a layer to be etched 201, and the layer to be etched 201 includes a first region I and a second region II surrounding the first region I.

[0045] The material of the etching layer 201 can be any material that needs to be etched, such as a dielectric material, a metal material, a semiconductor material, etc. The etching layer 201 can be a single layer or a multi-layer stacked structure. The layer to be etched 201 is located on a substrate (not shown), and the substrate can be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-silicon substrate, a gallium arsenide substrate, or a germanium-on-insulator substrate. In one embodiment, the substrate has a metal interconnect structure, etc. In this embodiment, the material of the layer to be etched 201 is a metal material, and the substrate is a silicon wafer with transistor devices.

[0046] It should be noted that the subsequent Figures 8 to 16 viewing directions are the same as those of Figure 6 the viewing directions.

[0047] Please refer to Figure 8 , a first pattern material layer 202 is formed on the surface of the layer to be etched 201, a first anti-reflection material layer 203 located on the surface of the first pattern material layer 202, and a second anti-reflection material layer 204 located on the surface of the first anti-reflection material layer 203.

[0048] In this embodiment, before forming the first pattern material layer 202, a second pattern material layer 205 is also formed on the surface of the layer to be etched, and the second pattern material layer 205 is located between the first pattern material layer 202 and the layer to be etched 201.

[0049] The material of the second pattern material layer 205 includes one or more of titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbonitride, and carbon oxynitride.

[0050] In this embodiment, the material of the second pattern material layer 205 includes silicon dioxide, titanium nitride, and carbon oxysilicon. The structure of the second pattern material layer 205 is a multi-layer structure, including a silicon dioxide material layer (not marked in the figure) located on the surface of the layer to be etched 201, a titanium nitride material layer (not marked in the figure) located on the silicon dioxide layer, and a carbon oxysilicon material layer (not marked in the figure) located on the titanium nitride material layer. The second pattern material layer 205 is used to form a second pattern layer subsequently.

[0051] The material of the first pattern material layer 202 includes silicon. In this embodiment, the material of the first pattern material layer 202 is amorphous silicon. In other embodiments, the material of the first pattern material layer 202 can also be polysilicon, silicon oxide, silicon carbide, etc. The second pattern material layer 202 is used to form a sidewall subsequently.

[0052] The material of the first anti-reflection material layer 203 includes a carbon-containing polymer. The first anti-reflection material layer 203 is subsequently used to form the first anti-reflection layer, which plays a role in pattern transfer. At the same time, since the first anti-reflection material layer 203 has etching resistance, during the subsequent etching process, the collapse of the first anti-reflection layer (and the photoresist layer located on the first anti-reflection layer) supported by the first anti-reflection material layer 203 can be reduced.

[0053] The formation process of the first anti-reflection material layer 203 includes a spin coating process.

[0054] The material of the second anti-reflection material layer 204 includes an organic polymer. In this embodiment, the second anti-reflection material layer 204 is a silicon-based anti-reflection material. The second anti-reflection material layer 204 is used to reduce the reflection of light at the bottom of the photoresist layer during the subsequent lithography process.

[0055] The formation process of the second anti-reflection material layer 204 includes a spin coating process. The second anti-reflection material layer 204 is a fluid. During the spin coating process, the second region II is located at the edge of the wafer, and the liquid is likely to accumulate at the edge of the wafer under the action of centrifugal force, making the thickness of the second anti-reflection material layer 204 on the second region II thicker.

[0056] Please refer to Figure 9 , pattern the second anti-reflection material layer 204 (as Figure 8 shown), form the second anti-reflection layer 206 and the first opening 207 located in the second anti-reflection layer 206, and expose the surface of the first anti-reflection material layer 203 at the bottom of the first opening 207 on the first region I. The remaining part of the second anti-reflection material layer 204 on the second region II forms the residual layer 208.

[0057] The thickness range of the residual layer 208 is less than or equal to 200 angstroms.

[0058] In this embodiment, the method for patterning the second anti-reflection material layer 204 includes: forming a patterned photoresist layer 209 on the second anti-reflection material layer 204, and the photoresist layer 209 exposes the second anti-reflection material layer 204 on the second region II and a part of the second anti-reflection material layer 204 on the first region I; using the photoresist layer 209 as a mask to etch the second anti-reflection material layer 204.

[0059] The process of etching the second anti-reflection material layer 204 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the process of etching the second anti-reflection material layer 204 is a dry etching process. The process parameters of the dry etching process include: the etching gas includes CF4 and CHF3, and the power range is from 300 watts to 1000 watts. Since the thickness of the second anti-reflection material layer 204 in the second region II is relatively thick, while the surface of the first anti-reflection layer 203 at the bottom of the first opening 207 in the first region I is exposed, there is still a residue of the second anti-reflection material layer 204 in the second region II, forming a residual layer 208.

[0060] Please refer to Figure 10 , inject a first ion 210 into the bottom of the first opening 207, so that the first anti-reflection material layer 203 exposed by the first opening 207 forms a first modified region 211, and the first anti-reflection material layer 203 on the second region II and the residual layer 208 form a second modified region 212.

[0061] The process parameters of injecting the first ion 210 include: the first ion 210 includes a P-type ion or an N-type ion, and the energy range is from 5 keV to 20 keV. In this embodiment, the first ion 210 is a boron ion.

[0062] The injection of the first ion 210 will increase the density of the first modified region 211. It is difficult for the first anti-reflection material layer 203 covered by the residual layer 208 to be injected with the first ion. Therefore, the first anti-reflection material layer 203 in the second modified region 212, that is, the first anti-reflection material layer 203 covered by the residual layer 208, has a lower density than the first modified region 211.

[0063] In this embodiment, after injecting the first ion 210 into the bottom of the first opening 207, the photoresist layer 209 is also removed.

[0064] The process of removing the photoresist layer 209 includes one or a combination of a dry process and a wet process. In this embodiment, the process of removing the photoresist layer 209 is a dry process. Specifically, the process of the photoresist layer 209 is an ashing process. The ashing process can improve the removal rate of the photoresist layer 209 and reduce the damage to the second anti-reflection layer 206 and the first anti-reflection material layer 203 during the process of removing the photoresist layer 209, and has high reliability.

[0065] Please refer to Figure 11, etch the first modified region 211 and the second modified region 212 until the first modified region 211 is removed, so that the first anti-reflection material layer 203 forms a first anti-reflection layer 213, and a second opening 214 is formed in the first anti-reflection layer 213, and the surface of the first pattern material layer 202 on the first region Ⅰ is exposed at the bottom of the second opening 214.

[0066] After removing the first modified region 211, the thickness of the remaining second modified region 215 on the surface of the first pattern material layer 202 in the second region Ⅱ is less than or equal to 200 angstroms. In this embodiment, after removing the first modified region 211, the thickness range of the remaining second modified region 215 on the surface of the second pattern material layer 202 in the second region Ⅱ is less than 100 angstroms. The thickness of the remaining second modified region 215 on the surface of the second pattern material layer 202 in the second region Ⅱ is small, which does not affect the subsequent etching process.

[0067] The etch process for the first modified region 211 and the second modified region 212 has a selectivity ratio range of greater than or equal to 1.2:1 for the first modified region 211 and the second modified region 212. Since an increase in film density leads to a decrease in etch rate. The first anti-reflection material layer 203 in the second modified region 212 has a lower density than the first modified region 211. In the process of etching the first modified region 211 and the second modified region 212, the first anti-reflection material layer 203 in the second modified region 212 has a relatively high etch rate. Therefore, while removing the first modified region 211, the removal amount of the second modified region 212 on the second region Ⅱ can be increased, or even completely removed, so that very little remains on the surface of the first pattern material layer 203 in the second region Ⅱ, which does not affect the subsequent etching process, enabling the subsequent formation of a uniform first pattern layer on the surface of the layer to be etched, reducing the situation of missing the first pattern layer in the second region Ⅱ, thereby improving the accuracy when defining the mask for the pattern.

[0068] The process of etching the first modified region 211 and the second modified region 212 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the process of etching the first modified region 211 and the second modified region 212 is a dry etching process. The process parameters of the dry etching process include: the etching gas includes CF4 and CHF3, and the power range is from 300 watts to 1000 watts. The dry etching process is beneficial to forming a second opening 214 with a better morphology.

[0069] Please refer to Figure 12, inject the second ions 216 to the bottom of the second opening 214, so that the first pattern material layer 202 located at the bottom of the second opening 214 forms a third modified region 217, and the first pattern material layer 202 located at the bottom of the first anti-reflection layer 212 forms a first pattern layer 218.

[0070] The process parameters for injecting the second ions 216 include: the second ions include P-type ions or N-type ions, and the energy range is 5 keV to 20 keV. In this embodiment, the second ions 216 are P-type ions. Specifically, the second ions 215 are boron.

[0071] After injecting the second ions 216, the etching rate of the first pattern material layer 202 in the subsequent process will be changed. The third modified region 217 is easily removed in the subsequent etching, and at the same time, the etching damage to the first pattern layer 218 is reduced.

[0072] Please refer to Figure 13 , remove the third modified region 217.

[0073] The process for removing the third modified region 217 includes one or a combination of both a dry etching process and a wet etching process. In this embodiment, the process for removing the third modified region 217 is a dry etching process. The process parameters of the dry etching process include: the etching gas includes CF4 and CHF3, and the power range is 300 watts to 1000 watts. The dry etching utilizes the first pattern layer 218 with a better sidewall morphology.

[0074] In this embodiment, after removing the third modified region 217, the first anti-reflection layer 213 is also removed.

[0075] In this embodiment, the first pattern layer 218 exposes a partial surface of the second pattern material layer 205.

[0076] The first pattern layer 218 can be used as a mask layer for pattern definition, or can be used as a mandrel in the process of pattern definition (such as self-aligned double patterning technology (SADP)). Subsequently, a sidewall is formed on the sidewall of the first pattern layer 218, and the sidewall is used to define a smaller size pattern. In this embodiment, the first pattern layer 218 is used as a mandrel, and a sidewall is formed on the sidewall of the first pattern layer 218 subsequently.

[0077] Please refer to Figure 14 , form a sidewall 219 on the sidewall of the first pattern layer 218.

[0078] The material of the sidewall 219 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon silicon oxide, carbon silicon nitride, and carbon silicon oxynitride. In this embodiment, the material of the sidewall 219 is silicon oxide.

[0079] The method for forming the sidewall 219 includes: depositing a sidewall material layer (not shown in the figure) on the surface of the first graphic layer 218 and the second graphic material layer 205, and etching back the sidewall material layer until the top surfaces of the first graphic layer 218 and the second graphic material layer 206 are exposed to form the sidewall 219.

[0080] The width of the sidewall 219 is determined by the thickness of the sidewall material layer. The thickness of the sidewall material layer can be adjusted to control the width of the sidewall 219. The sidewall 219 can be used as a mask for pattern definition. To improve the accuracy of pattern transfer, in this embodiment, the sidewall 219 is also used to form a second pattern layer, and the second pattern layer is used as a mask for pattern definition. For a method of forming the second pattern layer, please refer to Figures 15 to 16 .

[0081] Please refer to Figure 15 After forming the sidewall 219, the first graphic layer 218 is removed.

[0082] The process of removing the first pattern layer 218 includes one of a wet etching process and a dry etching process or a combination of the two.

[0083] In this embodiment, the material of the first graphic layer 218 is determined by the material of the first graphic material layer 202, the first graphic layer 218 is amorphous silicon, and the process of removing the first graphic layer 218 is a wet etching process. The parameters of the wet etching process include: the solution used includes an ammonia solution, the temperature is 30 degrees to 80 degrees, and the concentration of the ammonia solution is 30%-70% (volume ratio). Since the ammonia solution has a high selectivity ratio to the amorphous silicon material and the silicon oxide material, it is beneficial to reduce the damage to the sidewall 219 during the removal of the first graphic layer 218.

[0084] Since the above process reduces the missing of the first graphic layer 218 on the second area II, the formed sidewall 219 has the characteristic of being uniformly distributed in the second graphic material layer 205. Using the sidewall 219 as a mask can improve the accuracy of graphic definition.

[0085] Please refer to Figure 16 , using the sidewall 219 as a mask, etching the second graphic material layer 206 (such as Figure 15 As shown), until the surface of the layer to be etched 201 is exposed, forming a second pattern layer 220.

[0086] The process of etching the second graphic material layer 205 includes a dry etching process and a wet etching process. In this embodiment, the process of etching the second graphic material layer 205 is a dry etching process. The process parameters of the dry etching process include: the etching gas includes CF4 and CHF3, and the power range is from 300 watts to 1000 watts. The dry etching process is conducive to forming a second graphic layer 220 with a better morphology.

[0087] Subsequently, the second graphic layer 220 can be used as a mask in the graphic definition process. Since the second graphic layer 220 is obtained by transferring the pattern of the sidewall 219, it also has the characteristic of uniform distribution on the surface of the layer to be etched 201. Using the second graphic layer 220 as a mask can improve the accuracy of graphic definition.

[0088] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing an etch target layer, the etch target layer including a first region and a second region surrounding the first region; Forming a first pattern material layer on the surface of the etch target layer, a first anti-reflection material layer on the surface of the first pattern material layer, and a second anti-reflection material layer on the surface of the first anti-reflection material layer; Patterning the second anti-reflection material layer to form a second anti-reflection layer and a first opening within the second anti-reflection layer, and exposing the surface of the first anti-reflection material layer at the bottom of the first opening on the first region, with the remaining portion of the second anti-reflection material layer on the second region forming a residual layer; Injecting first ions into the bottom of the first opening to form a first modified region in the first anti-reflection material layer exposed by the first opening, forming a second modified region in the first anti-reflection material layer on the second region and the residual layer, such that the density of the first modified region is greater than the density of the first anti-reflection material layer in the second modified region; Etching the first modified region and the second modified region until the first modified region is removed, causing the first anti-reflection material layer to form a first anti-reflection layer, and the etching rate of the first anti-reflection material layer in the second modified region being greater than the etching rate of the first modified region.

2. The method for forming a semiconductor structure according to claim 1, wherein There is a second opening within the first anti-reflection layer, and the bottom of the second opening exposes the surface of the first pattern material layer on the first region.

3. The method for forming a semiconductor structure according to claim 2, wherein Further comprising: Injecting second ions into the bottom of the second opening to form a third modified region in the first pattern material layer at the bottom of the second opening, forming a first pattern layer in the first pattern material layer at the bottom of the first anti-reflection layer; removing the third modified region.

4. The method for forming a semiconductor structure as described in claim 3, wherein, Further comprising: Forming sidewalls on the sidewalls of the first pattern layer; before forming the sidewalls, also removing the first anti-reflection layer and the second anti-reflection layer; after forming the sidewalls, removing the first pattern layer.

5. The method for forming a semiconductor structure according to claim 4, wherein, The material of the sidewalls includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon silicon nitride, and carbon oxynitride silicon.

6. The method for forming a semiconductor structure according to claim 4, wherein, Before forming the first pattern material layer, further comprising: forming a second pattern material layer on the surface of the etch target layer, the second pattern material layer being located between the first pattern material layer and the etch target layer.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The material of the second pattern material layer includes one or more of titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon silicon nitride, and carbon oxynitride silicon.

8. The method for forming a semiconductor structure according to claim 6, wherein The first pattern layer exposes a partial surface of the second pattern material layer.

9. The method for forming a semiconductor structure according to claim 8, wherein, Further comprising: Using the sidewalls as a mask to etch the second pattern material layer until the surface of the etch target layer is exposed, forming a second pattern layer.

10. The method for forming a semiconductor structure as described in claim 1, wherein, The method of patterning the second anti-reflection material layer includes: forming a patterned photoresist layer on the second anti-reflection material layer, the photoresist layer exposing the second anti-reflection material layer on the second region and a partial second anti-reflection material layer on the first region; using the photoresist layer as a mask to etch the second anti-reflection material layer.

11. The method for forming a semiconductor structure according to claim 10, wherein, Further comprising: After injecting the first ions into the bottom of the first opening, removing the photoresist layer.

12. The method for forming a semiconductor structure according to claim 1, wherein, The process parameters for implanting the first ions include: the first ions include P-type ions or N-type ions, and the energy range is from 5 keV to 20 keV.

13. The method for forming a semiconductor structure according to claim 1, wherein, The selectivity range of the process for etching the first modified region and the second modified region with respect to the first modified region and the second modified region is greater than or equal to 1.2:

1.

14. The method for forming a semiconductor structure according to claim 1, wherein The process for etching the first modified region and the second modified region includes one or a combination of a dry etching process and a wet etching process.

15. The method for forming a semiconductor structure as described in claim 1, wherein, The process for etching the first modified region and the second modified region includes a dry etching process, and the process parameters of the dry etching process include: the etching gas includes one or a combination of CF4 and CHF3, and the power range is from 300 watts to 1000 watts.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, Including: The material of the second anti-reflection material layer includes an organic polymer.

17. The method for forming a semiconductor structure according to claim 1, wherein, Including: The material of the first anti-reflection material layer includes a carbon-containing polymer.

18. The method for forming a semiconductor structure according to claim 1, wherein, Including: The material of the first pattern material layer includes silicon.

19. The method for forming a semiconductor structure according to claim 1, wherein, The thickness range of the residual layer is less than or equal to 200 angstroms.

20. The method for forming a semiconductor structure according to claim 1, wherein, After removing the first modified region, the thickness of the second modified region remaining on the surface of the first pattern material layer located on the second region is less than or equal to 200 angstroms.

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