A semiconductor structure and a method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method includes: providing a substrate, the substrate including a base, a plurality of fin portions located on the surface of the base, and a first isolation structure located on the surface of the base, the first isolation structure being located on a partial sidewall surface of the fin portions, and a top surface of the first isolation structure being lower than a top surface of the fin portions, the fin portions including a first region and a second region arranged along an extending direction of the fin portions; removing the first region to form a trench in the fin portions, a bottom of the trench being lower than a top surface of the first isolation structure, and sidewalls of the trench exposing the first isolation structure and the second region; forming a second isolation structure in the trench, during the process of forming the second isolation structure, only etching the fin portions, without causing partial stress release of the first isolation structure, so that the stress distribution of the transistor remains unchanged, improving the electrical performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] As the semiconductor process scale shrinks, the impact of the process layout on circuit design, especially the design of analog circuits, becomes increasingly significant. More importantly, some of the impacts do not originate from the layout of the device itself, but are affected by the surrounding environment, such as the impact of the insulation isolation structure.

[0003] In the existing semiconductor field, the fin field-effect transistor (FinFET) has stronger short-channel suppression ability and stronger working current, and has now been widely used in various semiconductor devices. The substrate surface of the fin field-effect transistor has an STI (shallow trench isolation) isolation structure covering its fin portion, and the material of the STI isolation structure is an oxide isolation medium. In order to fabricate smaller and more densely distributed fins, the prior art introduces a single diffusion barrier, forming one or more barrier trenches along the length direction of the fin, and then filling these trenches with an oxide isolation medium through processes such as thermal oxidation to divide the fin into multiple small fins, thereby manufacturing smaller fin field-effect transistor devices. Due to the different thermal expansion coefficients of the silicon substrate and the isolation medium oxide, the STI isolation structure and the barrier trenches generate compressive stress to squeeze the active region and the channel of the adjacent MOS transistor, causing changes in the electrical parameters of the device.

[0004] Therefore, the method for forming the fin field-effect transistor structure in the prior art needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the performance of the semiconductor structure.

[0006] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a base, a plurality of fin portions located on the surface of the base, and a first isolation structure located on the surface of the base, the first isolation structure being located on the sidewall surface of a part of the fin portions, and the top surface of the first isolation structure being lower than the top surface of the fin portions, the fin portions including a first region and a second region arranged along the extending direction of the fin portions; removing the first region to form a trench in the fin portion, the bottom of the trench being lower than the top surface of the first isolation structure, and the sidewall of the trench exposing the first isolation structure and the second region; and forming a second isolation structure in the trench.

[0007] Optionally, the method for forming the trench includes: etching the first region using a first process to remove the fins above the surface of the first isolation structure; after the first process, etching the first region using a second process to form an initial trench within the fins, wherein the etching rate of the second process for the first region is greater than that for the first isolation structure; after the second process, etching the initial trench using a third process to form the trench.

[0008] Optionally, it includes: the first process includes one or a combination of a dry etching process and a wet etching process; the second process includes an anisotropic dry etching process; the third process includes a wet etching process or a dry etching process.

[0009] Optionally, the process parameters of the second process include: the gases used include CF4, HBr, O2, Cl2, wherein the flow rate of CF4 is from 30 standard milliliters per minute to 80 standard milliliters per minute, the flow rate of HBr is from 10 standard milliliters per minute to 300 standard milliliters per minute, the flow rate of O2 is from 30 standard milliliters per minute to 80 standard milliliters per minute, and the flow rate of Cl2 is from 50 standard milliliters per minute to 3000 standard milliliters per minute.

[0010] Optionally, before forming the trench, it further includes: forming a gate layer spanning across the fins, and a part of the gate layer is also located on the first isolation structure; forming source and drain regions within the fins on both sides of the gate layer; forming an interlayer dielectric layer on the substrate, and the interlayer dielectric layer is also located on the sidewalls of the gate layer.

[0011] Optionally, the material of the gate layer includes silicon or metal.

[0012] Optionally, the method for forming the trench includes: forming a patterned layer on the surfaces of the interlayer dielectric layer and the gate layer, and the patterned layer exposes the gate layer or the interlayer dielectric layer on the first region; using the patterned layer as a mask to etch the gate layer or the interlayer dielectric layer to form a first opening within the interlayer dielectric layer or between two adjacent gate layers, and the first opening exposes a part of the first region above the first isolation structure and the surface of the first isolation structure; using the patterned layer as a mask to etch the first region to form the trench within the first isolation structure.

[0013] Optionally, multiple gate layers respectively span across the first region and the second region; using the patterned layer as a mask to etch the gate layer on the first region.

[0014] Optionally, the gate layer spans across the second region, and the interlayer dielectric layer is located on the surface of the first region; using the patterned layer as a mask, the interlayer dielectric layer on the first region is etched.

[0015] Optionally, it further includes: removing a part of the first region at the bottom of the first opening that is higher than the first isolation layer, forming a second opening in the interlayer dielectric layer, between adjacent two gate layers, in the fin portion, and on the surface of the first isolation layer; forming sidewalls on the sidewall surfaces of the second opening.

[0016] Optionally, the material of the sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride; the thickness range of the sidewall is 1 to 5 nanometers.

[0017] Optionally, the second isolation structure is also located in the second opening.

[0018] Optionally, the material of the first isolation structure is an insulating dielectric material; the material of the first isolation structure includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride; the material of the second isolation structure is an insulating dielectric material; the material of the second isolation structure includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride.

[0019] Correspondingly, the technical solution of the present invention further provides a semiconductor structure, including: a substrate, the substrate includes a base, a plurality of fin portions located on the surface of the base, and a first isolation structure located on the surface of the base, the first isolation structure is located on a partial sidewall surface of the fin portion, and the top surface of the first isolation structure is lower than the top surface of the fin portion, the fin portion includes a first region and a second region arranged along the extending direction of the fin portion; a trench located in the fin portion and within the first isolation structure, the bottom of the trench is lower than the top surface of the first isolation structure, and the sidewall of the trench exposes the first isolation structure and the second region; a second isolation structure located in the trench.

[0020] Optionally, it further includes: a gate layer spanning across the fin portion, a part of the gate layer is located on the first isolation structure; source-drain regions in the fin portions on both sides of the gate layer; an interlayer dielectric layer located on the substrate, the interlayer dielectric layer is also located on the sidewall of the gate layer; a second opening located in the interlayer dielectric layer or between adjacent two gate layers, the bottom of the second opening is flush with the top surface of the first isolation structure; the second isolation structure is also located in the second opening.

[0021] Optionally, it further includes: sidewalls located on the sidewall surfaces of the second opening.

[0022] Optionally, it includes: the material of the sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride; the thickness range of the sidewall is 1 to 5 nanometers.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] In a method for forming a semiconductor device provided by the technical solution of the present invention, the fin portion includes a first region and a second region. The fin portion is etched to remove the first region, a trench is formed in the first isolation structure, and the sidewalls of the trench expose the first isolation structure and the second region. A second isolation structure is formed in the trench. During the process of forming the second isolation structure, only the fin portion is etched, so the original first isolation structure is not changed, and the situation of partial stress release of the first isolation structure will not occur, thereby keeping the transistor stress distribution unchanged and improving the electrical performance of the device.

[0025] Furthermore, the second isolation structure is also located in a second opening. By changing the filling method and filling material of the second opening, a stress distribution beneficial to improving the electrical performance of the transistor can be obtained, and the electrical performance of the device can be further improved.

[0026] In the structure of the semiconductor device provided by the technical solution of the present invention, a trench located in the first region and within the first isolation structure, the sidewalls of the trench expose the first isolation structure and the second region, and a second isolation structure is located in the trench. The original first isolation structure is not changed, and the situation of partial stress release of the first isolation structure will not occur, thereby keeping the transistor stress distribution unchanged and improving the electrical performance of the device.

[0027] Furthermore, the second isolation structure is also located in a second opening. By changing the filling material within the second opening, a stress distribution beneficial to improving the electrical performance of the transistor can be obtained, and the electrical performance of the device can be further improved. Description of the Drawings

[0028] Figures 1 to 4 is a schematic cross-sectional structure diagram of a semiconductor structure;

[0029] Figures 5 to 12 is a schematic cross-sectional structure diagram corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Embodiments

[0030] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0031] As described in the background art, the performance of the semiconductor structure formed by the existing fin field-effect transistor needs to be improved urgently. A semiconductor structure will be described and analyzed in combination below.

[0032] Figures 1 to 4 It is a cross-sectional schematic diagram of the process of forming a semiconductor structure.

[0033] This embodiment provides a cross-sectional schematic diagram of the process of forming a semiconductor structure along the X direction and a cross-sectional schematic diagram along the Y direction.

[0034] Please refer to Figure 1 , a substrate 100 is provided. The substrate 100 includes a base 101, fin portions 102 on the surface of the base, and a first isolation structure 103 covering part of the side walls of the fin portions 102. The top surface of the first isolation structure 103 is lower than the top surface of the fin portions 102; a gate layer 104 is formed across the fin portions 102, and the gate layer 104 is located on the first isolation structure 103; source-drain regions 105 are formed in the fin portions 102 on both sides of the gate layer 104; an interlayer dielectric layer 106 is formed on the surface of the substrate 100, and the interlayer dielectric layer 106 is also located on the side walls of the gate layer 104, exposing the surface of the gate layer 104.

[0035] The material of the first isolation structure 103 is silicon oxide, and the first isolation structure 103 is used to achieve electrical insulation between different semiconductor devices.

[0036] The materials of the base 101 and the fin portions 102 are silicon.

[0037] The material of the gate layer 104 is polysilicon.

[0038] Please refer to Figure 2 , a patterned hard mask layer 107 is formed on the surface of the interlayer dielectric layer 106, and the hard mask layer 107 exposes part of the gate layer 104; using the hard mask layer 107 as a mask, the gate layer 104 is etched to remove part of the gate layer 104, and a first opening 108 is formed in the interlayer dielectric layer 106.

[0039] Please refer to Figure 3 , using the hard mask layer 107 as a mask, the interlayer dielectric layer 106, the fin portions 102 and the first isolation structure 103 are etched, and a second opening 109 is formed in the substrate 100.

[0040] Please refer to Figure 4 , a silicon oxide material layer is filled in the first opening 108 and the second opening 109 to form a second isolation structure 110.

[0041] The above method is used in the fin isolation structure of a fin field-effect transistor. The materials of the second isolation structure 110 and the first isolation structure 103 are both oxide isolation dielectrics. Due to the different thermal expansion coefficients of the silicon substrate and the isolation dielectric oxide, the second isolation structure 110 will generate compressive stress on the substrate 100. When forming the second isolation structure 110, in addition to etching the fin 102, part of the first isolation structure 103 will also be etched away, resulting in partial stress release at the position where the etched-away first isolation structure 103 is located, thereby changing the distribution of the transistor stress, and further causing changes in the electrical parameters of the device, affecting the performance of the device.

[0042] To solve the above problems, in a semiconductor device structure and a method for forming the same provided by the present invention, the fin includes a first region and a second region. The fin is etched to remove the first region, a trench is formed in the first isolation structure, the sidewall of the trench exposes the first isolation structure, and a second isolation structure is formed in the trench. During the process of forming the second isolation structure, only the fin is etched, so the original first isolation structure is not changed, and the situation of partial stress release of the first isolation structure will not occur, thereby keeping the transistor stress distribution unchanged and improving the electrical performance of the device.

[0043] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0044] Figures 5 to 12 It is a schematic cross-sectional structure diagram corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present invention. This embodiment gives a schematic cross-sectional diagram of the semiconductor structure formation process along the X direction and a schematic cross-sectional diagram along the Y direction.

[0045] Please refer to Figure 5 , a substrate 200 is provided. The substrate 200 includes a base 201, a plurality of fins 202 located on the surface of the base 201, and a first isolation structure 203 located on the surface of the base 201. The first isolation structure 203 is located on the sidewall surface of a part of the fins 202, and the top surface of the first isolation structure 203 is lower than the top surface of the fins 202. The fins 202 include a first region Ⅰ and a second region Ⅱ arranged along the extending direction of the fins 202.

[0046] The material of the base 201 can be semiconductor materials such as silicon, single crystal germanium, silicon germanide, gallium arsenide, etc., and can also be a semiconductor-on-insulator structure. In this embodiment, the material of the base 201 is single crystal silicon.

[0047] The material of the fins 202 includes silicon, silicon germanium materials. In this embodiment, the material of the fins 202 is single crystal silicon.

[0048] The material of the first isolation structure 203 is an insulating dielectric material; the material of the first isolation structure 203 includes one or more of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride. In this embodiment, the material of the first isolation structure 203 is silicon oxide. The first isolation structure 203 is used for electrical insulation between different devices.

[0049] The forming process of the first isolation structure 203 includes a chemical vapor deposition process. In this embodiment, the forming process of the second isolation structure 203 is an HDP CVD (high density plasma chemical vapor deposition) process.

[0050] Subsequently, the first region I is removed, and a trench is formed in the fin 202. The bottom of the trench is lower than the top surface of the first isolation structure 203, and the sidewalls of the trench expose the first isolation structure 203 and the second region II. For the forming method, please refer to Figures 6 to 11 .

[0051] Please refer to Figure 6 , and a gate layer 204 is formed across the fin 202, and a part of the gate layer 204 is also located on the first isolation structure 203.

[0052] This embodiment further includes: forming source / drain regions 205 in the fins 202 on both sides of the gate layer 204; forming an interlayer dielectric layer 206 on the substrate 200, and the interlayer dielectric layer 206 is also located on the sidewalls of the gate layer 204. The material of the interlayer dielectric layer 206 includes one or more of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride.

[0053] In this embodiment, the gate layer 204 is located on the first region I and the second region II. In another embodiment, the gate layer 204 is located on the second region II, and the interlayer dielectric layer 206 is located on the surface of the first region I.

[0054] The material of the gate layer 204 includes silicon or metal. In this embodiment, the material of the gate layer 204 is polysilicon, and the gate layer 204 is used as a dummy gate of the device.

[0055] In another embodiment, the material of the gate layer is metal, and the gate layer is used as the gate of the device. Before forming the trench, it further includes: forming a dummy gate across the fin, and a part of the dummy gate is also located on the first isolation structure; forming source and drain regions in the fins on both sides of the dummy gate; forming an interlayer dielectric layer on the substrate, and the interlayer dielectric layer is also located on the sidewalls of the dummy gate; removing the dummy gate, forming a gate opening in the interlayer dielectric layer, and forming the gate layer in the gate opening.

[0056] Please refer to Figure 7 , a patterned layer 207 is formed on the surfaces of the interlayer dielectric layer 206 and the gate layer 204, and the patterned layer 207 exposes the gate layer 204 or the interlayer dielectric layer 206 on the first region I; using the patterned layer 207 as a mask, etching the gate layer 204 or the interlayer dielectric layer 206, and forming a first opening 208 in the interlayer dielectric layer 206 or between two adjacent gate layers 204, and the first opening 208 exposes a part of the first region I higher than the first isolation structure 203 and the surface of the first isolation structure 203.

[0057] The material of the patterned layer 207 includes one or more of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride.

[0058] In this embodiment, a plurality of gate layers 204 span across the first region I and the second region, and the patterned layer 207 exposes the gate layer 204 on the first region I.

[0059] In another embodiment, the gate layer 204 spans across the second region II, and the interlayer dielectric layer 206 is located on the surface of the first region I, and the patterned layer 207 exposes the interlayer dielectric layer 206 on the first region I.

[0060] In this embodiment, using the patterned layer 207 as a mask, etching the gate layer 204 to form a first opening 208 in the interlayer dielectric layer 206. In another embodiment, using the patterned layer 207 as a mask, etching the interlayer dielectric layer 206 to form a first opening 208 between two adjacent gate layers 204.

[0061] The process of etching the gate layer 204 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the process of etching the gate layer 204 is a wet etching process. The method of etching the gate layer 204 includes: the solution used includes tetramethylammonium hydroxide or potassium hydroxide solution, so that during the etching process of removing the gate layer 204, the gate layer 204 has a relatively large etching selectivity with respect to the interlayer dielectric 206 and the fin 200.

[0062] In another embodiment, the method of etching the interlayer dielectric layer 206 includes dry etching.

[0063] Please refer to Figure 8 , removing a part of the first region I at the bottom of the first opening 208 that is higher than the first isolation layer 203, and forming a second opening 209 in the interlayer dielectric layer 206, between two adjacent gate layers 204, in the fin portion 203, and on the surface of the first isolation layer 203.

[0064] In this embodiment, the second opening 209 is formed in the interlayer dielectric layer 206, in the fin portion 203, and on the surface of the first isolation layer 203. In another embodiment, the second opening 209 is formed between two adjacent gate layers 204, in the fin portion 203, and on the surface of the first isolation layer 203. Specifically, the surface of the fin portion 203 further has source / drain regions 205, and further includes: etching the source / drain regions 205.

[0065] Etch the first region I using a first process to remove the fin portion 203 that is higher than the surface of the first isolation structure 203. The first process includes one or both of a dry etching process and a wet etching process. In this embodiment, the first process is dry etching. The parameters of the first process include: the gases used include CF4, HBr, O2, and Cl2, where the flow rate of CF4 is 30 standard milliliters per minute to 80 standard milliliters per minute, the flow rate of HBr is 10 standard milliliters per minute to 300 standard milliliters per minute, the flow rate of O2 is 30 standard milliliters per minute to 80 standard milliliters per minute, and the flow rate of Cl2 is 50 standard milliliters per minute to 3000 standard milliliters per minute.

[0066] Please refer to Figure 9 , and form a sidewall 210 on the sidewall surface of the second opening 209.

[0067] The material of the sidewall 210 includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon nitride silicon, or carbon oxynitride silicon; the thickness range of the sidewall 210 is 1 to 5 nanometers. In this embodiment, the thickness of the sidewall 210 is 2 nanometers.

[0068] The sidewall 210 is used to protect the interlayer dielectric layer 206 from damage when forming a subsequent trench. The subsequent formed second isolation structure is located in the second opening 209, thereby further reducing the adverse impact of the damage on the sidewall surface of the interlayer dielectric layer 206 on the material filling in the second opening 209.

[0069] In this embodiment, the sidewall 210 is also located on the bottom surface of the second opening 209. In other embodiments, the sidewall 210 is only located on the sidewall surface of the second opening 209.

[0070] Subsequently, using the patterned layer 207 as a mask to etch the first region I, a trench is formed within the first isolation structure 203. For the method of forming the trench, please refer to Figures 10 to 11 .

[0071] Please refer to Figure 10 , and use a second process to etch the first region I to form an initial trench 211 within the fin 202. The etching rate of the second process for the first region I is greater than that for the first isolation structure 203.

[0072] The second process includes an anisotropic dry etching process. In this embodiment, the second process is an anisotropic dry etching process, and the etching selectivity of the second etching process for the first region I and the isolation structure 203 ranges from 30:1 to 10:1. The parameters of the second process include: the gases used include CF4, HBr, O2, and Cl2. Among them, the flow rate of CF4 is from 30 standard milliliters per minute to 80 standard milliliters per minute, the flow rate of HBr is from 10 standard milliliters per minute to 300 standard milliliters per minute, the flow rate of O2 is from 30 standard milliliters per minute to 80 standard milliliters per minute, and the flow rate of Cl2 is from 50 standard milliliters per minute to 3000 standard milliliters per minute.

[0073] In this embodiment, the first process and the second process are completed in one step in the same etching process, reducing the process steps and the production cost.

[0074] Since the second process is an anisotropic dry etching process, but the fin 211 has a shape with a wider bottom than the top in a direction parallel to the surface of the substrate 200 and perpendicular to the extending direction of the fin 211, therefore, after using the second process, there will be some remaining fins on the sidewall of the initial trench 211 adjacent to the first isolation structure 203, and the sidewall of the initial trench 211 does not expose the first isolation structure 203.

[0075] Please refer to Figure 11 , and after the second process, use a third process to etch the initial trench 211 to form the trench 212.

[0076] The third process includes a wet etching process or a dry etching process. In this embodiment, the third process is a wet etching process. In other embodiments, the third process is a dry etching process, and the etching selectivity range of the third process for the first region I and the isolation structure 203 is from 1.2:1 to 1:1. The etching rates of the third process for the first region I and the isolation structure 203 are not very different. The bottom of the trench 212 is lower than the top surface of the first isolation structure 203, and the sidewalls of the trench 212 expose the first isolation structure 203 and the second region II.

[0077] The significance of using the third process is that the initial trench 211 is further etched by the third process to remove some of the fins remaining on the sidewalls of the trench 212, so that the sidewalls of the trench 212 expose the first isolation structure 203. Due to over-etching of the third process, the initial trench 212 may have a shape with a middle bulge in the extending direction of the fin. In this embodiment, the formed trench 212 has a shape with a middle bulge.

[0078] The trench 212 is located within the fin 202 and does not change the first isolation structure 203. Subsequently, a second isolation structure is formed within the trench 212. Therefore, the stress of the first isolation structure 203 will not have a stress release situation when the second isolation structure is formed, and it will not cause a change in the stress distribution of the transistor, improving the performance of the device.

[0079] Please refer to Figure 12 , and a second isolation structure 213 is formed within the trench 212.

[0080] The formation process of the second isolation structure 213 includes a chemical vapor deposition process. In this embodiment, the formation process of the second isolation structure 213 is an HDP CVD (high density plasma chemical vapor deposition) process. The HDP CVD process bombards and sputters etch with a high density of ion plasma to prevent premature closing of the trench 212 during chemical vapor deposition and to avoid void phenomena within the trench 212. The step coverage of HDP CVD is very good and can effectively fill the voids in the trench 212.

[0081] The material of the second isolation structure 213 includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, or silicon carbon oxynitride. In this embodiment, the material of the second isolation structure 213 is silicon oxide.

[0082] The second isolation structure 213 is used as a single diffusion isolation or a double diffusion isolation of the device to achieve electrical insulation between different devices.

[0083] In this embodiment, the second isolation structure 213 is also located within the second opening 209. By changing the filling material within the second opening 209, a stress distribution beneficial for improving the electrical performance of the transistor can be obtained, further improving the electrical performance of the device.

[0084] Correspondingly, the technical solution of the present invention also provides an embodiment of a semiconductor structure formed by the above formation method. Please continue to refer to Figure 12 , including: a substrate 200, the substrate 200 includes a base 201, a plurality of fin portions 202 located on the surface of the base 201, and a first isolation structure 203 located on the surface of the base 201. The first isolation structure 203 is located on the sidewall surface of a part of the fin portions 202, and the top surface of the first isolation structure 203 is lower than the top surface of the fin portions 203. The fin portions 202 include a first region I and a second region II arranged along the extending direction of the fin portions 202; a trench 212 (as Figure 11 shown) located within the fin portions 202 and within the first isolation structure 203. The bottom of the trench 212 is lower than the top surface of the first isolation structure 203, and the sidewalls of the trench 212 expose the first isolation structure 203 and the second region II; a second isolation structure 213 located within the trench 212. The second isolation structure 213 is located within the fin portions 203, without changing the original first isolation structure, and will not cause partial stress release of the first isolation structure, thereby keeping the stress distribution of the transistor unchanged and improving the electrical performance of the device.

[0085] The semiconductor structure further includes: a gate layer 204 spanning the fin portions 203, and a part of the gate layer 204 is located on the first isolation structure 203 (not shown in the figure); source-drain regions 205 within the fin portions 203 on both sides of the gate layer 204; an interlayer dielectric layer 206 located on the substrate 200, and the interlayer dielectric layer 206 is also located on the sidewalls of the gate layer 204; a second opening 209 (as Figure 9 shown) within the interlayer dielectric layer 206 or between two adjacent gate layers 204. The bottom of the second opening 209 is flush with the top surface of the first isolation structure 203; the second isolation structure 213 is also located within the second opening 209 (as Figure 11 described). By changing the filling material within the second opening 209, a stress distribution beneficial for improving the electrical performance of the transistor can be obtained, further improving the electrical performance of the device.

[0086] In this embodiment, the second opening 209 is located within the interlayer dielectric layer 206. In another embodiment, the second opening 209 is located between two adjacent gate layers 204.

[0087] The semiconductor structure described above further includes: a spacer 210 located on the sidewall surface of the second opening 209.

[0088] The material of the spacer 210 includes one or more of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride.

[0089] The thickness range of the spacer 210 is from 1 to 5 nanometers.

[0090] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including a base, a plurality of fin portions located on the surface of the base, and a first isolation structure located on the surface of the base, the first isolation structure being located on the sidewall surface of a part of the fin portions, and the top surface of the first isolation structure being lower than the top surface of the fin portions, the fin portions including a first region and a second region arranged along the extending direction of the fin portions; Forming a gate layer across the fin portions, and a part of the gate layer is also located on the first isolation structure; Forming an interlayer dielectric layer on the substrate, and the interlayer dielectric layer is also located on the sidewalls of the gate layer; Etching the interlayer dielectric layer to form a first opening between two adjacent gate layers, the first opening exposing a part of the first region higher than the first isolation structure and the surface of the first isolation structure; Removing a part of the first region higher than the first isolation layer at the bottom of the first opening to form a second opening between two adjacent gate layers, within the fin portions, and on the surface of the first isolation layer; Continuing to etch the first region to remove the first region, forming a trench within the fin portions, the bottom of the trench being lower than the top surface of the first isolation structure, and the sidewalls of the trench exposing the first isolation structure and the second region; Forming a second isolation structure within the trench and within the second opening.

2. The method for forming a semiconductor structure according to claim 1, wherein The method of forming the trench includes: etching the first region using a first process to remove the fin portions higher than the surface of the first isolation structure; after the first process, etching the first region using a second process to form an initial trench within the fin portions, the etching rate of the second process for the first region being greater than the etching rate for the first isolation structure; after the second process, etching the initial trench using a third process to form the trench.

3. The method for forming a semiconductor structure according to claim 2, wherein, Including: The first process includes one or a combination of a dry etching process and a wet etching process; the second process includes an anisotropic dry etching process; the third process includes a wet etching process or a dry etching process.

4. The method for forming a semiconductor structure according to claim 2, wherein, The process parameters of the second process include: the gases used include CF4, HBr, O2, Cl2, wherein the flow rate of CF4 is 30 standard milliliters per minute to 80 standard milliliters per minute, the flow rate of HBr is 10 standard milliliters per minute to 300 standard milliliters per minute, the flow rate of O2 is 30 standard milliliters per minute to 80 standard milliliters per minute, and the flow rate of Cl2 is 50 standard milliliters per minute to 3000 standard milliliters per minute.

5. The method for forming a semiconductor structure according to claim 1, wherein, Before forming the trench, it further includes: forming source-drain regions within the fin portions on both sides of the gate layer.

6. The method for forming a semiconductor structure according to claim 5, wherein, The material of the gate layer includes silicon or metal.

7. The method for forming a semiconductor structure according to claim 5, wherein The method of forming the trench further includes: forming a patterned layer on the surfaces of the interlayer dielectric layer and the gate layer, the patterned layer exposing the interlayer dielectric layer on the first region; using the patterned layer as a mask to etch the interlayer dielectric layer; using the patterned layer as a mask to etch the first region to form the trench within the first isolation structure.

8. The method for forming a semiconductor structure according to claim 7, wherein The gate layer spans across the second region, and the interlayer dielectric layer is located on the surface of the first region; using the patterned layer as a mask, the interlayer dielectric layer on the first region is etched.

9. The method for forming a semiconductor structure according to claim 7, wherein, Further included are: A sidewall is formed on the sidewall surface of the second opening.

10. The method for forming a semiconductor structure according to claim 9, wherein, The material of the sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or silicon carbon nitride oxynitride; the thickness range of the sidewall is 1 to 5 nanometers.

11. The method for forming a semiconductor structure according to claim 9, wherein, The second isolation structure is also located within the second opening.

12. The method for forming a semiconductor structure according to claim 1, wherein, The material of the first isolation structure is an insulating dielectric material; the material of the first isolation structure includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or silicon carbon nitride oxynitride; the material of the second isolation structure is an insulating dielectric material; the material of the second isolation structure includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or silicon carbon nitride oxynitride.

13. A semiconductor structure, characterized in that, Included are: A substrate, the substrate includes a base, a plurality of fin portions located on the surface of the base, and a first isolation structure located on the surface of the base, the first isolation structure is located on a partial sidewall surface of the fin portions, and the top surface of the first isolation structure is lower than the top surface of the fin portions, the fin portions include a first region and a second region arranged along the extending direction of the fin portions; A gate layer spanning across the fin portions, a part of the gate layer is located on the first isolation structure; An interlayer dielectric layer located on the substrate, the interlayer dielectric layer is also located on the sidewalls of the gate layer; A second opening located between two adjacent gate layers, the bottom of the second opening is flush with the top surface of the first isolation structure; A trench located within the fin portions and within the first isolation structure, the bottom of the trench is lower than the top surface of the first isolation structure, and the sidewalls of the trench expose the first isolation structure and the second region; A second isolation structure located within the trench and within the second opening.

14. The semiconductor structure according to claim 13, wherein, Further included are: Source-drain regions located within the fin portions on both sides of the gate layer.

15. The semiconductor structure according to claim 14, wherein Further included are: A sidewall located on the sidewall surface of the second opening.

16. The semiconductor structure according to claim 15, wherein Included are: The material of the sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or silicon carbon nitride oxynitride; the thickness range of the sidewall is 1 to 5 nanometers.

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