A fan-out packaging method

Abstract

The application discloses a fan-out packaging method, which comprises the following steps: providing a carrier plate and arranging a first chip on the carrier plate; forming a plurality of blocking pieces and a plurality of conductive columns in sequence on the periphery of the first chip; wherein the plurality of conductive columns are located on the periphery of the plurality of blocking pieces, and the height of the conductive column is greater than the height of the blocking piece; forming a plastic sealing layer on the side of the carrier plate provided with the first chip, so that the first chip, the blocking piece and the conductive column form an integral structure; and removing the carrier plate. Through the above method, the application can reduce the deformation amount generated by the shrinkage of the plastic sealing material, and ensure the stability of the chip; and the blocking pieces and the conductive columns with different heights can also effectively save the packaging material, thereby reducing the packaging cost.

Description

TECHNICAL FIELD

[0001] The application relates to the chip packaging technical field, in particular to a fan-out packaging method. BACKGROUND

[0002] In a conventional fan-out packaging method, after a chip is molded, the molding compound in the packaging structure is deformed due to shrinkage, which easily causes the chip to deviate in the packaging structure, thereby reducing the service life of the chip. SUMMARY

[0003] The application mainly solves the technical problem of providing a fan-out packaging method, which can reduce the deformation amount of the molding compound due to shrinkage and ensure the stability of the chip.

[0004] To solve the above technical problem, one technical scheme of the application is to provide a fan-out packaging method, which comprises the following steps: providing a carrier plate and arranging a first chip on the carrier plate; forming a plurality of blocking pieces and a plurality of conductive columns in the periphery of the first chip in sequence; wherein the plurality of conductive columns are located in the periphery of the plurality of blocking pieces, and the height of the conductive column is greater than the height of the blocking piece; forming a molding layer on the side of the carrier plate provided with the first chip, so that the first chip, the blocking piece and the conductive column form an integral structure; and removing the carrier plate.

[0005] The blocking piece has a conductive property.

[0006] The step of forming the plurality of blocking pieces and the plurality of conductive columns in the periphery of the first chip in sequence comprises the following steps: forming a first photoresist layer on the side of the carrier plate provided with the first chip; exposing and developing the first photoresist layer to form a plurality of first vias on the first photoresist layer, and the plurality of first vias are located in the periphery of the first chip; forming the blocking piece in the first via; forming a second photoresist layer on the side of the first photoresist layer away from the carrier plate; exposing and developing the first photoresist layer and the second photoresist layer to form a plurality of second vias on the first photoresist layer and the second photoresist layer, and the plurality of second vias are located in the periphery of the plurality of first vias; and forming the conductive column in the second via.

[0007] The step of forming the blocking piece in the first via comprises the following steps: forming the blocking piece in the first via by sputtering metal process; and before the step of forming the second photoresist layer on the side of the first photoresist layer away from the carrier plate, the step of removing the sputtered metal on the surface of the side of the first photoresist layer away from the carrier plate is further included.

[0008] Before the step of forming a plastic encapsulation layer on the side of the carrier plate provided with the first chip, the method comprises: removing all the first photoresist layers and all the second photoresist layers; and forming insulating glue at least on the periphery of the plurality of blocking pieces.

[0009] Before the step of forming a plastic encapsulation layer on the side of the carrier plate provided with the first chip, the method comprises: removing all the second photoresist layers and the first photoresist layers around the conductive columns.

[0010] The first chip comprises a first functional surface and a first non-functional surface arranged oppositely, and the first non-functional surface of the first chip faces the carrier plate. Before the step of forming a plastic encapsulation layer on the side of the carrier plate provided with the first chip, the method further comprises: arranging at least one second chip on the side of the first chip away from the carrier plate, and forming underfill glue at least between the second functional surface of the second chip and the carrier plate, and the blocking pieces are located in the underfill glue. The second functional surface of the second chip faces the first functional surface of the first chip, the second chip spans at least part of the first chip and at least part of the blocking pieces adjacent to the at least part of the first chip, and the second pads on the second functional surface of the second chip are electrically connected with the first pads on the first functional surface of the first chip and the blocking pieces at corresponding positions.

[0011] The step of forming a plastic encapsulation layer on the side of the carrier plate provided with the first chip comprises: forming the plastic encapsulation layer on the side of the carrier plate provided with the first chip, and the plastic encapsulation layer covers the conductive columns, the second chip, and the gaps in the space surrounded by the conductive columns; and grinding the plastic encapsulation layer from the side of the plastic encapsulation layer away from the carrier plate, so that the surfaces of the plastic encapsulation layer, the conductive columns, and the second chip away from the carrier plate are flush.

[0012] The first chip comprises a first functional surface and a first non-functional surface arranged oppositely, and the first functional surface of the first chip faces the carrier plate. The step of forming a plastic encapsulation layer on the side of the carrier plate provided with the first chip comprises: forming the plastic encapsulation layer on the side of the carrier plate provided with the first chip, and the plastic encapsulation layer covers the conductive columns and the gaps in the space surrounded by the conductive columns. The surfaces of the plastic encapsulation layer and the conductive columns away from the carrier plate are flush.

[0013] The method further comprises: forming a first redistribution layer and a second redistribution layer on both sides of the conductive column in the length direction of the conductive column; the first redistribution layer is electrically connected with the conductive column and the first chip; the second redistribution layer is electrically connected with the conductive column; a first electrical connector is arranged on the side of the first redistribution layer away from the conductive column; and a second electrical connector is arranged on the side of the second redistribution layer away from the conductive column.

[0014] The application has the following advantages: different from the prior art, the application forms a plurality of blocking pieces and a plurality of conductive columns around the chip; the plurality of blocking pieces and the plurality of conductive columns are equivalent to coffer dams, which can limit the movement of the plastic encapsulation material in the plastic encapsulation layer, so as to reduce the deformation amount of the plastic encapsulation material due to shrinkage and reduce the probability of warping of the first chip; in addition, the conductive column can also realize a three-dimensional vertical interconnection structure, which is beneficial to reducing the height of the fan-out package device; in addition, the blocking pieces and the conductive columns with different heights can also effectively save material costs. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings. Among them:

[0016] Figure 1 is a flowchart of an embodiment of the fan-out packaging method of the application;

[0017] Figure 2 is a cross-sectional structure schematic diagram of an embodiment corresponding to step S101;

[0018] Figure 3 is a flowchart of an embodiment corresponding to step S102;

[0019] Figure 4a is a cross-sectional structure schematic diagram of an embodiment corresponding to step S201;

[0020] Figure 4b is a cross-sectional structure schematic diagram of an embodiment corresponding to step S202;

[0021] Figure 4c is a cross-sectional structure schematic diagram of another embodiment corresponding to step S202;

[0022] Figure 5 is a flowchart of an embodiment corresponding to step S103;

[0023] Figure 6ais a sectional structure schematic diagram of step S301 corresponding to an embodiment;

[0024] Figure 6b is a sectional structure schematic diagram of step S301 corresponding to an embodiment;

[0025] Figure 7a is a sectional structure schematic diagram of step S302 corresponding to an embodiment;

[0026] Figure 7b is a sectional structure schematic diagram of step S302 corresponding to an embodiment;

[0027] Figure 8 is a sectional structure schematic diagram of step S104 corresponding to an embodiment;

[0028] Figure 9 is a sectional structure schematic diagram of another embodiment of the fan-out packaging method of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0030] Please refer to Figure 1 , Figure 1 is a flowchart of an embodiment of the fan-out packaging method of the present application, which comprises the following steps:

[0031] S101: disposing a first chip on a carrier plate.

[0032] Specifically, please refer to Figure 2 , Figure 2 is a sectional structure schematic diagram of step S101 corresponding to an embodiment, Figure 2 is only schematic and for the purpose of convenience and understanding, Figure 2 only one first chip 100 is drawn, but in actual applications, multiple first chips 100 can be disposed on the carrier plate 50 at intervals, so that the fan-out packaging method of the present application is used for multiple first chips 100 to obtain multiple packaged chip structures, and a single packaged chip structure is obtained by cutting the middle part of two adjacent packaged chip structures.

[0033] In an application mode, step S101 specifically includes: disposing the first chip 100 on the carrier plate 50, the first chip 100 including a first functional surface 1001 and a first non-functional surface 1002 disposed opposite to each other, and the first non-functional surface 1002 of the first chip 100 facing the carrier plate 50. Wherein, the first functional surface 1001 of the first chip 100 is provided with a plurality of first pads 10 (only two are drawn in the figure) to receive and / or transmit signals.

[0034] Optionally, the first non-functional surface 1002 of the first chip 100 can be fixed with the carrier plate 50 by bonding glue; or at least one first chip 100 can be pasted on the double-sided adhesive tape by attaching the double-sided adhesive tape on the carrier plate 50, and at this time, the first non-functional surface 1002 of the first chip 100 faces the carrier plate 50. Wherein, the material of the carrier plate 50 can be one of silicon, glass, metal and organic compound. Disposing the first chip 100 on the carrier plate 50 can play a certain limiting role on the first chip 100.

[0035] S102: Forming a plurality of blocking pieces and a plurality of conductive columns on the periphery of the first chip in sequence.

[0036] Please refer to Figure 3 , Figure 3 For the flowchart of an embodiment corresponding to step S102, the step includes:

[0037] S201: Forming a first photoresist layer on the side of the carrier plate provided with the first chip, forming a plurality of first vias on the photoresist layer, and forming a blocking piece in the first via.

[0038] Please refer to Figure 4a , Figure 4ais a sectional structure schematic diagram corresponding to an embodiment of step S201. In an application, a first photoresist layer 101 is formed on the side of the carrier plate 50 facing the first chip 100; the first photoresist layer 101 is exposed and developed to form a plurality of first vias 1010 on the first photoresist layer 101, and the plurality of first vias 1010 are located at the periphery of the first chip 100. The barrier 20 is formed in the first via 1010. Wherein, the side of the first photoresist layer 101 facing away from the carrier plate 50 is flush with the first functional surface 1001 of the first chip 100, that is, the end of the barrier 20 facing away from the carrier plate 50 is flush with the first functional surface 1001 of the first chip 100, to facilitate the subsequent execution of step S301. Specifically, the part of the first photoresist layer 101 at the periphery of the first chip 100 is exposed and developed, and the first photoresist layer 101 after exposure and development is removed to form a plurality of first vias 1010, and the barrier 20 is formed in the first via 1010 by sputtering metal process. Specifically, a film with a plurality of openings can be provided on the side of the first photoresist layer 101 facing away from the carrier plate 50, and the side of the film facing away from the carrier plate 50 is exposed and developed to remove the first photoresist layer 101 at the positions corresponding to the plurality of openings on the film, thereby forming a plurality of first vias 1010, and the barrier 20 is formed in the first via 1010. Wherein, the barrier 20 has conductive performance to facilitate the subsequent execution of step S301, and the material thereof can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper. By using the method of forming the first via 1010 on the first photoresist layer 101 to form the barrier 20, the difficulty of forming the barrier 20 in the packaging process can be effectively reduced. In the present application, the first photoresist layer 101 can also cover the first functional surface 1001 of the first chip 100, and the first photoresist layer at the position corresponding to the first functional surface 1001 of the first chip 100 is exposed and developed to form a third via, and the third via is filled with conductive metal to form a conductive bump, and the conductive bump is helpful for the chip electrically connected to the first chip 100 to be arranged on the side of the first functional surface 1001 of the first chip 100.

[0039] S202: Forming a second photoresist layer on the side of the first photoresist layer facing away from the carrier plate, forming a plurality of second vias on the first photoresist layer and the second photoresist layer, and forming a conductive column in the second via.

[0040] Specifically, before forming the second photoresist layer 102 on the side of the first photoresist layer 101 away from the carrier plate 50, the sputtered metal on the surface of the side of the first photoresist layer 101 away from the carrier plate 50 is removed to avoid the sputtered metal on the surface affecting the exposure and development of the first photoresist layer 101 and the second photoresist layer 102, resulting in the failure to form the second via hole 1020. In this embodiment, the thickness of the first photoresist layer 101 can be reduced as a whole by using the method of exposing and developing the surface of the side of the first photoresist layer 101 away from the carrier plate 50 to remove the sputtered metal on the surface of the first photoresist layer 101.

[0041] Referring to Figure 4b , Figure 4b is a sectional structure schematic diagram of an embodiment corresponding to step S202. In an embodiment, the second photoresist layer 102 is formed on the side of the first photoresist layer 101 away from the carrier plate 50, the first photoresist layer 101 and the second photoresist layer 102 are exposed and developed to form a plurality of second via holes 1020 on the first photoresist layer 101 and the second photoresist layer 102, and the plurality of second via holes 1020 are located at the periphery of the plurality of first via holes 1010; and the conductive pillar 30 is formed in the second via hole 1020. Further, the part of the first photoresist layer 101 and the second photoresist layer 102 at the peripheral position of the first via hole 1010 are exposed and developed, and the part of the first photoresist layer 101 and the second photoresist layer 102 after the exposure and development are removed to form the plurality of second via holes 1020, the plurality of second via holes 1020 are located at the periphery of the plurality of first via holes 1010, and the conductive pillar 30 is formed in the second via hole 1020 by the sputtered metal process. The material of the conductive pillar 30 can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., and is preferably titanium or copper. By using the method of forming the second via hole 1020 on the first photoresist layer 101 and the second photoresist layer 102 to form the conductive pillar 30, the difficulty of forming the conductive pillar 30 in the packaging process can be effectively reduced.

[0042] Optionally, referring to Figure 4c , Figure 4c is a sectional structure schematic diagram of another embodiment corresponding to step S202. The embodiment includes: after step S201, exposing and developing all the remaining first photoresist layer 101 to remove all the remaining first photoresist layer 101. Further, the second photoresist layer 102 is reformed on the side of the carrier plate 50 provided with the first chip 100, the height of the second photoresist layer 102 is higher than the height of the blocking piece 20; the second photoresist layer 102 is exposed and developed to form a plurality of second via holes 1020 on the second photoresist layer 102, and the plurality of second via holes 1020 are located at the periphery of the blocking piece 20; and the conductive pillar 30 is formed in the second via hole 1020 by the sputtered metal process. The conductive pillar 30 can realize the interconnection in the vertical direction after the chip packaging.

[0043] S103: Forming a plastic encapsulation layer on the side of the carrier substrate facing the first chip.

[0044] When the non-functional side of the first chip faces the carrier substrate, refer to Figure 5 , Figure 5 A flowchart of an embodiment of step S103 is shown in the following. The method comprises:

[0045] S301: Providing at least one second chip on the side of the first chip facing away from the carrier substrate, and forming an underfill adhesive between at least the second functional side of the second chip and the carrier substrate.

[0046] When the non-functional side of the first chip faces the carrier substrate, refer to Figure 6a , Figure 6a A cross-sectional structure diagram of an embodiment before step S301 is shown in the following. In an application, before step S301, the first photoresist layer 101 and all second photoresist layers 102 are removed to expose the blocking pieces 20 and the conductive pillars 30, and an insulating adhesive 60 is formed at least on the periphery of the blocking pieces 20 to protect and position the blocking pieces 20. The insulating adhesive 60 can be formed by a drop method. Based on the surface tension of the adhesive, the surface of the insulating adhesive 60 is arc-shaped, and the height of the insulating adhesive 60 does not exceed the height of the blocking pieces 20. In another application, only the second photoresist layers 102 and the first photoresist layer 101 around the conductive pillars 30 are removed, and part of the first photoresist layer 101 around the blocking pieces 20 is retained. This method does not need to additionally provide the insulating adhesive 60, and the remaining first photoresist layer 101 around the blocking pieces 20 can protect and position the blocking pieces 20, thereby reducing the packaging cost.

[0047] When the non-functional side of the first chip faces the carrier substrate, refer to Figure 6b , Figure 6b A cross-sectional structure diagram of an embodiment of step S301 is shown in the following, Figure 6b which is only schematic and is provided for the purpose of explanation only, Figure 6bOnly two second chips 200 are drawn in the figure, but in actual applications, one or more second chips 200 can be arranged on the side of the first functional surface 1001 of the first chip 100. The second chip 200 includes a second functional surface 2001 and a second non-functional surface 2002 arranged oppositely, and a plurality of second pads 40 (only two are drawn in the figure) are arranged on the second functional surface 2001 of the second chip 200 to receive and / or transmit signals. Specifically, the implementation process of the above step S301 includes: arranging at least one second chip 200 on the side of the first functional surface 1001 of the first chip 100 away from the carrier board 50; wherein the second functional surface 2001 of the second chip 200 faces the first functional surface 1001 of the first chip 100, the second chip 200 spans at least part of the first chip 100 and at least part of the blocking member 20 adjacent to the at least part of the first chip 100, and the second pads 40 on the second functional surface 2001 of the second chip 200 are electrically connected with the first pads 10 on the first functional surface 1001 of the first chip 100 and the blocking member 20 at corresponding positions. Based on the electrical connection between the part of the second pads 40 of the second chip 200 and the part of the first pads 10 of the first chip 100, information interaction between the first chip 100 and the second chip 200 can be realized; and based on the electrical connection between the second chip 200 and the part of the blocking member 20, and the electrical conductivity of the blocking member 20, i.e., the blocking member 20 can be electrically connected with the first chip 100 through the second chip 200, and information interaction with the first chip 100 and the second chip 200 can be realized only through the blocking member 20. In response to the end of the blocking member 20 away from the carrier board 50 being flush with the first functional surface 1001 of the first chip 100, it can be ensured that no tilt occurs when the second chip 200 is arranged, thereby ensuring the stability of the second chip 200.

[0048] Further, please continue to refer to Figure 6b , step S301 further includes: forming an underfill adhesive 25 between at least the second functional surface 2001 of the second chip 200 and the carrier board 50, and the blocking member 20 is located in the underfill adhesive 25 to play a certain fixing and protection role for the first chip 100, the second chip 200 and the blocking member 20. Specifically, the vertical section of the underfill adhesive 25 in the present application is trapezoidal, which can improve the stability of the fan-out device; in other application modes, the vertical section of the underfill adhesive 25 can also be rectangular, etc. Optionally, the side of the underfill adhesive 25 away from the carrier board 50 can be flush with the second functional surface 2001 of the second chip 200, or can be higher than the second functional surface 2001 of the second chip 200, which is not limited in the present application. In addition, in other embodiments, the underfill adhesive 25 can also not be arranged, i.e., step S302 is directly performed after the second chip 200 is arranged.

[0049] S302: Forming a plastic encapsulation layer on the side of the carrier board where the first chip is arranged.

[0050] Referring to Figure 7a , Figure 7a A cross-sectional structure diagram corresponding to an embodiment of step S302 is shown in FIG. 4. In this embodiment, a plastic encapsulation layer 130 is formed on the side of the carrier substrate 50 where the first chip 100 is located. The plastic encapsulation layer 130 covers the conductive pillars 30, the second chip 200, and the gap in the space surrounded by the conductive pillars 30, thereby fixing and protecting the first chip 100, the second chip 200, the barrier 20, and the conductive pillars 30. The material of the plastic encapsulation layer 130 can be epoxy resin or the like, which can be formed by a compression process.

[0051] Further referring to Figure 7b , Figure 7b A cross-sectional structure diagram corresponding to an embodiment after step S302 is shown in FIG. 5. After the plastic encapsulation layer 130 is formed on the side of the carrier substrate 50 where the first chip 100 is located, the plastic encapsulation layer 130 can be ground from the side of the plastic encapsulation layer 130 away from the carrier substrate 50, so that the surfaces of the plastic encapsulation layer 130, the conductive pillars 30, and the second chip 200 away from the carrier substrate 50 are flush. Properly grinding the plastic encapsulation layer 130 can reduce the overall thickness of the chip package and improve heat dissipation.

[0052] S104: removing the carrier substrate.

[0053] Referring to Figure 8 , Figure 8 A cross-sectional structure diagram corresponding to an embodiment of step S104 is shown in FIG. 6. In one embodiment, step S104 specifically includes removing the carrier substrate 50 and forming a first redistribution layer 150 and a second redistribution layer 160 on both sides of the conductive pillars 30 in the length direction. The first redistribution layer 150 is located on the side of the first chip 100 away from the second chip 200, and the first redistribution layer 150 is electrically connected to the conductive pillars 30 and the barrier 20. The first redistribution layer 150 is electrically connected to the first chip 100 through the second chip 200 based on the barrier 20. The first redistribution layer 150 is electrically connected to at least the conductive pillars 30 and the first chip 100. The second redistribution layer 160 is located on the side of the second chip 200 away from the first chip 100, and the second redistribution layer 160 is electrically connected to the conductive pillars 30. Optionally, the first redistribution layer 150 and the second redistribution layer 160 each include a dielectric layer and a patterned metal layer. In addition, the number of layers of the first redistribution layer 150 and the second redistribution layer 160 can be one or more, which is not limited in the present application. The first redistribution layer 150 and the second redistribution layer 160 can be used to electrically connect the first chip 100 and / or the second chip 200.

[0054] Further, the first electric connecting body 170 is arranged on the side of the first re-wiring layer 150 away from the conductive column 30, and the second electric connecting body 180 is arranged on the side of the second re-wiring layer 160 away from the conductive column 30. Optionally, a plurality of solder balls 80 can be formed between the first re-wiring layer 150 and the first electric connecting body 170, and between the second re-wiring layer 160 and the second electric connecting body 180, to facilitate the connection between the first re-wiring layer 150 and the first electric connecting body 170, and the connection between the second re-wiring layer 160 and the second electric connecting body 180. The first electric connecting body 170 and the second electric connecting body 180 can be subsequently electrically connected with a substrate or other integrated chips, thereby realizing information interaction.

[0055] The present application forms a plurality of blocking pieces 20 and a plurality of conductive columns 30 on the periphery of the first chip 100, thereby realizing a three-dimensional vertical interconnection structure, reducing the deformation amount caused by the shrinkage of the plastic sealing material, and ensuring the stability of the chip. The blocking pieces 20 and the conductive columns 30 of different heights can also effectively save packaging materials, thereby reducing packaging costs.

[0056] Of course, in other embodiments, before step S102, the first functional surface 1001 of the first chip 100 faces the carrier board 50; at this time, please refer to Figure 9 , Figure 9 The cross-sectional structure diagram of another embodiment of the fan-out packaging method of the present application is shown in response to the first chip 100 including the first functional surface 1001 and the first non-functional surface 1002 arranged opposite to each other. In this embodiment, the first functional surface 1001 of the first chip 100 faces the carrier board 50, and a plurality of blocking pieces 20 and a plurality of conductive columns 30 are formed on the periphery of the first chip 100 in sequence through the above-mentioned Figure 1 step S102. Then, the plastic sealing layer 130 is formed on the side of the carrier board 50 where the first chip 100 is arranged, and the plastic sealing layer 130 covers the conductive column 30 and the gap in the space surrounded by the conductive column 30; wherein the surface of the plastic sealing layer 130 away from the carrier board 50 is flush with the surface of the conductive column 30.

[0057] Further, the carrier plate 50 is removed, and the first re-wiring layer 150 and the second re-wiring layer 160 are respectively formed on both sides of the conductive column 30 in the length direction. The first re-wiring layer 150 is located on the side of the first functional surface 1001 of the first chip 100, and the second re-wiring layer 160 is located on the side of the plastic sealing layer 130 away from the first functional surface 1001 of the first chip 100. Then, the first electrical connector 170 is arranged on the side of the first re-wiring layer 150 away from the conductive column 30, and the second electrical connector 180 is arranged on the side of the second re-wiring layer 160 away from the conductive column 30. Optionally, a plurality of solder balls 80 can be formed between the first re-wiring layer 150 and the first electrical connector 170, and between the second re-wiring layer 160 and the second electrical connector 180, to facilitate the connection between the first re-wiring layer 150 and the first electrical connector 170, and the connection between the second re-wiring layer 160 and the second electrical connector 180.

[0058] The above embodiment faces the first functional surface 1001 of the first chip 100 to the carrier plate 50, and then performs packaging on the first chip 100 by the fan-out packaging method provided in the present application. The three-dimensional vertical interconnection structure is realized, the deformation amount of the plastic sealing material due to shrinkage is reduced, the stability of the chip is ensured, and the packaging materials can be effectively saved by the design of the blocking member 20 and the conductive column 30 of different heights, thereby reducing the packaging cost.

[0059] The above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation, or direct or indirect application in other related technical fields based on the content of the specification and drawings of the present application, are also included in the patent protection scope of the present application.

Claims

1. A fan-out packaging method, characterized in that: include: Providing a carrier board, and placing a first chip on the carrier board; A plurality of blocking members and a plurality of conductive pillars are sequentially formed around the periphery of the first chip; wherein the plurality of conductive pillars are located around the plurality of blocking members, and the height of the conductive pillars is greater than the height of the blocking members; the blocking members are conductive, and an end of the blocking members facing away from the carrier is flush with the first functional surface of the first chip; forming a plastic packaging layer on a side of the carrier board where the first chip is provided, so that the first chip, the blocking member and the conductive pillar form an integral structure; Remove the carrier board; The step of sequentially forming a plurality of blocking members and a plurality of conductive pillars on the periphery of the first chip comprises: forming a first photoresist layer on a side of the carrier board on which the first chip is provided; exposing and developing the first photoresist layer to form a plurality of first via holes on the first photoresist layer, and the plurality of first via holes are located on the periphery of the first chip; forming the blocking members in the first via holes; forming a second photoresist layer on a side of the first photoresist layer facing away from the carrier board; exposing and developing the first photoresist layer and the second photoresist layer to form a plurality of second via holes on the first photoresist layer and the second photoresist layer, and the plurality of second via holes are located on the periphery of the plurality of first via holes; and forming the conductive pillars in the second via holes. Wherein, the first chip includes a first functional surface and a first non-functional surface arranged in back to back relation, and the first non-functional surface of the first chip faces the carrier; before the step of forming a plastic encapsulation layer on the side of the carrier where the first chip is arranged, it includes: removing all the second photoresist layers and the first photoresist layer around the conductive pillar; arranging at least one second chip on the side of the first functional surface of the first chip away from the carrier, and forming an underfill at least between the second functional surface of the second chip and the carrier, and the blocking member is located in the underfill; wherein, the second functional surface of the second chip faces the first functional surface of the first chip, the second chip spans at least a portion of the first chip and at least a portion of the blocking member adjacent to at least a portion of the first chip, and the second pad on the second functional surface of the second chip is electrically connected to the first pad on the first functional surface of the first chip at the corresponding position and the blocking member; wherein, the conductive pillar and the surface of the second chip away from the carrier are flush.

2. The fan-out packaging method according to claim 1, wherein: The step of forming the blocking member in the first via hole includes: forming the blocking member in the first via hole by a metal sputtering process; Before the step of forming the second photoresist layer on the side of the first photoresist layer facing away from the carrier, the method includes: removing the sputtered metal on the surface of the first photoresist layer facing away from the carrier.

3. The fan-out packaging method according to claim 1, wherein: The step of forming a plastic sealing layer on the side of the carrier board where the first chip is provided comprises: forming the plastic encapsulation layer on the side of the carrier board where the first chip is arranged, and the plastic encapsulation layer covers the conductive pillars, the second chip, and the gap in the space enclosed by the conductive pillars; The plastic encapsulation layer is ground from a side of the plastic encapsulation layer away from the carrier board, so that the plastic encapsulation layer, the conductive pillars and the second chip have flush surfaces on a side away from the carrier board.

4. The fan-out packaging method according to claim 1, wherein: The first chip includes a first functional surface and a first non-functional surface arranged in back to back relationship, and the first functional surface of the first chip faces the carrier board; the step of forming a plastic encapsulation layer on the side of the carrier board where the first chip is arranged includes: forming a plastic encapsulation layer on the side of the carrier board where the first chip is arranged, the plastic encapsulation layer covering the conductive pillars and the gaps in the space enclosed by the conductive pillars; wherein the plastic encapsulation layer is flush with the surface of the conductive pillars on the side facing away from the carrier board.

5. The fan-out packaging method according to claim 1, wherein: After removing the carrier board, the method further comprises: A first redistribution layer and a second redistribution layer are formed on both sides of the conductive pillar in the length direction, respectively; wherein the first redistribution layer is electrically connected to at least the conductive pillar and the first chip, and the second redistribution layer is electrically connected to the conductive pillar; A first electrical connector is provided on a side of the first redistribution layer away from the conductive pillar, and a second electrical connector is provided on a side of the second redistribution layer away from the conductive pillar.

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