A method for preparing a device and its structure

Abstract

A method for preparing a device and its structure disclosed in an embodiment of the present application includes performing ion implantation on a second substrate to form a defect layer inside the second substrate to obtain a structure to be bonded, bonding the structure to be bonded and a first substrate to obtain a heterogeneous substrate, and bonding a third substrate and the heterogeneous substrate to obtain a heterogeneous composite substrate; the heterogeneous composite substrate includes an area to be etched, an area to be grown, and an area to be fabricated; the area to be etched, the area to be grown, and the area to be fabricated are sequentially connected. A modulation-doped field-effect transistor structure is fabricated in the area to be etched, an isolation structure is fabricated in the area to be grown, and a complementary metal-oxide-semiconductor structure is fabricated in the area to be fabricated. The modulation-doped field-effect transistor structure is connected to the complementary metal-oxide-semiconductor structure to obtain a device. The present application can be compatible with modulation-doped field-effect transistors and complementary metal-oxide-semiconductors, and can reduce thermal stress.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic devices, and particularly to a method for fabricating a device and its structure. Background Art

[0002] A high electron mobility transistor (HEMT), also known as a modulation-doped field effect transistor, has characteristics such as high electron mobility, high efficiency and low power consumption, high operating frequency, high power gain, and radiation resistance, and is widely used in microwave, millimeter-wave integrated circuits, and ultra-high-speed digital integrated circuits.

[0003] Indium phosphide (InP) is an optimal material for fabricating HEMT. However, there are significant problems in its compatibility with the complementary metal oxide semiconductor (CMOS) process of silicon substrate integrated circuits. Therefore, the application of HEMT devices based on indium phosphide (InP) is severely restricted. To solve the compatibility problem, the prior art proposes a heterogeneous integration method that combines a silicon (Si) substrate and an indium phosphide (InP) thin film. The mainstream methods include the ion beam lift-off transfer method and the heteroepitaxial method. Due to the lattice mismatch and thermal mismatch between the silicon (Si) substrate and the indium phosphide (InP) thin film, the heteroepitaxial method will introduce a large number of defects, such as dislocations, antiphase domains, etc. These defects, as the scattering and recombination centers of carriers, will introduce defect energy levels in the forbidden band, thereby reducing the carrier mobility in the device. In contrast, the ion beam lift-off transfer method can improve the lattice quality of the indium phosphide (InP) thin film and reduce the influence of the device by lattice mismatch and thermal stress, which is beneficial to the growth of subsequent device structures and the improvement of performance.

[0004] During the fabrication process of the heterogeneous substrate, due to the design requirements of the device structure, there is a silicon dioxide layer between the silicon (Si) substrate and the indium phosphide (InP) thin film. Due to the low thermal conductivity of the silicon dioxide layer, such as 0.27 W / cm·K, during the operation of the device, the temperature is extremely likely to rise, seriously affecting the performance of the device, such as the threshold current, output power, power density, etc. Moreover, due to the different thermal expansion coefficients of the silicon (Si) substrate and the indium phosphide (InP) thin film, a large thermal stress will be introduced during the temperature rise process to damage the device. Summary of the Invention

[0005] The embodiments of the present application provide a method for preparing a device and its structure. Based on a traditional heterogeneous substrate including a silicon substrate and an indium phosphide layer disposed on the silicon substrate, silicon carbide is introduced, and the indium phosphide layer is disposed on the silicon carbide layer to form a heterogeneous composite substrate, so that the obtained device can be compatible with a modulation-doped field-effect transistor and a complementary metal-oxide semiconductor. Moreover, the problem that high-thermal-conductivity silicon carbide and a silicon substrate cannot coexist can be solved. In addition, by using the fact that silicon carbide has a thermal expansion coefficient close to that of the indium phosphide layer along the C axis, the thermal stress can be reduced, the performance of the device can be improved, and the service life of the device can be extended.

[0006] The embodiments of the present application provide a method for preparing a device, including:

[0007] Obtaining a first substrate, a second substrate, and a third substrate; the first substrate has a bonding surface, and the second substrate has an implantation surface;

[0008] Performing ion implantation on the second substrate from the implantation surface to form a defect layer inside the second substrate, obtaining a structure to be bonded;

[0009] Bonding the implantation surface of the structure to be bonded and the bonding surface of the first substrate to obtain a heterogeneous substrate;

[0010] Bonding the third substrate and the heterogeneous substrate to obtain a heterogeneous composite substrate; the heterogeneous composite substrate includes an area to be etched, an area to be grown, and an area to be prepared; the area to be etched, the area to be grown, and the area to be prepared are sequentially connected and arranged;

[0011] Preparing a modulation-doped field-effect transistor structure in the area to be etched, preparing an isolation structure in the area to be grown, and preparing a complementary metal-oxide semiconductor structure in the area to be prepared;

[0012] Connecting the modulation-doped field-effect transistor structure and the complementary metal-oxide semiconductor structure to obtain a device.

[0013] Further, the material of the first substrate is single-crystal silicon carbide; the single-crystal silicon carbide includes 6H-SiC and 4H-SiC;

[0014] The material of the second substrate is indium phosphide;

[0015] The material of the third substrate includes a first silicon layer, a buried oxide layer, and a second silicon layer. The first silicon layer is disposed on the buried oxide layer, and the buried oxide layer is disposed on the second silicon layer.

[0016] Further, the set range of the implantation temperature for performing ion implantation on the second substrate from the implantation surface is 0°C to 150°C;

[0017] The set range of the implantation energy for performing ion implantation on the second substrate from the implantation surface is 1 keV to 1000 keV;

[0018] The setting range of the ion implantation dose for ion implantation of the second substrate from the implantation surface is 1×10 16 cm -2 ~3×10 17 cm -2 ;

[0019] The ion implantation species for ion implantation of the second substrate from the implantation surface is light ions; the light ions include hydrogen ions, helium ions, and co-implantation of hydrogen and helium ions.

[0020] Furthermore, a modulation-doped field-effect transistor structure is fabricated in the area to be etched, including:

[0021] The area to be etched is etched to form a window structure; the implantation surface corresponding to the window structure is exposed to air;

[0022] A buffer layer, a channel layer, an isolation layer, a doping layer, a barrier layer, and a contact layer are sequentially fabricated in the window structure;

[0023] A source electrode, a drain electrode, and a gate electrode are fabricated on the contact layer to obtain a modulation-doped field-effect transistor structure.

[0024] Furthermore, an isolation structure is fabricated in the area to be grown, including:

[0025] The area to be grown is grooved by photolithography and wet etching to obtain a grooved structure; the first substrate corresponding to the grooved structure is exposed to air;

[0026] An isolation structure is grown in the grooved structure by plasma-enhanced chemical vapor deposition.

[0027] Furthermore, before ion implantation of the second substrate from the implantation surface, it further includes:

[0028] A deposition layer is fabricated on the implantation surface by chemical vapor deposition;

[0029] After obtaining the structure to be bonded, it further includes:

[0030] The structure to be bonded is cleaned to remove the deposition layer.

[0031] Furthermore, the bonding methods for bonding the third substrate and the hetero-substrate include hydrophilic bonding, dielectric layer bonding, surface activation bonding, and temperature-rising bonding.

[0032] Furthermore, bonding the implantation surface of the structure to be bonded and the bonding surface of the first substrate to obtain a hetero-substrate, including:

[0033] Bonding the implantation surface of the structure to be bonded and the bonding surface of the first substrate to obtain a first substrate to be processed;

[0034] Peel off a part of the first substrate along the defective layer of the first substrate to be processed, obtaining a second substrate to be processed;

[0035] Perform post-annealing treatment and surface polishing treatment on the second substrate to be processed, obtaining a heterogeneous substrate.

[0036] Further, the set range of the temperature of the post-annealing treatment is 300°C to 600°C;

[0037] The set range of the time of the post-annealing treatment is 1h to 10h;

[0038] The atmosphere of the post-annealing includes nitrogen, oxygen, vacuum, and nitrogen.

[0039] Correspondingly, the embodiment of the present application provides a device structure, including:

[0040] A heterogeneous composite substrate; the heterogeneous composite substrate includes a first substrate, a second substrate disposed on the first substrate, and a third substrate disposed on the second substrate. The third substrate includes an area to be etched, an area to be grown, and an area to be prepared; the area to be etched, the area to be grown, and the area to be prepared are connected in sequence;

[0041] A modulation-doped field-effect transistor structure disposed in the area to be etched;

[0042] An isolation structure disposed in the area to be grown;

[0043] A complementary metal-oxide semiconductor structure disposed in the area to be prepared; the modulation-doped field-effect transistor structure is connected to the complementary metal-oxide semiconductor structure.

[0044] The embodiment of the present application has the following beneficial effects:

[0045] A method for preparing a device and its structure disclosed in an embodiment of the present application. The preparation method includes obtaining a first substrate, a second substrate, and a third substrate. The first substrate has a bonding surface, and the second substrate has an implantation surface. Ion implantation is performed on the second substrate from the implantation surface to form a defect layer inside the second substrate, obtaining a structure to be bonded. The implantation surface of the structure to be bonded is bonded to the bonding surface of the first substrate to obtain a heterogeneous substrate. The third substrate is bonded to the heterogeneous substrate to obtain a heterogeneous composite substrate. The heterogeneous composite substrate includes an area to be etched, an area to be grown, and an area to be prepared. The area to be etched, the area to be grown, and the area to be prepared are sequentially connected. A modulation-doped field-effect transistor structure is prepared in the area to be etched, an isolation structure is prepared in the area to be grown, and a complementary metal-oxide-semiconductor structure is prepared in the area to be prepared. The modulation-doped field-effect transistor structure is connected to the complementary metal-oxide-semiconductor structure to obtain a device. Based on the embodiment of the present application, on the basis of a traditional heterogeneous substrate including a silicon substrate and an indium phosphide layer disposed on the silicon substrate, silicon carbide is introduced, and the indium phosphide layer is disposed on the silicon carbide layer to form a heterogeneous composite substrate, so that the obtained device can be compatible with a modulation-doped field-effect transistor and a complementary metal-oxide-semiconductor. And, the problem that high-thermal-conductivity silicon carbide and a silicon substrate cannot coexist can be solved. In addition, by using the fact that silicon carbide has a thermal expansion coefficient close to that of the indium phosphide layer along the C axis, thermal stress can be reduced, the performance of the device can be improved, and the service life of the device can be extended. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0047] Figure 1 It is a schematic flowchart of a method for preparing a device provided by an embodiment of the present application;

[0048] Figure 2 It is a schematic diagram of a method for preparing a device provided by an embodiment of the present application;

[0049] Figure 3 It is a schematic structural diagram of a device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings. Apparently, the described embodiments are only one embodiment of this application, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts belong to the scope of protection of this application.

[0051] As used herein, an "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation manner of this application. In the description of the embodiments of this application, it should be understood that the orientation or positional relationships indicated by terms such as "upper", "lower", "top", "bottom", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device, system, or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of this application. The terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first", "second", and "third" may explicitly or implicitly include one or more of such features. Moreover, terms such as "first", "second", and "third" are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of this application described here can be implemented in an order other than that illustrated or described here. In addition, the terms "include", "have", and "be" and any variations thereof are intended to cover non-exclusive inclusion.

[0052] The following introduces a specific embodiment of a method for preparing a device according to this application. Figure 1 is a schematic flowchart of a method for preparing a device provided by an embodiment of this application. Figure 2 is a schematic diagram of a method for preparing a device provided by an embodiment of this application. This specification provides the method operation steps as shown in the embodiments or flowcharts, but based on routine or non-creative labor, it may include more or fewer operation steps. The step sequences listed in the embodiments are only one way among many execution sequences and do not represent the only execution sequence. In actual execution, it can be executed in the order shown in the embodiments or the drawings or executed in parallel (for example, in an environment of parallel processors or multi-threaded processing).

[0053] Specifically, as Figure 1 and Figure 2 shown, the preparation method may include:

[0054] S101: Obtain a first substrate, a second substrate, and a third substrate; the first substrate has a bonding surface, and the second substrate has an implantation surface.

[0055] In the embodiments of the present application, the material of the first substrate may be single-crystalline silicon carbide SiC, and the single-crystalline silicon carbide SiC may be single-crystalline 6H-SiC or single-crystalline 4H-SiC. Optionally, the first substrate may be a single-crystalline silicon carbide SiC layer. The first substrate may have a bonding surface. Optionally, a polished surface of the single-crystalline silicon carbide SiC layer may be selected as the bonding surface. Figure 2 In FIG. a is a schematic diagram of a first substrate.

[0056] In the embodiments of the present application, the material of the second substrate may be indium phosphide InP, and the second substrate may have an implantation surface. Optionally, the second substrate may be an indium phosphide InP wafer.

[0057] In the embodiments of the present application, the third substrate may include a first silicon layer, a buried oxide layer, and a second silicon layer. The first silicon layer is disposed on the buried oxide layer, and the buried oxide layer is disposed on the second silicon layer. Optionally, the third substrate may be a silicon-on-insulator SOI, and the SOI substrate may include a buried oxide layer.

[0058] S103: Ion implant the second substrate from the implantation surface to form a defect layer inside the second substrate, obtaining a structure to be bonded.

[0059] In the embodiments of the present application, a deposition layer may be prepared on the implantation surface by chemical vapor deposition to reduce the contamination of the surface of the second substrate during subsequent ion implantation of the second substrate. Optionally, the material of the deposition layer may be silicon dioxide SiO2, and the thickness of the deposition layer may be less than or equal to 200 nm.

[0060] In the embodiments of the present application, after the deposition layer is prepared on the implantation surface of the second substrate, the second substrate may be ion implanted from the implantation surface to form a defect layer inside the second substrate, obtaining a structure to be bonded. Figure 2 In FIG. b is a schematic diagram of ion implanting the second substrate.

[0061] In a specific embodiment, the indium phosphide InP wafer may be ion implanted from the implantation surface to form a defect layer at a preset depth in the indium phosphide InP wafer, and the preset depth is related to the implantation temperature, implantation energy, and implantation species of the ion implantation. For example, the preset depth formed by a large implantation energy is deeper than the preset depth formed by a small implantation energy.

[0062] In an alternative embodiment, the implantation temperature for ion implanting the second substrate from the implantation surface may be between 0 °C and 150 °C. The implantation energy for ion implanting the second substrate from the implantation surface may be between 1 KeV and 1000 KeV. The implantation dose for ion implanting the second substrate from the implantation surface may be between 1×10 16 cm -2~3×10 17 cm -2 Between. The ion implantation species for ion implantation of the second substrate from the implantation surface may be light ions, such as hydrogen ions, helium ions, and co-implantation of hydrogen and helium ions.

[0063] In an embodiment of the present application, after obtaining the to-be-bonded structure, the to-be-bonded structure may be subjected to a cleaning process to remove the deposited layer on the second substrate. Optionally, a buffered oxide etchant (BOE) solution diluted 1:10 can be used to clean the indium phosphide (InP) wafer deposited with silicon dioxide (SiO2), so as to remove the deposited layer, i.e., silicon dioxide (SiO2), on the surface of the indium phosphide (InP) wafer. Figure 2 In FIG. c is a schematic diagram of a to-be-bonded structure, and the implantation surface of the second substrate is the implantation surface of the to-be-bonded structure.

[0064] S105: Bond the implantation surface of the to-be-bonded structure and the bonding surface of the first substrate to obtain a heterogeneous substrate.

[0065] In an embodiment of the present application, after the to-be-bonded structure is subjected to a cleaning process, the implantation surface of the to-be-bonded structure and the bonding surface of the first substrate can be bonded to obtain a first to-be-processed substrate, and a part of the first substrate is peeled off along the defect layer of the first to-be-processed substrate to obtain a second to-be-processed substrate, and then the second to-be-processed substrate is subjected to an annealing process and a surface polishing process to obtain a heterogeneous substrate. Figure 2 In FIG. d is a schematic diagram of a first to-be-processed substrate, Figure 2 In FIG. e is a schematic diagram of a heterogeneous substrate.

[0066] In an embodiment of the present application, the bonding methods for bonding the implantation surface of the to-be-bonded structure and the bonding surface of the first substrate include but are not limited to hydrophilic bonding, dielectric layer bonding, surface activation bonding, and temperature-raising bonding.

[0067] In an alternative embodiment, the bonding surface of the silicon carbide (SiC) layer can be bonded to the bonding surface of the indium phosphide (InP) wafer to initially form a SiC / InP hetero-substrate. Then, the SiC / InP hetero-substrate can be subjected to a temperature-raising peeling process to obtain a SiC / InP hetero-thin film structure. Among them, the temperature of the peeling process can be 150°C - 300°C, and the heating rate during the peeling process can be 1°C / min - 5°C / min. After initially forming the SiC / InP hetero-thin film structure, the surface residual damage layer of the SiC / InP hetero-thin film structure can be post-processed to obtain a high-quality single-crystal thin film. Optionally, the post-processing process of the SiC / InP hetero-thin film structure can include a post-annealing process and a surface treatment. The set range of the temperature of the post-annealing process can be between 300°C and 600°C, the set range of the time of the post-annealing process can be between 1h and 10h, and the atmosphere of the post-annealing can be any one of nitrogen, oxygen, vacuum, and nitrogen. The method of surface treatment can be at least one of chemical mechanical polishing, chemical etching, and low-energy particle radiation.

[0068] S107: Bond the third substrate to the hetero-substrate to obtain a hetero-composite substrate; the hetero-composite substrate includes an area to be etched, an area to be grown, and an area to be prepared; the area to be etched, the area to be grown, and the area to be prepared are sequentially connected.

[0069] In the embodiment of the present application, after obtaining the hetero-substrate, the front surface of the third substrate can be bonded to the bonding surface of the hetero-substrate to obtain a hetero-composite substrate to be processed. That is, the second silicon layer of the third substrate is bonded to the indium phosphide thin film of the hetero-substrate to obtain a hetero-composite substrate to be processed. Figure 2 Figure f is a schematic diagram of a hetero-composite substrate to be processed, Figure 2 Figure g is a schematic diagram of a hetero-composite substrate.

[0070] In the embodiment of the present application, the bonding methods for bonding the front surface of the third substrate to the bonding surface of the hetero-substrate include but are not limited to hydrophilic bonding, dielectric layer bonding, surface activation bonding, and temperature-raising bonding.

[0071] In the embodiments of the present application, after obtaining the to-be-processed heterogeneous composite substrate, the to-be-processed heterogeneous composite substrate can be subjected to post-annealing strengthening treatment, and the to-be-processed heterogeneous composite substrate after the post-annealing strengthening treatment can be subjected to etching treatment to etch the first silicon layer and the buried oxide layer to obtain a heterogeneous composite substrate. Then, the peeled heterogeneous composite substrate can be cleaned. The heterogeneous composite substrate can include an area to be etched, an area to be grown, and an area to be fabricated. The area to be etched is adjacent to the area to be grown, and the area to be grown is adjacent to the area to be fabricated. Among them, the temperature of the post-annealing treatment can be between 300°C and 600°C, the time of the post-annealing treatment can be between 1 h and 10 h, and the atmosphere of the post-annealing can be any one of nitrogen, oxygen, vacuum, and nitrogen. The solution for the etching treatment can be a hydrofluoric acid (HF) solution. Figure 2 Figure g is a schematic diagram of a heterogeneous composite substrate.

[0072] S109: Fabricate a modulation-doped field-effect transistor structure in the area to be etched, fabricate an isolation structure in the area to be grown, and fabricate a complementary metal-oxide semiconductor structure in the area to be fabricated.

[0073] In the embodiments of the present application, a complementary metal-oxide semiconductor structure, that is, a CMOS device, can be fabricated in the area to be fabricated of the heterogeneous composite substrate by using a photolithography technique.

[0074] In the embodiments of the present application, the area to be etched can be etched to form a window structure, and the injection surface corresponding to the window structure is exposed to the air. Then, a buffer layer, a channel layer, a doping layer, a barrier layer, and a contact layer are sequentially fabricated in the window structure, and a source electrode, a drain electrode, and a gate electrode are fabricated on the contact layer to obtain an adjusted-doping field-effect transistor structure, that is, a HEMT device. Optionally, a part of the second silicon layer on the heterogeneous composite substrate can be removed by using photolithography and wet etching to expose the indium phosphide layer to form a window with a certain depth. Then, a high electron mobility transistor, that is, a HEMT device structure, which is also an epitaxial structure, is epitaxially grown at the exposed window position. The HEMT device structure includes a buffer layer, a channel layer, a doping layer, a barrier layer, and a contact layer. Among them, the contact layer can be a highly doped layer to provide good ohmic contact. The sum of the thicknesses of the buffer layer, the channel layer, the doping layer, the barrier layer, and the contact layer is equal to the thickness of the unetched second silicon layer so that the fabricated CMOS device and the HMET device are coplanar, facilitating subsequent device connection. Figure 2 Figure h is a schematic diagram of a window structure. Figure 2 Figure i is a schematic diagram of an epitaxial structure.

[0075] In the embodiments of the present application, slotting treatment can be performed on the area to be grown by using photolithography and wet etching to obtain a slotted structure, and the first substrate corresponding to the slotted structure is exposed to air. Then, an isolation structure can be grown in the slotted structure by using Plasma Enhanced Chemical Vapor Deposition (PECVD). Optionally, photolithography and wet etching can be used to slot at the contact edge of the epitaxial structure and the MOS structure, and the width range of the trench can be between 5-50 μm, and the depth can penetrate through the second substrate to reach the first substrate, that is, penetrate through the indium phosphide InP wafer to reach the single-crystal silicon carbide SiC layer. Figure 2 Figure j is a schematic diagram of an isolation structure.

[0076] In an alternative embodiment, the growth material can be silicon nitride Si3N4, and the thickness of the silicon nitride Si3N4 can be higher than that of the HEMT device. Subsequently, the silicon nitride Si3N4 with a thickness higher than that of the HEMT device can be etched so that the thickness of the silicon nitride Si3N4 is equal to the thickness of the HEMT device.

[0077] S111: Connect the modulation-doped field-effect transistor structure and the complementary metal-oxide semiconductor structure to obtain a device.

[0078] In the embodiments of the present application, after preparing the modulation-doped field-effect transistor and the complementary metal-oxide semiconductor, the modulation-doped field-effect transistor and the complementary metal-oxide semiconductor can be interconnected in multiple layers to obtain a device. Figure 2 Figure k is a schematic diagram of a device.

[0079] Based on the device preparation method described above, an example will be given below for illustration.

[0080] Obtain a single-crystal 4H-SiC substrate and select a bonding surface. At the same time, an InP single-crystal substrate can be obtained, and a polished surface of the InP single-crystal substrate can be selected as the implantation surface. During the preparation process, chemical vapor deposition can be performed from the implantation surface of the InP single-crystal substrate to deposit SiO2 with a thickness of 200 nm, and at room temperature, He ion implantation can be performed from the implantation surface of the InP single-crystal substrate, and the implantation energy can be 115 KeV, and the implantation dose can be 5×10 16 cm -2Clean the InP single crystal substrate with a 1:10 diluted BOE solution to remove SiO2 on the surface of the InP single crystal substrate, hydrophilically bond the bonding surface of the single crystal 4H-SiC substrate to the implantation surface of the InP single crystal substrate, and perform a post-annealing peeling treatment on the bonded pair. The environment for the post-annealing peeling treatment is to heat up to 200 °C at a rate of 1 °C / min, hold for 5 h, and then naturally cool to room temperature to obtain a SiC / InP hetero-film structure. The InP surface of the SiC / InP hetero-film structure can be polished. Then, an SOI substrate can be obtained, and the depth of the buried oxide layer of the SOI substrate can be 660 nm from the surface. Then, hydrophilically bond the InP surface of the SiC / InP hetero-film structure to the SOI substrate, and perform a post-annealing peeling treatment on the bonded pair. The environment for the post-annealing peeling treatment is to heat up to 400 °C at a rate of 1 °C / min, hold for 2 h, and then naturally cool to room temperature, and perform etching treatment with HF to obtain a SiC / InP / Si three-layer structure. Subsequently, CMOS devices can be fabricated on a specific area of the Si layer surface of the cleaned SiC / InP / Si three-layer structure using photolithography technology, and windows can be fabricated on a specific area of the Si layer surface using photolithography and etching until the InP layer is exposed. Then, a 500-nm indium aluminum arsenide (InAlAs) buffer layer, a 30-nm indium gallium arsenide (InGaAs) buffer layer, a 10-nm indium aluminum arsenide (InAlAs) isolation layer, a 10-nm indium aluminum arsenide (InAlAs) doped layer doped with Si, a 10-nm indium aluminum arsenide (InAlAs) barrier layer, and a 100-nm indium gallium arsenide (InGaAs) contact layer doped with Si can be grown in sequence in the window. At the same time, grooves can be formed on a specific area of the Si layer surface using photolithography and wet etching. The width of the grooves can be 30 μm, and the depth can be 1350 nm. Si3N4 with a thickness of 1350 nm can be grown in the grooves using PECVD, and the Si3N4 outside the grooves can be removed by photolithography. Then, a gate, a source, and a drain can be fabricated on the indium gallium arsenide (InGaAs) contact layer using electron beam evaporation to complete the fabrication of the HEMT device, and the HMET device and the CMOS device can be connected using a multi-layer interconnect technology to obtain a device compatible with HEMT and CMOS.

[0081] Using the device fabrication method provided by the embodiments of the present application, on the basis of a traditional hetero-substrate including a silicon substrate and an indium phosphide layer disposed on the silicon substrate, silicon carbide is introduced, and the indium phosphide layer is disposed on the silicon carbide layer to form a hetero-composite substrate, so that the obtained device can be compatible with a modulation-doped field-effect transistor and a complementary metal-oxide semiconductor. And, the problem that high-thermal-conductivity silicon carbide and a silicon substrate cannot coexist can be solved. In addition, by using the fact that silicon carbide has a thermal expansion coefficient close to that of the indium phosphide layer along the C-axis, the thermal stress can be reduced, the performance of the device can be improved, and the service life of the device can be extended.

[0082] The embodiments of the present application also provide a structure of a device. Figure 3 It is a schematic structural diagram of a device provided by the embodiments of the present application. As Figure 3 shown, the device may include:

[0083] A heterogeneous composite substrate; the heterogeneous composite substrate includes a first substrate 301, a second substrate 303 disposed on the first substrate 301, and a third substrate 305 disposed on the second substrate 303. The third substrate 305 includes an area to be etched, an area to be grown, and an area to be fabricated; the area to be etched, the area to be grown, and the area to be fabricated are sequentially connected and arranged.

[0084] A modulation-doped field-effect transistor structure 307 disposed in the area to be etched;

[0085] An isolation structure 311 disposed in the area to be grown;

[0086] A complementary metal-oxide semiconductor structure 309 disposed in the area to be fabricated; the modulation-doped field-effect transistor structure 307 is connected to the complementary metal-oxide semiconductor structure 309.

[0087] The structure in the embodiments of the present application and the embodiments of the preparation method are based on the same application concept.

[0088] By using the device provided by the embodiments of the present application, on the basis of a traditional heterogeneous substrate including a silicon substrate and an indium phosphide layer disposed on the silicon substrate, silicon carbide is introduced, and the indium phosphide layer is disposed on the silicon carbide layer to form a heterogeneous composite substrate, so that the device can be compatible with a modulation-doped field-effect transistor and a complementary metal-oxide semiconductor. Moreover, the problem that high-thermal-conductivity silicon carbide and a silicon substrate cannot coexist can be solved. In addition, by using the fact that silicon carbide has a thermal expansion coefficient close to that of the indium phosphide layer along the C-axis, the thermal stress can be reduced, the performance of the device can be improved, and the service life of the device can be extended.

[0089] As can be seen from the embodiments of the device preparation method or the device structure provided by the present application above, the preparation method in the present application includes obtaining a first substrate, a second substrate, and a third substrate. The first substrate has a bonding surface, and the second substrate has an implantation surface. Ion implantation is performed on the second substrate from the implantation surface to form a defect layer inside the second substrate, obtaining a structure to be bonded. The implantation surface of the structure to be bonded is bonded to the bonding surface of the first substrate to obtain a heterogeneous substrate. The third substrate is bonded to the heterogeneous substrate to obtain a heterogeneous composite substrate; the heterogeneous composite substrate includes an area to be etched, an area to be grown, and an area to be fabricated; the area to be etched, the area to be grown, and the area to be fabricated are sequentially connected. A modulation-doped field-effect transistor structure is fabricated in the area to be etched, an isolation structure is fabricated in the area to be grown, and a complementary metal-oxide semiconductor structure is fabricated in the area to be fabricated. The modulation-doped field-effect transistor structure is connected to the complementary metal-oxide semiconductor structure to obtain a device. Based on the embodiments of the present application, on the basis of a traditional heterogeneous substrate including a silicon substrate and an indium phosphide layer disposed on the silicon substrate, silicon carbide is introduced, and the indium phosphide layer is disposed on the silicon carbide layer to form a heterogeneous composite substrate, so that the obtained device can be compatible with modulation-doped field-effect transistors and complementary metal-oxide semiconductors. And it can solve the problem that high-thermal-conductivity silicon carbide and a silicon substrate cannot coexist. In addition, by using the fact that silicon carbide has a thermal expansion coefficient close to that of the indium phosphide layer along the C axis, the thermal stress can be reduced, the performance of the device can be improved, and the service life of the device can be extended.

[0090] In the present invention, unless otherwise clearly defined and limited, terms such as "connected" and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the connection inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0091] It should be noted that: the above sequence of the embodiments of the present application is only for description and does not represent the superiority or inferiority of the embodiments. The above description of the present specification describes specific embodiments, and other embodiments are also within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be executed in the order of different embodiments and can achieve the expected results. In addition, the processes depicted in the drawings do not necessarily require a specific order or connection order to achieve the desired results. In certain embodiments, multi-task parallel processing is also possible or may be advantageous.

[0092] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and the key point of each embodiment is to illustrate the differences from other embodiments. In particular, for the structural embodiments, since they are based on and similar to the method embodiments, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the method embodiments.

[0093] The above is the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications are also regarded as the protection scope of the present invention.

Claims

1. A method for preparing a device, characterized in that, Including: Obtaining a first substrate, a second substrate, and a third substrate; the first substrate has a bonding surface, and the second substrate has an implantation surface; the material of the first substrate is single-crystal silicon carbide; the single-crystal silicon carbide includes 6H-SiC and 4H-SiC; the material of the second substrate is indium phosphide; the third substrate includes a first silicon layer, a buried oxide layer, and a second silicon layer, the first silicon layer is disposed on the buried oxide layer, and the buried oxide layer is disposed on the second silicon layer; Performing ion implantation on the second substrate from the implantation surface to form a defect layer inside the second substrate, obtaining a bonding structure to be bonded; Bonding the implantation surface of the bonding structure to be bonded and the bonding surface of the first substrate to obtain a first substrate to be processed; Peeling off a part of the first substrate along the defect layer of the first substrate to be processed to obtain a second substrate to be processed; Performing post-annealing treatment and surface polishing treatment on the second substrate to be processed to obtain a heterogeneous substrate; Bonding the third substrate along the surface of the second silicon layer to the heterogeneous substrate to obtain a heterogeneous composite substrate; the heterogeneous composite substrate includes an etching region to be etched, a growth region to be grown, and a preparation region to be prepared; the etching region to be etched, the growth region to be grown, and the preparation region to be prepared are sequentially connected; the bonding the third substrate along the surface of the second silicon layer to the heterogeneous substrate to obtain a heterogeneous composite substrate includes: bonding the second silicon layer of the third substrate to the heterogeneous substrate to obtain a heterogeneous composite substrate to be processed; performing post-annealing reinforcement treatment on the heterogeneous composite substrate to be processed, and performing etching treatment on the heterogeneous composite substrate to be processed after the post-annealing reinforcement treatment to etch the first silicon layer and the buried oxide layer to obtain the heterogeneous composite substrate; Preparing a modulation-doped field-effect transistor structure in the etching region to be etched, preparing an isolation structure in the growth region to be grown, and preparing a complementary metal-oxide semiconductor structure in the preparation region to be prepared; the modulation-doped field-effect transistor structure is prepared by epitaxial growth inside and outside a window structure; the window structure is obtained by etching the etching region to be etched so that a part of the second silicon layer is etched; a buffer layer, a channel layer, an isolation layer, a doping layer, a barrier layer, and a contact layer are sequentially prepared inside the window structure, and the sum of the thicknesses of the buffer layer, the channel layer, the isolation layer, the doping layer, the barrier layer, and the contact layer is equal to the thickness of the unetched second silicon layer; Connecting the modulation-doped field-effect transistor structure and the complementary metal-oxide semiconductor structure to obtain a device.

2. The method according to claim 1, characterized in that, The set range of the implantation temperature for performing ion implantation on the second substrate from the implantation surface is 0°C to 150°C; The set range of the implantation energy for performing ion implantation on the second substrate from the implantation surface is 1 KeV to 1000 KeV; The set range of the implantation dose for ion-implanting the second substrate from the implantation surface is 1×10 16 cm -2 ~3×10 17 cm -2 ; The ion implantation species for performing ion implantation on the second substrate from the implantation surface is light ions; the light ions include hydrogen ions, helium ions, and co-implantation of hydrogen and helium ions.

3. The method according to claim 1, wherein The preparing a modulation-doped field-effect transistor structure in the etching region to be etched includes: Etch the to-be-etched area to form a window structure; the injection surface corresponding to the window structure is exposed to air; Successively fabricate a buffer layer, a channel layer, an isolation layer, a doping layer, a barrier layer, and a contact layer within the window structure; Fabricate a source electrode, a drain electrode, and a gate electrode on the contact layer to obtain the modulation-doped field-effect transistor structure.

4. The method according to claim 1, wherein The fabricating an isolation structure in the to-be-grown area includes: Perform grooving on the to-be-grown area by using photolithography and wet etching to obtain a grooved structure; The first substrate corresponding to the grooved structure is exposed to air; Grow the isolation structure in the grooved structure by using plasma-enhanced chemical vapor deposition.

5. The method according to claim 1, characterized in that, Before performing ion implantation on the second substrate from the injection surface, further include: Fabricate a deposition layer on the injection surface by using chemical vapor deposition; After obtaining the to-be-bonded structure, further include: Perform a cleaning process on the to-be-bonded structure to remove the deposition layer.

6. The method according to claim 1, characterized in that, The bonding method for bonding the third substrate and the hetero-substrate includes hydrophilic bonding, dielectric layer bonding, surface activation bonding, and temperature-rising bonding.

7. According to the method described in claim 1, wherein, The set range of the temperature of the post-annealing treatment is 300°C to 600°C; The set range of the time of the post-annealing treatment is 1 h to 10 h; The atmosphere of the post-annealing includes any one of nitrogen, oxygen, and vacuum.

8. The structure of a device prepared by the method for preparing a device according to any one of claims 1-7, characterized in that, Includes: A hetero-composite substrate; The hetero-composite substrate includes a first substrate, a second substrate disposed on the first substrate, and a third substrate disposed on the second substrate. The third substrate includes a to-be-etched area, a to-be-grown area, and a to-be-fabricated area; the to-be-etched area, the to-be-grown area, and the to-be-fabricated area are sequentially connected and disposed; the material of the first substrate is single-crystal silicon carbide; the single-crystal silicon carbide includes 6H-SiC and 4H-SiC; the material of the second substrate is indium phosphide; the third substrate includes a first silicon layer, a buried oxide layer, and a second silicon layer. The first silicon layer is disposed on the buried oxide layer, and the buried oxide layer is disposed on the second silicon layer; A modulation-doped field-effect transistor structure disposed in the to-be-etched area; An isolation structure disposed in the to-be-grown area; A complementary metal-oxide semiconductor structure disposed in the to-be-fabricated area; the modulation-doped field-effect transistor structure is connected to the complementary metal-oxide semiconductor structure; the doped field-effect transistor structure is prepared by epitaxial growth inside and outside the window structure; the window structure is obtained by etching the to-be-etched area so that part of the second silicon layer is etched; a buffer layer, a channel layer, an isolation layer, a doping layer, a barrier layer, and a contact layer are successively prepared inside the window structure. The sum of the thicknesses of the buffer layer, the channel layer, the isolation layer, the doping layer, the barrier layer, and the contact layer, which is the thickness of the doped field-effect transistor structure, is equal to the thickness of the un-etched second silicon layer.

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