A manufacturing method of a formal dress LED lamp

Abstract

An embodiment of the present invention provides a method for manufacturing a face-up LED lamp, comprising: forming at least one insulating region and at least two conductive regions on one side of a substrate; fixing at least one group of chips on the insulating region of the substrate; connecting the chips and the conductive regions through wires. By providing an insulating region and a conductive region on the substrate and directly electrically connecting the chips to the conductive region of the substrate, the circuit layout of the LED lamp is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of LED lamps, and particularly to a manufacturing method of a face-up LED lamp. Background Art

[0002] LED lamps are lighting fixtures widely used in the world market at present. They have the advantages of small volume, high brightness, low power consumption, less heat generation, long service life, environmental protection, etc., and have a rich variety of colors, and are deeply loved by consumers.

[0003] The traditional way to manufacture LED lamps is as follows:

[0004] A front circuit layer is disposed on the upper surface of the substrate body in advance, a back circuit layer is disposed on the lower surface of the substrate body, and a connection circuit layer for electrically connecting the front circuit layer and the back circuit layer is disposed. Then, the LED chip is electrically connected to the front circuit layer through the processes of die bonding and wire bonding.

[0005] However, the LED lamps manufactured by the traditional method are large in volume, have poor light-emitting effects, and the process of the traditional method for manufacturing LED lamps is complex. Summary of the Invention

[0006] In view of the above problems, embodiments of the present invention are proposed to provide a manufacturing method of a face-up LED lamp that overcomes the above problems or at least partially solves the above problems.

[0007] To solve the above problems, embodiments of the present invention disclose a manufacturing method of a face-up LED lamp, including:

[0008] Forming at least one insulating region and at least two conductive regions on one side of the substrate;

[0009] Fixing at least one group of chips in the insulating region of the substrate;

[0010] Connecting the chips and the conductive regions through wires.

[0011] Optionally, the step of connecting the chips and the conductive regions through wires includes:

[0012] When the number of groups and the number of chips are both equal to 1, welding the positive electrode of the chip to one conductive region through a wire, and welding the negative electrode of the chip to another conductive region through a wire.

[0013] Optionally, the step of connecting the chips and the conductive regions through wires includes:

[0014] When the number of groups of the chips is equal to 1 and the number of the chips is greater than 1, the positive electrodes and negative electrodes of different chips are welded in sequence through wires; wherein, the positive electrode of the first-end chip and the negative electrode of the last-end chip are left vacant.

[0015] Weld the positive electrode of the first-end chip and a conductive region through a wire, and weld the negative electrode of the last-end chip and another conductive region through a wire.

[0016] Optionally, wherein the number of the conductive regions is greater than 3; the step of connecting the chips and the conductive regions through wires includes:

[0017] When the number of groups of the chips is greater than 1 and the number of each group of the chips is equal to 1, weld the positive electrode of the chip and a conductive region through a wire, and weld the negative electrode of the chip and other conductive regions through a wire; wherein, the conductive regions to which the negative electrodes of the chips in different groups are welded are different.

[0018] Optionally, wherein the number of the conductive regions is greater than 3; the step of connecting the chips and the conductive regions through wires includes:

[0019] When the number of groups of the chips is greater than 1 and the number of each group of the chips is greater than 1, weld the positive electrodes and negative electrodes of different chips in the same group in sequence through wires; wherein, the positive electrode of the first-end chip and the negative electrode of the last-end chip in each group are left vacant.

[0020] Weld the positive electrode of the first-end chip and a conductive region through a wire, and weld the negative electrode of the last-end chip and other conductive regions through a wire; wherein, the conductive regions to which the negative electrodes of the last-end chips in different groups are welded are different.

[0021] Optionally, the step of connecting the positive electrodes and negative electrodes of different chips in the same group in sequence through wires when the number of groups of the chips is greater than 1 and the number of each group of the chips is greater than 1 includes:

[0022] When the welding between a group of chips is completed, an insulating layer is formed between the chips to cover the wires between the chips.

[0023] Optionally, after the step of connecting the chips and the conductive regions through wires, it includes:

[0024] Determine the idle area of the conductive region according to the input area and the output area of the preset conductive region;

[0025] Form a protective layer in the idle area of the conductive region.

[0026] Optionally, after the step of forming a protective layer in the idle area of the conductive region, it includes:

[0027] A dam is formed around the insulating region on the output region of the conductive region.

[0028] Optionally, after the step of forming a dam around the insulating region on the output region of the conductive region, the following steps are included:

[0029] The chip is encapsulated with a special adhesive.

[0030] Optionally, after the step of connecting the chip and the conductive region through a wire, the following steps are included:

[0031] The chip is powdered by means of image recognition.

[0032] Embodiments of the present invention include the following advantages: at least one insulating region and at least two conductive regions are formed on one side of the substrate; at least one group of chips is fixed on the insulating region of the substrate; the chip and the conductive region are connected through a wire. By providing an insulating region and a conductive region on the substrate and directly electrically connecting the chip to the conductive region of the substrate, the circuit layout of the LED lamp is realized. Description of the Drawings

[0033] Figure 1 is a flowchart of the steps of an embodiment of a method for manufacturing a surface-mounted LED lamp according to the present invention;

[0034] Figure 2 is a first schematic structural diagram of an embodiment of a surface-mounted LED lamp according to the present invention;

[0035] Figure 3 is a second schematic structural diagram of an embodiment of a surface-mounted LED lamp according to the present invention;

[0036] Figure 4 is a third schematic structural diagram of an embodiment of a surface-mounted LED lamp according to the present invention.

[0037] Description of the Drawings: 1. Substrate, 11. Insulating region, 12. Conductive region, 13. Input region, 14. Output region, 2. Chip, 3. Wire, 4. Dam. Detailed Embodiments

[0038] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0039] One of the core concepts of the embodiments of the present invention is to form at least one insulating region 11 and at least two conductive regions 12 on one side of the substrate 1; fix at least one group of chips 2 on the insulating region 11 of the substrate 1; connect the chips 2 and the conductive regions 12 through wires 3. By providing the insulating region 11 and the conductive regions 12 on the substrate 1 and directly electrically connecting the chips 2 to the conductive regions 12 of the substrate 1, the circuit layout of the LED lamp is realized.

[0040] Referring to Figure 1 , a flowchart of the steps of an embodiment of a method for manufacturing a flip-chip LED lamp according to the present invention is shown, which may specifically include the following steps:

[0041] S110. Form at least one insulating region 11 and at least two conductive regions 12 on one side of the substrate 1;

[0042] S120. Fix at least one group of chips 2 on the insulating region 11 of the substrate 1;

[0043] S130. Connect the chips 2 and the conductive regions 12 through wires 3.

[0044] In the embodiments of the present application, at least one insulating region 11 and at least two conductive regions 12 are formed on one side of the substrate 1; at least one group of chips 2 are fixed on the insulating region 11 of the substrate 1; the chips 2 and the conductive regions 12 are connected through wires 3. By providing the insulating region 11 and the conductive regions 12 on the substrate 1 and directly electrically connecting the chips 2 to the conductive regions 12 of the substrate 1, the circuit layout of the LED lamp is realized.

[0045] Next, a method for manufacturing a flip-chip LED lamp in the above embodiments will be further described.

[0046] As described in step S110, at least one insulating region 11 and at least two conductive regions 12 are formed on one side of the substrate 1.

[0047] In an embodiment of the present application, the specific process of "forming at least one insulating region 11 and at least two conductive regions 12 on one side of the substrate 1" described in step S110 can be further described in combination with the following description.

[0048] It should be noted that the substrate 1 is a new type of superconducting mirror aluminum bracket.

[0049] As an example, an insulating material is coated on one side surface of the substrate 1 to form at least one insulating region 11; then at least two conductive sheets are fixed on the substrate 1 around the insulating region 11 through insulating glue to form at least two independent conductive regions 12; wherein, the formation order of the insulating region 11 and the conductive regions 12 can be reversed or carried out simultaneously, and the specific process is similar to the above and will not be elaborated here.

[0050] As described in step S120, at least one set of chips 2 is fixed in the insulating region 11 of the substrate 1.

[0051] It should be noted that the sets of chips 2 can be arranged crosswise with each other. For example, one set of chips 2 is respectively arranged between another set of chips 2; or they can be arranged in sequence by group. For example, one set of chips 2 is arranged in one area, and another set of chips 2 is arranged in another area, and the two areas are spaced apart or closely arranged.

[0052] In an embodiment of the present application, the specific process of "fixing at least one set of chips 2 in the insulating region 11 of the substrate 1" described in step S120 can be further described in combination with the following description.

[0053] As an example, at least one set of chips 2 is arranged in the insulating region 11 of the substrate 1 by using a die bonding method with a super high thermal conductivity underfill. With a special design, it can ensure that the light output of the light source is more uniform and there is no yellow spot.

[0054] As described in step S130, the chip 2 and the conductive region 12 are connected by a wire 3.

[0055] In an embodiment of the present application, the specific process of "connecting the chip 2 and the conductive region 12 by a wire 3" described in step S130 can be further described in combination with the following description.

[0056] As described in the following steps, when the number of sets and the number of chips 2 are both equal to 1, the positive electrode of the chip 2 is welded to a conductive region 12 by a wire 3, and the negative electrode of the chip 2 is welded to another conductive region 12 by a wire 3.

[0057] As an example, the positive electrode of the chip 2 is welded to a conductive region 12 by a wire 3, and the negative electrode of the chip 2 is welded to another conductive region 12 by a wire 3 to realize the electrical connection between the chip 2 and the conductive region 12.

[0058] In a specific implementation, there are two conductive regions 12. The positive electrode of the chip 2 and the negative electrode of the chip 2 are respectively electrically connected to one of the conductive regions 12 so that the chip 2 can be connected to a power source through the conductive region 12.

[0059] In an embodiment of the present application, the specific process of "connecting the chip 2 and the conductive region 12 by a wire 3" described in step S130 can be further described in combination with the following description.

[0060] As described in the following steps, when the number of groups of the chip 2 is equal to 1 and the number of the chip 2 is greater than 1, the positive and negative electrodes of different chips 2 are welded in sequence through the wire 3; wherein, the positive electrode of the first-end chip 2 and the negative electrode of the last-end chip 2 are left vacant;

[0061] The positive electrode of the first-end chip 2 and a conductive region 12 are welded through the wire 3, and the negative electrode of the last-end chip 2 and another conductive region 12 are welded through the wire 3.

[0062] As an example, all the chips 2 are connected in series in sequence through the wire 3; specifically, the positive electrode of one chip 2 is electrically connected to the negative electrode of the previous chip 2, and the negative electrode of this chip 2 is electrically connected to the positive electrode of the next chip 2; wherein, the positive electrode of the first-end chip 2 and the negative electrode of the last-end chip 2 are left vacant for electrical connection with the conductive region 12;

[0063] Then the positive electrode of the first-end chip 2 and a conductive region 12 are welded through the wire 3, and the negative electrode of the last-end chip 2 and another conductive region 12 are welded through the wire 3, so that the chip 2 can be connected to the power supply through the conductive region 12.

[0064] In an embodiment of the present application, the specific process of "connecting the chip 2 and the conductive region 12 through the wire 3" described in step S130 can be further described in combination with the following description.

[0065] As described in the following steps, when the number of groups of the chip 2 is greater than 1 and the number of each group of the chip 2 is equal to 1, the positive electrode of the chip 2 and a conductive region 12 are welded through the wire 3, and the negative electrode of the chip 2 and other conductive regions 12 are welded through the wire 3; wherein, the conductive regions 12 to which the negative electrodes of the chips 2 in different groups are welded are different.

[0066] It should be noted that the number of the conductive regions 12 is greater than 3.

[0067] As an example, the positive electrode of the chip 2 and a conductive region 12 are welded through the wire 3, and the negative electrode of the chip 2 and other conductive regions 12 are welded through the wire 3; wherein, the conductive regions 12 to which the negative electrodes of the chips 2 in different groups are welded are different to realize the electrical connection between the chip 2 and the conductive region 12.

[0068] In an embodiment of the present application, the specific process of "connecting the chip 2 and the conductive region 12 through the wire 3" described in step S130 can be further described in combination with the following description.

[0069] As described in the following steps, when the number of groups of the chips 2 is greater than 1 and the number of chips 2 in each group is greater than 1, the positive electrodes and negative electrodes of different chips 2 within the same group are successively welded through the wires 3; wherein, the positive electrodes of the head chips 2 and the negative electrodes of the tail chips 2 in each group are left vacant.

[0070] The positive electrode of the head chip 2 is welded to a conductive region 12 through the wire 3, and the negative electrode of the tail chip 2 is welded to other conductive regions 12 through the wire 3; wherein, the conductive regions 12 to which the negative electrodes of the tail chips 2 in different groups are welded are different.

[0071] It should be noted that the number of the conductive regions 12 is greater than 3.

[0072] As an example, all the chips 2 within each group are successively connected in series through the wires 3; specifically, the positive electrode of one chip 2 is electrically connected to the negative electrode of the previous chip 2, and the negative electrode of this chip 2 is electrically connected to the positive electrode of the next chip 2; wherein, the positive electrode of the head chip 2 and the negative electrode of the tail chip 2 are left vacant for electrical connection with the conductive region 12.

[0073] The positive electrode of the head chip 2 is welded to a conductive region 12 through the wire 3, and the negative electrode of the tail chip 2 is welded to other conductive regions 12 through the wire 3; wherein, the conductive regions 12 to which the negative electrodes of the tail chips 2 in different groups are welded are different.

[0074] In a specific implementation, the number of the conductive regions 12 is equal to 3, and the number of groups of the chips 2 is equal to 2; wherein, the positive electrodes of the head chips 2 in the two groups are electrically connected to one conductive region 12, and the negative electrodes of the tail chips 2 in the two groups are respectively connected to other conductive regions 12, that is, the negative electrode of the tail chips 2 in one group is connected to one of the other conductive regions 12, and the negative electrode of the tail chips 2 in the other group is connected to the other of the other conductive regions 12.

[0075] The step of successively connecting the positive electrodes and negative electrodes of different chips 2 within the same group through the wire 3 when the number of groups of the chips 2 is greater than 1 and the number of chips 2 in each group is greater than 1 includes:

[0076] When the welding between the chips 2 in one group is completed, an insulating layer is formed between the chips 2 to cover the wire 3 between the chips 2.

[0077] It should be noted that when the chips 2 in each group are arranged in a crosswise manner, the wires 3 connecting the chips 2 will inevitably have cross contacts, which may cause short circuits between the chips 2.

[0078] To avoid short circuits caused by cross - contact of the wires 3 between the chips 2, when completing the soldering between each group of chips 2, an insulating layer is formed between the chips 2 to cover the wires 3 between the chips 2; that is, the wires 3 between each group of chips 2 are spatially layered, and the wires 3 in different layers are isolated by the insulating layer to achieve insulation between the wires 3. By adopting a double - layer wire bonding method, it is ensured that the current of each group of chip 2 circuits can be evenly distributed and the normal conduction of the circuit is achieved.

[0079] In an embodiment of the present application, after the step of connecting the chip 2 and the conductive region 12 through the wire 3, it includes:

[0080] Determine the idle area of the conductive region 12 according to the preset input area 13 and output area 14 of the conductive region 12;

[0081] Form a protective layer in the idle area of the conductive region 12.

[0082] In an embodiment of the present application, after the step of forming a protective layer in the idle area of the conductive region 12, it includes:

[0083] Form a dam 4 around the insulating region 11 on the output area 14 of the conductive region 12.

[0084] In an embodiment of the present application, after the step of forming a dam 4 around the insulating region 11 on the output area 14 of the conductive region 12, it includes:

[0085] Package the chip 2 with special glue.

[0086] In an embodiment of the present application, after the step of connecting the chip 2 and the conductive region 12 through the wire 3, it includes:

[0087] Powder the chip 2 by means of image recognition.

[0088] In a specific implementation, a high - precision powdering device is used. The powdering process of the chip 2 is realized by using image recognition technology. The phosphor precipitation technology is adopted to ensure uniform light emission of the light source, reduce the temperature of the glue surface while having no yellow spots, and improve the reliability of the light source; a high - precision constant - temperature oven is used to make the colloid cure better, ensure the stability of the colloid and the reliability of the light source; a COB spectrometer is used to split the light source according to the requirements of spectral splitting and color separation to ensure that each light source can meet the customer's requirements; the light source is sliced and packaged according to the requirements.

[0089] Refer to Figures 2 - 4 , which shows a schematic structural diagram of a double - layer wire - routed surface - mounted LED lamp of the present invention, specifically including:

[0090] A substrate 1, a packaging structure, and at least one group of chips 2;

[0091] On one side of the substrate 1, there are provided at least one insulating region 11 and at least two conductive regions 12; the conductive regions 12 are circumferentially arranged within the insulating region 11;

[0092] The chips 2 are arranged within the insulating region 11 of the substrate 1; the chips 2 are electrically connected to the conductive regions 12 through wires 3; wherein, the chips 2 are encapsulated to the substrate 1 through the packaging structure;

[0093] When the LED lamp is powered on, the conductive region 12 is electrically connected to the power supply.

[0094] In an embodiment of the present application, there are a substrate 1, a packaging structure, and at least one group of chips 2; on one side of the substrate 1, there are provided at least one insulating region 11 and at least two conductive regions 12; the conductive regions 12 are circumferentially arranged within the insulating region 11; the chips 2 are arranged within the insulating region 11 of the substrate 1; the chips 2 are electrically connected to the conductive regions 12 through wires 3; wherein, the chips 2 are encapsulated to the substrate 1 through the packaging structure; when the LED lamp is powered on, the conductive region 12 is electrically connected to the power supply. By providing the insulating region 11 and the conductive region 12 on the substrate 1 and directly electrically connecting the chips 2 to the conductive regions 12 of the substrate 1, the circuit layout of the LED lamp is realized.

[0095] Next, a double - layer wiring front - mounted LED lamp in the above - mentioned embodiment will be further described.

[0096] It should be noted that in the present application, the wire 3 is an LED gold wire. Among them, the LED gold wire is formed by bonding and drawing a material with an Au purity of more than 99.99%, and contains trace elements such as Ag / Cu / Si / Ca / Mg.

[0097] In an embodiment of the present application, the substrate 1 is a new type of superconducting mirror aluminum two - color substrate 1; an insulating material is coated on one side surface of the substrate 1 to form at least one insulating region 11; then at least two conductive sheets are fixed around the insulating region 11 on one side surface of the substrate 1 through insulating glue to form at least two independent conductive regions 12.

[0098] In one example, the insulating region 11 is located at the middle position of one side surface of the substrate 1, and the conductive regions 12 are arranged around the insulating region 11 so that the shortest distance between each conductive region 12 and the insulating region 11 is equal.

[0099] In an embodiment of the present application, when the number of groups and the number of the chips 2 are both equal to 1, the positive electrode of the chip 2 is connected to a conductive region 12 through a wire 3, and the negative electrode of the chip 2 is connected to another conductive region 12 through the wire 3.

[0100] In an example, the number of groups and the number of the chips 2 are both equal to 1, and at the same time the number of the conductive regions 12 is equal to 2; wherein, the chip 2 is disposed in the insulating region 11, and the conductive regions 12 are symmetrically disposed on both sides of the insulating region 11; the positive electrode of the chip 2 is connected to one conductive region 12, and the negative electrode of the chip 2 is connected to the other conductive region 12. When the LED lamp is powered on, the positive electrode of the chip 2 is connected to the positive electrode of the power supply through the corresponding conductive region 12, and the negative electrode of the chip 2 is connected to the negative electrode of the power supply through the corresponding conductive region 12, so as to work normally.

[0101] In an embodiment of the present application, when the number of groups of the chips 2 is equal to 1 and the number of the chips 2 is greater than 1, the positive electrodes and negative electrodes of different chips 2 are connected through a wire 3; wherein, the positive electrode of the first-end chip 2 is connected to a conductive region 12 through the wire 3, and the negative electrode of the last-end chip 2 is connected to another conductive region 12 through the wire 3.

[0102] In an example, the number of groups of the chips 2 is equal to 1 and the number of the chips 2 is greater than 1, and at the same time the number of the conductive regions 12 is equal to 2; wherein, the chip 2 is disposed in the insulating region 11, and the conductive regions 12 are symmetrically disposed on both sides of the insulating region 11; wherein, the positive electrodes and negative electrodes of different chips 2 are connected through a wire 3, and the positive electrode of the first-end chip 2 is connected to a conductive region 12 through the wire 3, and the negative electrode of the last-end chip 2 is connected to another conductive region 12 through the wire 3. When the LED lamp is powered on, the positive electrode of the first-end chip 2 is connected to the positive electrode of the power supply through the corresponding conductive region 12, and the negative electrode of the last-end chip 2 is connected to the negative electrode of the power supply through the corresponding conductive region 12, so as to work normally.

[0103] In an embodiment of the present application, wherein, the number of the conductive regions 12 is greater than 3;

[0104] When the number of groups of the chips 2 is greater than 1 and the number of each group of the chips 2 is equal to 1, the positive electrode of the chip 2 is connected to a conductive region 12 through a wire 3, and the negative electrode of the chip 2 is connected to other conductive regions 12 through the wire 3; wherein, the conductive regions 12 connected by the negative electrodes of the chips 2 in different groups are different.

[0105] In one example, the number of groups of the chips 2 is greater than 1 and the number of chips 2 in each group is equal to 1. At the same time, the number of the conductive regions 12 is equal to 3. Among them, the chips 2 are arranged in the insulating region 11. One conductive region 12 is arranged on one side of the insulating region 11, and the other conductive regions 12 are arranged on the other side of the insulating region 11, and this conductive region 12 is arranged opposite to the other conductive regions 12. Among them, the positive electrode of the chip 2 is connected to one conductive region 12 through a wire 3, and the negative electrode of the chip 2 is connected to the other conductive region 12 through a wire 3. Among them, the conductive regions 12 connected by the negative electrodes of the chips 2 in different groups are different. When a group of chips 2 in the LED lamp is powered on, the positive electrode of this group of chips 2 is connected to the positive pole of the power supply through the corresponding conductive region 12, and the negative electrode of this group of chips 2 is connected to the negative pole of the power supply through the corresponding conductive region 12, so as to work normally. When two groups of chips 2 in the LED lamp are powered on, the positive electrodes of the two groups of chips 2 are connected to the positive pole of the power supply through the corresponding conductive regions 12, and the negative electrodes of the two groups of chips 2 are connected to the negative pole of the power supply through the corresponding conductive regions 12, so as to work normally.

[0106] In an embodiment of the present application, when the number of groups of the chips 2 is greater than 1 and the number of chips 2 in each group is greater than 1, the positive electrodes and negative electrodes of different chips 2 are connected through wires 3. The positive electrode of the first-end chip 2 is connected to one conductive region 12 through a wire 3, and the negative electrode of the last-end chip 2 is connected to the other conductive region 12 through a wire 3. Among them, the conductive regions 12 connected by the negative electrodes of the last-end chips 2 in different groups are different.

[0107] In one example, the number of groups of the chips 2 is greater than 1 and the number of chips 2 in each group is greater than 1. At the same time, the number of the conductive regions 12 is equal to 3. Among them, the chips 2 are arranged in the insulating region 11, and the chips 2 in different groups are arranged in a crosswise manner. One conductive region 12 is arranged on one side of the insulating region 11, and the other conductive regions 12 are arranged on the other side of the insulating region 11, and this conductive region 12 is arranged opposite to the other conductive regions 12. Among them, the positive electrodes and negative electrodes of different chips 2 are connected through wires 3. The positive electrode of the first-end chip 2 is connected to one conductive region 12 through a wire 3, and the negative electrode of the last-end chip 2 is connected to the other conductive region 12 through a wire 3. The conductive regions 12 connected by the negative electrodes of the last-end chips 2 in different groups are different. When a group of chips 2 in the LED lamp is powered on, the positive electrode of the first-end chip 2 in this group is connected to the positive pole of the power supply through the corresponding conductive region 12, and the negative electrode of the last-end chip 2 in this group is connected to the negative pole of the power supply through the corresponding conductive region 12, so as to work normally. When two groups of chips 2 in the LED lamp are powered on, the positive electrodes of the first-end chips 2 in the two groups are connected to the positive pole of the power supply through the corresponding conductive regions 12, and the negative electrodes of the last-end chips 2 in the two groups are connected to the negative pole of the power supply through the corresponding conductive regions 12, so as to work normally.

[0108] In one example, there are two sets of the chip 2, which are arranged with double-layer circuits, that is, distributed in upper and lower layers. The distance between the highest points of the two layers of circuits should be greater than 200um and less than 400um, which can ensure that there is no short circuit between the circuits and also avoid being exposed to the air due to the excessive height of the circuits.

[0109] In an embodiment of the present application, the chip 2 is fixedly arranged in the insulation area 11 of the substrate 1 by means of dispensing.

[0110] In an embodiment of the present application, the chip 2 is provided with phosphor; wherein, the colors of the phosphor of different sets of chips 2 are different.

[0111] In an embodiment of the present application, the conductive area 12 includes an input area 13, an output area 14 and an idle area;

[0112] The input area 13 is far from the insulation area 11; the output area 14 is close to the insulation area 11; the idle area is provided with a protective layer.

[0113] In an embodiment of the present application, it further includes a dam 4; the dam 4 is circumferentially arranged in the insulation area 11, and the dam 4 covers the output area 14.

[0114] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present invention.

[0115] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or terminal device including the element.

[0116] The above has introduced in detail a manufacturing method of a front-mounted LED lamp provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A manufacturing method of a formal dress LED lamp, characterized in that, it includes: forming at least one insulating area and at least two conductive areas on one side of the substrate; fixing at least one group of chips in the insulating area of the substrate; connecting the chips and the conductive areas through wires; wherein, the number of the conductive areas is greater than 3; the step of connecting the chips and the conductive areas through wires includes: when the number of groups of the chips is greater than 1 and the number of chips in each group is greater than 1, sequentially welding the positive electrodes and negative electrodes of different chips in the same group through wires; wherein, the positive electrodes of the first-end chips and the negative electrodes of the last-end chips in each group are left vacant; welding the positive electrode of the first-end chip to one conductive area through a wire, and welding the negative electrode of the last-end chip to other conductive areas through a wire; wherein, the conductive areas to which the negative electrodes of the last-end chips in different groups are welded are different; the step of sequentially connecting the positive electrodes and negative electrodes of different chips in the same group through wires when the number of groups of the chips is greater than 1 and the number of chips in each group is greater than 1 includes: when the welding between a group of chips is completed, forming an insulating layer between the chips to cover the wires between the chips; wherein, the wires between each group of chips are arranged in layers in space, and are isolated by an insulating layer between the wires in different layers.

2. The method according to claim 1, characterized in that, the step of connecting the chips and the conductive areas through wires includes: when the number of groups and the number of chips of the chips are respectively equal to 1, welding the positive electrode of the chip to one conductive area through a wire, and welding the negative electrode of the chip to another conductive area through a wire.

3. The method according to claim 1, characterized in that, the step of connecting the chips and the conductive areas through wires includes: when the number of groups of the chips is equal to 1 and the number of chips is greater than 1, sequentially welding the positive electrodes and negative electrodes of different chips through wires; wherein, the positive electrode of the first-end chip and the negative electrode of the last-end chip are left vacant; welding the positive electrode of the first-end chip and one conductive area through a wire, and welding the negative electrode of the last-end chip and another conductive area through a wire.

4. The method according to claim 1, characterized in that, wherein, the number of the conductive areas is greater than 3; the step of connecting the chips and the conductive areas through wires includes: when the number of groups of the chips is greater than 1 and the number of chips in each group is equal to 1, welding the positive electrode of the chip to one conductive area through a wire, and welding the negative electrode of the chip to other conductive areas through a wire; wherein, the conductive areas to which the negative electrodes of the chips in different groups are welded are different.

5. The method according to claim 1, characterized in that, after the step of connecting the chips and the conductive areas through wires, it includes: determining the idle area of the conductive area according to the preset input area and output area of the conductive area; forming a protective layer in the idle area of the conductive area.

6. The method according to claim 5, characterized in that, After the step of forming the protective layer in the idle area of the conductive region, it includes: Form a dam around the insulating region on the output region of the conductive region.

7. According to the method described in claim 6, Characterized in that, After the step of forming a dam around the insulating region on the output region of the conductive region, it includes: Package the chip with special glue.

8. According to the method described in claim 1, Characterized in that, After the step of connecting the chip and the conductive region through a wire, it includes: Powder the chip by means of image recognition.

Images