An N-face GaN-based p-channel device with improved ohmic contact resistance and a method for preparing the same

Abstract

The present invention discloses an N-face GaN-based P-channel device for improving ohmic contact resistance and a preparation method thereof, including: a first Si substrate layer, a first protective layer, a P-GaN layer, and a P-In x GaN layer, an Al y GaN barrier layer, and a second protective layer, which are sequentially arranged from bottom to top; the Al y GaN barrier layer, the P-In x GaN layer, and the P-GaN layer form a heterojunction structure on the N face; the thickness of the P-In x GaN layer is 10 nm to 20 nm; wherein, 0.05 ≤ x ≤ 0.1; a second groove opposite to the first groove is formed on the Al y GaN barrier layer; source electrodes and drain electrodes are respectively deposited on both sides of the Al y GaN barrier layer; wherein, 0.2 ≤ y ≤ 0.3; a gate electrode is arranged on the second groove; interconnection metals penetrating through the second protective layer are respectively deposited above the source electrodes, the drain electrodes, and the gate electrode. The P-channel device prepared by using the N-face heterojunction material in the present invention can avoid the influence of interface charges introduced by the deposition of an insulating medium under the gate in the case of the Ga face on the hole mobility, avoid the reduction of the hole mobility, improve the ohmic contact characteristics of the device, and thus improve the performance of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to an N-face GaN-based P-channel device with improved ohmic contact resistance and a preparation method thereof. Background Art

[0002] Due to its excellent material properties, GaN has become the first choice for the next generation of high-frequency, high-power devices and power electronic devices. With the increasing application demand for devices such as power switches, the additional parasitic effects caused by using Si-based CMOS devices to drive GaN power switches and other devices affect the characteristics of the devices. Therefore, it is particularly important to prepare GaN-based CMOS devices and GaN-based power switches and other devices on the same wafer. GaN-based P-channel devices, as an important component of GaN-based CMOS devices, are currently valued and have begun to be widely studied. Among them, the actual hole concentration in the grown P-GaN layer (30) is low due to the high activation energy of Mg acceptor impurities in the Mg-doped P-GaN layer (30). The low hole concentration makes the ohmic contact characteristics prepared on this P-GaN poor, which in turn affects the characteristics of the P-channel device. In addition, the additional interface charge caused by the deposition of the dielectric under the gate insulating layer further reduces the hole mobility in GaN. These problems greatly deteriorate the electrical characteristics of the P-channel device. Summary of the invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides an N-face GaN-based P-channel device with improved ohmic contact resistance and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0004] A first aspect of an embodiment of the present invention provides an N-face GaN-based P-channel device with improved ohmic contact resistance, comprising: a first Si substrate layer, a first protective layer, a P-GaN layer, a P-In layer, and a P-GaN layer. x GaN layer, Al y GaN barrier layer and second protective layer;

[0005] The Al y GaN barrier layer, the P-In x The GaN layer and the P-GaN layer form an N-face heterojunction structure;

[0006] A first groove is formed on the P-GaN layer;

[0007] The first groove has a notch facing the first protective layer and is filled with the first protective layer;

[0008] The P-In x The GaN layer is doped with Mg, the P-Inx The thickness of the GaN layer is 10 nm to 20 nm; wherein, 0.05≤x≤0.1;

[0009] The Al y The GaN barrier layer is provided with a second groove opposite to the first groove; y A source electrode and a drain electrode are deposited on both sides of the GaN barrier layer, respectively; wherein 0.2≤y≤0.3;

[0010] The source electrode and the drain electrode both extend into the second protective layer;

[0011] The second groove has a groove opening facing in the opposite direction to the groove opening of the first groove; a gate electrode is disposed on the second groove;

[0012] The gate electrode extends into the second protective layer;

[0013] Interconnection metals penetrating the second protection layer are deposited on the source electrode, the drain electrode and the gate electrode respectively.

[0014] In one embodiment of the present invention, the maximum thickness of the P-GaN layer is 30nm to 50nm; the thickness between the inner bottom of the first groove and the bottom of the P-GaN layer is 10nm to 20nm; the depth of the second groove is 5nm to 15nm;

[0015] The Al y The thickness of the GaN barrier layer is 15nm to 25nm;

[0016] The thickness of the first protective layer is 200nm to 300nm;

[0017] The thickness of the second protective layer is 180nm to 220nm;

[0018] The P-In x The Mg doping concentration of the GaN layer is 2e19 / cm 3 ~3e19 / cm 3 .

[0019] A second aspect of an embodiment of the present invention provides a method for preparing an N-face GaN-based P-channel device with improved ohmic contact resistance, comprising:

[0020] Step 1: epitaxially grow materials on the second Si substrate layer. The epitaxial layers from bottom to top are GaN buffer layer, GaN layer, Al y GaN barrier layer, P-In x GaN layer and P-GaN layer; wherein the P-In x The Mg doping concentration of the GaN layer is 2e19 / cm3 ~3e19 / cm 3 , thickness is 10nm~20nm; wherein, 0.05≤x≤0.1, 0.2≤y≤0.3;

[0021] Step 2, etching a first groove in the P-GaN layer;

[0022] Step 3: depositing a first protective layer on the surface of the P-GaN layer and filling the first groove;

[0023] Step 4: bonding a first Si substrate layer on the surface of the first protective layer;

[0024] Step 5: Flip the product prepared in step 4 to achieve the Al y GaN barrier layer (50), the P-In x An N-face heterojunction structure formed by the GaN layer (40) and the P-GaN layer (30), and etching away the second Si substrate layer;

[0025] Step 6: Completely etching the GaN buffer layer and the GaN layer;

[0026] Step 7: Make a source electrode and a drain electrode on the product prepared in step 6. The source electrode and the drain electrode are respectively located on the Al y Both sides of the GaN barrier layer;

[0027] Step eight, in the Al y Etching a second groove on the GaN barrier layer, wherein the second groove is opposite to the first groove;

[0028] Step nine, preparing a gate electrode on the product prepared in step eight;

[0029] Step ten, growing a second protective layer on the surface of the product prepared in step nine;

[0030] Step 11, photolithography an opening area of ​​the metal interconnection layer on the second protective layer; the opening area corresponds to the source electrode, the drain electrode and the gate electrode;

[0031] Step 12: evaporate interconnect metal in the opening area, lead out electrodes, and prepare the device described in the first aspect of the embodiment of the present invention.

[0032] In one embodiment of the present invention, the thickness of the GaN buffer layer is 2 μm to 5 μm;

[0033] The thickness of the GaN layer is 100nm to 200nm; yThe thickness of the GaN barrier layer is 15nm to 25nm; the thickness of the P-GaN layer is 30nm to 50nm, and the Mg doping concentration of the P-GaN layer is 2e19 / cm 3 ~3e19 / cm 3 .

[0034] In one embodiment of the present invention, the specific steps of step 2 are:

[0035] The product prepared in step 1 is baked, and then placed on a coating machine, and EPI621 photoresist is dripped onto the substrate of the P-GaN layer for coating, and then developed and rinsed with ultrapure water and dried with nitrogen;

[0036] The first groove is etched in the P-GaN layer by using an etcher until the remaining thickness is 10 nm to 20 nm.

[0037] In one embodiment of the present invention, the specific steps of step three are:

[0038] The product prepared in step 2 was ultrasonically cleaned with acetone, then ultrasonically cleaned with ethanol, and then rinsed with ultrapure water. 2 Blow dry;

[0039] 2% SiH was introduced by vapor deposition. 4 and N 2 Mixed gas, NH 3 and He gas to deposit a first protective layer on the surface of the P-GaN layer and fill the first groove, wherein the first protective layer is a SiN layer.

[0040] In one embodiment of the present invention, the specific steps of step seven include:

[0041] The product prepared in step 6 is placed on a hot plate for baking, and then the photoresist is coated and spun, and the product is placed on a hot plate for baking, and then the product is placed in a photolithography machine to expose the photoresist in the source and drain area of ​​the P-channel device; then, the product is placed in a developer to remove the photoresist in the electrical isolation area, and then the product is rinsed with ultrapure water and dried with nitrogen;

[0042] Al in the etched development area y GaN barrier layer until the P-In x GaN layer;

[0043] The product prepared in the previous step is sequentially placed in an acetone solution, a stripping solution, an acetone solution, and an ethanol solution for cleaning to remove the photoresist outside the electrical isolation area, and the product is rinsed with ultrapure water and blown dry with nitrogen gas;

[0044] The product prepared in the previous step is placed on a hot plate for baking; then, the stripping glue is coated and spun, and the product is placed on a hot plate for baking, then, the photoresist is coated and spun on the stripping glue, and the product is placed on a hot plate for baking, then, the product after the coating and spun glue is placed in a photolithography machine to expose the photoresist in the source electrode area and the drain electrode area, then, the exposed product is placed in a developer to remove the photoresist and stripping glue in the source electrode area and the drain electrode area, and then it is rinsed with ultrapure water and blown dry with nitrogen;

[0045] Evaporation of source and drain electrodes: Place the products with active and drain electrode photolithography patterns into a plasma stripper for bottom film treatment;

[0046] Put it into an electron beam evaporation table to evaporate the ohmic metal, which is a metal stacked structure consisting of two layers of metal, Pd and Ni, from bottom to top;

[0047] Stripping the product after ohmic metal evaporation to remove the ohmic metal, photoresist and stripping glue outside the source electrode area and the drain electrode area, rinsing the product with ultrapure water and drying it with nitrogen;

[0048] Perform annealing treatment.

[0049] In one embodiment of the present invention, the specific steps of step nine include:

[0050] Put the product with the second groove photolithography pattern into a plasma stripper to perform bottom film treatment;

[0051] Put it into an electron beam evaporation table to evaporate the gate metal, which is a metal stacked structure consisting of two layers of metal, Ni and Au, from bottom to top;

[0052] The product after gate metal evaporation is stripped to remove the gate metal, photoresist and stripping glue outside the gate electrode area, and then the product is rinsed with ultrapure water and blown dry with nitrogen to form a product with a gate electrode.

[0053] In one embodiment of the present invention, the specific steps of step 11 include:

[0054] The product prepared in step 10 is placed on a hot plate for baking, and then the photoresist is coated and spun, and the product is placed on a hot plate for baking, and then the product is placed in a photolithography machine to expose the photoresist in the opening area of ​​the metal interconnection layer, and finally, the product after exposure is placed in a developer to remove the photoresist in the opening area, and then the product is rinsed with ultrapure water and dried with nitrogen; the opening area is located above the source electrode, the drain electrode and the gate electrode;

[0055] When the reaction gas is CF 4 and O 2Under the condition of, the second protective layer in the opening area is etched; the etching depth is to penetrate the second protective layer.

[0056] In one embodiment of the present invention, the specific steps of step twelve include:

[0057] The product with the metal interconnection layer hole-etched is placed on a hot plate for baking, and then, the stripping glue is applied and spun on the source electrode, the drain electrode and the second protective layer without hole-etched in the opening area, and the product is placed on a hot plate for baking; then, the photoresist is applied and spun on the stripping glue, and the product is placed on a hot plate for baking, and then, the product with the coated and spun glue is placed in a photolithography machine to expose the photoresist in the opening area; finally, the exposed product is placed in a developer to remove the photoresist and stripping glue in the opening area, and the product is rinsed with ultrapure water and blown dry with nitrogen;

[0058] Putting the product with the photolithography pattern of the opening area into a plasma stripper for bottom film treatment;

[0059] Putting the interconnection metal into an electron beam evaporation table to evaporate the interconnection metal, wherein the interconnection metal is a metal stacking structure composed of two layers of metal, Ti and Au, from bottom to top;

[0060] The product after interconnect metal evaporation is stripped to remove the interconnect metal, photoresist and stripping glue outside the metal interconnect layer area, and the product is rinsed with ultrapure water and blown dry with nitrogen to complete the preparation and obtain the device described in the first aspect of the embodiment of the present invention.

[0061] Beneficial effects of the present invention:

[0062] The P-channel device prepared by the heterojunction material of the N-side of the present invention can avoid the influence of the interface charge introduced by the insulating medium deposited under the gate on the hole mobility in the case of the Ga-side, avoid the reduction of the hole mobility, improve the ohmic contact characteristics of the device, and thus improve the performance of the device. x As the contact layer between the ohmic metal and the P-GaN layer, the GaN layer can reduce the barrier thickness of carrier tunneling and reduce the ohmic contact resistivity, thus further improving the ohmic contact characteristics and device performance. x The polarization electric field generated by the polarization characteristics of GaN / GaN will further increase the activation rate of Mg impurities, thereby further increasing the probability of hole tunneling and improving the ohmic contact characteristics.

[0063] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1A schematic diagram of the structure of an N-face GaN-based P-channel device for improving ohmic contact resistance provided by an embodiment of the present invention:

[0065] Figure 2a-2j A preparation process diagram of a method for preparing an N-face GaN-based P-channel device with improved ohmic contact resistance provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0066] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0067] Embodiment 1

[0068] See also Figure 1 The embodiment of the present invention provides an N-face GaN-based P-channel device with improved ohmic contact resistance, comprising: a first Si substrate layer 10, a first protective layer 20, a P-GaN layer 30, a P-In x GaN layer 40, Al y The GaN barrier layer 50 and the second protective layer 60 .

[0069] Al y GaN barrier layer 50, P-In x The GaN layer 40 and the P-GaN layer 30 form an N-face heterojunction structure. A first groove 31 is formed on the P-GaN layer 30. The opening of the first groove 31 faces the first protective layer 20, and the first groove 31 is filled with the first protective layer 20.

[0070] P-In x The Mg doping concentration of the GaN layer 40 is 2e19 / cm 3 ~3e19 / cm 3 , with a thickness of 10nm to 20nm. Among them, 0.05≤x≤0.1.

[0071] Al y The GaN barrier layer 50 is provided with a second groove 51 opposite to the first groove 31. y A source electrode 81 and a drain electrode 82 are deposited on both sides of the GaN barrier layer 50, respectively. Wherein, 0.2≤y≤0.3. The source electrode 81 and the drain electrode 82 both extend into the second protective layer 60. The notch direction of the second groove 51 is opposite to the notch direction of the first groove 31. A gate electrode 70 is disposed on the second groove 51. The gate electrode 70 extends into the second protective layer 60. Interconnection metals 90 penetrating the second protective layer 60 are deposited above the source electrode 81, the drain electrode 82 and the gate electrode 70, respectively.

[0072] Furthermore, the maximum thickness of the P-GaN layer 30 is 30nm to 50nm, the thickness between the inner bottom of the first groove 31 and the bottom of the P-GaN layer 30 is 10nm to 20nm, and the depth of the first groove 31 is 10nm to 40nm. The depth of the second groove 51 is 5nm to 15nm. y The thickness of the GaN barrier layer 50 is 15 nm to 25 nm. The thickness of the first protective layer 20 is 200 nm to 300 nm. The thickness of the second protective layer 60 is 180 nm to 220 nm.

[0073] In this embodiment, the P-channel device made of N-face heterojunction material can avoid the influence of interface charge introduced by the insulating medium deposited under the gate on the hole mobility in the case of Ga-face, avoid the reduction of hole mobility, improve the ohmic contact characteristics of the device, and thus improve the performance of the device. x The GaN layer 40, as a contact layer between the ohmic metal and the P-GaN layer 30, can reduce the barrier thickness of carrier tunneling and reduce the ohmic contact resistivity, thereby further improving the ohmic contact characteristics and device performance. x The polarization electric field generated by the polarization characteristics of GaN / GaN will further increase the activation rate of Mg impurities, thereby further increasing the probability of hole tunneling and improving the ohmic contact characteristics.

[0074] It should be noted that P-In x If the thickness of the GaN layer 40 is greater than 20 nm, the ohmic contact characteristics of the device will deteriorate, and the P-In x If the thickness of the GaN layer 40 is less than 5 nm, the current characteristics of the device will deteriorate, which will make the device unusable. Preferably, the thickness is 10 nm. x If the In composition x in the GaN layer 40 is less than 0.05, the current characteristics of the device will deteriorate, and if it is greater than 0.1, In will precipitate and the growth requirements cannot be met, resulting in poor device quality and the device cannot be used. Preferably, x is 0.05.

[0075] Al y If the Al composition y in the GaN barrier layer 50 is less than 0.2, the current characteristics of the device will deteriorate, and if it is greater than 0.3, the growth requirements cannot be met, resulting in poor device quality and the device cannot be used. Preferably, y is 0.25.

[0076] In a feasible implementation, the material of the first protective layer 20 and the second protective layer 60 is SiN. Preferably, the thickness of the second protective layer 60 is 200 nm. The doping concentration of Mg in the P-GaN layer 30 is 2e19-3e19 / cm 3 .

[0077] In a feasible implementation, the source electrode 81 and the drain electrode 82 are both metal stack structures, which are composed of two metal layers of 20 nm thick Pd and 20 nm thick Ni from bottom to top. The gate electrode 70 is a metal stack structure composed of two metal layers of 40 nm thick Ni and 200 nm thick Au from bottom to top. The interconnect metal 90 is a metal stack structure composed of two metal layers of 40 nm thick Ti and 200 nm thick Au from bottom to top.

[0078] Embodiment 2

[0079] A second aspect of the embodiment of the present invention provides a method for preparing an N-face GaN-based P-channel device with improved ohmic contact resistance, which is used to prepare the device in the first embodiment, comprising the following steps:

[0080] Step 1: epitaxially grow materials on the second Si substrate layer 11. The epitaxial layers from bottom to top are GaN buffer layer 12, GaN layer 13, Al y GaN barrier layer 50, P-In x GaN layer 40 and P-GaN layer 30; wherein P-In x The Mg doping concentration of the GaN layer 40 is 2e19 / cm 3 ~3e19 / cm 3 , thickness is 10nm~20nm.

[0081] Step 2: etching the first groove 31 in the P-GaN layer 30 .

[0082] Step 3: depositing the first protection layer 20 on the surface of the P-GaN layer 30 and filling the first groove 31 .

[0083] Step 4: bonding the first Si substrate layer 10 on the surface of the first protection layer 20 .

[0084] Step 5: Flip the product prepared in step 4 to achieve the Al y GaN barrier layer (50), the P-In x The GaN layer (40) and the P-GaN layer (30) form an N-face heterojunction structure, and the second Si substrate layer 11 is etched away.

[0085] Step six: completely etch the GaN buffer layer 12 and the GaN layer 13.

[0086] Step 7: Make a source electrode 81 and a drain electrode 82 on the product prepared in step 6. The source electrode 81 and the drain electrode 82 are respectively located on the Al y Both sides of the GaN barrier layer 50 .

[0087] Step 8: In Aly A second groove 51 is etched on the GaN barrier layer 50 , and the second groove 51 is opposite to the first groove 31 .

[0088] Step nine: prepare a gate electrode 70 on the product prepared in step eight.

[0089] Step ten: growing a second protective layer 60 on the surface of the product prepared in step nine.

[0090] Step 11: photolithography an opening area of ​​the metal interconnection layer on the second protection layer 60 ; the opening area corresponds to the source electrode 81 , the drain electrode 82 and the gate electrode 70 .

[0091] Step 12: evaporate interconnect metal 90 in the opening area, lead out electrodes, and prepare the device of Example 1.

[0092] Furthermore, the thickness of the GaN buffer layer 12 is 2 μm to 5 μm. The thickness of the GaN layer 13 is 100 nm to 200 nm. y The thickness of the GaN barrier layer 50 is 15 nm to 25 nm. The thickness of the P-GaN layer 30 is 30 nm to 50 nm. The Mg doping concentration of the P-GaN layer 30 is 2e19 / cm 3 ~3e19 / cm 3 .

[0093] Embodiment 3

[0094] The embodiment of the present invention provides a method for preparing an N-face GaN-based P-channel device with improved ohmic contact resistance, which is used to prepare the device in the first embodiment, comprising the following steps:

[0095] Step 301: epitaxially grow materials on the second Si substrate layer 11 by MOCVD method. The epitaxial layers from bottom to top are GaN buffer layer 12, GaN layer 13, Al y GaN barrier layer 50, P-In x GaN layer 40 and P-GaN layer 30; wherein P-In x The Mg doping concentration of the GaN layer 40 is 2e19 / cm 3 ~3e19 / cm 3 , with a thickness of 10nm to 20nm. Figure 2a shown.

[0096] The thickness of the GaN buffer layer 12 is 2 μm to 5 μm. The thickness of the GaN layer 13 is 100 nm to 200 nm. y The thickness of the GaN barrier layer 50 is 15 nm to 25 nm. The thickness of the P-GaN layer 30 is 30 to 50 nm. The Mg doping concentration of the P-GaN layer 30 is 2e19 / cm 3~3e19 / cm 3 .

[0097] It should be noted that P-In x If the thickness of the GaN layer 40 is greater than 20 nm, the ohmic contact characteristics of the device will deteriorate, and the P-In x If the thickness of the GaN layer 40 is less than 5 nm, the current characteristics of the device will deteriorate, which will make the device unusable. Preferably, the thickness is 10 nm. x If the In composition x in the GaN layer 40 is less than 0.05, the current characteristics of the device will deteriorate, and if it is greater than 0.1, In will precipitate and the growth requirements cannot be met, resulting in poor device quality and the device cannot be used. Preferably, x is 0.05.

[0098] Al y If the Al composition y in the GaN barrier layer 50 is less than 0.2, the current characteristics of the device will deteriorate, and if it is greater than 0.3, the growth requirements cannot be met, resulting in poor device quality and the device cannot be used. Preferably, y is 0.25.

[0099] Step 302, P-channel GaN groove etching. The product prepared in step 301 is baked at 200°C, then placed on a coating machine, and EPI621 photoresist is dripped on the surface of the P-GaN layer 30 for coating; coating conditions: run at a speed of 500 rpm for 5 seconds, then run at a speed of 3500 rpm for 40 seconds, and bake at 90°C, then develop in a developer, rinse with ultrapure water for 2 minutes, and blow dry with nitrogen.

[0100] Step 303: Use a chlorine-based ICP etcher to etch the first groove 31 in the P-GaN layer 30. The etching conditions are: upper electrode power 40W-60W, lower electrode power 10W-20W, pressure 5mTorr, Cl 2 and BCl 3 The flow rate ratio is 8 / 20 sccm, and the P-GaN layer 30 is etched until about 10nm to 20nm remain, forming a first groove 31. The etching depth is 10nm to 40nm. Figure 2b shown.

[0101] Step 304: PECVD deposits SiN with a thickness of 200 nm to 300 nm to fill the first groove 31. Ultrasonic cleaning is performed with acetone for 3 min at an ultrasonic intensity of 2.0, and then ultrasonic cleaning is performed with ethanol for 2 min at an ultrasonic intensity of 2.0, followed by rinsing with ultrapure water for 2 min and drying with nitrogen.

[0102] Step 305: Add SiH 4 and N 2 Mixed gas, NH 3The first protective layer 20 is deposited on the surface of the P-GaN layer 30 and in the first groove 31 by using He gas. The first protective layer 20 is a SiN layer. The thickness of the first protective layer 20 on the surface of the P-GaN layer 30 is 200nm to 300nm. The flow rate ratio of the mixed gas is 200sccm, SiH 4 The ratio in the mixed gas is 2%, NH 3 The flow rate of He is 2sccm, the flow rate of He is 200sccm, the pressure is about 600mT, the temperature is 250 degrees Celsius, and the power is about 20W. Figure 2c shown.

[0103] Step 306: Use chemical mechanical polishing to bond a first Si substrate layer 10 with a thickness of 500 μm to 700 μm on the surface of the first protective layer 20. Figure 2d shown.

[0104] Step 307: Flip the product obtained in step 306 to achieve Al y GaN barrier layer 50, P-In x The N-face heterojunction structure formed by the GaN layer (40) and the P-GaN layer 30, such as Figure 2e As shown, the second Si substrate layer 11 is completely etched away. Etching conditions: upper electrode power 250W-350W, lower electrode power 20W-40W, pressure 5mTorr, SF 6 The flow rate is 50 sccm.

[0105] Step 308: Completely etch the GaN buffer layer 12 and the GaN layer 13 to the Al y The GaN barrier layer 50 is etched using ICP chlorine-based conditions. The etching conditions are: upper electrode power 40W-60W, lower electrode power 20W-30W, pressure 5mT, Cl 2 Flow rate 8sccm, BCl 3 The flow rate is 20sccm. Figure 2f shown.

[0106] P-channel device production source electrode 81 and drain electrode 82:

[0107] Al in source and drain regions y GaN etching:

[0108] Step 309, bake the product prepared in step 308 on a hot plate at 200°C, then apply and spin the photoresist at a spinning speed of 3500 rpm, bake the product on a hot plate at 90°C, then place it in a photolithography machine to expose the photoresist in the source and drain area of ​​the P-channel device; then, place it in a developer to remove the photoresist in the electrical isolation area, and rinse it with ultrapure water and blow it dry with nitrogen.

[0109] Step 310: Etch the Al in the development area using the ICP process y GaN barrier layer 50 to P-In x GaN layer 40. Etching conditions: upper electrode power 15W~25W, lower electrode power 3W~5W, pressure 5mT, Cl 2 Flow rate 4sccm, BCl 3 Flow rate 10sccm.

[0110] Step 311, placing the product prepared in step 310 into acetone solution, stripping solution, acetone solution and ethanol solution in turn for cleaning to remove the photoresist outside the electrical isolation area, rinse the product with ultrapure water and blow dry with nitrogen.

[0111] Photolithography source and drain electrode area:

[0112] Step 312, bake the product prepared in step 311 on a hot plate at 200°C; then, apply and spin the stripping glue, the spinning conditions are: SF6, 2000 rpm, 40sec, thickness 0.35μm, and bake the product on a hot plate at 200°C; then, apply and spin the photoresist on the stripping glue, the spinning conditions are: EPI621, 5000 rpm, time 30sec, thickness 0.77μm, and bake on a hot plate at 90°C, then, put the product that has been coated and spun into a photolithography machine to expose the photoresist in the source electrode area and the drain electrode area, then, put the exposed product into a developer to remove the photoresist and stripping glue in the source electrode area and the drain electrode area, rinse it with ultrapure water and blow it dry with nitrogen.

[0113] Evaporation source electrode 81 and drain electrode 82:

[0114] Step 313, evaporation of source electrode 81 and drain electrode 82: Place the product with the photolithography pattern of the active electrode and drain electrode into a plasma stripper for bottom film treatment. Treatment conditions: α-plasma plasma stripper, vacuum for 2 minutes, then, O 2 Flow rate: 100sccm~150sccm, power: 150W~250W, processing time: 5min~10min.

[0115] Step 314: Place the evaporator in an electron beam evaporator until the vacuum degree of the reaction chamber of the electron beam evaporator reaches 2×10 - 6 After the Torr, an ohmic metal is evaporated. The ohmic metal is a metal stacked structure consisting of two layers of metal, 20nm thick Pd and 20nm thick Ni, from bottom to top.

[0116] Step 315: strip the product after ohmic metal evaporation to remove the ohmic metal, photoresist and stripping glue outside the source electrode 81 area and the drain electrode 82 area, rinse the product with ultrapure water and blow dry with nitrogen. Figure 2g shown.

[0117] Step 316: perform annealing. The annealing atmosphere is O 2 The annealing temperature is 400℃~550℃, and the annealing time is 5min~10min.

[0118] Step 317: P-channel device gate groove etching. The second groove 51 should be aligned with the first groove 31 of the P-GaN layer 30. The chlorine-based ICP etching Al y GaN barrier layer 5nm~15nm. Etching conditions: upper electrode power 15W~25W, lower electrode power 3W~5W, pressure 5mT, Cl 2 Flow rate 4sccm, BCl 3 Flow rate 10sccm. Figure 2h shown.

[0119] P-channel device gate electrode 70 production:

[0120] Step 318, put the product with the second groove 51 photolithography pattern into a plasma stripper for bottom film treatment; treatment conditions: α-plasma plasma stripper, vacuum for 2 minutes, then O 2 Flow rate: 100sccm~150sccm, power: 150W~250W, processing time: 5min~10min.

[0121] Step 319: Place the evaporator in an electron beam evaporator until the vacuum degree of the reaction chamber of the evaporator reaches 2×10 - 6 After the Torr, a gate metal is evaporated. The gate metal is a metal stacked structure consisting of two metal layers, Ni with a thickness of 40 nm and Au with a thickness of 200 nm, from bottom to top.

[0122] Step 320: stripping the product after gate metal evaporation to remove the gate metal, photoresist and stripping glue outside the gate electrode 70 area, then rinse the product with ultrapure water and blow dry with nitrogen to form a product with a gate electrode 70. Figure 2i shown.

[0123] Step 321, growing a SiN second protective layer 60. The SiN second protective layer 60 with a thickness of 200 nm is grown by PECVD process. The process conditions for the growth are: using NH 3 and SiH 4As the reaction gas, the substrate temperature is about 250°C, the reaction chamber pressure is 600mTorr, and the RF power is 20W~25W.

[0124] Photolithography electrode opening:

[0125] Step 322, bake the product prepared in step 321 on a hot plate at 200°C, then apply and spin the photoresist, the spinning speed is 3500 rpm, bake the product on a hot plate at 90°C, then put it into a photolithography machine to expose the photoresist in the opening area of ​​the metal interconnect layer, finally, put the exposed product into a developer to remove the photoresist in the opening area, and rinse it with ultrapure water and blow it dry with nitrogen. The opening area is located above the source electrode 81, the drain electrode 82 and the gate electrode 70.

[0126] Step 323: ICP etching. When the reaction gas is CF 4 and O 2 Under the condition of , the 200 nm thick second protective layer 60 in the opening area is etched. The etching depth penetrates the second protective layer 60.

[0127] Lead out the electrodes and complete the device fabrication:

[0128] Step 324, bake the product after the metal interconnection layer hole etching is completed on a hot plate at 200°C, then, apply and spin the stripping glue on the source electrode 81 and the drain electrode 82 in the hole area and the second protective layer 60 that is not etched by the hole, and the thickness of the stripping glue is 0.35μm, and the product is baked on a hot plate at 200°C; then, apply and spin the photoresist on the stripping glue, and the thickness of the spin is 0.77μm, and the product is baked on a hot plate at 90°C, after which, the product after the coating and spinning is placed in a photolithography machine to expose the photoresist in the hole area; finally, the exposed product is placed in a developer to remove the photoresist and stripping glue in the hole area, and is rinsed with ultrapure water and blown dry with nitrogen.

[0129] Evaporated Interconnect Metal 90:

[0130] Step 325: Place the product with the photolithography pattern of the opening area into a plasma stripper for bottom film treatment. Treatment conditions: α-plasma plasma stripper, vacuum for 2 minutes, then 2 Flow rate: 100sccm~150sccm, power: 150W~250W, processing time: 5min~10min.

[0131] Step 326: Place the evaporator in an electron beam evaporator until the vacuum degree of the reaction chamber of the evaporator reaches 2×10 - 6After the Torr, the interconnect metal 90 is evaporated. The interconnect metal 90 is a metal stacked structure consisting of two metal layers, Ti with a thickness of 40 nm and Au with a thickness of 200 nm, from bottom to top.

[0132] Step 327, stripping the product after evaporation of the interconnection metal 90 to remove the interconnection metal, photoresist and stripping glue outside the metal interconnection layer area, washing the product with ultrapure water and drying it with nitrogen to complete the preparation and obtain the device in Example 1, such as Figure 2j shown.

[0133] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0134] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0135] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0136] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0137] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0138] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. An N-face GaN-based P-channel device with improved ohmic contact resistance, It is characterized in that include: A first Si substrate layer (10), a first protective layer (20), a P-GaN layer (30), a P-In x GaN layer (40), Al y A GaN barrier layer (50) and a second protective layer (60); The Al y GaN barrier layer (50), the P-In x The GaN layer (40) and the P-GaN layer (30) form an N-face heterojunction structure; The P-GaN layer (30) is provided with a first groove (31); The first groove (31) has a notch facing the first protective layer (20) and is filled with the first protective layer (20); The P-In x The GaN layer (40) is doped with Mg, and the P-In x The thickness of the GaN layer is 10 nm to 20 nm; wherein 0.05≤x≤0.1; The Al y A second groove (51) opposite to the first groove (31) is formed on the GaN barrier layer (50); y A source electrode (81) and a drain electrode (82) are deposited on both sides of the GaN barrier layer (50), respectively; wherein 0.2≤y≤0.3; The source electrode (81) and the drain electrode (82) both extend into the second protective layer (60); The second groove (51) has a groove opening facing in the opposite direction to the groove opening of the first groove (31); a gate electrode (70) is disposed on the second groove (51); The gate electrode (70) extends into the second protective layer (60); Interconnection metals (90) penetrating the second protective layer (60) are deposited above the source electrode (81), the drain electrode (82) and the gate electrode (70).

2. The N-face GaN-based P-channel device with improved ohmic contact resistance according to claim 1, It is characterized in that The maximum thickness of the P-GaN layer (30) is 30 nm to 50 nm; the thickness between the inner bottom of the first groove (31) and the bottom of the P-GaN layer (30) is 10 nm to 20 nm; the depth of the second groove (51) is 5 nm to 15 nm; The Al y The thickness of the GaN barrier layer (50) is 15 nm to 25 nm; The thickness of the first protective layer (20) is 200nm to 300nm; The thickness of the second protective layer (60) is 180nm to 220nm; The P-In x The Mg doping concentration of the GaN layer (40) is 2e19 / cm 3 ~3e19 / cm 3 .

3. A method for preparing an N-face GaN-based P-channel device with improved ohmic contact resistance, It is characterized in that include: Step 1: epitaxially grow materials on the second Si substrate layer (11), wherein the epitaxial layers from bottom to top are GaN buffer layer (12), GaN layer (13), Al y GaN barrier layer (50), P-In x GaN layer (40) and P-GaN layer (30); wherein the P-In x The Mg doping concentration of the GaN layer (40) is 2e19 / cm 3 ~3e19 / cm 3 , thickness is 10nm~20nm; wherein, 0.05≤x≤0.1, 0.2≤y≤0.3; Step 2: etching a first groove (31) in the P-GaN layer (30); Step three, depositing a first protective layer (20) on the surface of the P-GaN layer (30) and filling the first groove (31); Step 4: bonding the first Si substrate layer (10) to the surface of the first protective layer (20); Step 5: Flip the product prepared in step 4 to achieve the Al y GaN barrier layer (50), the P-In x An N-face heterojunction structure formed by the GaN layer (40) and the P-GaN layer (30), and etching away the second Si substrate layer (11); Step six: completely etching the GaN buffer layer (12) and the GaN layer (13); Step 7: Make a source electrode (81) and a drain electrode (82) on the product prepared in step 6. The source electrode (81) and the drain electrode (82) are respectively located on the Al y Both sides of the GaN barrier layer (50); Step eight, in the Al y Etching a second groove (51) on the GaN barrier layer (50), wherein the second groove (51) is opposite to the first groove (31); Step nine, preparing a gate electrode (70) on the product prepared in step eight; Step ten, growing a second protective layer (60) on the surface of the product prepared in step nine; Step 11: photolithography an opening area of ​​the metal interconnection layer on the second protective layer (60); the opening area corresponds to the source electrode (81), the drain electrode (82) and the gate electrode (70); Step 12: evaporate interconnect metal (90) in the opening area, lead out electrodes, and prepare the device as claimed in claim 1 or 2.

4. A method for preparing an N-face GaN-based P-channel device with improved ohmic contact resistance according to claim 3, It is characterized in that The thickness of the GaN buffer layer (12) is 2 μm to 5 μm; The thickness of the GaN layer (13) is 100nm to 200nm; y The thickness of the GaN barrier layer (50) is 15 nm to 25 nm; the thickness of the P-GaN layer (30) is 30 nm to 50 nm, and the Mg doping concentration of the P-GaN layer (30) is 2e19 / cm 3 ~3e19 / cm 3 .

5. A method for preparing an N-face GaN-based P-channel device with improved ohmic contact resistance according to claim 4, It is characterized in that The specific steps of step 2 are: The product prepared in step 1 is baked, and then placed on a coating machine, and EPI621 photoresist is dripped on the surface of the P-GaN layer (30) for coating, and then developed, rinsed with ultrapure water, and dried with nitrogen; An etching machine is used to etch the first groove (31) in the P-GaN layer (30) until the remaining thickness is 10 nm to 20 nm.

6. A method for preparing an N-face GaN-based P-channel device with improved ohmic contact resistance according to claim 5, It is characterized in that The specific steps of step three are: The product prepared in step 2 was ultrasonically cleaned with acetone, then ultrasonically cleaned with ethanol, and then rinsed with ultrapure water. 2 Blow dry; 2% SiH was introduced by vapor deposition. 4 and N 2 Mixed gas, NH 3 and He gas to deposit a first protective layer (20) on the surface of the P-GaN layer (30) and fill the first groove (31), wherein the first protective layer (20) is a SiN layer.

7. A method for preparing an N-face GaN-based P-channel device with improved ohmic contact resistance according to claim 6, It is characterized in that The specific steps of step seven include: The product prepared in step 6 is placed on a hot plate for baking, and then the photoresist is coated and spun, and the product is placed on a hot plate for baking, and then the product is placed in a photolithography machine to expose the photoresist in the source and drain area of ​​the P-channel device; then, the product is placed in a developer to remove the photoresist in the electrical isolation area, and then the product is rinsed with ultrapure water and dried with nitrogen; Al in the etched development area y The GaN barrier layer (50) extends to the P-In x GaN layer (40); The product prepared in the previous step is sequentially placed in an acetone solution, a stripping solution, an acetone solution, and an ethanol solution for cleaning to remove the photoresist outside the electrical isolation area, and the product is rinsed with ultrapure water and blown dry with nitrogen gas; The product prepared in the previous step is placed on a hot plate for baking; then, the stripping glue is coated and spun, and the product is placed on a hot plate for baking, then, the photoresist is coated and spun on the stripping glue, and the product is placed on a hot plate for baking, then, the product after the coating and spun glue is placed in a photolithography machine to expose the photoresist in the source electrode area and the drain electrode area, then, the exposed product is placed in a developer to remove the photoresist and stripping glue in the source electrode area and the drain electrode area, and then it is rinsed with ultrapure water and blown dry with nitrogen; Evaporating the source electrode (81) and the drain electrode (82): placing the photolithographic patterned product of the active electrode (81) and the drain electrode (82) into a plasma degumming machine for bottom film treatment; Put it into an electron beam evaporation table to evaporate the ohmic metal, which is a metal stacked structure consisting of two layers of metal, Pd and Ni, from bottom to top; Stripping the product after ohmic metal evaporation to remove the ohmic metal, photoresist and stripping glue outside the source electrode (81) region and the drain electrode (82) region, washing the product with ultrapure water and drying it with nitrogen; Perform annealing treatment.

8. A method for preparing an N-face GaN-based P-channel device with improved ohmic contact resistance according to claim 7, It is characterized in that The specific steps of step nine include: Putting the product with the second groove (51) photolithography pattern into a plasma stripping machine for bottom film treatment; Put it into an electron beam evaporation table to evaporate the gate metal, which is a metal stacked structure consisting of two layers of metal, Ni and Au, from bottom to top; The product after gate metal evaporation is stripped to remove the gate metal, photoresist and stripping glue outside the gate electrode (70) area, and then the product is rinsed with ultrapure water and blown dry with nitrogen to form a product with a gate electrode (70).

9. A method for preparing an N-face GaN-based P-channel device with improved ohmic contact resistance according to claim 8, It is characterized in that The specific steps of step 11 include: The product prepared in step 10 is placed on a hot plate for baking, and then the photoresist is coated and spun, and the product is placed on a hot plate for baking, and then the product is placed in a photolithography machine to expose the photoresist in the opening area of ​​the metal interconnection layer, and finally, the product after exposure is placed in a developer to remove the photoresist in the opening area, and then it is rinsed with ultrapure water and dried with nitrogen; the opening area is located above the source electrode (81), the drain electrode (82) and the gate electrode (70); When the reaction gas is CF 4 and O 2 Under the condition of, the second protective layer (60) in the opening area is etched; the etching depth is to penetrate the second protective layer (60).

10. A method for preparing an N-face GaN-based P-channel device with improved ohmic contact resistance according to claim 9, It is characterized in that The specific steps of step twelve include: The product after the metal interconnection layer hole etching is placed on a hot plate for baking, then the stripping glue is coated and spun on the source electrode (81) and the drain electrode (82) in the hole area and the second protective layer (60) not etched by the hole, and the product is placed on a hot plate for baking; then, the photoresist is coated and spun on the stripping glue, and the product is placed on a hot plate for baking, and then the product after the coating and spun is placed in a photolithography machine to expose the photoresist in the hole area; finally, the exposed product is placed in a developer to remove the photoresist and stripping glue in the hole area, and it is rinsed with ultrapure water and blown dry with nitrogen; Putting the product with the photolithography pattern of the opening area into a plasma stripper for bottom film treatment; Putting the interconnection metal (90) into an electron beam evaporation table to evaporate the interconnection metal (90), wherein the interconnection metal (90) is a metal stacked structure composed of two layers of metal, Ti and Au, in order from bottom to top; The product after evaporation of the interconnect metal (90) is stripped to remove the interconnect metal (90), photoresist and stripping glue outside the metal interconnect layer area, and the product is rinsed with ultrapure water and blown dry with nitrogen to complete the preparation and obtain the device as claimed in claim 1 or 2.

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