A power converter peak power control circuit and control method

Abstract

The application discloses a power converter peak power control circuit, and relates to the field of integrated circuits.The power converter peak power control circuit comprises a power conversion system control unit 100, a power tube 140, a transformer 110 and an output feedback circuit 120.The power conversion system control unit 100 is used for calculating demagnetization time of a period to control the power tube 140 to be turned on.The power tube 140 is used for controlling alternating current to flow through the input side of the transformer 110 when being turned on.The transformer 110 is used for outputting alternating current according to the turn-on time of the power tube 140.The output feedback circuit 120 is used for outputting winding voltage division feedback signals to the power conversion system control unit 100.Compared with the prior art, the power converter peak power control circuit has the advantages that the original side feedback flyback structure is adopted, the devices such as 431 and optical coupler are omitted, the cost of the power converter is reduced, the demagnetization time iterative algorithm control is adopted to realize the original side CCM peak frequency work, the switching frequency of the original side controller is improved when the system enters the peak power, and thus the power switch and transformer stress are reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, specifically to a peak power control circuit and control method for a power converter. Background Technology

[0002] Peak power refers to the power that a power supply can output more than 50% of its maximum rated output power for a short period of time, usually lasting only tens of milliseconds to a few seconds. Peak power is mostly used in fields with drastic transient load changes, such as smart speakers, cameras, and printers.

[0003] Currently, power converters with peak power functionality mainly adopt a flyback architecture with secondary-side feedback. The output signal is fed back to the primary controller via a 431 microcontroller and an optocoupler. When the output is overloaded, the primary controller increases the switching frequency through the feedback signal to increase the output power. The peak frequency is usually more than twice the normal full-load frequency and is maintained for tens of milliseconds to several seconds. If the load recovers within this maintenance time, the primary controller resumes normal operation. If the load continues to be overloaded within this maintenance time, the primary controller stops working and the power converter restarts.

[0004] To reduce system costs, some companies on the market use a primary-side feedback flyback architecture that omits the 431 and optocoupler to achieve peak power. However, there are technical difficulties in implementing CCM high-frequency technology with primary-side feedback. Usually, the peak current is increased to achieve peak power output, which leads to increased stress on the power switch and transformer, and is prone to transformer saturation problems, posing a risk to operational reliability. Improvements are needed. Summary of the Invention

[0005] The purpose of this invention is to provide a peak power control circuit and control method for a power converter to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A peak power control circuit for a power converter, comprising:

[0008] The power conversion system control unit 100 controls the switching of the power transistor 140 by iterative calculation of the demagnetization time;

[0009] Power transistor 140 is used to control transformer 110 to store energy when it is turned on;

[0010] Transformer 110 is used for isolated primary and secondary energy transfer.

[0011] The output rectifier and filter circuit 130 is used to filter and store the energy transmitted from the primary stage;

[0012] The output feedback circuit 120 is used to feed the output signal back to the power conversion system control unit 100 through the auxiliary winding;

[0013] The output terminal of the power conversion system control unit 100 is connected to the gate (G) terminal of the power transistor 140. The drain (D) terminal of the power transistor 140 is connected to one end of the input terminal of the transformer 110. The source (S) terminal of the power transistor 140 is grounded through the sampling resistor 141. The other end of the input terminal of the transformer 110 is connected to the input voltage VIN. The output terminal of the transformer 110 is connected to the input terminal of the output rectifier and filter module 130 and the input terminal of the output feedback module 120. The output terminal of the output feedback module 120 is connected to the input terminal of the power conversion system control unit 100.

[0014] As a further embodiment of the present invention: the power conversion system control unit 100 includes an on signal trigger module 150, an off signal trigger module 154, a demagnetization iterative algorithm module 152, an AND gate 153, an RS flip-flop 155, a drive module 156, an OR gate 157, and a counter 158. The second terminal of the on signal trigger module 150 is connected to the first terminal of the demagnetization iterative algorithm module 152 and the output terminal of the output feedback module 120. The first terminal of the on signal trigger module 150 is connected to the second terminal of the demagnetization iterative algorithm module 152, the output terminal of the drive module 156, and the gate (G) of the power transistor 140. The third terminal of the on signal trigger module 150 is connected to the second terminal of the off signal trigger module 154. The fourth terminal is connected to the third terminal of the demagnetizing iterative algorithm module 152. The fifth terminal of the turn-on signal trigger module 150 is connected to one input terminal of AND gate 153 and the input terminal of counter 158. The fourth terminal of the demagnetizing iterative algorithm module 152 is connected to the other input terminal of AND gate 153. The output terminal of AND gate 153 is connected to the S pin of RS flip-flop 155. The R pin of RS flip-flop 155 is connected to the output terminal of OR gate 157. One input terminal of OR gate 157 is connected to the first terminal of turn-off signal trigger module 154. The other input terminal of OR gate 157 is connected to the output terminal of counter 158. The Q pin of RS flip-flop 155 is connected to the input terminal of drive module 156. The input terminal of turn-off signal trigger module 154 is connected to the S pole of power transistor 140.

[0015] As a further embodiment of the present invention: the enable signal triggering module 150 includes a sample and hold module 210, an error amplifier 220, and a compensation capacitor C. COMP Comparator 240, exponential sawtooth wave signal generation module 230, transconductance current I COMP 250. The input terminal of the sample-and-hold module 210 is connected to the output terminal of the output feedback module 120. The output terminal of the sample-and-hold module 210 is connected to the inverting input of the error amplifier 220. The non-inverting input of the error amplifier 220 is connected to the reference voltage signal V. th_EAThe output of error amplifier 220 is connected to compensation capacitor C. COMP The non-inverting input of comparator 240, and the compensation capacitor C COMP The other end is grounded. The inverting input of comparator 240 is connected to the output of exponential sawtooth wave signal generation module 230. The input of exponential sawtooth wave signal generation module 230 is connected to the output of driver module 156. The output of comparator 240 is connected to one input of AND gate 153. Compensation capacitor C... COMP The above generates an error signal V COMP Error signal V COMP Connecting transconducting current I COMP 250, transconductance current I COMP The other end of 250 is connected to the third end of the shutdown signal trigger module 154.

[0016] As a further embodiment of the present invention: the shutdown signal triggering module 154 includes a comparator 310 and a current peak reference voltage generation module 320. The input terminal of the current peak reference voltage generation module 320 is connected to the third terminal of the turn-on signal triggering module 150, the output terminal of the current peak reference voltage generation module 320 is connected to the inverting terminal of the comparator 310, the non-inverting terminal of the comparator 310 is connected to the sampling resistor 141, and the output terminal of the comparator 310 is connected to one of the input terminals of the OR gate 157.

[0017] As a further embodiment of the present invention: the demagnetization iterative algorithm module 152 includes comparators 410, 440, and 470; edge pulse generation module 420 and 460; MOSFETs SW1, SW2, SW3, SW4, SW5, and SW6; capacitors C1, C2, and C3; a buffer 430; error signals 431 and 432; and a trigger 450. The non-inverting input of comparator 410 is connected to the output of the output feedback module 120, and the inverting input of comparator 410 is connected to the reference voltage Vth. DEMThe output of comparator 410 is connected to the input of edge pulse generation module 420 and the gate (G) of MOSFET SW1. The output of edge pulse generation module 420 is connected to the gate (G) of MOSFET SW2. The drain (D) of MOSFET SW1 is connected to bias current 401. The source (S) of MOSFET SW1 is connected to the drain (D) of MOSFET SW2, capacitor C1, the drain (D) of MOSFET SW3, and the non-inverting input of comparator 440. The source (S) of MOSFET SW2 is grounded, and the other end of capacitor C1 is grounded. The source (S) of MOSFET SW3 is connected to capacitor C2 and the input of buffer 430. The other end of capacitor C2 is grounded. The output of buffer 430 is connected to error signal 43. 1. Error signal 432 and error signal 431 are connected at one end to the drain (D) of MOSFET SW5 and the other end to the drain (D) of MOSFET SW6. The source (S) of MOSFET SW6 is connected to the source (S) of MOSFET SW5 and the inverting input of comparator 440. The gate (G) of MOSFET SW6 is connected to the Q pin of flip-flop 450. The gate (G) of MOSFET SW5 is connected to the -Q- pin of flip-flop 450. The output of comparator 440 is connected to the drain (D) pin of flip-flop 450 and the other end of the input of AND gate 153. The CLK pin of flip-flop 440 is connected to the output of comparator 470. The inverting input of comparator 470 is connected to the reference voltage Vth. TS The non-inverting terminal of comparator 470 is connected to capacitor C3 and the drain of MOSFET SW4. The source of MOSFET SW4 is grounded, and the other end of capacitor C3 is grounded. The gate of MOSFET SW4 is connected to the output terminal of edge pulse generation module 460 and the gate of MOSFET SW3. The input terminal of edge pulse generation module 460 is connected to the output terminal of drive module 156.

[0018] A peak power control method for a power converter, applied to the peak power control circuit of the power converter as described above, the method includes: Step 1: The power signal triggering module 150 outputs one of the signals Ton, which controls the power transistor 140 to turn on; Step 2: The demagnetization iteration algorithm module 152 generates a demagnetization end signal Demit, which serves as another control signal for the power transistor 140 to turn on; Step 3: The signals Ton and Demit trigger the power transistor 140 to turn on; Step 4: The power transistor 140 is turned off.

[0019] As a further aspect of the present invention: In step 1: the signal triggering module 150 is activated to sample and hold the feedback signal FB, and compared with the reference voltage V. th_EA Error amplification to generate V COMP The signal, simultaneously receiving the drive signal DRV from power transistor 140, generates a synchronous exponential sawtooth wave signal RAMP; by comparing V... COMP The signal and the exponential sawtooth wave signal RAMP generate one of the signals Ton, which controls the power transistor 140 to turn on.

[0020] As a further aspect of the present invention: In step 2: the demagnetization iterative algorithm module 152 receives V COMP The transconducting current I is calculated by the difference between the signal and the maximum value of the exponential sawtooth wave signal RAMP. COMP Simultaneously, through the feedback signal FB and the reference signal Vth DEM By comparing the demagnetization time of the previous cycle with that of the current cycle, the demagnetization iteration algorithm module 152 calculates the demagnetization time of the next cycle and generates a demagnetization end signal Demit as another control signal for turning on the power transistor.

[0021] As a further aspect of the present invention: In step 3: after the signals Ton and Demit are combined through AND gate 153, a signal Ton2 is generated and sent to the S pin of RS flip-flop 155 for triggering. After the Q pin signal of RS flip-flop 155 is amplified by the driver module 156, a DRV signal is generated and connected to the G terminal of power transistor 140 to drive power transistor 140 to conduct.

[0022] As a further aspect of the present invention: In step 4: the turn-off signal trigger module 154 compares the CS signal with the peak current threshold voltage signal V CS_th The system generates a Toff signal; counter 158 is controlled by the Ton signal. When the Ton signal is high, counter 158 starts counting. After 10 milliseconds to 5 seconds, the output signal Tpk of counter 158 becomes high. The Toff and Tpk signals pass through OR gate 157 and are then connected to the R pin of RS flip-flop 155 for reset. The peak current reference voltage signal V... CS_th With output signal V COMP They are in a proportional relationship.

[0023] Compared with the prior art, the beneficial effects of the present invention are: the present invention adopts a primary-side feedback flyback architecture, which eliminates devices such as 431 and optocouplers, reducing the cost of the power converter. It uses a demagnetization time iteration algorithm to control the primary-side CCM peak frequency operation. When the system enters the peak power, it increases the switching frequency of the primary-side controller, thereby reducing the stress on the power switch and transformer. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a peak power control circuit for a power converter.

[0025] Figure 2 This is the schematic diagram of the signal trigger module.

[0026] Figure 3 This is the schematic diagram of the shutdown signal trigger module.

[0027] Figure 4This is a schematic diagram of the demagnetization iterative algorithm module.

[0028] Figure 5 This is a schematic diagram of peak power control.

[0029] In the diagram: Switching power supply control unit-100, transformer-110, output feedback circuit-120, output rectifier and filter circuit-130, power transistor-140, sampling resistor-141, turn-on signal trigger module-150, demagnetization iterative algorithm module-152, AND gate-153, turn-off signal trigger module-154, RS flip-flop-155, driver module-156, OR gate-157, counter-158, sample and hold module-210, error amplifier-220, exponential sawtooth wave signal generator module-230, comparator-240, transconductance current I COMP -250, Comparator -310, Current Peak Reference Voltage Generation Module -320, Bias Current -401, Bias Current -402, Comparator -410, Edge Pulse Generation Module -420, Buffer -430, Error Signal -431, Error Signal -432, Comparator -440, Flip-flop -450, Edge Pulse Generation Module -460, Comparator -470. Detailed Implementation

[0030] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0031] Please see Figure 1 A peak power control circuit for a power converter, comprising:

[0032] The power conversion system control unit 100 controls the switching of the power transistor 140 by iterative calculation of the demagnetization time;

[0033] Power transistor 140 is used to control transformer 110 to store energy when it is turned on;

[0034] Transformer 110 is used for isolated primary and secondary energy transfer.

[0035] The output rectifier and filter circuit 130 is used to filter and store the energy transmitted from the primary stage;

[0036] The output feedback circuit 120 is used to feed the output signal back to the power conversion system control unit 100 through the auxiliary winding;

[0037] The output terminal of the power conversion system control unit 100 is connected to the gate (G) terminal of the power transistor 140. The drain (D) terminal of the power transistor 140 is connected to one end of the input terminal of the transformer 110. The source (S) terminal of the power transistor 140 is grounded through the sampling resistor 141. The other end of the input terminal of the transformer 110 is connected to the input voltage VIN. The output terminal of the transformer 110 is connected to the input terminal of the output rectifier and filter module 130 and the input terminal of the output feedback module 120. The output terminal of the output feedback module 120 is connected to the input terminal of the power conversion system control unit 100.

[0038] In a specific embodiment: the power conversion system control unit 100 controls the conduction of the power transistor 140 according to the peak power time of the power converter, thereby ensuring that the rectifier filter circuit 130 does not output DC power when the power converter is at its peak power, thus completing the power-off protection work during peak power.

[0039] Please see Figure 5 When the output voltage of the output rectifier and filter circuit 130 supplies a small load current, the controller operates at a constant voltage. As the output load increases, the output voltage V... COMP As this increases, the switching frequency timing signal T... S (The control circuit remains unchanged after being disconnected and then reconnected. When the load instantaneously increases beyond the overcurrent protection value, V...) COMP Continue to increase, when V COMP Greater than the reference signal V RAMP_max Subsequently, the transconductance current ICOMMP increases, causing the switching frequency timing signal T to... S Decreasing the peak power frequency corresponds to increasing the switching frequency, and the system enters the peak power mode. This means that when the peak power frequency is higher, the switching frequency is also higher, thus reducing the impact of peak power.

[0040] In this embodiment: Please refer to Figure 1The power conversion system control unit 100 includes an on signal trigger module 150, an off signal trigger module 154, a demagnetization iterative algorithm module 152, an AND gate 153, an RS flip-flop 155, a drive module 156, an OR gate 157, and a counter 158. The second terminal of the on signal trigger module 150 is connected to the first terminal of the demagnetization iterative algorithm module 152 and the output terminal of the output feedback module 120. The first terminal of the on signal trigger module 150 is connected to the second terminal of the demagnetization iterative algorithm module 152, the output terminal of the drive module 156, and the gate (G) of the power transistor 140. The third terminal of the on signal trigger module 150 is connected to the second terminal of the off signal trigger module 154. The fourth terminal of the on signal trigger module 150 is connected to... The third terminal of the demagnetization iterative algorithm module 152 and the fifth terminal of the turn-on signal trigger module 150 are connected to one input terminal of AND gate 153 and the input terminal of counter 158. The fourth terminal of the demagnetization iterative algorithm module 152 is connected to the other input terminal of AND gate 153. The output terminal of AND gate 153 is connected to the S pin of RS flip-flop 155. The R pin of RS flip-flop 155 is connected to the output terminal of OR gate 157. One input terminal of OR gate 157 is connected to the first terminal of turn-off signal trigger module 154. The other input terminal of OR gate 157 is connected to the output terminal of counter 158. The Q pin of RS flip-flop 155 is connected to the input terminal of drive module 156. The input terminal of turn-off signal trigger module 154 is connected to the S pole of power transistor 140.

[0041] AND gate 153 only conducts when all inputs are high. Outside of peak power periods, both Ton and Demit signals are high, and AND gate 153 conducts, outputting a high level to control RS flip-flop 155 to conduct. The Q pin of RS flip-flop 155 outputs a high level, which is amplified by driver module 156, driving power transistor 140 to conduct. This causes the input voltage VIN to flow into transformer 110, and transformer 110 outputs AC power. This AC power is then rectified and filtered by rectifier and filter module 130 to provide power and fed back by output feedback module 120. During peak power periods, turn-off signal trigger module 154 and counter 158 output Toff and Tpk signals respectively, causing OR gate 157 to conduct and output a high level, controlling RS flip-flop 155 to reset. The Q pin of RS flip-flop 155 stops outputting a high level, thus turning off power transistor 144 and preventing subsequent circuits from conducting.

[0042] In this embodiment: Please refer to Figure 2 The start signal trigger module 150 includes a sample and hold module 210, an error amplifier 220, and a compensation capacitor C. COMP Comparator 240, exponential sawtooth wave signal generation module 230, transconductance current I COMP250. The input terminal of the sample-and-hold module 210 is connected to the output terminal of the output feedback module 120. The output terminal of the sample-and-hold module 210 is connected to the inverting input of the error amplifier 220. The non-inverting input of the error amplifier 220 is connected to the reference voltage signal V. th_EA The output of error amplifier 220 is connected to compensation capacitor C. COMP The non-inverting input of comparator 240, and the compensation capacitor C COMP The other end is grounded. The inverting input of comparator 240 is connected to the output of exponential sawtooth wave signal generation module 230. The input of exponential sawtooth wave signal generation module 230 is connected to the output of driver module 156. The output of comparator 240 is connected to one input of AND gate 153. Compensation capacitor C... COMP The above generates an error signal V COMP Error signal V COMP Connecting transconducting current I COMP 250, transconductance current I COMP The other end of 250 is connected to the third end of the shutdown signal trigger module 154.

[0043] The auxiliary winding voltage division feedback signal FB, after passing through the sample-and-hold module 210, is connected to the inverting input of the error amplifier, and compared with the reference voltage signal V. th_EA After error amplification, at the output capacitor C COMP The above generates an error signal V COMP Error signal V COMP The signal and feedback signal FB are opposite (the error signal V is generated by comparator 220). COMP Therefore, the error signal V COMP The signal also reflects the magnitude of the output load energy; when the output energy is low, V COMP Low, correspondingly, when the output energy is large, V COMP high.

[0044] The drive signal DRV generates an exponential sawtooth wave signal RAMP through the exponential sawtooth wave signal generator module 230 (the input DRV square wave signal is converted into a sawtooth wave signal RAMP). Figure 2 As shown in the image, the exponential sawtooth wave signal RAMP is an amplitude-limited sawtooth wave signal that represents the turn-on frequency of power transistor 140. Its maximum value is less than or equal to the input reference signal V. RAMP_max The minimum value is greater than or equal to the input reference signal V. RAMP_min .

[0045] Comparator 240 compares the error signal V COMPThe magnitudes of the square wave signal and the exponential sawtooth wave signal RAMP are compared to determine the relationship between the output load energy and the voltage generated by the power transistor 140 during conduction. When the output load energy is large, the duty cycle of the square wave output by comparator 240 increases. The output signal Ton further increases the duty cycle of the DRV signal output, increases the conduction frequency of power transistor 140, and increases the voltage supplied to the load, maintaining peak load power operation. This generates one of the signals Ton that controls the conduction of power transistor 140. Transconductance current I COMP 250 is V per unit time COMP The maximum value V of the signal and the exponential sawtooth wave signal RAMP_max The difference (the upper limit voltage of the signal RAMP per unit time) is calculated when V COMP When the signal is less than or equal to the maximum value of the exponential sawtooth wave signal, I COMP The sum of the values ​​of signal RAMP and signal V per unit time is zero. COMP This indicates that the load does not require further increases in operating voltage.

[0046] In this embodiment: Please refer to Figure 3 The turn-off signal trigger module 154 includes a comparator 310 and a current peak reference voltage generation module 320. The input terminal of the current peak reference voltage generation module 320 is connected to the third terminal of the turn-on signal trigger module 150. The output terminal of the current peak reference voltage generation module 320 is connected to the inverting terminal of the comparator 310. The non-inverting terminal of the comparator 310 is connected to the sampling resistor 141. The output terminal of the comparator 310 is connected to one of the input terminals of the OR gate 157.

[0047] Peak current reference voltage signal V CS_th By inputting the reference signal V CS_max Input reference signal V CS_min Input V COMP Obtain the output signal V of the error amplifier. COMP Dynamically changing, peak current reference voltage signal V CS_th It is an amplitude-limited signal whose maximum value is less than or equal to the reference signal V. CS_max The minimum value is greater than or equal to the reference signal V. CS_min Peak current reference voltage signal V CS_th The signal is connected to the negative input of comparator 310 and compared with the peak current sampling signal CS of the primary power transistor at the positive input. When the peak current sampling signal CS is greater than the reference voltage signal V, the signal is selected. CS_th When the comparator's output signal Toff changes from low to high, it triggers the power transistor 140 to turn off. Toff is a signal that controls the power transistor to turn off, thus stopping power supply during peak power.

[0048] In this embodiment: Please refer to Figure 4The demagnetization iterative algorithm module 152 includes comparators 410, 440, and 470; edge pulse generation modules 420 and 460; MOSFETs SW1, SW2, SW3, SW4, SW5, and SW6; capacitors C1, C2, and C3; a buffer 430; error signals 431 and 432; and a trigger 450. The non-inverting input of comparator 410 is connected to the output of the output feedback module 120, and the inverting input of comparator 410 is connected to the reference voltage Vth. DEM The output of comparator 410 is connected to the input of edge pulse generation module 420 and the gate (G) of MOSFET SW1. The output of edge pulse generation module 420 is connected to the gate (G) of MOSFET SW2. The drain (D) of MOSFET SW1 is connected to bias current 401. The source (S) of MOSFET SW1 is connected to the drain (D) of MOSFET SW2, capacitor C1, the drain (D) of MOSFET SW3, and the non-inverting input of comparator 440. The source (S) of MOSFET SW2 is grounded, and the other end of capacitor C1 is grounded. The source (S) of MOSFET SW3 is connected to capacitor C2 and the input of buffer 430. The other end of capacitor C2 is grounded. The output of buffer 430 is connected to error signal 43. 1. Error signal 432 and error signal 431 are connected at one end to the drain (D) of MOSFET SW5 and the other end to the drain (D) of MOSFET SW6. The source (S) of MOSFET SW6 is connected to the source (S) of MOSFET SW5 and the inverting input of comparator 440. The gate (G) of MOSFET SW6 is connected to the Q pin of flip-flop 450. The gate (G) of MOSFET SW5 is connected to the -Q- pin of flip-flop 450. The output of comparator 440 is connected to the drain (D) pin of flip-flop 450 and the other end of the input of AND gate 153. The CLK pin of flip-flop 440 is connected to the output of comparator 470. The inverting input of comparator 470 is connected to the reference voltage Vth. TS The non-inverting terminal of comparator 470 is connected to capacitor C3 and the drain of MOSFET SW4. The source of MOSFET SW4 is grounded, and the other end of capacitor C3 is grounded. The gate of MOSFET SW4 is connected to the output terminal of edge pulse generation module 460 and the gate of MOSFET SW3. The input terminal of edge pulse generation module 460 is connected to the output terminal of drive module 156.

[0049] When the system reaches peak power, it typically doubles its operating frequency to achieve greater energy output. In this mode, the system operates in CCM (Continuous Core Module) mode. The transformer re-energizes and stores energy before the demagnetization release is complete. The duration of the demagnetization time in this switching cycle can only be determined after the next switch. A common approach to implementing CCM mode is to use a fixed-frequency switch. However, this method is prone to harmonic oscillations under high duty cycles in peak power mode, resulting in drastic changes in demagnetization time, system instability, and poor EMI handling. The principle of iterative demagnetization CCM mode is to sample the demagnetization time of the previous cycle and obtain a reference demagnetization time by adding or subtracting it from the error value. When the demagnetization time of the current cycle reaches this reference value, demagnetization ends and the next switching cycle begins. Simultaneously, the demagnetization time of the current cycle is stored for subsequent iterations. The accumulation or subtraction of the error value helps the system's switching frequency approach the target frequency. This method prevents drastic changes in demagnetization time between cycles, ensuring system stability under various operating modes. Furthermore, the system's switching frequency consistently approaches the target frequency repeatedly, resulting in minimal frequency fluctuations and excellent EMI performance. Below is an example of an iterative demagnetization circuit implementation.

[0050] When power transistor 140 is turned on, the DRV signal changes from low to high, and edge pulse generation module 460 generates a narrow pulse at the rising edge of the DRV square wave signal, such as... Figure 4 As shown, a narrow pulse signal is generated to control the brief conduction of MOS transistors SW3 and SW4. Capacitor C1 charges and discharges capacitor C2. This process is used to store the demagnetization time of the system in the previous switching cycle. Capacitor C3 is discharged quickly. This process controls the demagnetization iteration calculation to be synchronized with the switching frequency. At the end of the narrow pulse signal, the voltage of capacitor C2 is equal to the voltage of capacitor C1, and the voltage of capacitor C3 is zero.

[0051] When switch SW4 is turned off, the above-mentioned transconductance current I COMP (Generated by the RAMP signal from the DRV signal) and bias current 402 charge capacitor C3. When the voltage on capacitor C3 reaches the reference voltage Vth... TS At that time, comparator 470 outputs signal T S The signal transitions from low to high, and the trigger 450 latches the signal on pin D. This process is used to set the system's switching frequency.

[0052] The above transconducting current I COMP When the bias current is zero, the maximum full-load operating frequency of the system is determined solely by the magnitude of the bias current Ibais2, the capacitance of capacitor C3, and the reference voltage Vth. TS The magnitude determines the frequency, and the formula is f = Ibais² / (Vth). TS *C3); When the transconducting current I COMP When it is greater than zero, according to the formula f = (Ibais2 + I COMP) / (Vth TS As shown in *C3), the system operating frequency increases, and it enters the peak current (peak power) mode.

[0053] The output feedback sampling signal FB is compared with the reference voltage Vth by comparator 410. DEM A comparison is made to generate a demagnetization signal T. DEM Signal T DEM The duration of the high level indicates the system demagnetization time.

[0054] Signal T DEM When the signal changes from low to high, the edge pulse generation module 420 ( Figure 4 As described in the text, with T DEM A narrow pulse is generated at the rising edge of the square wave signal, outputting a high-level pulse signal to briefly turn on the MOSFET SW2. This causes capacitor C1 to discharge rapidly to ground, resulting in zero voltage across C1. Simultaneously, after MOSFET SW1 turns on, the bias current 401 charges capacitor C1 through MOSFET SW1, causing the voltage across C1 to gradually rise. At the end of demagnetization, the voltage across capacitor C1 is I. bais1 *T DEM / C1. This process is used to store the demagnetization time of the system during this switch cycle.

[0055] The positive terminal of capacitor C1 is connected to the positive input terminal of comparator 440, and to the common connection terminal V of SW5 and SW6 mentioned above. DEM For comparison, when the voltage at the positive terminal of capacitor C1 is higher than V... DEM When the demagnetization time exceeds the sum of the demagnetization time and the error, comparator 440 outputs a high level. This process indicates that if the demagnetization time of the current cycle exceeds the sum of the demagnetization time and the error amount of the previous cycle, the next switching cycle will be executed immediately. The error amount can be positive or negative, depending on the timing of the outputs of comparators 440 and 470 changing from low to high. When the output of comparator 440 changes from low to high before comparator 470, the error amount is positive; otherwise, it is negative.

[0056] When comparator 470's T S When the signal changes from low to high, the D flip-flop 450 latches the output signal Demit of the comparator 440. When the output signal Demit of the comparator 440 is low, the Q input of the D flip-flop 450 is low. When the Demit signal is high, MOSFET SW5 is off and SW6 is on; when the Demit signal is high, the Q input of the D flip-flop 450 is high. When the terminal is at a low level, MOSFET SW5 is turned on and SW6 is turned off. This process iterates repeatedly around the actual demagnetization time of the system.

[0057] A peak power control method for a power converter, applied to the peak power control circuit of the power converter as described above, includes the following steps: Step 1: The turn-on signal trigger module 150 outputs one of the signals Ton, which controls the power transistor 140 to turn on; Step 2: The demagnetization iteration algorithm module 152 generates a demagnetization end signal Demit, which serves as another control signal for the power transistor 140 to turn on; Step 3: The signals Ton and Demit trigger the power transistor 140 to turn on; Step 4: The turn-off signal trigger module 154 and the counter 158 cooperate to control the power transistor 140 to turn off.

[0058] As a further aspect of the present invention: In step 1: the signal triggering module 150 is activated to sample and hold the feedback signal FB, and compared with the reference voltage V. th_EA Error amplification to generate V COMP The signal, simultaneously receiving the drive signal DRV from power transistor 140, generates a synchronous exponential sawtooth wave signal RAMP; by comparing V... COMP The signal and the exponential sawtooth wave signal RAMP generate one of the signals Ton, which controls the power transistor 140 to turn on.

[0059] As a further aspect of the present invention: In step 2: the demagnetization iterative algorithm module 152 receives V COMP The transconducting current I is calculated by the difference between the signal and the maximum value of the exponential sawtooth wave signal RAMP. COMP Simultaneously, through the feedback signal FB and the reference signal Vth DEM By comparing the demagnetization time of the previous cycle with that of the current cycle, the demagnetization iteration algorithm module 152 calculates the demagnetization time of the next cycle and generates a demagnetization end signal Demit as another control signal for turning on the power transistor.

[0060] As a further aspect of the present invention: In step 3: after the signals Ton and Demit are combined through AND gate 153, a signal Ton2 is generated and sent to the S pin of RS flip-flop 155 for triggering. After the Q pin signal of RS flip-flop 155 is amplified by the driver module 156, a DRV signal is generated and connected to the G terminal of power transistor 140 to drive power transistor 140 to conduct.

[0061] As a further aspect of the present invention: In step 4: the turn-off signal trigger module 154 compares the CS signal with the peak current threshold voltage signal V CS_thThe system generates a Toff signal; counter 158 is controlled by the Ton signal. When the Ton signal is high, counter 158 starts counting. After 10 milliseconds to 5 seconds, the output signal Tpk of counter 158 becomes high. The Toff and Tpk signals pass through OR gate 157 and are then connected to the R pin of RS flip-flop 155 for reset. The peak current reference voltage signal V... CS_th With output signal V COMP The relationship is proportional. In practice, the counting time of counter 158 is from tens of milliseconds to several seconds; here, we choose ten milliseconds to five seconds.

[0062] The working principle of this invention: The system generates signal V based on the feedback signal FB. COMP To control peak power; when the system output load increases, the corresponding output signal of FB decreases slightly, and the V signal is amplified in reverse. COMP As the signal increases, the corresponding system operating frequency gradually rises (the conduction frequency of the 140V switching transistor) and stabilizes at the maximum frequency at rated output power. When the system output load continues to increase beyond the maximum rated output power, the FB signal continues to decrease, and V... COMP The signal continues to increase and exceeds the highest voltage V of the aforementioned sawtooth wave signal RAMP. RAMP_max When the system enters peak power operation mode, the operating frequency will continue to increase to improve the output power. However, at this time, the output power has exceeded the maximum rated power and cannot be maintained for a long time. When the operating time exceeds the timing of the counter 158 circuit, the RS flip-flop 155 is controlled by the OR gate to reset the power transistor 140 to cut off, the peak power operation ends, and the system restarts. This ensures that as the load increases, the conduction frequency of the switching transistor 140 increases, increasing the power supply to the load and maintaining the peak power.

[0063] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0064] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A peak power control circuit for a power converter, comprising: The power conversion system control unit (100) controls the switching of the power transistor (140) by iterative calculation of the demagnetization time; A power transistor (140) is used to control the transformer (110) to store energy when it is turned on; Transformer (110) for isolated primary and secondary energy transfer; The output rectifier filter circuit (130) is used to filter and store the energy transmitted from the primary stage; The output feedback circuit (120) is used to feed the output signal back to the power conversion system control unit (100) through the auxiliary winding. The output terminal of the power conversion system control unit (100) is connected to the gate (G) of the power transistor (140), the drain (D) of the power transistor (140) is connected to one end of the input terminal of the transformer (110), the source (S) of the power transistor (140) outputs a current sampling signal CS and is grounded through a sampling resistor (141), the other end of the input terminal of the transformer (110) is connected to the input voltage VIN, the output terminal of the transformer (110) is connected to the input terminal of the output rectifier filter circuit (130) and the input terminal of the output feedback circuit (120), and the output terminal of the output feedback circuit (120) outputs a feedback signal FB; characterized in that: The power conversion system control unit (100) includes an on signal trigger module (150), an off signal trigger module (154), a demagnetization iterative algorithm module (152), an AND gate (153), an RS flip-flop (155), a drive module (156), an OR gate (157), and a counter (158). The first terminal of the power-on signal trigger module (150), the second terminal of the demagnetization iteration algorithm module (152), and the output terminal of the drive module (156) are connected to the gate (G) of the power transistor (140), i.e., the drive signal DRV. The second terminal of the power-on signal trigger module (150) and the first terminal of the demagnetization iteration algorithm module (152) are connected to the signal FB. The third terminal of the power-on signal trigger module (150) is connected to the second input terminal of the power-off signal trigger module (154), i.e., the error signal V. COMP The fourth terminal of the signal trigger module (150) is connected to the third terminal of the demagnetization iterative algorithm module (152) and outputs a transconductance current I. COMP The fifth terminal of the turn signal trigger module (150) outputs the signal Ton and connects to one end of the input terminal of the AND gate (153) and the input terminal of the counter (158). The fourth terminal of the demagnetization iteration algorithm module (152) outputs the demagnetization end signal Demit and connects to the other end of the input terminal of the AND gate (153). The output terminal of the AND gate (153) is connected to the S pin of the RS flip-flop (155). The R pin of the RS flip-flop (155) is connected to the output terminal of the OR gate (157). One end of the input terminal of the OR gate (157) is connected to the output terminal of the turn-off signal trigger module (154) and outputs the signal Toff. The other end of the input terminal of the OR gate (157) is connected to the output terminal of the counter (158). The Q pin of the RS flip-flop (155) is connected to the input terminal of the drive module (156). The power-on signal trigger module (150) includes a sample-and-hold module (210), an error amplifier (220), and a compensation capacitor C. COMP Comparator (240), exponential sawtooth wave signal generation module (230), transconductance current I COMP (250) The input terminal of the sample-and-hold module (210) is connected to the FB signal, the output terminal of the sample-and-hold module (210) is connected to the inverting terminal of the error amplifier (220), and the non-inverting terminal of the error amplifier (220) is connected to the reference voltage V. th_EA The output of the error amplifier (220) is connected to a compensation capacitor C. COMP One end of the comparator (240) is the non-inverting input, and the compensation capacitor C is... COMP The other end is grounded, the inverting input of the comparator (240) is connected to the output of the exponential sawtooth wave signal generator module (230), and the input of the exponential sawtooth wave signal generator module (230) is connected to the drive signal DRV and the maximum value V. RAMP_max and minimum value V RAMP_min The comparator (240) outputs a signal Ton, and the compensation capacitor C... COMP The above generates an error signal V COMP Transconducting current I COMP V per unit time COMP With the maximum value V RAMP_max The difference is calculated when V COMP Less than or equal to V RAMP_max Time I COMP It is zero; The shutdown signal trigger module (154) includes a comparator (310) and a current peak reference voltage generation module (320), the input of which is connected to signal V. COMP The output of the current peak reference voltage generation module (320) is connected to the inverting input of the comparator (310), the non-inverting input of the comparator (310) is connected to the signal CS, and the output of the comparator (310) outputs the signal Toff. The demagnetization iterative algorithm module (152) includes a comparator (470), an edge pulse generation module (460), a MOSFET SW4, a capacitor C3, and a bias current I. bias2 The flip-flop (450) outputs the signal Demit from its D pin. The CLK pin of the flip-flop is connected to the output of the comparator (470), and the inverting input of the comparator (470) is connected to the reference voltage V. thTS The non-inverting input of comparator (470) is connected to one end of capacitor C3, the drain of MOSFET SW4, and the bias current I. bias2 Output terminal, transconductance current I COMP The output terminal of MOSFET SW4 is grounded, the other end of capacitor C3 is grounded, the gate of MOSFET SW4 is connected to the output terminal of the edge pulse generation module (460), the input terminal of the edge pulse generation module (460) is connected to the drive signal DRV, and the demagnetization iterative algorithm module is used to set the switching frequency of the system. When the transconductance current I COMP When the frequency is greater than zero, the system switching frequency f = (I bais2 +I COMP ) / (V thTS *C3), the system switching frequency increases, entering peak power mode.

2. A peak power control method for a power converter, applied to the peak power control circuit of the power converter as described in claim 1, characterized in that, The method includes the following steps: Step 1: The signal triggering module (150) outputs one of the signals Ton, which controls the power transistor (140) to turn on; Step 2: The demagnetization iteration algorithm module (152) generates a demagnetization end signal Demit, which serves as another control signal for the power transistor (140) to turn on; Step 3: The signals Ton and Demit trigger the power transistor (140) to turn on; Step 4: The power transistor (140) is turned off.

3. The peak power control method for a power converter according to claim 2, characterized in that, In step 1: the signal trigger module (150) is activated to sample and hold the feedback signal FB, and compared with the reference voltage V. th_EA Error amplification to generate V COMP The signal, while receiving the drive signal DRV from the power transistor (140), generates a synchronous exponential sawtooth wave signal RAMP; by comparing V COMP The signal RAMP generates one of the signals Ton, which controls the power transistor (140) to turn on.

4. The peak power control method for a power converter according to claim 3, characterized in that, In step 2: the demagnetization iterative algorithm module (152) receives the transconductance current I. COMP Simultaneously, through the feedback signal FB and the reference signal V thDEM By comparing the demagnetization time of the previous cycle with the demagnetization time of the current cycle, the demagnetization iteration algorithm module (152) calculates the demagnetization time of the next cycle and generates a demagnetization end signal Demit as another control signal for the power transistor to turn on.

5. The peak power control method for a power converter according to claim 4, characterized in that, In step 3, the signals Ton and Demit are combined through AND gate (153) to generate signal Ton2, which is sent to the S pin of RS flip-flop (155) for triggering. The Q pin signal of RS flip-flop (155) is amplified by the driver module (156) to generate DRV signal, which is connected to the G terminal of power transistor (140) to drive power transistor (140) to conduct.

6. The peak power control method for a power converter according to claim 5, characterized in that, In step 4: The turn-off signal trigger module (154) compares the CS signal with the current peak reference voltage signal V. CS_th The counter (158) is controlled by the Ton signal. When the Ton signal is high, the counter (158) starts counting. After the counter timeout period, the output signal Tpk of the counter (158) is high. The Toff signal and the Tpk signal are connected to the R pin of the RS flip-flop for reset after passing through the OR gate (157). The peak current reference voltage signal V CS_th With signal V COMP They are in a proportional relationship.

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