Phase-locked loop, method of generating periodic output waveform, and clock generation circuit

Abstract

A phase-locked loop, a method of generating a periodic output waveform, and a clock generation circuit are provided. The phase-locked loop includes a phase / frequency detector, a charge pump, an oscillator, and a realignment path. The phase / frequency detector is configured to receive a reference signal and a feedback signal. The charge pump is configured to receive an output from the phase / frequency detector and generate pulses. The oscillator is configured to generate an output waveform based on the pulses from the charge pump. The realignment path is configured to generate a clock realignment signal to the oscillator based on the output from the phase / frequency detector.

Description

Technical Field

[0001] This disclosure relates to a phase-locked loop, and more specifically to a phase-locked loop for generating a circuit clock. Background Technology

[0002] High-speed clock signals have a variety of applications, including wireless data communications and medical devices and instruments. A phase-locked loop (PLL) is typically implemented to lock the phase and frequency of a first device (usually a higher-frequency local oscillator such as a voltage-controlled oscillator (VCO)) to a lower-frequency reference device (usually a temperature-compensated (TCXO) or oven-controlled oscillator (OCXO)). PLLs are used because the phase and frequency of the first device (usually a higher-frequency device) may not be very stable with respect to temperature and time, while the second device performs better with respect to these characteristics. Summary of the Invention

[0003] According to one embodiment of this disclosure, a phase-locked loop is disclosed, comprising a phase / frequency detector, a charge pump, an oscillator, a filter, and a realignment path. The phase / frequency detector receives a reference signal and a feedback signal. The charge pump receives a first output and a second output from the phase / frequency detector and generates pulses. The oscillator generates an output waveform based on the charge pump pulses. A filter is located between the charge pump and the oscillator. The realignment path generates a clock realignment signal for the oscillator based on a third output from the charge pump, bypassing the filter and routing it through a first matching gate.

[0004] According to another embodiment of this disclosure, a method for generating a periodic output waveform is disclosed, comprising: comparing the phase and frequency of a reference signal and a feedback signal using a phase / frequency detector; generating a pulse using a charge pump based on a first output and a second output of the phase / frequency detector; generating an output waveform based on the charge pump pulse and a clock realignment signal, the clock realignment signal being based on a third output from the charge pump; and providing the third output from the charge pump to a first alignment logic gate such that the third output bypasses a filter before generating the clock realignment signal.

[0005] According to another embodiment of this disclosure, a clock generation circuit is disclosed, comprising a charge pump, a realignment circuit, and an oscillator. The charge pump receives a first input signal and a second input signal, routes the first and second input signals to corresponding first and second alignment logic gates, and generates a pulse signal and an output signal based on the first and second input signals. The realignment circuit generates a realignment signal based on the output signal from the charge pump after bypassing a filter and routing it through a third alignment logic gate. The oscillator generates an output waveform based on the pulse signal and the realignment signal.

[0006] According to one embodiment of this disclosure, a phase-locked loop is disclosed, comprising a charge pump, an oscillator, a filter, and a realignment path. The filter is located between the charge pump and the oscillator. The realignment path generates a clock realignment signal provided to the oscillator. The clock realignment signal is based on the first output from the charge pump after bypassing the filter and routing through a first matched gate.

[0007] According to another embodiment of this disclosure, a method for generating a periodic output waveform is disclosed, comprising generating a clock realignment signal based on the output from a charge pump; and providing the output from the charge pump to a first alignment logic gate such that the output is bypassed by a filter before generating the clock realignment signal.

[0008] According to another embodiment of this disclosure, a clock generation circuit is disclosed, comprising a charge pump, a realignment circuit, and an oscillator. The charge pump receives an input signal to generate an output signal based on the output signal, and generates a plurality of pulse signals based on the output signal after the output signal is routed through a first alignment logic gate. The realignment circuit generates a realignment signal based on the output signal after bypassing a filter and routing the output signal through a second alignment logic gate. The oscillator generates an output waveform based on the pulse signals and the realignment signal. Attached Figure Description

[0009] An embodiment of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0010] Figure 1 It is a block diagram depicting a phase-locked loop with charge pump-based realignment according to an embodiment;

[0011] Figure 2 This is a diagram depicting a phase-locked loop with a matching skew mitigation circuit according to an embodiment;

[0012] Figure 3 The above describes about Figure 2 The relative timing of the described signals;

[0013] Figure 4 This is a diagram showing the relative pulse widths of the PLL signals according to an embodiment;

[0014] Figure 5 This is a diagram showing a PLL with a pulse generator that operates based on a realigned pulse width control signal;

[0015] Figure 6 This is a diagram illustrating a pulse generator with controllable pulse width according to an embodiment;

[0016] Figure 7 A phase-locked loop utilizing an OR gate skew mitigation circuit according to an embodiment is described;

[0017] Figure 8 It is a flowchart depicting a method for generating periodic output waveforms.

[0018] [Symbol Explanation]

[0019] 100:PLL

[0020] 102:VCO

[0021] 104: Charge Pump

[0022] 106: Feedback Path

[0023] 108: Feedback Path Circuit

[0024] 110: Phase / Frequency Detector (PFD)

[0025] 112: Low-pass filter

[0026] 114: Realign the path

[0027] 116: Pulse Generator

[0028] 118: (Matching) Skew Reduction Circuit A

[0029] 120: (Matching) Skew Reduction Circuit B

[0030] CLK RL (Clock) Realign signal

[0031] F out Output waveform

[0032] UP BUF ,DN BUF :Signal, buffered output

[0033] F REF Reference frequency

[0034] UPPFD ,DN PFD Control signals

[0035] F IN ,F BK :enter

[0036] VCO IN Voltage, voltage level

[0037] UP PUMP ,DN PUMP :Signal

[0038] F UP_AND_DN : Signal, Input

[0039] 302, 304, 306, 402, 404, 406: Time

[0040] 200: Frequency divider

[0041] 201: Buffer

[0042] 202,208: Buffer

[0043] 204, 206: Current source

[0044] 502: Realignment pulse width control signal

[0045] 600: Pulse Generator

[0046] 602: Inverter Series

[0047] 604: Width Control Circuit

[0048] 606, 608, 610, 612, 614: NAND gates

[0049] 616, 618, 620: Inverters

[0050] Widthcontrol[2:0]: (3-bit) Width control signal

[0051] 702: Skew Reduction Circuit A

[0052] 704: Skew Reduction Circuit B

[0053] F UP_OR_DN :Signal

[0054] 802, 804, 806: Steps Detailed Implementation

[0055] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify one embodiment of this disclosure. Of course, these are merely examples and are not intended to be limiting. Furthermore, one embodiment of this disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0056] As described above, a PLL can be used to maintain the correct operating behavior of a high-frequency oscillator (e.g., a VCO as described in the examples herein). However, the PLL itself may sometimes be nominally off, sometimes due to small errors accumulated over a period of time. To address this imperfect PLL behavior, a realignment path can be used to implement the PLL, which generates a clock realignment signal provided to the VCO (e.g., periodically, by command, or upon the occurrence of an error or other predetermined condition) to realign the VCO operation with a reference device. In some embodiments, correct alignment of the clock realignment signal with the current state of the VCO and PLL may be important for achieving correct realignment operations so that the locked state is not compromised. In embodiments, the systems and methods of this document provide the VCO with a clock realignment signal with accurate timing.

[0057] Figure 1 This is a block diagram depicting a phase-locked loop with charge pump-based realignment according to an embodiment. PLL 100 controls VCO 102, which is used to operate based on charge pump pulses generated by charge pump 104 and a realignment signal (CLK). RL To generate a periodic output waveform (F) out The exemplary PLL 100 is used as a negative feedback system that locks the phase and frequency of the VCO 102 to the value originating from F. REF The device provides a more stable signal, typically at a lower frequency. Feedback path 106 includes feedback path circuitry 108, which, in an embodiment, includes a frequency divider to divide the output frequency V of VCO 102. out Reduced to the reference frequency F REF The frequency approximation is achieved. In an embodiment, as further described herein, after some delay, the phase / frequency detector (PFD) 110 at F... IN The reference frequency is received at the input F. BK Receives feedback signal from feedback path 106. PFD110 compares input F. IN F BK The system receives the signal and generates a control signal UP. PFDand DN PFD The control signal UP PFD and DN PFD Instruct the charge pump 104 to operate at a reference frequency F REF Rate absorption or supply of current pulses. Those current pulses from charge pump 104 are processed by low-pass filter 112 to generate the voltage VCO applied to the tuning port of VCO 102. IN This continues until the input of PFD (F) IN F BK The adjustment process continues until the inputs are equal and in phase. When these inputs are equal, the PLL 100 is said to be locked.

[0058] Despite the locked state, phase noise, spurious signals, and other phenomena can cause abnormal behavior of PLL100 over time, resulting in suboptimal output of VCO102. To mitigate this suboptimal behavior, realignment path 114 uses realignment circuit 116, which includes a pulse generator in the embodiment, to provide VCO102 with (e.g., periodically) clock realignment pulses CLK. RL The realignment circuit 116 receives the UP signal based on signals received directly in front of or near the charge pump 104. BUF and DN BUF The input signal. To maintain the click realign signal CLK. RL To ensure proper alignment with the current states of VCO102 and PLL without disrupting the locked state of PLL100, charge pump 104 and realignment path 114 may include matching circuitry for processing the UP signal. BUF and DN BUF The (matching) skew reduction circuits are A118 and B120. For example, the skew reduction circuit A118 can use the first logic gate to process the signal UP. BUF And use the second logic gate to process DN BUF The skew mitigation circuit B120 can use a third logic gate to process the UP signal. BUF and DN BUF Both, wherein the first, second and third logic gates have the same type (e.g., AND gate, OR gate), and in the embodiments, have the same logic gates (e.g., the same part number, gates of the same type on a multi-gate integrated circuit).

[0059] Figure 2 This is a diagram depicting a phase-locked loop with a matching skew mitigation circuit according to an embodiment. PLL100 includes PFD110, which... BK After receiving feedback loop 106, at input F IN The reference signal F is received at the location.REF And receive feedback signals from feedback path circuit 108 (e.g., frequency divider 200 and buffer 201), and based on the input F IN F BK The output control signal UP is generated by comparing the frequency and phase of the input signals at the specified location. PFD DN PFD The charge pump 104 receives the output of the PFD 110 and uses these outputs to generate current pulses that are supplied to the low-pass filter 112, which converts the current pulses into a voltage level VCO 102. IN PLL 100 further includes a realignment path 114 for generating an output based on the PFD 110 (i.e., derived from the control signal UP). PFD DN PFD The signal provided to VCO102 is the clock realignment signal CLK. RL .

[0060] Further referring to charge pump 104, charge pump 104 receives the input control signal UP from PFD 110. PFD DN PFD Furthermore, in this embodiment, those input signals can be provided to buffer 202. In this embodiment, the amount of delay provided by buffer 202 is user-controllable during the design phase, such as when using computer-aided circuit design software. The buffered output UP from buffer 202... BUF DN BUF Provided to the skew reduction circuit A118. Figure 2 In the example, the skew reduction circuits A118 and B120 are implemented using AND gates. Skew reduction circuit A118 includes AND gates, one of which is pulled high, and the other input receives a buffered output UP. BUF DN BUF One of them, to generate the UP signal respectively. PUMP DN PUMP Signal UP PUMP Control the switch connected to current source 204 so that it responds to the UP signal. PUMP A current pulse is supplied to low-pass filter 112. Signal DN PUMP Control the switch connected to another current source 206 so that it is based on the signal DN PUMP The current pulse is absorbed into the low-pass filter 112.

[0061] Looking further into the realignment path 114, the skew mitigation circuit B 120 receives the UP signal from the charge pump 104. BUF and DNBUF The skew mitigation circuit B 120 uses AND gates that are substantially the same as or identical to those used in the skew mitigation circuit A 118 (e.g., gates of the same type, size, or part number). The skew mitigation circuit B 120 will activate the UP signal. BUF and DN BUF All inputs are provided to the AND gate to generate a signal F that is supplied to the pulse generator realignment circuit 116. UP_AND_DN The pulse generator 116 is based on the received signal F UP_AND_DN To provide the clock realignment signal CLK RL In one embodiment, the clock realignment signal CLK RL The width is controllable, as further described in this article.

[0062] Figure 2 The exemplary realignment path 114 provides several features that individually or jointly maintain the clock realignment signal CLK. RL Alignment with the current state of VCO102 and PLL100 is achieved to avoid disrupting the locked state of PLL100 during realignment. Firstly, using the post-PFD 110 signal as the input to realignment path 114 alleviates the difficulty of estimating buffer delays during the circuit design phase. As mentioned above, some buffer delays (e.g., delays from buffer 202) can be controlled by the user during computer-aided circuit design. However, in some cases, other signal delays (e.g., delays at input F) are buffered. REF With F IN The buffer 208 between the PLL 100 and other components in the larger circuit can be selected by the automatic placement and routing routines of computer-aided circuit design software to resolve timing issues between the PLL 100 and other components in the larger circuit. If the realigned path 114 originates from before PFD 110 (e.g., from the reference frequency F before buffer 208), REF If the buffer delay at buffer 208 is not near the source, the uncertain buffer delay will introduce uncertainty into the realignment path 114. Early provision of the realignment path 114 may require the use of a programmable delay line or delay-locked loop to address the uncertain total delay in buffers 208 and 202. By providing the realignment path 114 after buffer 208 (buffer 202 in this embodiment), any need for a programmable delay line or delay-locked loop can be avoided.

[0063] Second, the clock realignment signal CLK is improved by using the same or substantially the same structure (e.g., logic gates, one or more transistors) at the skew mitigation circuits 118 and 120. RLAlignment with the current states of VCO102 and PLL100. The use of the same or substantially the same gates results in the timing from the output of buffer 202 to the input of low-pass filter 112 being substantially the same as the timing from the output of buffer 202 to the input of pulse generator 116. In the embodiment, skew mitigation circuit A 118 compensates for the UP at skew mitigation circuit B120 by using a common logic gate design for each of the logic gates depicted at skew mitigation circuit A118 and skew mitigation circuit B120. BUF and DN BUF The combined waiting time. Therefore, in the embodiment, when PLL 100 is in a locked state, input F IN With F BK Alignment, and control signal UP PFD With DN PFD Alignment, both signals have a common pulse width, where by signal F UP_AND_DN With signal UP PUMP and DN PUMP Alignment reduces the contribution of phase error to VCO102.

[0064] Figure 3 The above describes about Figure 2 The relative timing of the described signals. At 302, the reference signal F REF Transform to high. In some cases, during the design phase before automatic placement and routing, there is an unknown length of delay. PFD 110 compares the input F. IN and F BK The signal at the location is further buffered at buffer 202, and the signal UP is... BUF and DN BUF During the PLL 100's locked state, alignment transitions to high at 304. (Signal UP) BUF Traversing its AND gates in the skew reduction circuit A118, signal DN BUF Traverse the AND gates in the skew reduction circuit A 118, and process the signal UP at the AND gate in the skew reduction circuit B 120. BUF and DN BUF Both form a signal UP PUMP DN PUMP and F UP_AND_DN The signal UP PUMP DN PUMP and F UP_AND_DN During the locked state of PLL100, the signal consistently transitions high at 306, i.e., signal F. UP_AND_DN With signal UP PUMP DN PUMP alignment.

[0065] In some cases, it has been observed that the realignment path exhibits improved performance when the pulse width from PFD 110 is greater than the pulse width output from pulse generator 116, and when the pulse width from pulse generator 116 is less than half the period of the VCO clock. That is:

[0066] PFD 脉冲_宽度 Pulse Generator 脉冲_宽度 ;and

[0067] Pulse generator 脉冲_宽度 <0.5x VCO 周期 .

[0068] Figure 4 This is a graph showing the relative pulse widths of the PLL signals according to an embodiment. At 402, the reference signal F REF Convert to high. PFD 110 compares input F IN and F BK The signal at the location, and after being buffered at buffer 202, the signal UP BUF and DN BUF During the locked state of PLL 100, alignment transitions to high at position 404. (Signal UP) BUF and Dn BUF Both are processed at the AND gate in the skew reduction circuit B120 to form signal F. UP_AND_DN The signal F UP_AND_DN Command pulse generator 116 generates clock realignment signal CLK RL Signal UP BUF DN BUF and F UP_AND_DN Each pulse width is based on the pulse width output from the PFD110 (PFD reset pulse). Figure 4 In one example, pulse generator 116 is used to output a pulse with a value that is smaller than VCO. 周期 Half of which is smaller than PFD 脉冲_宽度 The pulse width (realigned pulse width) is either greater than the pulse width of the PFD reset pulse, or conversely, the PFD reset pulse width is greater than the pulse width of the realigned pulse.

[0069] To ensure that a realigned path pulse width can be provided according to the desired parameters, in this embodiment, the pulse generator 116 is implemented using a configuration that controls the pulse width according to modifiable control parameters. Figure 5 This diagram illustrates a PLL 100 with a pulse generator that operates based on a realigned pulse width control signal. The PLL 100 includes a PFD 110, which... IN The reference signal is received at the input F. BKThe system receives feedback signals. The charge pump 104 receives the output from the PFD 110 and generates pulses, which are output to the low-pass filter 112, which provides the control voltage VCO to the VCO 102. IN The realignment path 114 includes a clock realignment circuit 116, which generates a clock realignment signal CLK to be provided to the VCO 102. RL .exist Figure 5 In this embodiment, the realignment circuit system 116 receives a realignment pulse width control signal 502, which is used to control the clock realignment signal CLK. RL The pulse width, such as to meet the pulse width standard mentioned above.

[0070] Figure 6 This is a diagram illustrating a pulse generator with controllable pulse width according to an embodiment. The pulse generator 600 receives an input signal F. UP_AND_DN It provides a clock realignment signal CLK at its output based on the width control signals Widthcontrol[2:0]. RL Specifically, signal F UP_AND_DN Received by inverter array 602, which is used to make signal F UP_AND_DN Delay and inversion. As shown in the figure, signal F UP_AND_DN The delayed and inverted versions are received by a width control circuit 604, which includes NAND gates 606, 608, 610, 612, 614 and inverters 616, 618, 620 electrically connected together. The width control circuit 604 also receives a three-bit width control signal Widthcontrol[2:0] and uses this received signal to control the width of the pulse generated by the pulse generator 600.

[0071] More specifically, such as in Figure 6 As seen in the exemplary embodiment, the first bit of the three-bit width control signal Widthcontrol[2:0] is received at NAND gate 606, the second bit of the three-bit width control signal Widthcontrol[2:0] is received at NAND gate 608, and the third bit of the three-bit width control signal Widthcontrol[2:0] is received at NAND gate 610. The following illustrates an exemplary scheme through which the three-bit width control signal Widthcontrol[2:0] can be used to control the width of the pulse generated by pulse generator 600:

[0072]

[0073] As can be seen from the table above, in this example, if the first bit (e.g., the least significant bit) is high (e.g., logic level high or "1"), and the second and third bits are low (e.g., logic level low or "0"), the pulse signal generated by pulse generator 600 has a first width (e.g., the narrowest width). Furthermore, in this example, if the third bit (e.g., the most significant bit) is high, and the first and second bits are low, the pulse signal generated by pulse generator 600 has a second width (e.g., the widest width). Additionally, in this example, if the second bit is high, and the first and third bits are low, the pulse signal generated by pulse generator 600 has a third width (e.g., a moderate width between the aforementioned narrowest and widest widths). Further details of exemplary operation of a controllable pulse width generator are described in U.S. Patent Application No. 16 / 744,413, entitled "Oscillator Circuits and Methods for Realignment of an Oscillator Circuit," the entire contents of which are incorporated herein by reference.

[0074] While previous examples have used AND gates in implementing skew reduction circuits A118 and B120, other circuits, such as different logic gates or different circuit components (e.g., transistors), can be used. Figure 7 A phase-locked loop utilizing an OR gate skew mitigation circuit according to an embodiment is depicted. PLL 100 includes PFD 110, which in turn... BK After receiving feedback loop 106, at input F IN The reference signal F is received at the location. REF And receive feedback signals from feedback path circuit 108 (e.g., frequency divider 200 and buffer 201), and based on the input F IN F BK The output control signal UP is generated by comparing the frequency and phase of the input signals at the specified location. PFD DN PFD The charge pump 104 receives the output of the PFD 110 and uses these outputs to generate current pulses that are supplied to the low-pass filter 112, which converts the current pulses into a voltage level VCO 102. IN PLL 100 further includes a realignment path 114 for generating an output based on the PFD 110 (i.e., derived from the control signal UP). PFD DN PFD The signal provided to VCO102 is the clock realignment signal CLK. RL .

[0075] Further referring to charge pump 104, charge pump 104 receives input control signal UP from PFD 110. PFD DN PFD Furthermore, in this embodiment, those input signals can be provided to buffer 202. The signal UP from buffer 202... BUF DN BUF The buffered output is provided to the skew reduction circuit A702 at the skew reduction circuit A702. Figure 7 In the example, the skew reduction circuits A702 and B704 are implemented using OR gates. Skew reduction circuit A702 includes AND gates, one of which is pulled low, and the other input receives the signal UP. BUF DN BUF One of them, to generate the UP signal respectively. PUMP DN PUMP Signal UP PUMP Control the switch connected to current source 204 so that it responds to the UP signal. PUMP A current pulse is supplied to low-pass filter 112. Signal DN PUMP Control the switch connected to another current source 206 so that it is based on the signal DN PUMP The current pulse is absorbed into the low-pass filter 112.

[0076] Further regarding the realignment path 114, the skew mitigation circuit B 704 receives the UP signal from the charge pump 104. BUF and DN BUF The skew reduction circuit B 704 is implemented using an OR gate that is substantially the same as or identical to the OR gate used in the skew reduction circuit A 702. The skew reduction circuit B 704 will push the signal UP... BUF and DN BUF All inputs are provided to the OR gate input to generate a signal F that is supplied to the pulse generator realignment circuit 116. UP_OR_DN The pulse generator 116 is based on the received signal F UP_OR_DN To provide the clock realignment signal CLK RL .

[0077] Figure 8 This is a flowchart depicting a method for generating a periodic output waveform. The method includes comparing the phase and frequency of a reference signal with a feedback signal using a phase / frequency detector at 802. At 804, a charge pump generates pulses based on the output of the phase / frequency detector. At 806, the output waveform is generated based on the charge pump pulses and a clock realignment signal, the clock realignment signal being based on the output from the phase / frequency detector.

[0078] The systems and methods described herein can take various forms. In one example, a system and method for a phase-locked loop (PLL) are provided. The PLL includes a phase / frequency detector, a charge pump, an oscillator, and a realignment path. The phase / frequency detector receives a reference signal and a feedback signal. The charge pump receives the output from the phase / frequency detector and generates pulses. The oscillator generates an output waveform based on the charge pump pulses. The realignment path generates a clock realignment signal for the oscillator based on the output from the phase / frequency detector.

[0079] In some embodiments, the charge pump and realignment path include a plurality of matching logic gates, wherein a first matching gate in the matching logic gates receives a first signal from a phase / frequency detector, a second matching gate in the matching logic gates receives a second signal from a phase / frequency detector, and a third matching gate in the matching logic gates receives both the first and second signals from the phase / frequency detector.

[0080] In some embodiments, the first matching gate, the second matching gate, and the third matching gate are all AND gates or all OR gates.

[0081] In some embodiments, the phase-locked loop further includes a low-pass filter for receiving pulses from the charge pump and generating inputs to the oscillator.

[0082] In some embodiments, a clock realignment signal is periodically generated to reset any accumulated errors in the phase-locked loop.

[0083] In some embodiments, the realignment path does not receive input from prior to the phase / frequency detector.

[0084] In some embodiments, the realignment path does not include a programmable delay line or a delay-locked loop.

[0085] In some embodiments, the phase-locked loop further includes a feedback path that provides the output waveform as a feedback signal to the phase / frequency detector.

[0086] In some embodiments, the feedback path includes a frequency divider.

[0087] In some embodiments, the reference signal is provided to the phase / frequency detector after a first delay period, wherein the delay period is determined by the automatic placement and routing routines of computer-aided circuit design software.

[0088] In some embodiments, the charge pump receives the output from the phase / frequency detector after a second delay period, wherein the second delay period is selectable by the user using computer-aided design software.

[0089] In some embodiments, the realignment path includes a pulse generator, wherein the realignment signal is generated by the pulse generator and the clock realignment signal is provided to the oscillator.

[0090] In some embodiments, the pulse width of the realignment signal can be controlled via an input to the pulse generator.

[0091] In some embodiments, the pulse width of the pulse generator is controlled to have a length shorter than the width of the pulse generated by the phase / frequency detector, and a length shorter than half the period of the output waveform.

[0092] In some embodiments, the input selects one of a plurality of sequential logic gates to provide a selection signal, wherein each of the sequential logic gates is associated with a different pulse width of a realignment signal.

[0093] In another example, a method for generating a periodic output waveform includes using a phase / frequency detector to compare the phase and frequency of a reference signal with that of a feedback signal. A charge pump is used to generate pulses based on the output of the phase / frequency detector. The output waveform is generated based on the charge pump pulses and a clock realignment signal, which is based on the output of the phase / frequency detector.

[0094] In some embodiments, the method further includes the steps of: providing each of the outputs of the phase / frequency detectors to a corresponding first alignment logic gate and a second alignment logic gate before generating a pulse; and providing both of the outputs of the phase / frequency detectors to a third alignment logic gate before generating a clock realignment signal.

[0095] In some embodiments, the first alignment logic gate, the second alignment logic gate, and the third alignment logic gate are ordinary type logic gates.

[0096] As another example, the clock generation circuit includes a charge pump, a realignment circuit, and an oscillator. The charge pump receives a first input signal and a second input signal, routes them to corresponding first and second alignment logic gates, and generates a pulse signal based on the first and second input signals. The realignment circuit generates a realignment signal based on the first and second input signals after both signals have been routed through a third alignment logic gate. The oscillator generates an output waveform based on the pulse signal and the realignment signal.

[0097] In some embodiments, the first alignment logic gate, the second alignment logic gate, and the third alignment logic gate are ordinary type logic gates.

[0098] The foregoing has outlined the features of several embodiments, enabling those skilled in the art to better understand the appearance of one embodiment of this disclosure. Those skilled in the art should understand that they can readily use one embodiment of this disclosure as the basis for designing or modifying other processes and structures to achieve the same purpose and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of one embodiment of this disclosure, and that various changes, substitutions, and modifications can be made to them without departing from the spirit and scope of one embodiment of this disclosure.

Claims

1. A phase-locked loop, characterized in that, Include: A phase / frequency detector for receiving a reference signal and a feedback signal; A charge pump is used to receive the first and second outputs from the phase / frequency detector and generate multiple pulses; An oscillator for generating an output waveform based on the plurality of pulses from the charge pump; A filter is provided between the charge pump and the oscillator. as well as A realignment path is provided to generate a clock realignment signal for the oscillator based on the third output from the charge pump, after bypassing the filter and routing through a third matched gate.

2. The phase-locked loop as described in claim 1, characterized in that, The charge pump includes a first matching gate and a second matching gate.

3. The phase-locked loop as described in claim 2, characterized in that, The first matching gate, the second matching gate, and the third matching gate are all AND gates or all OR gates.

4. The phase-locked loop as described in claim 1, characterized in that, The filter is a low-pass filter used to receive the plurality of pulses from the charge pump and generate an input to the oscillator.

5. The phase-locked loop as described in claim 1, characterized in that, The clock realignment signal is generated periodically to reset any accumulated errors in the phase-locked loop.

6. The phase-locked loop as described in claim 1, characterized in that, The realignment path does not receive input from prior to the phase / frequency detector.

7. The phase-locked loop as described in claim 1, characterized in that, The realignment path does not include a programmable delay line or a delay-locked loop.

8. The phase-locked loop as described in claim 1, characterized in that, Further includes: A feedback path is provided to the phase / frequency detector as the feedback signal, wherein the output waveform is provided as the feedback signal.

9. The phase-locked loop as described in claim 8, characterized in that, The feedback path includes a frequency divider.

10. The phase-locked loop as described in claim 1, characterized in that, The reference signal is provided to the phase / frequency detector after a first delay period, wherein the delay period is determined by an automatic placement and routing routine of computer-aided circuit design software.

11. The phase-locked loop as described in claim 10, characterized in that, The charge pump receives the first output and the second output from the phase / frequency detector after a second delay period, wherein the second delay period is selectable by the user using the computer-aided circuit design software.

12. The phase-locked loop as described in claim 1, characterized in that, The realignment path includes: A pulse generator, wherein the realignment signal is generated by the pulse generator, and the clock realignment signal is provided to the oscillator.

13. The phase-locked loop as described in claim 12, characterized in that, The pulse width of the realignment signal can be controlled via an input to the pulse generator.

14. The phase-locked loop as described in claim 13, characterized in that, The pulse width of the pulse generator is controlled to have a length shorter than the width of the pulse generated by the phase / frequency detector, and a length shorter than half the period of the output waveform.

15. The phase-locked loop as described in claim 13, characterized in that, The input selects one of a plurality of sequential logic gates to provide a selection signal, wherein each of the plurality of sequential logic gates is associated with a different pulse width of the realignment signal.

16. A method for generating a periodic output waveform, characterized in that, Includes the following steps: A phase / frequency detector is used to compare the phase and frequency of a reference signal with a feedback signal. A charge pump is used to generate multiple pulses based on the first and second outputs of the phase / frequency detector; An output waveform is generated based on the plurality of pulses from the charge pump and a clock realignment signal, the clock realignment signal being based on a third output from the charge pump; as well as The third output from the charge pump is provided to the first alignment logic gate such that the third output bypasses a filter before generating the clock realign signal.

17. The method as described in claim 16, characterized in that, Further steps include: Each of the first and second outputs of the phase / frequency detector is provided to a corresponding second and third alignment logic gate before being used to generate the plurality of pulses.

18. The method as described in claim 17, characterized in that, The first alignment logic gate, the second alignment logic gate, and the third alignment logic gate are ordinary type logic gates.

19. A clock generating circuit, characterized in that, Include: A charge pump is configured to receive a first input signal and a second input signal, the charge pump being configured to route the first input signal and the second input signal to a corresponding first alignment logic gate and a second alignment logic gate, and the charge pump being configured to generate a plurality of pulse signals and an output signal based on the first input signal and the second input signal; A realignment circuit is used to generate a realignment signal based on the output signal from the charge pump after bypassing a filter and routing the output signal from the charge pump through a third alignment logic gate. as well as An oscillator for generating an output waveform based on the plurality of pulse signals and the realignment signal.

20. The clock generating circuit as described in claim 19, characterized in that, The first alignment logic gate, the second alignment logic gate, and the third alignment logic gate are ordinary type logic gates.

21. A phase-locked loop, characterized in that, Include: A charge pump; An oscillator; A filter is placed between the charge pump and the oscillator; and A realignment path is provided to generate a clock realignment signal for the oscillator, the clock realignment signal being based on the first output from the charge pump after bypassing the filter and routing through a first matched gate.

22. The phase-locked loop as described in claim 21, characterized in that, The charge pump includes: A second matching gate is used to receive the first output and generate a control signal; A current source; and A switch, which is controlled by the control signal to connect to and disconnect from the filter.

23. The phase-locked loop as described in claim 22, characterized in that, Each of the first matching gate and the second matching gate is an AND gate or an OR gate.

24. The phase-locked loop as described in claim 21, characterized in that, The filter is a low-pass filter used to receive multiple pulses from the charge pump and generate an input to the oscillator.

25. The phase-locked loop as described in claim 21, characterized in that, The clock realignment signal is generated periodically to reset the accumulated error in the phase-locked loop.

26. The phase-locked loop as described in claim 21, characterized in that, The realignment path does not receive input from the phase / frequency detector.

27. The phase-locked loop as described in claim 21, characterized in that, The realignment path does not include a programmable delay line or a delay-locked loop.

28. The phase-locked loop as described in claim 21, characterized in that, Further includes: A feedback path is provided to provide an output waveform from the oscillator as a feedback signal.

29. The phase-locked loop as described in claim 28, characterized in that, The feedback path includes a frequency divider.

30. The phase-locked loop as described in claim 21, characterized in that, The realignment path is further used to generate the clock realignment signal based on a second output from the charge pump, the second output bypassing the filter and routing through the first matching gate.

31. The phase-locked loop as described in claim 21, characterized in that, The charge pump is used to receive a first input to generate the first output.

32. The phase-locked loop as described in claim 21, characterized in that, The realignment path includes: A pulse generator, wherein the realignment signal is generated by the pulse generator.

33. The phase-locked loop as described in claim 32, characterized in that, The pulse width of the realignment signal can be controlled via an input to the pulse generator.

34. The phase-locked loop as described in claim 33, characterized in that, The pulse width of the pulse generator is controlled to have a length shorter than the pulse width generated by the phase / frequency detector, and a length shorter than half the period of the output waveform from the oscillator.

35. The phase-locked loop as described in claim 33, characterized in that, The input selects one of a plurality of sequential logic gates to provide a selection signal, and each of the plurality of sequential logic gates is associated with a different pulse width of the realignment signal.

36. A method for generating a periodic output waveform, characterized in that, Includes the following steps: A clock realignment signal is generated based on the output from the charge pump; and The output from the charge pump is provided to a first alignment logic gate such that the output is bypassed by a filter before generating the clock realign signal.

37. The method as described in claim 36, characterized in that, Further steps include: The output is provided to a second alignment logic gate to generate multiple pulses.

38. The method as described in claim 37, characterized in that, The first alignment logic gate and the second alignment logic gate are ordinary type logic gates.

39. A clock generating circuit, characterized in that, Include: A charge pump is configured to receive an input signal to generate an output signal based on the input signal, and to generate a plurality of pulse signals based on the output signal after the output signal is routed through a first alignment logic gate. A realignment circuit is used to generate a realignment signal based on the output signal after the output signal is bypassed by a filter and routed through a second alignment logic gate. as well as An oscillator for generating an output waveform based on the plurality of pulse signals and the realignment signal.

40. The clock generating circuit as described in claim 39, characterized in that, The first alignment logic gate and the second alignment logic gate are ordinary type logic gates.

Images