Display device and driving method of display device

Abstract

A display device includes a display panel including a plurality of data lines and a plurality of pixels connected to the plurality of data lines, a data driver including a plurality of channels that supply data voltages to the plurality of pixels through the plurality of data lines, and a controller that controls the data driver. The plurality of channels are grouped into a first channel group to an Nth channel group (N is an integer of 2 or more). The first channel group to the Nth channel group sequentially start first dummy data voltage output operations in a first blank interval before an active interval in order of the first channel group to the Nth channel group. The first channel group to the Nth channel group sequentially end second dummy data voltage output operations in a second blank interval after the active interval in order of the Nth channel group to the first channel group.

Description

Technical Field

[0001] This invention relates to display devices, and more particularly to display devices that perform virtual data voltage output operations and a driving method for said display devices. Background Technology

[0002] Typically, a display device may include: a display panel including a plurality of pixels; a data driver that provides data voltage to the plurality of pixels via data lines; a scan driver that provides scan signals to the plurality of pixels via scan lines; and a controller that controls the data driver and the scan driver.

[0003] The frame interval of the display device may include an active interval and a blank interval (or a vertical blank interval). In the active interval, the data driver can output the data voltage to the data line, and the plurality of pixels can display an image based on the data voltage received through the data line. In the blank interval, the data driver either does not output the data voltage to the data line or outputs a black data voltage to the data line.

[0004] On the other hand, between the blank interval where the data voltage is not output and the effective interval where the data voltage is output, the current in the display device (e.g., the current flowing through the analog power supply voltage line) may change drastically (increase or decrease). Due to this drastic current change, the components of the display device (e.g., capacitors, inductors, plates, etc.) may vibrate, and noise may be generated in the display device due to the vibration of the components. Summary of the Invention

[0005] One object of the present invention is to provide a display device that can prevent the generation of noise.

[0006] Another object of the present invention is to provide a driving method for a display device that can prevent the generation of sound noise.

[0007] However, the problems to be solved by the present invention are not limited to those mentioned above, and various extensions can be made without departing from the scope and ideas of the present invention.

[0008] To achieve an objective of the present invention, the display device according to various embodiments of the present invention includes: a display panel including a plurality of data lines and a plurality of pixels connected to the plurality of data lines; a data driver including a plurality of channels providing data voltage to the plurality of pixels through the plurality of data lines; and a controller for controlling the data driver. The plurality of channels are grouped into a first channel group to a Nth channel group (N is an integer greater than or equal to 2). In a first blank interval before the effective interval, the first channel group to the Nth channel group sequentially initiate a first virtual data voltage output operation in the order of the first channel group to the Nth channel group. In a second blank interval after the effective interval, the first channel group to the Nth channel group sequentially terminate a second virtual data voltage output operation in the order of the Nth channel group to the first channel group.

[0009] In one embodiment, the first virtual data voltage output operation may be terminated simultaneously at the end time point of the first blank interval from the first channel group to the Nth channel group, and the second virtual data voltage output operation may be started simultaneously at the beginning time point of the second blank interval from the first channel group to the Nth channel group.

[0010] In one embodiment, the display panel may further include: virtual pixels configured in a first virtual region, the first virtual region being located above a display region configured with the plurality of pixels, the first blank interval including a first virtual region interval for outputting virtual data voltages to the virtual pixels configured in the first virtual region, and the first channel group to the Nth channel group sequentially starting the first virtual data voltage output operation in the first virtual region interval according to the order of the first channel group to the Nth channel group.

[0011] In one embodiment, the first virtual region may be divided into a first sub-region to an Nth sub-region, and the first channel group to the Nth channel group may start the first virtual data voltage output operation at the start time point of the first sub-region to the Nth sub-region, respectively.

[0012] In one embodiment, the first virtual data voltage output operation may be an operation that alternately outputs the maximum data voltage and the black data voltage to the virtual pixel as the virtual data voltage.

[0013] In one embodiment, the first virtual data voltage output operation may be an operation of alternately outputting progressively increasing data voltage and black data voltage as the virtual data voltage to the virtual pixel.

[0014] In one embodiment, the display panel may further include: virtual pixels configured in a second virtual region, the second virtual region being located below the display region configured with the plurality of pixels, the second blank interval including a second virtual region interval for outputting virtual data voltage to the virtual pixels configured in the second virtual region, the first channel group to the Nth channel group being in the second virtual region interval, and the second virtual data voltage output operation being completed sequentially in the order of the Nth channel group to the first channel group.

[0015] In one embodiment, the second virtual region may be divided into a first sub-region to an Nth sub-region, and the first channel group to the Nth channel group may respectively end the second virtual data voltage output operation at the end time point of the Nth sub-region to the first sub-region.

[0016] In one embodiment, the second virtual data voltage output operation may be an operation that alternately outputs the maximum data voltage and the black data voltage to the virtual pixel as the virtual data voltage.

[0017] In one embodiment, the second virtual data voltage output operation may be an operation that alternately outputs progressively decreasing data voltage and black data voltage as the virtual data voltage to the virtual pixel.

[0018] In one embodiment, the controller may transmit line data for each pixel row to the data driver. The line data includes line start data indicating the start of the line data, composition data indicating composition information, pixel data for the plurality of pixels included in each pixel row, and horizontal blanking interval data corresponding to a horizontal blanking interval. The first virtual data voltage output operation of the first channel group to the Nth channel group in the first blanking interval is controlled by the pixel data of the line data in the first blanking interval, and the second virtual data voltage output operation of the first channel group to the Nth channel group in the second blanking interval is controlled by the pixel data of the line data in the second blanking interval.

[0019] In one embodiment, the controller may transmit line data for each pixel row to the data driver. The line data includes line start data indicating the start of the line data, composition data indicating composition information, pixel data for the plurality of pixels included in each pixel row, and horizontal blanking interval data corresponding to a horizontal blanking interval. The first virtual data voltage output operation of the first channel group to the Nth channel group in the first blanking interval is controlled by the composition data of the line data in the first blanking interval, and the second virtual data voltage output operation of the first channel group to the Nth channel group in the second blanking interval is controlled by the composition data of the line data in the second blanking interval.

[0020] In one embodiment, the data driver may include: a counter for counting clock signals, wherein the first virtual data voltage output operation of the first channel group to the Nth channel group within the first blank interval and the second virtual data voltage output operation of the first channel group to the Nth channel group within the second blank interval are controlled based on the counted clock signals.

[0021] To achieve other objectives of the present invention, in the driving method of the display device according to various embodiments of the present invention, multiple channels of the data driver of the display device are grouped into a first channel group to a Nth channel group (N is an integer greater than 2). In a first blank interval before the effective interval, a first virtual data voltage output operation of the first channel group to the Nth channel group is started sequentially in the order of the first channel group to the Nth channel group. In the effective interval, a valid data voltage output operation of the first channel group to the Nth channel group is executed. In a second blank interval after the effective interval, a second virtual data voltage output operation of the first channel group to the Nth channel group is ended sequentially in the order of the Nth channel group to the first channel group.

[0022] In one embodiment, the first virtual data voltage output operation from the first channel group to the Nth channel group may be terminated at the end of the first blank interval, and the second virtual data voltage output operation from the first channel group to the Nth channel group may be terminated at the beginning of the second blank interval.

[0023] In one embodiment, the display panel of the display device may include: a plurality of pixels disposed in a display area; and virtual pixels disposed in a first virtual area located above the display area. The first blank interval includes a first virtual area interval for outputting virtual data voltage to the virtual pixels disposed in the first virtual area. The first channel group to the Nth channel group sequentially start the first virtual data voltage output operation in the first virtual area interval in the order of the first channel group to the Nth channel group.

[0024] In one embodiment, the display panel of the display device may include: a plurality of pixels disposed in a display area; and virtual pixels disposed in a second virtual area located at the lower part of the display area. The second blank interval includes a second virtual area interval for outputting virtual data voltage to the virtual pixels disposed in the second virtual area. The first channel group to the Nth channel group sequentially terminate the second virtual data voltage output operation in the second virtual area interval in the order of the Nth channel group to the first channel group.

[0025] In one embodiment, the controller of the display device may transmit line data for each pixel row to the data driver. The line data includes line start data indicating the start of the line data, composition data indicating composition information, pixel data for the plurality of pixels included in each pixel row, and horizontal blanking interval data corresponding to a horizontal blanking interval. The first virtual data voltage output operation of the first channel group to the Nth channel group in the first blanking interval is controlled by the pixel data of the line data in the first blanking interval, and the second virtual data voltage output operation of the first channel group to the Nth channel group in the second blanking interval is controlled by the pixel data of the line data in the second blanking interval.

[0026] In one embodiment, the controller of the display device may transmit line data for each pixel row to the data driver. The line data includes line start data indicating the start of the line data, composition data indicating composition information, pixel data for the plurality of pixels included in each pixel row, and horizontal blanking interval data corresponding to a horizontal blanking interval. The first virtual data voltage output operation of the first channel group to the Nth channel group in the first blanking interval is controlled by the composition data of the line data in the first blanking interval, and the second virtual data voltage output operation of the first channel group to the Nth channel group in the second blanking interval is controlled by the composition data of the line data in the second blanking interval.

[0027] In one embodiment, the data driver may include: a counter for counting clock signals, wherein the first virtual data voltage output operation of the first channel group to the Nth channel group within the first blank interval and the second virtual data voltage output operation of the first channel group to the Nth channel group within the second blank interval are controlled based on the counted clock signals.

[0028] (Invention Effects)

[0029] In the display device and driving method of the display device according to various embodiments of the present invention, multiple channels of the data driver can be grouped into a first channel group to a Nth channel group (N is an integer greater than or equal to 2). In a first blank interval before the effective interval, the first virtual data voltage output operation of the first channel group to the Nth channel group can be started sequentially in the order of the first channel group to the Nth channel group, and in a second blank interval after the effective interval, the second virtual data voltage output operation of the first channel group to the Nth channel group can be ended sequentially in the order of the Nth channel group to the first channel group. Therefore, in the first blank interval before the effective interval, the current in the display device can gradually increase, and in the second blank interval after the effective interval, the current in the display device can gradually decrease, thus preventing the generation of noise caused by abrupt changes in the current. Furthermore, since the first channel group to the Nth channel group are driven sequentially in each blank interval, power consumption can be reduced compared to the case where all multiple channels are driven in each blank interval.

[0030] However, the effects of the present invention are not limited to those described above, and various extensions can be made without departing from the scope and ideas of the present invention. Attached Figure Description

[0031] Figure 1 This is a block diagram illustrating the display device involved in various embodiments of the present invention.

[0032] Figure 2 This is a block diagram illustrating an example of a display panel included in a display device according to various embodiments of the present invention.

[0033] Figure 3 This is a timing diagram illustrating an example of the first virtual data voltage output operation and the second virtual data voltage output operation of the data driver of the display device according to various embodiments of the present invention, for example.

[0034] Figure 4This is a timing diagram illustrating an example of the first virtual data voltage output operation and the second virtual data voltage output operation of the first channel group to the Nth channel group of the data driver of a display device according to an embodiment of the present invention.

[0035] Figure 5 This is a timing diagram illustrating an example of the first virtual data voltage output operation and the second virtual data voltage output operation of the first channel group to the Nth channel group of the data driver of the display device according to other embodiments of the present invention.

[0036] Figure 6 This is a sequence diagram illustrating the driving methods of the display device according to various embodiments of the present invention.

[0037] Figure 7 This is a sequence diagram illustrating a driving method for a display device according to an embodiment of the present invention.

[0038] Figure 8 This is a diagram illustrating an example of line data provided from the controller to the data driver.

[0039] Figure 9 This is a diagram illustrating an example of frame data including line data used to control the first channel group to the Nth channel group in order to perform a first virtual data voltage output operation and a second virtual data voltage output operation.

[0040] Figure 10 This is a sequence diagram illustrating the driving method of a display device according to other embodiments of the present invention.

[0041] Figure 11 This is a diagram illustrating an example of line data used to control the first to Nth channel groups in order to perform a first virtual data voltage output operation and a second virtual data voltage output operation.

[0042] Figure 12 This is a sequence diagram illustrating a driving method for a display device according to another embodiment of the present invention.

[0043] Figure 13 This is a block diagram illustrating an example of a data driver that includes a counter that counts clock signals.

[0044] Figure 14 This is a block diagram illustrating an electronic device including a display device according to various embodiments of the present invention.

[0045] (Symbol Explanation)

[0046] 100: Display device;

[0047] 110: Display panel;

[0048] 120: Scan driver;

[0049] 130: Data drive;

[0050] 140: Controller;

[0051] DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM: Data cables;

[0052] SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM: Channels;

[0053] SCG1, SCG2, ..., SCGN: Channel groups. Detailed Implementation

[0054] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and repeated descriptions of the same constituent elements are omitted.

[0055] Figure 1 This is a block diagram illustrating the display device according to various embodiments of the present invention. Figure 2 This is a block diagram illustrating an example of a display panel included in a display device according to various embodiments of the present invention. Figure 3 This is a timing diagram illustrating an example of the first virtual data voltage output operation and the second virtual data voltage output operation of the data driver of the display device according to various embodiments of the present invention, for example.

[0056] Reference Figure 1 The display device 100 according to various embodiments of the present invention may include a display panel 110 having a plurality of pixels PX, a scan driver 120 providing scan signals SS to the plurality of pixels PX, a data driver 130 providing data voltage to the plurality of pixels PX, and a controller 140 controlling the scan driver 120 and the data driver 130.

[0057] Display panel 110 may include multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM, multiple scan lines, and multiple pixels PX connected to these lines. In one embodiment, each pixel PX may include at least two transistors, at least one capacitor, and an organic light-emitting diode (OLED), and display panel 110 may be an OLED display panel. In other embodiments, each pixel PX may include a switching transistor and a liquid crystal capacitor connected to the switching transistor, and display panel 110 may be a liquid crystal display (LCD) panel. However, display panel 110 is not limited to the LCD panel and the OLED display panel, and may be any display panel.

[0058] In one embodiment, such as Figure 2 As shown, the display panel 110 may further include: virtual pixels DPX, disposed in a first virtual region DUMR1, the first virtual region DUMR1 being located on the upper side of a display area DISPR disposed of a plurality of pixels PX; and virtual pixels DPX, disposed in a second virtual region DUMR2, the second virtual region DUMR2 being located on the lower side of the display area DISPR. The display panel 110 may further include virtual scan lines disposed in the first virtual region DUMR1 and the second virtual region DUMR2, and the virtual pixels DPX may be connected to a plurality of data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM and the virtual scan lines. In one embodiment, each virtual pixel DPX may have the same structure as the pixels PX of the display area DISPR. However, a light-shielding pattern (or black mask) may be disposed on the virtual pixels DPX, so that the image based on the virtual pixels DPX may not be recognized by the user. On the other hand, Figure 2 An example of a display panel 110 including virtual pixels (DPX) is shown, but the display panel 110 of the display device 100 according to various embodiments of the present invention is not limited to... Figure 2 For example, the display panel 110 may include virtual pixels (DPX) only in one of the upper and lower parts of the display area DISPR, or it may not include virtual pixels (DPX).

[0059] The scan driver 120 can generate a scan signal SS based on the scan control signal SCTRL received from the controller 140, and can provide the scan signal SS to a plurality of pixels PX (and / or virtual pixels DPX) through the plurality of scan lines (and / or the virtual scan lines). In one embodiment, the scan control signal SCTRL may include a scan start signal and a scan clock signal, but is not limited thereto. In one embodiment, the scan driver 120 may be formed or integrated in the peripheral area of ​​the display panel 110. In other embodiments, the scan driver 120 may be implemented by more than one scan integrated circuit (IC). Furthermore, according to embodiments, the scan driver 120 may be directly mounted on the display panel 110 in a COG (Chip On Glass) or COP (Chip On Plastic) form, or connected to the display panel 110 in a COF (Chip On Film) form via a flexible film.

[0060] Data driver 130 can receive output image data ODAT from controller 140, including multiple line data LDATs for rows of multiple pixels PX (and / or virtual pixels DPX), generate data voltages based on the output image data ODATs, and provide the data voltages to the multiple pixels PXs via multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM. Data driver 130 can receive analog power supply voltage AVDD from controller 140 or power management circuitry (e.g., a power management integrated circuit (PMIC)). Analog components of data driver 130 (e.g., output buffers) can operate based on the analog power supply voltage AVDD.

[0061] In one embodiment, a high-speed interface (e.g., a USI-T (Unified Standard Interface for TV) for transmitting output image data ODAT can be used between the controller 140 and the data driver 130. The output image data ODAT can be transmitted from the controller 140 to the data driver 130 in the form of a clock-embedded data signal defined under the standard of the high-speed interface. In one embodiment, the controller 140 can transmit clock training pattern data as output image data ODAT to the data driver 130 within a blanking interval, and the data driver 130 can train a clock signal within the data driver 130 based on the clock training pattern data. Furthermore, the controller 140 can notify the data driver 130 of the transmission of the clock training pattern data using a shared forward channel (SFC). In one embodiment, the data driver 130 can be implemented by multiple data driver ICs. Furthermore, in one embodiment, the shared forward channel (SFC) can be commonly connected to and shared by the multiple data driver ICs. According to embodiments, the plurality of data driver ICs can be directly mounted on the display panel 110 in a COG (Chip On Glass) or COP (Chip On Plastic) form, or connected to the display panel 110 in a COF (Chip On Film) form via a flexible film. In other embodiments, the data driver 130 can be implemented by a single data driver IC, or the data driver 130 and the controller 140 can be implemented by a single IC.

[0062] In one embodiment, the data driver 130 may include multiple channels SC11, SC1M, SC21, SC2M, SCN1, SCNM that provide the data voltage to multiple pixels PX (and / or virtual pixels DPX) via multiple data lines DL11, ..., DL1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM. Here, each channel SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM may represent more than one component of the data driver 130 for outputting a data voltage. Each channel SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM may include the output buffer for outputting the data voltage, and may also include, for example, a digital-to-analog converter, a latch, etc. In one embodiment, multiple channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM can output the data voltage to multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM in response to the clock signal of the data driver 130. In one embodiment, as... Figure 1 As shown, the number of channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM can be substantially the same as the number of data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM. In other embodiments, the number of channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM can be different from the number of data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM. For example, the ratio of the number of channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM to the number of data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM can be 1:2, 1:3, etc.

[0063] The controller (e.g., a timing controller (TCON)) 140 can receive input image data IDAT and control signals CTRL from an external main processor (e.g., an application processor (AP), a graphics processing unit (GPU), or a graphics card). In one embodiment, the input image data IDAT may be RGB image data including red image data, green image data, and blue image data. Furthermore, in one embodiment, the control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, a data strobe signal, a master clock signal, etc., but is not limited thereto. The controller 140 can generate output image data ODAT and a scan control signal SCTRL based on the input image data IDAT and the control signal CTRL. The controller 140 can provide the scan control signal SCTRL to the scan driver 120 to control the operation of the scan driver 120, and can provide the output image data ODAT to the data driver 130 to control the operation of the data driver 130.

[0064] Typically, the frame intervals of the display device 100 may include effective intervals that provide the data voltage to multiple pixels PX of the display area DISPR, and blank intervals (or vertical blank intervals) where the data voltage is not output to multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM, or where a black data voltage (or the minimum data voltage corresponding to the minimum gray level (e.g., 0-gray level)) is output. On the other hand, between the blank intervals where the data voltage is not output or where the black data voltage is output, and the effective intervals where the data voltage is output, the current within the display device 100 (e.g., the current flowing through the lines of the analog power supply voltage AVDD) may change drastically (increase or decrease). Due to this drastic current change, the components of the display device 100 (e.g., capacitors of the power management circuit, inductors of the power management circuit, control board with controller 140, source board with data driver 130, etc.) may vibrate, and noise may be generated in the display device 100 due to the vibration of these components.

[0065] However, in the display device 100 according to various embodiments of the present invention, in order to prevent the generation of the noise, the multiple channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM of the data driver 130 are grouped into a first channel group SCG1, a second channel group SCG2, ..., and an Nth channel group SCGN (N is an integer greater than 2). In the first blank interval before the effective interval, the first virtual data voltage output operation is sequentially started in the order of the first channel group SCG1 to the Nth channel group SCGN, and substantially simultaneously ends at the end of the first blank interval. In the second blank interval after the effective interval, the second virtual data voltage output operation is substantially simultaneously started, and sequentially ends in the order of the Nth channel group SCGN to the first channel group SCG1 in the second blank interval. On the other hand, Figure 1 An example is shown where each channel group (e.g., SCG1) comprises M channels (M is an integer) (e.g., SC11, ..., SC1M), but the number of channels in each channel group (e.g., SCG1) (e.g., SC11, ..., SC1M) can be more than one arbitrary integer number. For example, any two channel groups (e.g., SCG1, SCG2) can include different numbers of channels from each other.

[0066] For example, such as Figure 3 As shown, each frame interval FP of the display device 100 may include an effective interval AP and a blank interval BP2. Within the effective interval AP, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can substantially simultaneously perform an effective data voltage output operation AOP, providing the data voltage (or the effective data voltage corresponding to the output image data ODAT) to multiple pixels PX of the display area DISPR via multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM. Within the effective interval AP, the multiple pixels PX of the display area DISPR can display an image based on the data voltage.

[0067] In one embodiment, such as Figure 3As shown, each blank interval BP1, BP2 may include a second virtual region interval DUMP2 allocated to the second virtual region DUMR2 located below the display area DISPR, a clock training interval CKTP for performing clock training operations, and a first virtual region interval DUMP1 allocated to the first virtual region DUMR1 located above the display area DISPR. In the clock training interval CKTP, the controller 140 may transmit the clock training pattern data to the data driver 130, changing the shared forward channel SFC to a low level, thereby notifying the data driver 130 of the transmission of the clock training pattern data. The data driver 130 may train the clock signal based on the clock training pattern data.

[0068] In the first virtual region DUMP1 of the first blank interval BP1 before the effective interval AP, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can perform a first virtual data voltage output operation DOP1, which provides virtual data voltage to the virtual pixel DPX configured in the first virtual region DUMR1 via multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM. Specifically, in the first virtual region DUMP1 of the first blank interval BP1 before the effective interval AP, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can sequentially begin the first virtual data voltage output operation DOP1 in the order of the first channel group SCG1 to the Nth channel group SCGN. For example, in the first virtual region DUMP1, as... Figure 3As shown, the first channel group SCG1 begins the first virtual data voltage output operation DOP1, which outputs the virtual data voltage to data lines DL11, ..., DL1M. Then, the second channel group SCG2 begins the first virtual data voltage output operation DOP1, which outputs the virtual data voltage to data lines DL21, ..., DL2M. In this way, the Nth channel group SCGN can perform the first virtual data voltage output operation DOP1, which outputs the virtual data voltage to data lines DLN1, ..., DLNM, at the very end. Furthermore, the first channel group SCG1, the second channel group SCG2, ..., and the Nth channel group SCGN can substantially simultaneously end the first virtual data voltage output operation DOP1 at the end time of the first blank interval BP1 or the end time of the first virtual region interval DUMP1. As described above, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN are driven sequentially in the first virtual region interval DUMP1 according to the order of the first channel group SCG1 to the Nth channel group SCGN. Therefore, the current in the display device 100 (e.g., the current flowing through the line of the analog power supply voltage AVDD) can be gradually increased in the first virtual region interval DUMP1. This prevents the generation of noise caused by the sudden increase of the current. Furthermore, in the first virtual region interval DUMP1, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN are driven sequentially, so power consumption can be reduced compared to the case where multiple channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM are driven in each blank interval BP1, BP2.

[0069] Furthermore, in the second virtual region interval DUMP2 of the second blank interval BP2 following the effective interval AP, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can perform a second virtual data voltage output operation DOP2, providing the virtual data voltage to the virtual pixel DPX configured in the second virtual region DUMR2 via multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM. The first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can substantially start the second virtual data voltage output operation DOP2 simultaneously at the start time of the second blank interval BP2 or the start time of the second virtual region interval DUMP2. In particular, in the second virtual region interval DUMP2 of the second blank interval BP2 following the effective interval AP, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can sequentially end the second virtual data voltage output operation DOP2 in the order from the Nth channel group SCGN to the first channel group SCG1. For example, in the second virtual region interval DUMP2, such as Figure 3 As shown, the Nth channel group SCGN can be the first to end the second virtual data voltage output operation DOP2, which outputs the virtual data voltage to data lines DLN1, ..., DLNM. Then, the subsequent channel groups (i.e., the (N-1)th channel group) end the second virtual data voltage output operation DOP2. In this way, the second channel group SCG2 can end the second virtual data voltage output operation DOP2, which outputs the virtual data voltage to data lines DL21, ..., DL2M, and then the first channel group SCG1 can end the second virtual data voltage output operation DOP2, which outputs the virtual data voltage to data lines DL11, ..., DL1M. As described above, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN sequentially end the second virtual data voltage output operation DOP2 in the second virtual region interval DUMP2 in the order from the Nth channel group SCGN to the first channel group SCG1. Therefore, the current within the display device 100 (e.g., the current flowing through the line of the analog power supply voltage AVDD) can gradually decrease in the second virtual region interval DUMP2. This prevents the generation of noise caused by the sharp decrease in current. Furthermore, since the driving of the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN is sequentially terminated in the second virtual region interval DUMP2, power consumption can be reduced compared to the case where multiple channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM are driven in each blank interval BP1, BP2.

[0070] The data driver 130 can be controlled by the controller 140 or utilize the clock signal of the data driver 130 to cause the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN to sequentially start the first virtual data voltage output operation in the first blank interval BP1 before the effective interval AP in the order of the first channel group SCG1 to the Nth channel group SCGN, and to sequentially end the second virtual data voltage output operation in the second blank interval BP2 after the effective interval AP in the order of the Nth channel group SCGN to the first channel group SCG1.

[0071] In one embodiment, such as Figures 7 to 9 As shown, the controller 140 can use the pixel data in the line data LDAT within the first blank interval BP1 to control the first virtual data voltage output operation of the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN, and can use the pixel data in the line data LDAT within the second blank interval BP2 to control the second virtual data voltage output operation of the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN.

[0072] In other embodiments, such as Figure 10 and Figure 11 As shown, the controller 140 can use the constituent data in the line data LDAT within the first blank interval BP1 to control the first virtual data voltage output operation of the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN, and can use the constituent data in the line data LDAT within the second blank interval BP2 to control the second virtual data voltage output operation of the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN.

[0073] In yet another embodiment, such as Figure 12 and Figure 13 As shown, the data driver 130 may include a counter for counting the clock signal. The first virtual data voltage output operations of the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN within the first blank interval BP1, and the second virtual data voltage output operations of the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN within the second blank interval BP2, can be controlled based on the counted clock signal.

[0074] As described above, in the display device 100 according to various embodiments of the present invention, the multiple channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM of the data driver 130 can be grouped into a first channel group SCG1, a second channel group SCG2, ..., and an Nth channel group SCGN. In the first blank interval BP1 before the effective interval AP, the first virtual data voltage output operation of the first channel group SCG1, the second channel group SCG2, ..., and the Nth channel group SCGN is started sequentially in the order of the first channel group SCG1 to the Nth channel group SCGN. In the second blank interval BP2 after the effective interval AP, the second virtual data voltage output operation of the first channel group SCG1, the second channel group SCG2, ..., and the Nth channel group SCGN is ended sequentially in the order of the Nth channel group SCGN to the first channel group SCG1. Therefore, in the first blank interval BP1 before the effective interval AP, the current in the display device 100 gradually increases, and in the second blank interval BP2 after the effective interval AP, the current in the display device 100 gradually decreases, thus preventing the generation of noise caused by the abrupt change in current. Furthermore, in each blank interval BP1, BP2, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN are driven sequentially, thus reducing power consumption compared to the case where multiple channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM are driven in each blank interval BP1, BP2.

[0075] Figure 4 This is a timing diagram illustrating an example of the first virtual data voltage output operation and the second virtual data voltage output operation of the first channel group to the Nth channel group of the data driver of a display device according to an embodiment of the present invention.

[0076] Reference Figure 1 and Figure 4In the display device 100 according to various embodiments of the present invention, the multiple channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM of the data driver 130 can be grouped into a first channel group SCG1, a second channel group SCG2, ..., and an Nth channel group SCGN. The first virtual region interval DUMP1 of the first blank interval BP1 before the effective interval AP of the first channel group SCG1, the second channel group SCG2, ..., and the Nth channel group SCGN is sequentially sent to the multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ... in the order of the first channel group SCG1 to the Nth channel group SCGN. The first virtual data voltage output operation of DLNM outputs virtual data voltage. At the end time of the first virtual region interval DUMP1, the first virtual data voltage output operation essentially ends simultaneously. And at the start time of the second virtual region interval DUMP2, which is the second blank interval BP2 after the effective interval AP, the second virtual data voltage output operation, which outputs the virtual data voltage to multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM, essentially begins simultaneously. In the second virtual region interval DUMP2, the second virtual data voltage output operation ends sequentially in the order from the Nth channel group SCGN to the first channel group SCG1. Figure 4 In this context, SFC can represent a common forward channel used by the controller 140 to notify the data driver 130 of the clock training pattern data transmission, and CLK can represent the clock signal of the data driver 130. Multiple channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM of the data driver 130 can output the virtual data voltage or valid data voltage for a pixel row to multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM in response to each pulse of the clock signal CLK.

[0077] In one embodiment, such as Figure 4As shown, the first virtual region interval DUMP1 of the first blank interval BP1 before the effective interval AP can be divided (e.g., equally divided) into the first sub-interval SP11, the second sub-interval SP12, ..., the Nth sub-interval SP1N. The first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can start the first virtual data voltage output operation at the start time of the first sub-interval SP11, the second sub-interval SP12, ..., the Nth sub-interval SP1N of the first virtual region interval DUMP1, respectively. That is, the first channel group SCG1 can start the first virtual data voltage output operation at the start time of the first sub-interval SP11 of the first virtual region interval DUMP1, the second channel group SCG2 can start the first virtual data voltage output operation at the start time of the second sub-interval SP12 of the first virtual region interval DUMP1, and in this way, the Nth channel group SCGN can start the first virtual data voltage output operation at the start time of the Nth sub-interval SP1N of the first virtual region interval DUMP1. In addition, as Figure 4 As shown, the first virtual data voltage output operation can be an operation in which the maximum data voltage MDV and the black data voltage BDV are alternately output to the virtual pixels DPX in the first virtual area DUMR1 located above the display area DISPR of the display panel 110. For example, the maximum data voltage MDV can be the data voltage corresponding to the maximum gray level (e.g., 255-gray level), and the black data voltage BDV can be the data voltage corresponding to the minimum gray level (e.g., 0-gray level), but it is not limited to this. As described above, since the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN start the first virtual data voltage output operation sequentially in the first virtual area interval DUMP1 according to the order of the first channel group SCG1 to the Nth channel group SCGN, therefore, Figure 4 As shown, the current AVDDC flowing through the simulated power supply voltage AVDD can be gradually increased. This prevents the generation of noise caused by a sharp increase in current AVDDC. Furthermore, since the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN are driven sequentially in the first virtual region DUMP1, power consumption can be reduced compared to the case where multiple channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM are driven in each blank region BP1, BP2.

[0078] In addition, such as Figure 4As shown, the second virtual region interval DUMP2, the second blank interval BP2 following the effective interval AP, can be divided (e.g., equally divided) into the first sub-interval SP21, ..., the (N-1)th sub-interval SP2N-1, and the Nth sub-interval SP2N. The first channel group SCG1, the second channel group SCG2, ..., and the Nth channel group SCGN can respectively end the second virtual data voltage output operation at the end time of the Nth sub-interval SP2N, the (N-1)th sub-interval SP2N-1, ..., and the first sub-interval SP21 of the second virtual region interval DUMP2. That is, the Nth channel group SCGN can end the second virtual data voltage output operation at the end time of the first sub-interval SP21 of the second virtual region interval DUMP2, the second channel group SCG2 can end the second virtual data voltage output operation at the end time of the (N-1)th sub-interval SP2N-1 of the second virtual region interval DUMP2, and the first channel group SCG1 can end the second virtual data voltage output operation at the end time of the Nth sub-interval SP2N of the second virtual region interval DUMP2. Furthermore, as Figure 4 As shown, the second virtual data voltage output operation can be an operation in which the maximum data voltage MDV and the black data voltage BDV are alternately output to the virtual pixel DPX in the second virtual area DUMR2 located below the display area DISPR of the display panel 110 as the virtual data voltage. As described above, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN sequentially end the second virtual data voltage output operation in the second virtual area interval DUMP2 in the order from the Nth channel group SCGN to the first channel group SCG1. Therefore, as Figure 4 As shown, the current AVDDC flowing through the simulated power supply voltage AVDD can be gradually reduced. This prevents the generation of noise caused by a sharp decrease in current AVDDC. Furthermore, since the driving of the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN sequentially ends in the second virtual region interval DUMP2, power consumption can be reduced compared to the case where multiple channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM are driven in each blank interval BP1, BP2.

[0079] Figure 5 This is a timing diagram illustrating an example of the first virtual data voltage output operation and the second virtual data voltage output operation of the first channel group to the Nth channel group of the data driver of the display device according to other embodiments of the present invention.

[0080] Figure 5The operations of the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN shown can be performed in addition to the virtual data voltage output by the first virtual data voltage output operation in the first virtual region interval DUMP1 including a progressively increasing data voltage and the virtual data voltage output by the second virtual data voltage output operation in the second virtual region interval DUMP2 including a progressively decreasing data voltage, except that they can be performed in conjunction with... Figure 4 The operation of the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN is similar.

[0081] Reference Figure 1 and Figure 5 The first virtual data voltage output operation within the first virtual region interval DUMP1 can be an operation in which progressively increasing data voltages and black data voltages (BDVs) are alternately output to virtual pixels DPX in the first virtual region DUMR1, which is configured above the display region DISPR on the display panel 110, as the virtual data voltages. For example, as Figure 5 As shown, the virtual data voltage output from the first channel group SCG1 can progressively increase from the black data voltage BDV to the maximum data voltage MDV in the first sub-interval SP11 of the first virtual region interval DUMP1; the virtual data voltage output from the second channel group SCG2 can progressively increase from the black data voltage BDV to the maximum data voltage MDV in the second sub-interval SP12 of the first virtual region interval DUMP1; and the virtual data voltage output from the Nth channel group SCGN can progressively increase from the black data voltage BDV to the maximum data voltage MDV in the Nth sub-interval SP1N of the first virtual region interval DUMP1. Thus, in the first virtual region interval DUMP1, the current AVDDC flowing through the simulated power supply voltage AVDD can increase progressively (e.g., linearly).

[0082] Furthermore, the second virtual data voltage output operation within the second virtual region interval DUMP2 can be an operation in which progressively decreasing data voltages and black data voltages (BDVs) are alternately output to virtual pixels DPX in the second virtual region DUMR2, which is located below the display region DISPR of the display panel 110, as the virtual data voltages. For example, as... Figure 5As shown, the virtual data voltage output from the Nth channel group SCGN can gradually decrease from the maximum data voltage MDV to the black data voltage BDV in the first sub-interval SP21 of the second virtual region interval DUMP2; the virtual data voltage output from the second channel group SCG2 can gradually decrease from the maximum data voltage MDV to the black data voltage BDV in the (N-1)th sub-interval SP2N-1 of the second virtual region interval DUMP2; and the virtual data voltage output from the first channel group SCG1 can gradually decrease from the maximum data voltage MDV to the black data voltage BDV in the Nth sub-interval SP2N of the second virtual region interval DUMP2. Therefore, in the second virtual region interval DUMP2, the current AVDDC flowing through the simulated power supply voltage AVDD can gradually (e.g., linearly) decrease.

[0083] Figure 6 This is a sequence diagram illustrating the driving methods of the display device according to various embodiments of the present invention.

[0084] Reference Figure 1 and Figure 6 In the driving method of the display device 100 according to various embodiments of the present invention, the multiple channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM of the data driver 130 can be grouped into a first channel group SCG1, a second channel group SCG2, ..., and an Nth channel group SCGN (S210).

[0085] The first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can sequentially begin a first virtual data voltage output operation (S230) in a first blank interval before the effective interval, outputting virtual data voltages to multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM in the order of the first channel group SCG1 to the Nth channel group SCGN. In one embodiment, the first blank interval may include a first virtual region interval that outputs virtual data voltages to virtual pixels DPX configured in the first virtual region DUMR1 located above the display region DISPR. The first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can sequentially begin the first virtual data voltage output operation in the first virtual region interval in the order of the first channel group SCG1 to the Nth channel group SCGN. Furthermore, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can substantially simultaneously end the first virtual data voltage output operation at the end time point of the first blank interval. Therefore, in the first blank area, the current in the display device 100 can be gradually increased.

[0086] The first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can perform an effective data voltage output operation (S250) within the effective range, providing data voltages to multiple pixels PX of the display area DISPR of the display panel 110 via multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM. Within the effective range, the multiple pixels PX can display an image based on the data voltage.

[0087] The first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can substantially simultaneously begin a second virtual data voltage output operation, outputting the virtual data voltage to multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM, at the start time of the second blank interval following the effective interval. During the second blank interval, the second virtual data voltage output operation can be sequentially terminated in the order from the Nth channel group SCGN to the first channel group SCG1 (S270). In one embodiment, the second blank interval may include a second virtual region interval that outputs virtual data voltage to virtual pixels DPX located in the second virtual region DUMR2 situated below the display region DISPR. The first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can sequentially terminate the second virtual data voltage output operation during the second virtual region interval in the order from the Nth channel group SCGN to the first channel group SCG1. Therefore, during the second blank interval, the current within the display device 100 can gradually decrease.

[0088] Figure 7 This is a sequence diagram illustrating a driving method for a display device according to an embodiment of the present invention. Figure 8 This is a diagram illustrating an example of line data supplied from the controller to the data driver. Figure 9 This is a diagram illustrating an example of frame data including line data used to control the first channel group to the Nth channel group in order to perform a first virtual data voltage output operation and a second virtual data voltage output operation.

[0089] Reference Figure 1 and Figure 7 In a driving method of a display device 100 according to an embodiment of the present invention, a plurality of channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM of the data driver 130 can be grouped into a first channel group SCG1, a second channel group SCG2, ..., and an Nth channel group SCGN (S310).

[0090] In the first blank interval before the effective interval, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can be controlled by the pixel data of the line data LDAT, so that the first virtual data voltage output operation starts sequentially in the order of the first channel group SCG1 to the Nth channel group SCGN (S330). In one embodiment, as... Figure 8 As shown, the line data LDAT for each pixel row may include line start data SOLD indicating the start of the line data LDAT, composition data CFGD indicating composition information, pixel data PXD for the multiple pixels PX (or virtual pixels DPX) included in the pixel row, and horizontal blanking interval data HBPD corresponding to the horizontal blanking interval. The first virtual data voltage output operation of the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can be controlled by the pixel data PXD of the line data LDAT.

[0091] Figure 9 The output image data ODAT transmitted from controller 140 to data driver 130 discloses frame data FRMD corresponding to a frame interval. Frame data FRMD may include clock training pattern data CTPD for clock training operations and multiple line data LDAT relating to pixel rows (rows of virtual pixels DPX and rows of multiple pixels PX) of display panel 110. The line data LDAT of frame data FRMD may include first virtual line data DLD1 relating to pixel rows (rows of virtual pixels DPX) of first virtual area DUMR1 of display panel 110, valid line data ALD relating to pixel rows (rows of multiple pixels PX) of display area DISPR of display panel 110, and second virtual line data DLD2 relating to pixel rows (rows of virtual pixels DPX) of second virtual area DUMR2 of display panel 110.

[0092] In the first blank interval before the effective interval, the controller 140 can use the pixel data PXD of the first virtual line data DLD1 with respect to the first virtual region DUMR1 to cause the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN to start the first virtual data voltage output operation sequentially in the order of the first channel group SCG1 to the Nth channel group SCGN. For example, as Figure 9As shown, for the first pixel row of the first virtual region DUMR1, in order to enable the first channel group SCG1 to perform the first virtual data voltage output operation while the Nth channel group SCGN does not perform the first virtual data voltage output operation, the controller 140 can transmit the maximum pixel data MPXD representing the maximum grayscale as the pixel data PXD_SCG1 for the first channel group SCG1, and transmit the black pixel data BPXD representing the minimum grayscale or black grayscale as the pixel data PXD_SCGN for the Nth channel group SCGN. For subsequent pixel rows of the first virtual region DUMR1, the number of maximum pixel data MPXDs included in the pixel data PXD of each first virtual line data DLD1 can be progressively increased, and the number of black pixel data BPXDs included in the pixel data PXD of each first virtual line data DLD1 can be progressively decreased. For the last pixel row of the first virtual region DUMR1, in order for the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN to all perform the first virtual data voltage output operation, the controller 140 can transmit the first virtual line data DLD1, which includes only the maximum pixel data MPXD, to the data driver 130. In response to this first virtual line data DLD1, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can sequentially begin the first virtual data voltage output operation in the first blank interval in the order of the first channel group SCG1 to the Nth channel group SCGN.

[0093] During the effective interval, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can perform an effective data voltage output operation (S350) to provide data voltage to multiple pixels PX of the display area DISPR of the display panel 110 through multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM.

[0094] In the second blank interval following the effective interval, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can be controlled by the pixel data of the line data LDAT, so that the second virtual data voltage output operation is completed sequentially from the Nth channel group SCGN to the first channel group SCG1 (S370). In the second blank interval following the effective interval, the controller 140 can use the pixel data PXD of the second virtual line data DLD2 with respect to the second virtual region DUMR2, so that the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN are completed sequentially from the Nth channel group SCGN to the first channel group SCG1.

[0095] For example, such as Figure 9 As shown, for the first pixel row of the second virtual region DUMR2, in order for the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN to all perform the second virtual data voltage output operation, the controller 140 can transmit the second virtual line data DLD2, which only includes the maximum pixel data MPXD, to the data driver 130. For subsequent pixel rows of the second virtual region DUMR2, the number of maximum pixel data MPXDs included in the pixel data PXD of each second virtual line data DLD2 can be progressively reduced, and the number of black pixel data BPXDs included in the pixel data PXD of each second virtual line data DLD2 can be progressively reduced. For the last pixel row of the second virtual region DUMR2, in order to enable the first channel group SCG1 to perform the second virtual data voltage output operation while the Nth channel group SCGN does not perform the second virtual data voltage output operation, the controller 140 can transmit the maximum pixel data MPXD as the pixel data PXD_SCG1 for the first channel group SCG1, and transmit the black pixel data BPXD as the pixel data PXD_SCGN for the Nth channel group SCGN, to the data driver 130. In response to this second virtual line data DLD2, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can sequentially end the second virtual data voltage output operation in the second blank interval in the order from the Nth channel group SCGN to the first channel group SCG1.

[0096] Figure 10 This is a sequence diagram illustrating the driving method of a display device according to other embodiments of the present invention. Figure 11 This is a diagram illustrating an example of line data used to control the first to Nth channel groups in order to perform a first virtual data voltage output operation and a second virtual data voltage output operation.

[0097] Reference Figure 1 and Figure 10 In the driving method of the display device 100 in other embodiments of the present invention, the multiple channels SC11, ..., SC1M, SC21, ..., SC2M, ..., SCN1, ..., SCNM of the data driver 130 can be grouped into a first channel group SCG1, a second channel group SCG2, ..., and an Nth channel group SCGN (S410).

[0098] In the first blank interval before the effective interval, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can be controlled by the configuration data of the line data LDAT, so that the first virtual data voltage output operation starts sequentially in the order of the first channel group SCG1 to the Nth channel group SCGN (S430). In one embodiment, as... Figure 11As shown, the constituent data CFGD of the line data LDAT may include first channel group operation data SCG1D, second channel group operation data SCG2D, ..., Nth channel group operation data SCGND, indicating whether the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN execute the first virtual data voltage output operation. In response to the first channel group operation data SCG1D, the second channel group operation data SCG2D, ..., the Nth channel group operation data SCGND, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN may sequentially start the first virtual data voltage output operation in the first blank interval, according to the order of the first channel group SCG1 to the Nth channel group SCGN.

[0099] During the effective interval, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can perform an effective data voltage output operation (S450) to provide data voltage to multiple pixels PX of the display area DISPR of the display panel 110 through multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM.

[0100] In the second blank interval following the effective interval, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can be controlled by the configuration data of the line data LDAT, so that the second virtual data voltage output operation is completed sequentially in the order of the Nth channel group SCGN to the first channel group SCG1 (S470). In one embodiment, as... Figure 11 As shown, the constituent data CFGD of the line data LDAT may include the first channel group operation data SCG1D, the second channel group operation data SCG2D, ..., the Nth channel group operation data SCGND. The first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can, in response to the first channel group operation data SCG1D, the second channel group operation data SCG2D, ..., the Nth channel group operation data SCGND, sequentially end the second virtual data voltage output operation in the order from the Nth channel group SCGN to the first channel group SCG1 during the second blanking interval.

[0101] Figure 12 This is a sequence diagram illustrating a driving method for a display device according to another embodiment of the present invention. Figure 13 This is a block diagram illustrating an example of a data driver that includes a counter that counts clock signals.

[0102] Reference Figure 1 , Figure 12 and Figure 13In another embodiment of the present invention, the driving method of the display device 100 can be grouped into a first channel group SCG1, a second channel group SCG2, ..., and an Nth channel group SCGN (S510).

[0103] In the first virtual region interval within the first blank interval before the effective interval, the clock signal of the data driver 600 can be counted (S520), and based on the counted clock signal, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN are controlled, such that the first virtual data voltage output operation is started sequentially in the order of the first channel group SCG1 to the Nth channel group SCGN (S530). To perform this operation, in one embodiment, as... Figure 13 As shown, the data driver 600 may include a counter 610 that counts a clock signal CLK to generate a count signal SCNT, and a control unit 630 that controls the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN in response to the count signal SCNT. For example, in order to sequentially start the first virtual data voltage output operation of the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN, the control unit 630 controls the first channel group SCG1 to start the first virtual data voltage output operation when the count signal SCNT reaches the first reference count value RCNT1, and controls the Nth channel group SCGN to start the first virtual data voltage output operation when the count signal SCNT reaches the Nth reference count value RCNTN.

[0104] During the effective interval, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN can perform an effective data voltage output operation (S550) to provide data voltage to multiple pixels PX of the display area DISPR of the display panel 110 through multiple data lines DL11, ..., DL1M, DL21, ..., DL2M, ..., DLN1, ..., DLNM.

[0105] In the second virtual region interval within the second blank interval following the effective interval, the clock signal of the data driver 600 can be counted (S560), and based on the counted clock signal, the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN are controlled, so that the second virtual data voltage output operation is completed sequentially in the order of the Nth channel group SCGN to the first channel group SCG1 (S570). Figure 13In the example, in order to sequentially end the second virtual data voltage output operation of the first channel group SCG1, the second channel group SCG2, ..., the Nth channel group SCGN, the control unit 630 can control the Nth channel group SCGN to end the second virtual data voltage output operation when the counting signal SCNT reaches the first reference count value RCNT1, and control the first channel group SCG1 to end the second virtual data voltage output operation when the counting signal SCNT reaches the Nth reference count value RCNTN.

[0106] Figure 14 This is a block diagram illustrating an electronic device including a display device according to various embodiments of the present invention.

[0107] Reference Figure 14 Electronic device 1100 may include processor 1110, storage device 1120, storage device 1130, input / output device 1140, power supply 1150, and display device 1160. Electronic device 1100 may communicate with graphics card, sound card, memory card, USB device, etc., or may also include various ports that can communicate with other systems.

[0108] Processor 1110 can perform specific calculations or tasks. According to embodiments, processor 1110 can be a microprocessor, central processing unit (CPU), etc. Processor 1110 can be connected to other components via address bus, control bus, and data bus, etc. According to embodiments, processor 1110 can also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0109] Storage device 1120 can store data required for the operation of electronic device 1100. For example, storage device 1120 may include non-volatile storage devices such as EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), Flash Memory, PRAM (Phase Change Random Access Memory), RRAM (Resistance Random Access Memory), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), MRAM (Magnetic Random Access Memory), FRAM (Ferroelectric Random Access Memory) and / or volatile storage devices such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and mobile DRAM.

[0110] Storage device 1130 may include solid-state drives (SSDs), hard disk drives (HDDs), CD-ROMs, etc. Input / output devices 1140 may include input components such as keyboards, keypads, touchpads, touchscreens, mice, etc., and output components such as speakers, printers, etc. Power supply 1150 provides the power required for the operation of electronic device 1100. Display device 1160 can be connected to other components via the aforementioned bus or other communication links.

[0111] In the display device 1160, multiple channels of the data driver are grouped into a first channel group to a Nth channel group. In a first blank interval before the effective interval, a first virtual data voltage output operation is sequentially initiated from the first channel group to the Nth channel group. In a second blank interval after the effective interval, a second virtual data voltage output operation is sequentially terminated from the Nth channel group to the first channel group. Therefore, in the first blank interval before the effective interval, the current in the display device 1160 can gradually increase, and in the second blank interval after the effective interval, the current in the display device 1160 can gradually decrease, thus preventing noise caused by abrupt changes in current. Furthermore, since the first channel group to the Nth channel group are driven sequentially in each blank interval, power consumption can be reduced compared to the case where all channels are driven in each blank interval.

[0112] According to the embodiments, the electronic device 1100 may be any electronic device including the display device 1160, such as a digital television (Digital Television), 3D TV, personal computer (PC), home electronic device, laptop computer, tablet computer, mobile phone, smartphone, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, music player, portable game console, navigation device, etc.

[0113] (Industry availability)

[0114] This invention is applicable to any display device and electronic device including it. For example, this invention is applicable to any electronic device including a display device such as a TV, digital TV, 3D TV, mobile phone, smartphone, tablet computer, laptop computer, personal computer (PC), home electronic device, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, music player, portable game console, navigator, etc.

[0115] The present invention has been described above with reference to various embodiments thereof. However, those skilled in the art should understand that various modifications and alterations can be made to the present invention without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display device, characterized in that, include: The display panel includes multiple data lines and multiple pixels connected to the multiple data lines; A data driver includes multiple channels that provide data voltages to the multiple pixels via the multiple data lines; as well as The controller controls the data driver. The display panel further includes virtual pixels, configured in a first virtual region and a second virtual region. The first virtual region is located above the display area configured with the plurality of pixels, and the second virtual region is located below the display area configured with the plurality of pixels. The image based on the virtual pixels is obscured. The multiple channels are grouped into channel group 1 through channel group N, where N is an integer greater than or equal to 2. In the first blank interval before the effective interval, from the first channel group to the Nth channel group, a first virtual data voltage output operation is sequentially initiated to supply virtual data voltage to the virtual pixels of the first virtual region, in the order from the first channel group to the Nth channel group. In the second blank interval following the effective interval, from the first channel group to the Nth channel group, the second virtual data voltage output operation of supplying virtual data voltage to the virtual pixels of the second virtual region is completed sequentially in the order from the Nth channel group to the first channel group.

2. The display device according to claim 1, characterized in that, The first virtual data voltage output operation is simultaneously terminated at the end time point of the first blank interval for the first channel group to the Nth channel group. The first channel group to the Nth channel group simultaneously begin the second virtual data voltage output operation at the start time point of the second blank interval.

3. The display device according to claim 1, characterized in that, The first blank interval includes a first virtual region interval that outputs virtual data voltages to the virtual pixels configured in the first virtual region. Within the first virtual region, the first virtual data voltage output operation is started sequentially from the first channel group to the Nth channel group.

4. The display device according to claim 3, characterized in that, The first virtual region interval is divided into the first sub-interval to the Nth sub-interval. The first channel group to the Nth channel group each start the first virtual data voltage output operation at the start time point of the first sub-interval to the Nth sub-interval, respectively.

5. The display device according to claim 3, characterized in that, The first virtual data voltage output operation is an operation that alternately outputs the maximum data voltage and the black data voltage to the virtual pixel as the virtual data voltage.

6. The display device according to claim 3, characterized in that, The first virtual data voltage output operation is an operation that alternately outputs progressively increasing data voltage and black data voltage to the virtual pixel as the virtual data voltage.

7. The display device according to claim 1, characterized in that, The second blank interval includes a second virtual region interval that outputs virtual data voltage to the virtual pixels configured in the second virtual region. In the second virtual region, from the first channel group to the Nth channel group, the second virtual data voltage output operation is completed sequentially according to the order from the Nth channel group to the first channel group.

8. The display device according to claim 7, characterized in that, The second virtual region is divided into the first sub-interval to the Nth sub-interval. The first channel group to the Nth channel group respectively end the second virtual data voltage output operation at the end time point from the Nth sub-interval to the first sub-interval.

9. The display device according to claim 7, characterized in that, The second virtual data voltage output operation is an operation that alternately outputs the maximum data voltage and the black data voltage to the virtual pixel as the virtual data voltage.

10. The display device according to claim 7, characterized in that, The second virtual data voltage output operation is an operation that alternately outputs progressively decreasing data voltage and black data voltage to the virtual pixel as the virtual data voltage.

11. The display device according to claim 1, characterized in that, The controller transmits line data for each pixel row to the data driver. The line data includes line start data indicating the start of the line data, composition data indicating composition information, pixel data about the plurality of pixels included in each pixel row, and horizontal blanking interval data corresponding to the horizontal blanking interval. The first virtual data voltage output operation of the first channel group to the Nth channel group within the first blank interval is controlled by the pixel data of the line data within the first blank interval. The second virtual data voltage output operation of the first channel group to the Nth channel group within the second blank interval is controlled by the pixel data of the line data within the second blank interval.

12. The display device according to claim 1, characterized in that, The controller transmits line data for each pixel row to the data driver. The line data includes line start data indicating the start of the line data, composition data indicating composition information, pixel data about the plurality of pixels included in each pixel row, and horizontal blanking interval data corresponding to the horizontal blanking interval. The first virtual data voltage output operation of the first channel group to the Nth channel group within the first blank interval is controlled by the constituent data of the line data within the first blank interval. The second virtual data voltage output operation of the first channel group to the Nth channel group within the second blank interval is controlled by the constituent data of the line data within the second blank interval.

13. The display device according to claim 1, characterized in that, The data driver includes a counter for counting clock signals. The first virtual data voltage output operation of the first channel group to the Nth channel group in the first blank interval and the second virtual data voltage output operation of the first channel group to the Nth channel group in the second blank interval are controlled based on the counted clock signal.

14. A driving method for a display device, wherein, The display panel of the display device includes: a plurality of pixels disposed in a display area; and virtual pixels disposed in a first virtual area and a second virtual area, wherein the first virtual area is located at the upper part of the display area and the second virtual area is located at the lower part of the display area, and an image based on the virtual pixels is occluded, the driving method including: The step of grouping multiple channels of the data driver of the display device into a first channel group to a Nth channel group, wherein N is an integer greater than or equal to 2; In the first blank interval before the effective interval, the first virtual data voltage output operation of supplying virtual data voltage to the virtual pixels of the first virtual region is started sequentially in the order of the first channel group to the Nth channel group; The steps of performing valid data voltage output operations from the first channel group to the Nth channel group within the effective interval; and In the second blank interval following the effective interval, the steps of supplying virtual data voltage to the virtual pixels of the second virtual region in the order of the Nth channel group to the first channel group are completed sequentially.

15. The driving method for the display device according to claim 14, characterized in that, Also includes: At the end of the first blank interval, the first virtual data voltage output operation of the first channel group to the Nth channel group is simultaneously terminated; as well as At the beginning of the second blank interval, the second virtual data voltage output operation of the first channel group to the Nth channel group is started simultaneously.

16. The driving method for the display device according to claim 14, characterized in that, The first blank interval includes a first virtual region interval that outputs virtual data voltages to the virtual pixels configured in the first virtual region. The first channel group to the Nth channel group sequentially begin the first virtual data voltage output operation in the first virtual region according to the order of the first channel group to the Nth channel group.

17. The driving method for the display device according to claim 14, characterized in that, The second blank interval includes a second virtual region interval that outputs virtual data voltage to the virtual pixels configured in the second virtual region. The first channel group to the Nth channel group sequentially terminate the second virtual data voltage output operation in the second virtual region according to the order from the Nth channel group to the first channel group.

18. The driving method for a display device according to claim 14, characterized in that, The controller of the display device transmits line data about each pixel row to the data driver. The line data includes line start data indicating the start of the line data, composition data indicating composition information, pixel data about the multiple pixels included in each pixel row, and horizontal blanking interval data corresponding to the horizontal blanking interval. The first virtual data voltage output operation of the first channel group to the Nth channel group within the first blank interval is controlled by the pixel data of the line data within the first blank interval. The second virtual data voltage output operation of the first channel group to the Nth channel group within the second blank interval is controlled by the pixel data of the line data within the second blank interval.

19. The driving method for a display device according to claim 14, characterized in that, The controller of the display device transmits line data about each pixel row to the data driver. The line data includes line start data indicating the start of the line data, composition data indicating composition information, pixel data about the multiple pixels included in each pixel row, and horizontal blanking interval data corresponding to the horizontal blanking interval. The first virtual data voltage output operation of the first channel group to the Nth channel group within the first blank interval is controlled by the constituent data of the line data within the first blank interval. The second virtual data voltage output operation of the first channel group to the Nth channel group within the second blank interval is controlled by the constituent data of the line data within the second blank interval.

20. The driving method for a display device according to claim 14, characterized in that, The data driver includes a counter for counting clock signals. The first virtual data voltage output operation of the first channel group to the Nth channel group in the first blank interval and the second virtual data voltage output operation of the first channel group to the Nth channel group in the second blank interval are controlled based on the counted clock signal.

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