Semiconductor memory device

Abstract

The present disclosure relates to a semiconductor memory device including: a memory cell array disposed in a first semiconductor layer and including a plurality of cell portions and at least two via regions arranged in a second direction intersecting a first direction, wherein a width of each of the via regions in the second direction has a size corresponding to a multiple of a width of each of the plurality of cell portions in the second direction.

Description

Technical Field

[0001] The various embodiments generally relate to semiconductor technology, and more specifically, to a semiconductor memory device. Background Technology

[0002] Recently, vertical memory devices in which memory cells are vertically stacked have been developed for the high integration of semiconductor memory devices. Furthermore, PUC (peripheral under cell) structures, in which logic circuitry for controlling memory cells is placed beneath the memory cells, are under investigation. In the PUC structure, by placing the logic circuitry vertically overlapping the memory cells, more memory cells can be integrated within the same region. Summary of the Invention

[0003] Various embodiments relate to semiconductor memory devices with improved uniformity and reduced size.

[0004] In one embodiment, a semiconductor memory device may include: a memory cell array disposed on a substrate extending in a first semiconductor layer in a first direction and a second direction intersecting the first direction, the memory cell array including a plurality of cell portions arranged in the second direction and at least two via regions, wherein the width of each of the at least two via regions in the second direction is a multiple of the width of each of the plurality of cell portions in the second direction.

[0005] In one embodiment, a semiconductor memory device may include: a memory cell array disposed on a substrate extending in a first semiconductor layer in a first direction and a second direction intersecting the first direction, the memory cell array including a plurality of cell portions and at least two via regions arranged in the second direction; and a plurality of block select units included in a second semiconductor layer arranged vertically from the first semiconductor layer, the plurality of block select units arranged in the second direction, wherein the spacing between adjacent via regions corresponds to a multiple of the width of each of the plurality of block select units in the second direction. Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0007] Figure 2 yes Figure 1 The equivalent circuit diagram of one of the memory blocks shown.

[0008] Figure 3This is a diagram that schematically illustrates a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 4 This is an example Figure 3 A top view of a portion of the first semiconductor layer shown.

[0010] Figure 5 This is an example and Figure 4 A top view of the second semiconductor layer overlapping the first semiconductor layer.

[0011] Figure 6 This is a top view illustrating a portion of a semiconductor memory device according to one embodiment of the present disclosure.

[0012] Figure 7A It is along Figure 6 The cross-sectional view taken from line I-I'.

[0013] Figure 7B It is along Figure 6 The cross-sectional view taken from line II-II'.

[0014] Figure 7C It is along Figure 6 The cross-sectional view taken from line III-III'.

[0015] Figures 8A to 8D This is a top view illustrating various examples of unit sections according to embodiments of the present disclosure.

[0016] Figures 9A to 9C This is a block diagram illustrating various examples of block selection units according to embodiments of the present disclosure.

[0017] Figure 10A and Figure 10B This is an exemplary top view illustrating a semiconductor memory device that differs from this disclosure.

[0018] Figure 11 This is a block diagram illustrating a memory system including a semiconductor memory device according to one embodiment of the present disclosure.

[0019] Figure 12 This is a block diagram illustrating a computing system including a semiconductor memory device according to one embodiment of the present disclosure. Detailed Implementation

[0020] The advantages and features of this disclosure, as well as methods for implementing them, will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in a variety of different ways. The exemplary embodiments of this disclosure convey the scope of this disclosure to those skilled in the art.

[0021] Because the numerical values, dimensions, ratios, angles, and number of elements given in the accompanying drawings to describe embodiments of this disclosure are illustrative only, this disclosure is not limited to what is illustrated. Throughout the specification, the same reference numerals refer to the same components. In describing this disclosure, detailed descriptions of the prior art will be omitted where it is determined that such detailed descriptions may obscure the gist or clarity of this disclosure. It should be understood that, unless expressly stated otherwise, the terms “comprising,” “having,” and “including,” etc., as used in the specification and claims should not be construed as limited to the means listed thereafter. When referring to a singular noun, the use of an indefinite or definite article (e.g., “a,” “one,” or “the”) may include the plural form of the noun unless expressly stated otherwise.

[0022] When interpreting the elements in the embodiments of this disclosure, they should be interpreted as including tolerances, even if not explicitly stated otherwise.

[0023] Furthermore, in describing the components of this disclosure, terms such as first, second, A, B, (a), and (b) may be used. These are for the purpose of distinguishing one component from another and do not limit the nature, order, sequence, or number of the components. Additionally, the components in embodiments of this disclosure are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, as used herein, within the spirit of the present disclosure, a first component may be a second component.

[0024] If a component is described as “connected,” “linked,” or “attached” to another component, this can mean that the component is not only directly “connected,” “linked,” or “attached,” but also indirectly “connected,” “linked,” or “attached” via a third component. When describing positional relationships such as “component A on component B,” “component A above component B,” “component A below component B,” and “component A adjacent to component B,” one or more other components may be positioned between component A and component B unless the terms “directly” or “immediately” are explicitly used.

[0025] The features of the various exemplary embodiments of this disclosure can be combined, integrated, or separated, in whole or in part. Various technical interactions and operations are possible. The various exemplary embodiments can be practiced individually or in combination.

[0026] In this specification, the term "dummy" is used to refer to a component that has the same or similar structure and shape as other components but exists only in pattern form and does not have the ability to perform a substantial function. Therefore, a "dummy" component may not be able to perform a particular electrical function, or no electrical signal may be applied to a "dummy" component.

[0027] In the following, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0029] Reference Figure 1 A semiconductor memory device according to one embodiment of the present disclosure may include a memory cell array 100, a row decoder 210, a page buffer circuit 220, and peripheral circuitry 230. Peripheral circuitry 230 may include control logic 231, a voltage generator 232, and input / output (I / O) circuitry 233.

[0030] The memory cell array 100 may include a plurality of memory cells. The memory cell array 100 may be configured as a three-dimensional memory array in which the memory cells are stacked in a direction perpendicular to the surface of the substrate.

[0031] The memory cell array 100 can be connected to the row decoder 210 via multiple row lines RL. The row lines RL can include word lines and select lines, and the select lines can include drain select lines and source select lines.

[0032] The memory cell array 100 can be connected to the page buffer circuit 220 via bit lines BL. The memory cell array 100 can store data received through the page buffer circuit 220 during programming operations, and can send the stored data to the page buffer circuit 220 during read operations.

[0033] Memory cell array 100 may include multiple memory blocks BLK. Each memory block BLK may be an erase unit. Row lines RL and bit lines BL may be connected to each memory block BLK. Row lines RL may be connected to individual memory blocks BLK, and bit lines BL may be collectively connected to multiple memory blocks BLK. See below for further details. Figure 2 Describe the memory block BLK.

[0034] The line decoder 210 may include a transmission transistor circuit 211 and a block decoder circuit 212.

[0035] The transfer transistor circuit 211 may include multiple transfer transistor groups Pass TR, each corresponding to a plurality of memory blocks BLK. Each transfer transistor group Pass TR can be connected to the corresponding memory block BLK via a row line RL.

[0036] The block decoder circuit 212 can activate one of a plurality of block select signals BLKWL in response to the row address signal RADD from the control logic 231. One of a plurality of transfer transistor groups Pass TR can be selected via the activated block select signal BLKWL. The selected transfer transistor group Pass TR transmits the operating voltage Vop from the voltage generator 232 to the corresponding memory block BLK via the row line RL.

[0037] Page buffer circuit 220 can be connected to memory cell array 100 via bit line BL. Page buffer circuit 220 can receive page buffer control signal PBCON from control logic 231, and can send data signal DATA to I / O circuit 233 and receive data signal DATA from I / O circuit 233.

[0038] Page buffer circuit 220 can control bit lines BL connected to memory cell array 100 in response to page buffer control signal PBCON. For example, page buffer circuit 220 can detect data stored in memory cells of memory cell array 100 by sensing the signal of bit line BL of memory cell array 100 in response to page buffer control signal PBCON, and can send data signal DATA to IO circuit 233 according to the detected data. In response to page buffer control signal PBCON, page buffer circuit 220 can apply a signal to bit line BL based on data signal DATA received from IO circuit 233, and therefore, data can be written into memory cells of memory cell array 100. Page buffer circuit 220 can write data to memory cells connected to word lines activated by row decoder 210 or read data from memory cells connected to word lines activated by row decoder 210.

[0039] Control logic 231 can output a voltage control signal VCON to generate the voltage necessary for the operation of the semiconductor memory device in response to the command CMD input through I / O circuit 233. Control logic 231 can output a page buffer control signal PBCON to control the page buffer circuit 220. Control logic 231 can output a row address signal RADD and a column address signal CADD in response to the address signal ADD input through I / O circuit 233.

[0040] Voltage generator 232 can generate various operating voltages Vop that will be used in programming, reading, or erasing operations in response to the voltage control signal VCON of control logic 231. For example, voltage generator 232 can generate various levels of programming voltage, pass voltage, read voltage, and erase voltage in response to the voltage control signal VCON.

[0041] The I / O circuit 233 can transmit command CMD or address signal ADD input from an external source of the semiconductor memory device to the control logic 231, or it can exchange data signal DATA with the page buffer circuit 220. The I / O circuit 233 can send data DATA to and receive data DATA from an external source of the semiconductor memory device (e.g., a memory controller) via the input / output path I / O. The input / output path I / O can include 2... N (Where N is a natural number of 2 or greater) data input / output pins. For example, if N = 3, the input / output path IO can include IO pins. <0> To IO <7> The eight data input / output pins are represented.

[0042] Figure 2 yes Figure 1 The equivalent circuit diagram of one of the memory blocks BLK is shown.

[0043] Reference Figure 2 The memory block BLK may include multiple cell strings CSTRs connected between multiple bit lines BL and a common source line CSL.

[0044] Each cell string (CSTR) can be connected between its corresponding bit line (BL) and the common source line (CSL). Each cell string (CSTR) may include a source select transistor (SST) connected to the common source line (CSL), a drain select transistor (DST) connected to the bit line (BL), and multiple memory cells (MCs) connected between the source select transistor (SST) and the drain select transistor (DST). The gate of the source select transistor (SST) can be connected to the source select line (SSL). The gate of each memory cell (MC) can be connected to its corresponding word line (WL). The gate of the drain select transistor (DST) can be connected to the drain select line (DSL).

[0045] The source select line (SSL), word line (WL), and drain select line (DSL) can be positioned in a direction perpendicular to the bit line (BL). The source select line (SSL), word line (WL), and drain select line (DSL) can be stacked vertically on the surface of a substrate to form a three-dimensional structure.

[0046] Memory cells (MCs) included in a memory block (BLK) can be divided into physical page cells or logical page cells. For example, memory cells (MCs) that share a word line (WL) and are connected to different cell strings (CSTRs) can constitute a physical page (PG). Such a page can be the basic unit of read operations.

[0047] For example, Figure 2An example is shown where one drain-select transistor (DST) and one source-select transistor (SST) are placed in each cell string (CSTR). However, it should be noted that at least two drain-select transistors or at least two source-select transistors can be placed in each cell string (CSTR).

[0048] Figure 3 This is a diagram that schematically illustrates a semiconductor memory device according to an embodiment of the present disclosure.

[0049] Reference Figure 3 A semiconductor memory device according to one embodiment of the present disclosure may include a first semiconductor layer S1 and a second semiconductor layer S2. The first semiconductor layer S1 may be stacked on the second semiconductor layer S2 in the vertical direction VD. For ease of understanding, Figure 3 For example, the first semiconductor layer S1 and the second semiconductor layer S2 are separated from each other, but it should be understood that the top surface of the second semiconductor layer S2 and the bottom surface of the first semiconductor layer S1 are actually in contact with each other.

[0050] The memory cell array 100 may be included in the first semiconductor layer S1, and the row decoder 210, page buffer circuit 220, and peripheral circuit 230 may be included in the second semiconductor layer S2. The semiconductor memory device according to this embodiment may have a PUC (lower peripheral cell) structure.

[0051] Multiple row lines RL and multiple bit lines BL can be arranged in the memory cell array 100. The multiple row lines RL can extend along a first direction FD and can be arranged along a second direction SD that intersects the first direction FD. The multiple bit lines BL can extend along the second direction SD and can be arranged along the first direction FD. For example, the first direction FD and the second direction SD can intersect each other perpendicularly.

[0052] In order to reduce the delay of the signal provided from the row decoder 210 to the row line RL, the row decoder 210 may be configured to have a shape extending in a second direction SD which is the direction in which the row lines RL are arranged, and may be configured to have a length in the second direction SD that is substantially the same as or similar to the length of the memory cell array 100.

[0053] In order to reduce the delay of signals applied to bit lines BL from page buffer circuit 220 or received from bit lines BL in page buffer circuit 220, page buffer circuit 220 may be configured to have a length substantially the same as or similar to the length of memory cell array 100 in a first direction FD which is the direction in which bit lines BL are arranged.

[0054] Page buffer circuit 220 may include multiple page buffer high-voltage regions (HV), multiple page buffer low-voltage regions (LV), multiple cache latch regions (Cache), and multiple column decoder regions (CSDEC).

[0055] Multiple page buffer high-voltage regions (HVs) can be spaced apart along the second direction (SD), and a column decoder region (CSDEC) can be positioned in the middle between two adjacent page buffer high-voltage regions (HVs) along the second direction (SD). A page buffer low-voltage region (LV) and a cache latch region (Cache) can be positioned between adjacent page buffer high-voltage regions (HVs) and the column decoder region (CSDEC). The page buffer low-voltage region (LV) can be positioned adjacent to the page buffer high-voltage region (HV), and the cache latch region (Cache) can be positioned adjacent to the column decoder region (CSDEC).

[0056] Page buffer circuit 220 may include a plurality of page buffer high-voltage cells connected to memory cell array 100 via bit line BL. The plurality of page buffer high-voltage cells may be divided into groups of the same number as the number of page buffer high-voltage regions HV, and each group of page buffer high-voltage cells may be set in a corresponding page buffer high-voltage region HV.

[0057] Page buffer circuit 220 may include multiple page buffer low-voltage units. These multiple page buffer low-voltage units may be divided into groups of the same number as the number of page buffer low-voltage regions LV, and each group of page buffer low-voltage units may be located in a corresponding page buffer low-voltage region LV. Each page buffer low-voltage unit may be connected to the page buffer high-voltage unit of an adjacent page buffer high-voltage region HV via a connecting line.

[0058] The page buffer low-voltage unit can apply a voltage to the connection line based on the data stored therein. The voltage applied to the connection line can be transmitted to the bit line BL through the page buffer high-voltage unit. The page buffer low-voltage unit can perform latching based on the voltage of the connection line. The page buffer low-voltage unit can also perform latching based on the voltage transmitted from the bit line BL to the connection line through the page buffer high-voltage unit.

[0059] Page buffer circuit 220 may include multiple cache latches. These cache latches may be grouped into groups equal in number to the number of cache latch regions (Cache), and each group of cache latches may be located in a corresponding cache latch region (Cache). Each cache latch may be connected to a page buffer low-voltage cell in an adjacent page buffer low-voltage region (LV) via a page line.

[0060] The cache latch can exchange data with the I / O circuitry included in the peripheral circuitry 230 via data lines. The cache latch can store data received from the low-voltage cell of the page buffer via page lines, and can transmit the stored data to the I / O circuitry via data lines in response to column decoder signals. The cache latch can exchange data with the low-voltage cell of the page buffer or the I / O circuitry in response to page buffer control signals received from the peripheral circuitry 230.

[0061] Page buffer circuit 220 may include multiple column decoders. These column decoders can be divided into groups equal in number to the number of column decoder regions (CSDECs), and each group of column decoders can be configured within a corresponding column decoder region (CSDEC). The column decoders can be connected to cache latches in adjacent cache latch regions (Cache) via column lines.

[0062] The column decoder can generate a column select signal in response to a column address provided from peripheral circuitry 230. When using eight data input / output pins, eight cache latches can be selected from a plurality of cache latches included in page buffer circuitry 220 in response to the column select signal, and data stored in the eight selected cache latches can be sent to the I / O circuitry via data lines.

[0063] According to this layout, each interconnect line can be configured with a short length connecting adjacent page buffer high-voltage regions (HV) and low-voltage regions (LV); each page line can be configured with a short length connecting adjacent page buffer low-voltage regions (LV) and cache latch regions (Cache); and each column line can be configured with a short length connecting adjacent cache latch regions (Cache) and column decoder regions (CSDEC). Therefore, the number of wires connected between adjacent page buffer high-voltage regions (HV) and low-voltage regions (LV), between adjacent page buffer low-voltage regions (LV) and cache latch regions (Cache), and between adjacent cache latch regions (Cache) and column decoder regions (CSDEC) can be reduced. Thus, by placing a large number of lines in a single routing layer, the utilization efficiency of the routing layer can be improved.

[0064] Although this embodiment illustrates a page buffer high-voltage region HV of four, the number of page buffer high-voltage regions HV is not limited to this. Embodiments of this disclosure may include all cases where the number of page buffer high-voltage regions HV is two or more.

[0065] Figure 4 It is shown Figure 3 A top view of a portion of the first semiconductor layer shown, and Figure 5 It is shown that... Figure 4 A top view of the second semiconductor layer overlapping the first semiconductor layer.

[0066] Reference Figure 4 and Figure 5 According to one embodiment of the present disclosure, the first semiconductor layer S1 of a semiconductor memory device may include a memory cell array 100, which includes a plurality of cell units (CELL UNIT) and at least two via regions (BLOFC) disposed on a second direction SD. The width of each via region (BLOFC) on the second direction SD may have a size corresponding to a multiple of the width L1 of each cell unit on the second direction SD.

[0067] The second semiconductor layer S2 may include a plurality of block selection units BLKWL SW disposed in the second direction SD. The spacing between adjacent via regions BL OFC may have a size corresponding to a multiple of the width M1 of each block selection unit BLKWL SW in the second direction SD.

[0068] More specifically, the first semiconductor layer S1 and the second semiconductor layer S2 may each include a cell region CR, a slimming region SR extending from the cell region CR along the first direction FD, and a peripheral region PR extending from the slimming region SR along the first direction FD.

[0069] The memory cell array 100 can be disposed in the cell region CR of the first semiconductor layer S1, and can include multiple cell units and multiple via regions BL OFC.

[0070] Multiple cell units can be arranged in a row on the second direction SD, and each can include multiple memory cells. One or at least two cell units can constitute a memory block. Figure 1 (BLK). That is to say, each memory block can consist of one or at least two cell units. Figure 4 and Figure 5 An example is shown of a memory block consisting of a cell unit.

[0071] Although not shown, in the case where a memory block is composed of at least two cell units, the cell units included in a memory block can be arranged consecutively with each other adjacent to each other on the second direction SD.

[0072] The via region BL OFC is a region in which vias are provided to connect bit lines arranged on the memory cell array 100 to the page buffer circuit 220 of the second semiconductor layer S2. Each via region BL OFC can be provided between two adjacent cell units.

[0073] As described above, the width of a via region BL OFC in the second direction SD can have a size corresponding to a multiple of the width of a cell unit in the second direction SD. For example, if the width of a cell unit in the second direction SD is L1, then the width of a via region BL OFC in the second direction SD can have a size corresponding to a multiple of L1. Figure 4 The width of the via region BL OFC in the second direction SD is exemplified as twice the width L1 of the CELL UNIT in the second direction SD.

[0074] The first semiconductor layer S1 may include multiple main slimpatterns (Main SLIM) and multiple dummy slimpatterns (Dummy SLIM) disposed in the thinning region SR.

[0075] Multiple main slender patterns can each correspond to multiple cell units, each can be connected to its corresponding cell unit, and each can extend from its corresponding cell unit in the first direction FD. The width of each main slender pattern in the second direction SD can be substantially the same as the width of each cell unit in the second direction SD.

[0076] As will be referred to later Figures 6 to 7B The cell unit may include multiple electrode layers and multiple interlayer dielectric layers. These electrode layers and interlayer dielectric layers may extend in the thinned region SR along the first direction FD to configure a main slender pattern (Main SLIM).

[0077] A dummy SLIM can be configured to ensure pattern uniformity in the manufacturing process of the main SLIM. The dummy SLIM can be connected to the via area BL OFC and can be arranged in a row with the main SLIM in the second direction SD.

[0078] The width of each dummy slid pattern in the second direction SD can be substantially the same as the width of each cell unit in the second direction SD. As described above, the width of the via region BL OFC in the second direction SD has a dimension corresponding to a multiple of the width of the cell unit in the second direction SD. Therefore, all dummy slid patterns connected to the via region BL OFC can be configured such that the width of each dummy slid pattern in the second direction SD has the same dimension as the width of the cell unit in the second direction SD.

[0079] The width of the main slender pattern (Main SLIM) in the second direction (SD) is substantially the same as the width of the cell unit (CELL UNIT) in the second direction (SD). Therefore, the fact that the width of the dummy slender pattern (Dummy SLIM) in the second direction (SD) is the same as the width of the cell unit (CELL UNIT) in the second direction (SD) can be interpreted as the dummy slender pattern (Dummy SLIM) having the same width as the main slender pattern (Main SLIM) in the second direction (SD).

[0080] Figure 4 The width of a via region BL OFC in the second direction SD is exemplified as twice the width of a cell unit in the second direction SD. In this case, two dummy slimm patterns are joined to a via region BL OFC. When the width of a via region BL OFC in the second direction SD is K times the width of a cell unit in the second direction SD (where K is a natural number), K dummy slimm patterns can be joined to a via region BL OFC.

[0081] Reference Figure 5 The line decoder 210 may include a plurality of transmission transistor groups Pass TR and a plurality of dummy transmission transistor groups Dummy Pass TR arranged in a row in the second direction SD in the thinned region SR of the second semiconductor layer S2, and a plurality of block selection units BLKWLSW arranged in a row in the second direction SD in the peripheral region PR of the second semiconductor layer S2.

[0082] Multiple transmission transistor groups Pass TR can be configured to overlap with the main elongated pattern Main SLIM of the first semiconductor layer S1 in the vertical direction VD, and multiple dummy transmission transistor groups Dummy Pass TR can be configured to overlap with the dummy elongated pattern Dummy SLIM of the first semiconductor layer S1 in the vertical direction VD.

[0083] The width of a transmission transistor group (Pass TR) in the second direction SD can be substantially the same as the width of a memory block in the second direction SD. As described above, a memory block can be composed of one or at least two cell units, and the width of a memory block in the second direction SD has a size corresponding to a multiple of the width of a cell unit in the second direction SD. Therefore, it can be understood that the width of a transmission transistor group (Pass TR) in the second direction SD has a size corresponding to a multiple of the width of a cell unit in the second direction SD. This embodiment illustrates a case where a memory block is composed of a single cell unit. In this case, the width of a transmission transistor group (Pass TR) in the second direction SD can be substantially the same as the width of a cell unit in the second direction SD.

[0084] A transfer transistor group (Pass TR) may include multiple transfer transistors. The transfer transistors included in the transfer transistor group (Pass TR) can be identified later by referring to... Figure 7B The described contacts and wiring are electrically connected to the electrode layer of the main SLIM, thereby enabling the transmission of operating voltage to the electrode layer.

[0085] A dummy pass transistor group (Dummy Pass TR) can be configured to ensure pattern uniformity in the manufacturing process of the pass transistor group. The width of a dummy pass transistor group (Dummy Pass TR) in the second direction SD can have substantially the same dimensions as the width of a pass transistor group (Pass TR) in the second direction SD.

[0086] Each dummy pass transistor group (Dummy Pass TR) may include multiple dummy pass transistors. The dummy pass transistors included in each dummy pass transistor group (Dummy Pass TR) may have substantially the same arrangement and size as the pass transistors included in each pass transistor group (Pass TR).

[0087] Unlike transfer transistors, which deliver operating voltage to the electrode layer, dummy transfer transistors are not used to deliver operating voltage to the electrode layer. Dummy transfer transistors can be used in circuits that do not perform any electrical function or perform functions other than delivering operating voltage to the electrode layer.

[0088] The block selection unit BLKWL SW can be used with the configuration Figure 1 This corresponds to the basic unit of the block decoder circuit 212. Although this embodiment exemplifies that the width M1 of a block selection unit BLKWL SW in the second direction SD is twice the width of the transmission transistor group Pass TR in the second direction SD, this disclosure is not limited thereto. As will be referred to later... Figure 10A and Figure 10B As described, the width of a block selection cell BLKWL SW in the second direction SD can have a size corresponding to a multiple of the width of a transmission transistor group Pass TR in the second direction SD.

[0089] The page buffer circuit 220 and the peripheral circuit 230 can be disposed in the cell region CR of the second semiconductor layer S2. This can be referenced above. Figure 3 The number of page buffer high-voltage regions HV is the same as the number of via regions BLOFC. Although not shown, the via regions BLOFC can correspond to the page buffer high-voltage regions HV respectively, and the corresponding via regions BLOFC and page buffer high-voltage regions HV can overlap each other in the vertical direction VD.

[0090] Please refer to later. Figure 6 and Figure 7C As described, the vias disposed in the via region BL OFC can be connected to the page buffer high-voltage region HV via an electrical connection path (not shown). Since the via region BL OFC and the page buffer high-voltage region HV are configured to overlap each other in the vertical direction VD, the electrical connection path connecting the vias disposed in the via region BL OFC and the page buffer high-voltage region HV can be configured to have the same length as the shortest distance between the vias and the page buffer high-voltage region HV.

[0091] As described above, the spacing between adjacent via regions BL OFC can be configured to have a size corresponding to a multiple of the width of a block selection unit BLKWL SW in the second direction SD. For example, when the width of a block selection unit BLKWL SW in the second direction SD is M1, the spacing between adjacent via regions BL OFC can be a multiple of M1. Figure 5 The example illustrates the case where the interval between adjacent via regions BL OFC is n times M1, where n is a natural number.

[0092] Figure 6 This is a top view illustrating a portion of a semiconductor memory device according to one embodiment of the present disclosure. Figures 7A to 7C yes Figure 6 A cross-sectional view of a semiconductor memory device. Figures 7A to 7C Examples of the same as Figure 6 The cross sections corresponding to cutting lines I-I', II-II', and III-III'. For simplicity, in... Figure 6 Some components such as bit lines, contacts, and wiring are omitted.

[0093] Reference Figure 6 , Figure 7A and Figure 7B The first semiconductor layer S1 may include a plurality of electrode layers 20 and a plurality of interlayer dielectric layers 22 stacked alternately.

[0094] The electrode layer 20 may include at least one selected from semiconductors (e.g., doped silicon), metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and transition metals (e.g., titanium or tantalum). The interlayer dielectric layer 22 may include silicon oxide.

[0095] When multiple electrode layers 20 and multiple interlayer dielectric layers 22 are separated by the first slit SLT1, multiple cell units and multiple via regions BL OFC can be set and arranged in the cell region CR in the second direction SD. Although Figure 6 Only one via region BL OFC is illustrated, but it should be understood that, as referenced above... Figure 4 As mentioned above, multiple through-hole regions BLOFC are provided.

[0096] Each of the multiple cell units may include multiple electrode layers 20 and multiple interlayer dielectric layers 22 stacked alternately, and multiple vertical channels CH passing through the multiple electrode layers 20 and multiple interlayer dielectric layers 22 in the vertical direction VD. In addition, the cell unit may also include multiple dummy vertical channels DCH.

[0097] The electrode layer 20 of each cell unit can be configured Figure 1 The row line RL. Specifically, in the electrode layers 20, at least one electrode layer 20 starting from the bottommost electrode layer 20 can form a source select line, and at least one electrode layer 20 starting from the topmost electrode layer 20 can form a drain select line. The electrode layers 20 between the source select line and the drain select line can form a word line. Although Figure 7A and Figure 7B Eight stacked electrode layers 20 are illustrated, but this is for illustrative purposes only. The number of electrode layers 20 selected can vary depending on the memory capacity.

[0098] In each cell unit, multiple vertical channels (CH) and multiple dummy vertical channels (DCH) can be arranged in multiple channel rows extending in the first direction (FD). Although Figure 6 An example of a cell unit comprising nine channels is shown, but this disclosure is not limited thereto. (See later...) Figures 8A to 8D As described, the number of channel rows included in each cell unit can be changed to eight, seventeen (17) or nineteen (19), and other numbers can be used in other embodiments.

[0099] Multiple vertical channels CH can extend to the first substrate 10 by passing through multiple electrode layers 20 and multiple interlayer dielectric layers 22 in the vertical direction VD.

[0100] Each vertical channel (CH) may include a channel layer and a gate dielectric layer. The channel layer may include polysilicon or monocrystalline silicon and may include p-type impurities such as boron (B) in certain regions. The gate dielectric layer may have a shape surrounding the outer wall of the channel layer. The gate dielectric layer may include a tunnel dielectric layer, a charge storage layer, and a barrier layer sequentially stacked starting from the outer wall of the channel layer. In some embodiments, the gate dielectric layer may have an ONO (oxide-nitride-oxide) stacked structure in which oxide layers, nitride layers, and oxide layers are sequentially stacked. Although not shown, a dummy vertical channel (DCH) may have the same structure as a vertical channel CH.

[0101] Source-select transistors can be configured in a region or area where the source-select line surrounds the vertical channel CH. Memory cells can be configured in a region or area where the word line surrounds the vertical channel CH. Drain-select transistors can be configured in a region or area where the drain-select line surrounds the vertical channel CH. Source-select transistors, multiple memory cells, and drain-select transistors arranged along a vertical channel CH can form a cell string.

[0102] Multiple bit lines BL can be disposed above a stack comprising alternating electrode layers 20 and multiple interlayer dielectric layers 22. Each bit line BL can be connected to a corresponding vertical channel CH via a bit line contact BLC.

[0103] Each main slender pattern can be configured with an electrode layer 20 and an interlayer dielectric layer 22 extending from the cell region CR in the first direction FD to the thinned region SR of the corresponding cell unit, and these layers can be configured to have a stepped structure. The main slender pattern can include various structures, such as dummy pillars (DP) and dummy slits (DSLT).

[0104] Multiple electrode layers 20 and multiple interlayer dielectric layers 22 can be formed by alternatingly stacking multiple sacrificial layers (not shown) and multiple interlayer dielectric layers 22, partially removing the sacrificial layers by injecting etchant through a first slit SLT1 and a dummy slit DSLT, and filling the space from which the sacrificial layers have been removed with electrode material.

[0105] In the process of removing the sacrificial layer, the following problems may occur: the interlayer dielectric layer 22 may collapse or bend, and the spacing between the interlayer dielectric layers 22 may not be maintained or may change. To reliably remove the sacrificial layer in the process, or to alleviate stress, dummy pillars DP can be used to support the interlayer dielectric layer 22, thereby preventing deformation of the interlayer dielectric layer 22 during the process of removing the sacrificial layer, and dummy slits DSLT can be used as channels through which etchant for removing the sacrificial layer is introduced. However, the functions of dummy pillars DP and dummy slits DSLT are not limited to these.

[0106] Multiple first slits SLT1 can extend in the first direction FD while passing through multiple electrode layers 20 and multiple interlayer dielectric layers 22 along the vertical direction VD. Each cell unit can be separated from another adjacent cell unit or from the adjacent via region BL OFC by the first slits SLT1.

[0107] A second slit SLT2 extending in the first direction FD can be formed to divide at least one electrode layer located on the upper part of the electrode layer 20 included in each cell unit into a plurality of electrode layers 20. The electrode layers 20 divided or segmented by the second slit SLT2 can form a drain selection line. A plurality of first dielectric stacks LS1 can be configured in the thinning region SR. Each first dielectric stack LS1 can have a structure in which a plurality of dielectric layers and a plurality of interlayer dielectric layers 22 are alternately stacked. The dielectric layers of the first dielectric stack LS1 correspond to the sacrificial layers that are not removed in the process of removing the sacrificial layers by injecting etchant through the first slit SLT1 and the dummy slit DSLT.

[0108] Contact CNT11 can be connected to each electrode layer 20 of the main slender pattern. Each electrode layer 20 can be connected to the pass transistor group Pass TR via contacts CNT12 and CNT13 connected to contact CNT11 and wiring M11 and M12. For simplicity, Figure 7B Only wiring M11 and M12 and contacts CNT11 to CNT13 connecting an electrode layer 20 and a transmission transistor group Pass TR are shown as examples. However, it should be understood that wiring and contacts connecting each electrode layer 20 to the transmission transistor group Pass TR are provided respectively.

[0109] The transmission transistor group Pass TR may include multiple transmission transistors on the second substrate 12. Each transmission transistor is connected to a corresponding electrode layer 20 via contacts CNT11 to CNT13 and wirings M11 and M12, thereby transmitting an operating voltage to the electrode layer 20. The transmission transistors included in the transmission transistor group Pass TR are connected to a corresponding block select unit BLKWL SW via contacts CNT14 and CNT15 and wiring M13, thereby being provided with a block select signal from the block select unit BLKWL SW. The transmission transistors can transmit an operating voltage to the corresponding electrode layer 20 in response to the block select signal.

[0110] Reference Figure 6 and Figure 7C The via region BL OFC may include multiple electrode layers 20 and multiple interlayer dielectric layers 22 alternately stacked on the cell region CR of the first substrate 10, multiple dummy channels DCH' through the multiple electrode layers 20 and multiple interlayer dielectric layers 22, and a second dielectric stack LS2. The second dielectric stack LS2 may have a structure in which multiple dielectric layers 24 and multiple interlayer dielectric layers 22 are alternately stacked. The dielectric layers 24 may be made of a dielectric material with a different etch selectivity than the interlayer dielectric layers 22. For example, if the interlayer dielectric layers 22 are made of silicon oxide, then the dielectric layers 24 may be made of nitride. The second dielectric stack LS2 may be formed by the same process as that used to form the first dielectric stack LS1 as described above. That is, the dielectric layer 24 of the second dielectric stack LS2 corresponds to the sacrificial layer that was not removed during the process of removing the sacrificial layer by injecting etchant through the first slit SLT1 and the dummy slit DSLT.

[0111] The via VIA can be located in the second dielectric stack LS2 of the via region BL OFC. The via VIA can be connected to the bit line BL and can pass vertically through the second dielectric stack LS2 into the second semiconductor layer S2 to connect to the wiring M21. The via VIA can be connected to the page buffer circuit 220 through the contact CNT21 connected to the wiring M21.

[0112] The dummy slender pattern (Dummy SLIM) can be fabricated using the same design as the main slender pattern (Main SLIM). For example, the Dummy SLIM can have substantially the same structure as the main slender pattern (Main SLIM), or it can have a structure that is symmetrical to the main slender pattern (Main SLIM) based on a virtual line extending in the first direction (FD). If the main slender pattern (Main SLIM) has a stepped structure and is configured to include a dummy pillar (DP), a dummy slit (DSLT), and a first dielectric laminate (LS1), then the Dummy SLIM can also have a stepped structure and be configured to include a dummy pillar (DP), a dummy slit (DSLT), and a first dielectric laminate (LS1).

[0113] Conductive patterns, such as those for contacts, may not be formed on the dummy slim. Alternatively, dummy conductive patterns that are not used for electrical connection may be formed on the dummy slim.

[0114] As referenced above Figure 4 The width of a via region BL OFC in the second direction SD has a dimension corresponding to a multiple of the width of a cell unit in the second direction SD. Therefore, the width of a dummy slime pattern in the second direction SD can also be configured to have the same dimension as the width of the main slime pattern in the second direction SD.

[0115] Unlike this embodiment, where the width of a via region BL OFC in the second direction SD is not a multiple of the width of a cell unit in the second direction SD, at least one dummy slime pattern in the second direction SD will have a different width than the main slime pattern in the second direction SD.

[0116] The structures included in the Main SLIM and Dummy SLIM (e.g., dummy pillar DP, dummy slit DSLT, and first dielectric stack LS1) are designed to perform the target function. Therefore, if the size of either pattern is changed, the pattern design needs to be changed accordingly.

[0117] If there exists a dummy slender pattern (Dummy SLIM) whose width in the second direction SD is different from that of the main slender pattern (Main SLIM) in the second direction SD, then the corresponding dummy slender pattern (Dummy SLIM) needs to be designed separately, and therefore, the design development requires a lot of effort and time.

[0118] According to embodiments of this disclosure, by configuring the width of a via region BL OFC in the second direction SD to have a size corresponding to a multiple of the width of a cell unit in the second direction SD, the width of the dummy slime in the second direction SD can be configured to have the same size as the width of the main slime in the second direction SD. Therefore, the dummy slime can be fabricated using the same design as the main slime. Consequently, the effort and time spent developing different designs for any given pattern can be reduced.

[0119] Figures 8A to 8D This is a top view illustrating various examples of unit sections according to embodiments of the present disclosure.

[0120] Reference Figure 8A The unit may include multiple channels. Figure 8A An embodiment is illustrated in which nine rows of channels (9 rows) extending in a first direction FD and arranged in a second direction SD are included in a unit portion between two first slits SLT1. To provide a compact layout, odd-numbered and even-numbered channel rows can be set to be offset from each other in the first direction FD.

[0121] The second slit SLT2 can divide the electrode layer used for configuring the drain selection line, which is included in the electrode layer of the cell section, into two parts. For example, it can be... Figure 8A The unit shown has two drain selection lines, and the structure can be defined as a two-string structure.

[0122] In this embodiment, the second slit SLT2 can be configured to traverse the fifth of the nine channel rows. The dummy vertical channel DCH can be configured in the fifth channel row traversed by the second slit SLT2, while the vertical channel CH can be configured in other channel rows.

[0123] Reference Figure 8B In one embodiment, the second slit SLT2 can be formed to undulate along the outer edge or sidewall of the vertical channels CH disposed in two adjacent and offset channel rows. That is, the second slit SLT2 can be configured as a wavy shape extending along the first direction FD between the vertical channels CH. In this case, since the second slit SLT2 does not traverse the channel rows, no dummy vertical channels are configured in a single cell. Therefore, the same memory capacity as a structure including nine channel rows (9 rows) can be achieved using only eight channel rows (8 rows).

[0124] Reference Figure 8C In one embodiment, a cell section may include 19 channel rows (19 rows) and three second slits SLT2. In this case, the electrode layer for configuring the drain select lines is divided into four sections by the second slits SLT2, which provides four drain select lines in a cell section. This structure can be defined as a four-string structure.

[0125] Among the 19 channel rows, the dummy vertical channel DCH can be configured in the fifth, tenth, and fifteenth channel rows traversed by the second slit SLT2. The vertical channel CH can be configured in other channel rows.

[0126] Reference Figure 8D In one implementation, a unit may include 17 channel rows (17 rows), two second slits SLT2 and one third slit SLT3.

[0127] The second slit SLT2 can divide the electrode layer included in the cell section for configuring the drain selection line, and can be configured in a waveform shape between the vertical channels CH. For example, one second slit SLT2 can be disposed between the fourth and fifth channel rows, and another second slit SLT2 can be disposed between the thirteenth and fourteenth channel rows.

[0128] The third slit SLT3 can divide the electrode layer included in the cell section for configuring the source selection line. As a result, two source selection lines can be provided in one cell section. The third slit SLT3 can be configured to traverse the ninth channel row of 17 channel rows in the first direction FD. A dummy vertical channel DCH can be configured in the ninth channel row traversed by the third slit SLT3, and the vertical channel CH can be configured in other channel rows.

[0129] Because the second slit SLT2 does not cross the channel rows, the same memory capacity as a structure with 19 channel rows can be achieved using only 17 channel rows (17 rows).

[0130] Figures 9A to 9C This is a block diagram illustrating various examples of block selection units according to embodiments of the present disclosure. Figures 9A to 9C The structure corresponding to the four memory blocks BLK 1 to BLK 4 is illustrated.

[0131] Reference Figure 9A It is possible to set four transfer transistor groups, Pass TR 1 to Pass TR 4, corresponding to the four memory blocks BLK 1 to BLK 4 respectively.

[0132] Multiple global row lines GRL can be connected together to the transmission transistor groups Pass TR 1 to Pass TR 4, and therefore, the transmission transistor groups Pass TR 1 to Pass TR 4 can share the multiple global row lines GRL.

[0133] Four block selection units BLKWL SW1 to BLKWL SW4 can be configured, each corresponding to one of the four transmission transistor groups Pass TR1 to Pass TR4. The width of each of the block selection units BLKWL SW1 to BLKWL SW4 in the second direction SD can be substantially the same as the width of one of the transmission transistor groups (Pass TR1 to Pass TR4) in the second direction SD.

[0134] Each of the block selection units BLKWL SW1 to BLKWL SW4 can provide a block selection signal (one of BLKSW1 to BLKSW4) to a corresponding transmission transistor group (one of Pass TR1 to Pass TR4). For example, the first block selection unit BLKWL SW1 can provide the block selection signal BLKSW1 to the first transmission transistor group PassTR1.

[0135] Any one of the block select signals BLKSW 1 to BLKSW 4 can be activated. The transfer transistor group provided with the activated block select signal can transmit the operating voltage applied to the global row line GRL to the corresponding memory block.

[0136] Reference Figure 9B Two block selection units BLKWL SW1 and BLKWL SW2 can be provided corresponding to the four transmission transistor groups Pass TR1 to Pass TR4. In the example, the width of each of the block selection units BLKWL SW1 and BLKWL SW2 in the second direction SD can have a size corresponding to twice the width of one of the transmission transistor groups (Pass TR1 to Pass TR4) in the second direction SD, or the width of each of the block selection units BLKWL SW1 and BLKWL SW2 in the second direction SD can have a size corresponding to the width of a pair of transmission transistor groups in the second direction SD.

[0137] Each of the block selection units BLKWL SW1 and BLKWL SW2 can correspond to two transmission transistor groups and can provide different block selection signals to the corresponding two transmission transistor groups. For example, the first block selection unit BLKWL SW1 can correspond to the first transmission transistor group Pass TR1 and the second transmission transistor group Pass TR2. The first block selection unit BLKWL SW1 can provide the first block selection signal BLKSW1 to the first transmission transistor group Pass TR1, and can provide the second block selection signal BLKSW2 to the second transmission transistor group Pass TR2.

[0138] Any one of the block select signals BLKSW 1 to BLKSW 4 can be activated, and the transfer transistor group provided with the activated block select signal can transmit the operating voltage applied to the global row line GRL to the corresponding memory block.

[0139] Reference Figure 9C The first transfer transistor group Pass TR 1 and the second transfer transistor group Pass TR 2 can be connected to different global row lines with the third transfer transistor group Pass TR 3 and the fourth transfer transistor group Pass TR 4. For example, the first transfer transistor group Pass TR 1 and the second transfer transistor group Pass TR 2 can be connected to multiple first global row lines GRL1, and the third transfer transistor group Pass TR 3 and the fourth transfer transistor group Pass TR 4 can be connected to multiple second global row lines GRL2.

[0140] A block selection unit BLKWL SW can be provided corresponding to the four transmission transistor groups Pass TR 1 to Pass TR 4. The width of the block selection unit BLKWL SW in the second direction SD can have a size corresponding to four times the width of one transmission transistor group in the second direction SD, or a size corresponding to the width of the four transmission transistor groups Pass TR 1 to Pass TR 4 in the second direction SD.

[0141] The block selection unit BLKWL SW can provide a block selection signal to two transmission transistor groups connected to different global row lines. For example, the block selection unit BLKWL SW can provide a first block selection signal BLKSW1 to the first transmission transistor group Pass TR1 connected to the first global row line GRL1, and to the third transmission transistor group Pass TR3 connected to the second global row line GRL2. Additionally, the block selection unit BLKWL SW can provide a second block selection signal BLKSW 2 to the second transmission transistor group Pass TR2 connected to the first global row line GRL1, and to the fourth transmission transistor group Pass TR 4 connected to the second global row line GRL2. This structure can be defined as a shared decoder structure.

[0142] In a shared decoder architecture, two sets of transmission transistors sharing a block select signal can be connected to different global row lines, and the operating voltage can be applied only to the global row line connected to either of these two sets of transmission transistors. Therefore, the operating voltage can be supplied to one of the two memory blocks sharing the block select signal.

[0143] Figure 10A and Figure 10B This is an exemplary top view illustrating a semiconductor memory device that differs from this disclosure.

[0144] Figure 10A and Figure 10B This example illustrates a case where the spacing between adjacent via regions BL OFC is not a multiple of the width M1 of the block selection unit BLKWL SW in the second direction SD.

[0145] Reference Figure 10A When the spacing between adjacent via regions BL OFC is not a multiple of M1, as shown in region A, a block selection cell with a width less than M1 will be formed in the second direction SD. M1 represents the width of the standard block selection cell BLKWL SW that meets a predetermined standard in the second direction SD.

[0146] Because of the different widths in the second direction SD, it is impossible to configure block selection unit A with the same layout as the standard block selection unit BLKWL SW. As a result, due to the change in layout, it is difficult to ensure device characteristics, which leads to performance degradation.

[0147] Reference Figure 10BWithout using block select unit A and its associated transfer transistor group B and cell section C, and treating them as dummy objects, there is no performance degradation problem caused by block select unit A. However, the presence of dummy cell section C consumes additional area, thus requiring a larger area to implement the memory with the desired capacity. In other words, the size of the semiconductor memory device will increase.

[0148] According to embodiments of this disclosure, by configuring the spacing between adjacent via regions BL OFC to a size corresponding to a multiple of M1, block select cells with a width smaller than M1 formed on the second direction SD can be prevented. Therefore, performance degradation due to layout changes and corresponding changes in device characteristics can be prevented. Furthermore, the formation of dummy cell sections can be prevented, thereby contributing to the miniaturization of semiconductor memory devices.

[0149] Figure 11 This is a block diagram illustrating a memory system including a semiconductor memory device according to one embodiment of the present disclosure.

[0150] Reference Figure 11 According to one embodiment, the memory system 600 may include a non-volatile memory device (NVM device) 610 and a memory controller 620.

[0151] The non-volatile memory device (NVM device) 610 can be configured from the aforementioned semiconductor memory device and can operate in the manner described above. The memory controller 620 can be configured to control the non-volatile memory device (NVM device) 610. The combination of the non-volatile memory device (NVM device) 610 and the memory controller 620 can provide a memory card or solid-state drive (SSD). SRAM 621 serves as the working memory for the processing unit (CPU) 622. The host interface (host I / F) 623 includes a data exchange protocol for a host connected to the memory system 600.

[0152] Error correction code block (ECC) 624 detects and corrects errors included in data read from non-volatile memory device (NVM device) 610.

[0153] The memory interface (memory I / F) 625 interfaces with the non-volatile memory device 610 of this embodiment. The processing unit (CPU) 622 performs general control operations for data exchange with the memory controller 620.

[0154] Although not shown in the accompanying drawings, it will be apparent to those skilled in the art that the memory system 600 according to the embodiment may additionally include a ROM for storing code data for interfacing with a host. The non-volatile memory device (NVM device) 610 may be configured as a multi-chip package consisting of multiple flash memory chips.

[0155] The memory system 600 according to the above embodiment can be configured as a highly reliable storage medium with a low probability of error occurrence. In particular, the non-volatile memory device of this embodiment can be included in a memory system such as a solid-state drive (SSD), which is currently under active research. In this case, the memory controller 620 can be configured to communicate with an external (e.g., a host) via one of various interface protocols such as USB (Universal Serial Bus), MMC (Multimedia Card), PCI-E (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attached), PATA (Parallel Advanced Technology Attached), SCSI (Small Computer System Interface), ESDI (Enhanced Small Disk Interface), and IDE (Integrated Drive Electronics).

[0156] Figure 12 This is a block diagram illustrating a computing system including a semiconductor memory device according to one embodiment of the present disclosure.

[0157] Reference Figure 12 A computing system 700 according to one embodiment may include a memory system 710, a microprocessor (CPU) 720, RAM 730, a user interface 740, and a modem 750 such as a baseband chipset, all electrically connected to a system bus 760. If the computing system 700 according to the embodiment is a mobile device, a battery (not shown) may be additionally provided to supply the operating voltage of the computing system 700. Although not shown in the figures, it will be apparent to those skilled in the art that the computing system 700 according to the embodiment may additionally include an application chipset, a camera image processor (CIS), and mobile DRAM, etc. The memory system 710 may be configured, for example, to use a non-volatile memory (SSD) to store data. Alternatively, the memory system 710 may be configured as a converged flash memory (e.g., OneNAND flash memory).

[0158] Although exemplary embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered in a descriptive sense only and not as limiting the scope of the technology. The scope of this disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of this disclosure should be interpreted by the appended claims and include all equivalents falling within the scope of the appended claims.

[0159] Cross-references to related applications

[0160] This application claims priority to Korean Patent Application No. 10-2020-0160671, filed on November 26, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: an array of memory cells disposed on a substrate extending in a first direction and a second direction intersecting the first direction in a first semiconductor layer, the array of memory cells including a plurality of cell portions and at least two via regions arranged in the second direction, wherein each of the at least two via regions has a width in the second direction that is a multiple of a width in the second direction of each of the plurality of cell portions, wherein each of the plurality of cell portions includes a plurality of electrode layers and a plurality of interlayer dielectric layers alternately stacked, and includes a plurality of vertical channels passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in a vertical direction, and wherein the first semiconductor layer includes a plurality of first slits extending in the first direction and passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in the vertical direction to define and separate the plurality of cell portions and the at least two via regions. 2.The semiconductor memory device of claim 1, wherein the first semiconductor layer further comprising: a plurality of main elongated patterns respectively coupled to the plurality of cell portions, and each of the plurality of main elongated patterns extending from a corresponding cell portion along the first direction; and a plurality of dummy elongated patterns coupled to each of the at least two via regions, wherein the plurality of main elongated patterns and the plurality of dummy elongated patterns are arranged in the second direction, and wherein each of the plurality of main elongated patterns and each of the plurality of dummy elongated patterns has a width in the second direction that is the same as a width in the second direction of each of the plurality of cell portions. 3.The semiconductor memory device of claim 2, wherein each of the plurality of main elongated patterns is configured by the plurality of electrode layers and the plurality of interlayer dielectric layers extending from the plurality of cell portions along the first direction.

4. The semiconductor memory device of claim 2, wherein, each of the plurality of dummy elongated patterns has a same structure as one of the plurality of main elongated patterns, or has a structure symmetrical to one of the plurality of main elongated patterns based on a virtual line extending in the first direction. 5.The semiconductor memory device of claim 2, further comprising: a second semiconductor layer arranged from the first semiconductor layer along the vertical direction, wherein the second semiconductor layer includes: a plurality of transfer transistor groups disposed to overlap the plurality of main elongated patterns in the vertical direction; and a plurality of dummy transfer transistor groups disposed to overlap the plurality of dummy elongated patterns in the vertical direction, wherein the plurality of transfer transistor groups and the plurality of dummy transfer transistor groups are arranged in the second direction, and Each of the plurality of dummy transfer transistor groups has the same width in the second direction as each of the plurality of transfer transistor groups.

6. The semiconductor memory device according to claim 1, further comprising: a second semiconductor layer arranged from the first semiconductor layer along the vertical direction, wherein the second semiconductor layer includes a page buffer circuit including a plurality of page buffer high voltage regions arranged at intervals from each other in the second direction, and wherein the number of the at least two via regions is the same as the number of the plurality of page buffer high voltage regions.

7. The semiconductor memory device according to claim 6, wherein, the at least two via regions respectively correspond to the plurality of page buffer high voltage regions, and the page buffer high voltage regions and the corresponding via regions overlap with each other in the vertical direction.

8. A semiconductor memory device, comprising: a memory cell array provided on a substrate extending in a first direction and a second direction intersecting the first direction in a first semiconductor layer, the memory cell array including a plurality of cell portions arranged in the second direction and at least two via regions; and a plurality of block selection units included in a second semiconductor layer arranged from the first semiconductor layer along a vertical direction, the plurality of block selection units arranged in the second direction, wherein a spacing between adjacent via regions corresponds to a multiple of a width of each of the plurality of block selection units in the second direction.

9. The semiconductor memory device of claim 8, wherein, Each of the at least two via regions has a width in the second direction that is a multiple of a width of each of the plurality of cell portions in the second direction.

10. The semiconductor memory device according to claim 9, wherein the first semiconductor layer includes: a plurality of main elongated patterns respectively coupled to the plurality of cell portions, and each of the plurality of main elongated patterns extending from a corresponding cell portion along the first direction; and a plurality of dummy elongated patterns coupled to each of the at least two via regions, wherein the plurality of main elongated patterns and the plurality of dummy elongated patterns are arranged in the second direction, and wherein each of the plurality of main elongated patterns and each of the plurality of dummy elongated patterns has the same width in the second direction as each of the plurality of cell portions in the second direction.

11. The semiconductor memory device according to claim 10, wherein each of the plurality of cell portions includes a plurality of electrode layers and a plurality of interlayer dielectric layers alternately laminated, and includes a plurality of vertical channels passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in a vertical direction, and Each of the plurality of main elongated patterns is configured by the plurality of electrode layers and the plurality of interlayer dielectric layers extending along the first direction from the plurality of cell portions.

12. The semiconductor memory device of claim 10, wherein, Each of the plurality of dummy elongated patterns has the same structure as one of the plurality of main elongated patterns, or has a structure symmetrical to one of the plurality of main elongated patterns based on a virtual line extending in the first direction.

13. The semiconductor memory device according to claim 10, wherein The second semiconductor layer further includes: a plurality of transfer transistor groups arranged to overlap the plurality of main elongated patterns in the vertical direction; and a plurality of dummy transfer transistor groups arranged to overlap the plurality of dummy elongated patterns in the vertical direction, wherein the plurality of transfer transistor groups and the plurality of dummy transfer transistor groups are arranged in the second direction, and wherein a width of each of the plurality of dummy transfer transistor groups in the second direction is the same as a width of each of the plurality of transfer transistor groups in the second direction.

14. The semiconductor memory device according to claim 8, wherein, The second semiconductor layer further includes a page buffer circuit including a plurality of page buffer high voltage regions arranged to be spaced apart from each other at intervals in the second direction, and wherein a number of the at least two via regions is the same as a number of the plurality of page buffer high voltage regions.

15. The semiconductor memory device according to claim 11, wherein, a plurality of first slits extending in the first direction and passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in the vertical direction to define and separate the plurality of cell portions and the at least two via regions, wherein each of the plurality of cell portions includes a plurality of channel rows extending in the first direction and arranged in the second direction, the plurality of channel rows passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in the vertical direction, and wherein channel rows of the plurality of channel rows of each of the plurality of cell portions are offset from each other in the first direction.

16. The semiconductor memory device according to claim 15, wherein, a second slit extending in the first direction divides at least one upper layer of the plurality of electrode layers, and wherein in the second slit, a plurality of dummy vertical channels are arranged in the first direction and pass through the plurality of electrode layers and the plurality of interlayer dielectric layers in the vertical direction.

17. The semiconductor memory device according to claim 15, wherein, a second slit extending in the first direction divides at least one upper layer of the plurality of electrode layers, and wherein the second slit has a wave shape that undulates between two adjacent offset channel rows among the plurality of channel rows.

18. The semiconductor memory device according to claim 11, wherein a plurality of first slits extending in the first direction and passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in the perpendicular direction to define and separate the plurality of cell portions and the at least two via regions, wherein each of the plurality of cell portions includes a plurality of channel rows extending in the first direction and arranged in the second direction, the plurality of channel rows passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in the perpendicular direction, and wherein channel rows of the plurality of channel rows of each of the plurality of cell portions are offset from each other in the first direction.

19. The semiconductor memory device of claim 18, wherein a second slit extending in the first direction divides at least one upper layer of the plurality of electrode layers, and wherein in the second slit, a plurality of dummy vertical channels are arranged in the first direction and pass through the plurality of electrode layers and the plurality of interlayer dielectric layers in the perpendicular direction.

20. The semiconductor memory device of claim 18, wherein, a second slit extending in the first direction divides at least one upper layer of the plurality of electrode layers, and wherein the second slit has a wave shape that undulates between two adjacent offset channel rows among the plurality of channel rows.

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