Memory system, method for controlling the refresh of memory device, memory device

Abstract

A memory system, a method for controlling the refresh of a memory device, and a memory device are provided. The memory system includes a memory controller and a memory device. The memory controller periodically generates refresh commands at an average refresh interval. The memory device performs a normal refresh operation and a hammer refresh operation during the refresh cycle time. The memory device includes: a memory cell array including memory cells connected to the plurality of word lines; a temperature sensor configured to provide temperature information by measuring the operating temperature of the memory cell array; and a refresh controller configured to control the normal refresh operation and the hammer refresh operation. The refresh controller changes the hammer rate, which is the number of hammer executions per unit of hammer refresh operation performed during the refresh cycle time relative to the number of normal executions per unit of normal refresh operation performed during the refresh cycle time.

Description

[0001] Cross-reference to related applications

[0002] Korean Patent Application No. 10-2020-0155414, entitled "Memory System Performing Hammer Refresh Operation and Method for Controlling Refresh of Memory Device", filed on November 19, 2020 with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiments generally relate to a semiconductor integrated circuit, and more specifically, to a memory system that performs a hammer refresh operation and a method for controlling the refresh of a memory device. Background Technology

[0004] Semiconductor memory devices used for storing data can be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices, such as Dynamic Random Access Memory (DRAM), store data by charging or discharging capacitors in memory cells, and lose the stored data when power is off. Non-volatile memory devices, such as Flash Memory, retain the stored data even when power is off. Volatile memory devices are widely used as main memory in various devices, while non-volatile memory devices are widely used to store program code and / or data in various electronic devices such as computers, mobile devices, etc.

[0005] In volatile memory devices, the cell charge stored in memory cells can be lost due to leakage current. Additionally, when word lines frequently transition between active and precharge states (e.g., when word lines are accessed intensively or frequently), memory cells connected to word lines adjacent to frequently accessed word lines may be affected and lose their stored charge, potentially leading to data loss. The charge stored in memory cells can be retained by recharging before data loss due to charge leakage occurs. This recharging of cell charge is called a refresh operation, and refresh operations can be repeated before a significant amount of cell charge is lost. Summary of the Invention

[0006] The embodiment relates to a memory system comprising: a memory controller configured to periodically generate refresh commands at an average refresh interval; and a memory device configured to perform a normal refresh operation and a hammer refresh operation during a refresh cycle time starting from the time point at which each refresh command is received, suppressing the generation of other commands during the refresh cycle time, performing the normal refresh operation by sequentially selecting multiple word lines one by one during the refresh cycle time, and performing the hammer refresh operation by selecting a disturbed word line physically adjacent to a hammer word line accessed more frequently than other word lines. The memory device may include: a memory cell array including memory cells connected to the multiple word lines; a temperature sensor configured to provide temperature information by measuring the operating temperature of the memory cell array; and a refresh controller configured to control the normal refresh operation and the hammer refresh operation, and configured to change the hammer rate of the number of hammer executions per unit of hammer refresh operation performed during the refresh cycle time relative to the number of normal executions per unit of normal refresh operation performed during the refresh cycle time.

[0007] The embodiments also relate to a method for controlling the refresh of a memory device, comprising: providing temperature information by measuring the operating temperature of the memory cell array included in the memory device; periodically receiving refresh commands from a memory controller at an average refresh interval; performing normal refresh operations by sequentially selecting multiple word lines one by one during a refresh period; performing hammer refresh operations by selecting a disturbed word line that is physically adjacent to a hammer word line that is accessed more frequently than other word lines; and changing the hammer rate, based on the temperature information, the number of hammer executions per hammer refresh operation performed during the refresh period relative to the number of normal executions per normal refresh operation performed during the refresh period.

[0008] The embodiments also relate to a memory device, the memory device comprising: a memory cell array including memory cells connected to a plurality of word lines; a temperature sensor configured to provide temperature information by measuring the operating temperature of the memory cell array; and a refresh controller configured to control a normal refresh operation and a hammer refresh operation, performing the normal refresh operation by sequentially selecting a plurality of word lines one by one during a refresh period, and performing the hammer refresh operation by selecting an interfering word line physically adjacent to a hammer word line accessed more frequently than other word lines, and the refresh controller is configured to, based on the temperature information, change the hammer rate of the number of hammer executions per hammer operation performed during the refresh cycle time relative to the number of normal executions per normal refresh operation performed during the refresh cycle time. Attached Figure Description

[0009] The features will become clear to those skilled in the art from a detailed description of the exemplary embodiments with reference to the accompanying drawings, wherein:

[0010] Figure 1This is a flowchart illustrating a method for controlling the refresh of a memory device according to an example embodiment.

[0011] Figure 2 This is a diagram illustrating an example of refresh conditions for a memory device according to an example embodiment.

[0012] Figure 3 This is a diagram illustrating an example of setting the temperature level of a memory device according to an example embodiment.

[0013] Figure 4 This is a diagram illustrating an example of register information of a memory device according to an example embodiment.

[0014] Figure 5 This is a timing diagram illustrating an example of a fixed hammer control mode of a memory device according to an example embodiment.

[0015] Figure 6 and Figure 7 This is a diagram illustrating an example of a variable hammer control mode for a memory device according to an example embodiment.

[0016] Figure 8 This is a block diagram illustrating a memory system according to an example embodiment.

[0017] Figure 9 This is a block diagram illustrating a memory device according to an example embodiment.

[0018] Figure 10 It is shown Figure 9 A block diagram of an example embodiment of a refresh controller included in a memory device.

[0019] Figure 11 This is a flowchart illustrating a method for controlling the refresh of a memory device according to an example embodiment.

[0020] Figures 12 to 15 This is a timing diagram illustrating an example of a variable hammer control mode for a memory device according to an example embodiment.

[0021] Figure 16 It is shown Figure 9 A block diagram of an example embodiment of a hammer address manager included in a memory device.

[0022] Figure 17 and Figure 18 It is shown Figure 16 A diagram of an example embodiment of accessing memory included in the hammer address manager.

[0023] Figure 19 This is a diagram illustrating a portion of a memory cell array used to describe data loss due to word line coupling.

[0024] Figure 20 This is a block diagram illustrating a memory device according to an example embodiment.

[0025] Figure 21 and Figure 22 This is a diagram used to describe the hammer refresh operation of a memory device according to an example embodiment.

[0026] Figure 23 and Figure 24 This is a diagram illustrating a stacked memory device according to an example embodiment.

[0027] Figure 25 This is a block diagram illustrating a mobile system according to an example embodiment. Detailed Implementation

[0028] Figure 1 This is a flowchart illustrating a method for controlling the refresh of a memory device according to an example embodiment.

[0029] Reference Figure 1 Temperature information can be provided by measuring the operating temperature of the memory cell array included in the memory device (S100). The operating temperature can be measured using on-chip sensors or other types of sensors located near the memory cell array.

[0030] The memory device can periodically receive refresh commands from the memory controller at an average refresh interval (S200). The memory device can receive refresh commands according to predetermined refresh conditions and perform refresh operations based on the timing of receiving the refresh commands. The following will refer to... Figure 2 Describe refresh conditions such as refresh time period, average refresh interval, and refresh cycle time.

[0031] In a memory device, during the refresh period, a normal refresh operation can be performed by sequentially selecting multiple word lines (S300), and a hammer refresh operation can be performed by selecting a victim word line that is physically adjacent to a hammer word line that is accessed more frequently than other word lines (S400). The following will refer to... Figure 9 and Figure 10 To describe normal refresh operations and hammer refresh operations.

[0032] The hammer rate can be varied based on temperature information (S500). The hammer rate represents the ratio of the number of hammer refresh operations performed per unit during the refresh cycle time to the number of normal refresh operations performed per unit during the refresh cycle time. Normal refresh operations and hammer refresh operations can be performed during the refresh cycle time, starting from the time point when each refresh command is received via the memory device, while other commands can be suppressed during the refresh cycle time.

[0033] Volatile memory devices such as Dynamic Random Access Memory (DRAM) can periodically perform refresh operations due to charge leakage from the memory cells storing data. As DRAM manufacturing processes shrink, the storage capacitance of memory cells can be reduced, thus shortening the refresh period. When the memory capacity of DRAM increases, the refresh period can be shortened further because the overall refresh time increases.

[0034] To compensate for the degradation of adjacent memory cells due to intensive access to specific rows or hammer addresses, a Target Row Refresh (TRR) scheme can be used, and an in-memory refresh scheme can be used to reduce the burden on the memory controller. In this example embodiment, in the TRR scheme, the memory controller is fully responsible for the hammer refresh operation, while in the in-memory refresh scheme, the memory device is fully responsible for the hammer refresh operation. As memory devices evolve to have larger memory capacities and lower power consumption, hammer refresh operations can help prevent data loss in response to hammer events or hammer attacks.

[0035] By changing the hammer rate, which represents the ratio of the number of hammer attacks to the number of normal attacks, based on temperature information, the method for refreshing the memory system and controlling the memory device according to the example embodiment can effectively prevent data loss due to hammer attacks and improve the operational reliability of the memory device and memory system.

[0036] Figure 2 This is a diagram illustrating an example of refresh conditions for a memory device according to an example embodiment.

[0037] Figure 2 The refresh conditions for single-channel synchronous dynamic random access memory (SDRAM) with various densities per channel according to the Low Power Double Data Rate 4 (LPDDR4) standard are shown. As an example, Figure 2 The refresh conditions are shown for temperature levels corresponding to TCASE operating temperatures below or equal to 85°C.

[0038] The refresh period or refresh window tREFW represents the time required to refresh each memory cell or word line. In other words, because the refresh operation is performed on a word line basis, the refresh window tREFW represents the time required to refresh all word lines.

[0039] Here, the refresh cycle time tRFC can be collectively referred to as the refresh cycle time of all memory banks (all memory banks refresh tRFCab) and the refresh cycle time per memory bank (per memory bank refresh tRFCpb). See reference. Figure 2 The refresh conditions can differ depending on whether the refresh is applied to all storage units or per storage unit.

[0040] For example, with 8Gb DDR4 DRAM, when the number of refresh commands in the refresh window tREFW is 8192, the refresh window tREFW is 32ms, the average refresh interval tREFI between two adjacent refresh commands transmitted from the memory controller is approximately 3.904μs, and the refresh cycle time tRFCab is approximately 280ns. Therefore, the memory controller issues refresh commands in an average period of 3.904μs, and the memory device performs the refresh operation within 280ns ​​corresponding to the refresh cycle time tRFCab. In this example embodiment, the issuance of other commands and access to the memory device are suppressed during the refresh cycle time tRFC. Therefore, the time allocated to the refresh cycle time tRFC affects the performance of the memory system.

[0041] Figure 3 This is a diagram illustrating an embodiment of the set temperature level of a memory device according to an example embodiment. Figure 3 Examples are shown to describe exemplary embodiments, but the temperature level settings are not limited to these examples. Figure 3 shown.

[0042] Reference Figure 3 Temperature levels can be set by dividing the operating temperature To of the memory cell array (or memory device including the memory cell array) into multiple temperature ranges. For example, the temperature range between 65°C and 85°C can be set as a high temperature level (TLH), the temperature range between 45°C and 65°C can be set as a medium temperature level (TLM), and the temperature range below 45°C can be set as a low temperature level (TLL). For example, it can be assumed that the memory device will not function properly in a temperature range above 85°C.

[0043] Because the leakage of charge stored in memory cells decreases as the operating temperature To decreases, the refresh window tREFW and the average refresh interval tREFI can be increased as the operating temperature To decreases. For example, refer to Figure 2 The described refresh window tREFW can be 16 ms at high temperature level TLH, 32 ms at medium temperature level TLM, and 64 ms at low temperature level TLL. Therefore, the average refresh interval tREFI can be 3.9 μs at high temperature level TLH, 7.8 μs at medium temperature level TLM, and 15.6 μs at low temperature level TLL.

[0044] Temperature levels can be represented by the value of the temperature code (TCODE). For example, in... Figure 3In this context, a temperature code value of '110' represents a high temperature level (TLH), a temperature code value of '101' represents a medium temperature level (TLM), and a temperature code value of '100' represents a low temperature level (TLL). The temperature sensor in the memory device can convert analog temperature information into a digital temperature code (TCODE) and provide the TCODE to the memory controller and / or refresh controller.

[0045] In the following text, the temperature level corresponding to a relatively high temperature range may be referred to as the first temperature level, and the temperature level corresponding to a relatively low temperature range may be referred to as the second temperature level. For example, the high temperature level THL may be the first temperature level, and the medium temperature level TLM and / or the low temperature level TLL may be the second temperature level. As another example, the medium temperature level THM may be the first temperature level, and the low temperature level TLL may be the second temperature level.

[0046] Figure 4 This is a diagram illustrating register information of a memory device according to an example embodiment.

[0047] For example, the mode register in the mode register set MRS ( Figure 9 412) may have a configuration setting MRSET. Operational values ​​OP7 to OP0 may include mode information MD, hammer rate information HMRT, flag information F, and maximum activity count information MAC. Mode information MD and hammer rate information may be collectively referred to as hammer control information HCINF.

[0048] The mode information MD indicates whether the memory system operates in fixed hammer control mode (FHCM) or variable hammer control mode (VHCM). In the example embodiment, a value of '0' in the mode information MD represents fixed hammer control mode (FHCM), and a value of '1' in the mode information MD represents variable hammer control mode (VHCM). The following will refer to... Figures 5 to 7 Describe the fixed hammer control mode (FHCM) and the variable hammer control mode (VHCM).

[0049] Hammer rate information HMRT may include the hammer rate, which represents the ratio of the number of hammer refresh operations performed per unit during refresh cycle time tRFC to the number of normal refresh operations performed per unit during refresh cycle time tRFC. The memory controller may determine the hammer rate information HMRT based on the operating temperature To of the memory cell array and / or the importance of the data stored in the memory cell array. In an example embodiment, a larger hammer rate information HMRT value may indicate that a larger number of hammer refresh operations are to be performed during each refresh cycle time tRFC.

[0050] The flag information F indicates the validity of the Maximum Activity Count (MAC) information. The Maximum Activity Count (MAC) information indicates the maximum number of active operations allowed for a hammer line (or hammer row) in the refresh window tREFW before refreshing the disturbed word line (or disturbed row) that is physically adjacent to the hammer line.

[0051] The memory controller can generate hammer control information HCINF based on temperature information or temperature code TCODE provided from the memory device, and transmit the hammer control information HCINF using a mode register set (MRS) write command. In Variable Hammer Control Mode (VHCM), the memory device can store the hammer control information HCINF in the mode register, and the refresh controller in the memory device can change the hammer rate based on the hammer control information HCINF stored in the mode register.

[0052] In the following text, refer to Figures 5 to 7 The Fixed Hammer Control Mode (FHCM) and the Variable Hammer Control Mode (VHCM) are described. As described above, the memory controller can generate refresh commands (REF) via the command signal CMD, and during the refresh cycle time tRFC, starting from the time point when each refresh command (REF) is received, the memory device can perform a refresh operation (RFO) including a normal refresh operation (NRO) and a hammer refresh operation (HRO). In the example embodiment, the issuance of other commands is suppressed during the refresh cycle time tRFC.

[0053] For ease of description, based on Figure 3 Example temperature level description Figures 5 to 7 Example implementations. Combined with Figures 5 to 7 The number of normal refresh operations (NRO) and hammer refresh operations (HRO) shown, as well as the values ​​of time (tREFIH, average refresh interval for TLH), (tREFIM, average refresh interval for TLM), (tREFIL, average refresh interval for TLL), and (tRFC, refresh cycle time) are described in the example embodiment.

[0054] Figure 5 This is a timing diagram illustrating an example embodiment of the fixed hammer control mode (FHCM) of a memory device according to an example embodiment.

[0055] Reference Figure 5 In the fixed hammer control mode (FHCM), the memory controller can change the average refresh interval so that the average refresh interval tREFIM (corresponding to the medium temperature level TLM) is longer than the average refresh interval tREFIH (corresponding to the high temperature level TLM), and the average refresh interval tREFIL (corresponding to the low temperature level TLL) is longer than the average refresh interval tREFIM (corresponding to the medium temperature level TLM).

[0056] exist Figure 2 In the example embodiment shown, the refresh window tREFW can be 16 ms at the high temperature level TLH, 32 ms at the medium temperature level TLM, and 64 ms at the low temperature level TLL. The average refresh interval tREFI can be 3.9 μs at the high temperature level TLH (tREFIH), 7.8 μs at the medium temperature level TLM (tREFIM), and 17.6 μs at the low temperature level TLL (tREFIL). Therefore, the number of refresh commands REF included in the respective refresh window tREFW of the high temperature level TLH, the medium temperature level TLM, and the low temperature level TLL can be 8192, and is equal to each other regardless of the temperature level.

[0057] In this way, the memory controller can increase the average refresh interval corresponding to the second temperature level in the lower temperature range, so that it is longer than the average refresh interval corresponding to the first temperature level in the higher temperature range.

[0058] In the fixed hammer control mode (FHCM), regardless of the operating temperature, the refresh controller in the memory device can maintain the number of normal executions (NN) of the normal refresh operation NRO performed during the refresh cycle time tRFC, and the number of hammer executions (NH) of the hammer refresh operation HRO performed during the refresh cycle time tRFC.

[0059] For example, in Figure 5 In the fixed hammer control mode FHCM shown, during the refresh cycle time tRFC, regardless of whether it is the high temperature level TLH, the medium temperature level TLM, or the low temperature level TLL, the number of normal executions NN of the normal refresh operation NRO can be fixed at four, and the number of hammer executions NH of the hammer refresh operation HRO can be fixed at one.

[0060] Figure 6 and Figure 7 This is a diagram illustrating an example embodiment of the variable hammer control mode (VHCM) of a memory device according to an example embodiment.

[0061] Reference Figure 6 and Figure 7 In Variable Hammer Control Mode (VHCM), the memory controller can maintain the average refresh interval tREFI regardless of the operating temperature. In other words, the average refresh interval tREFIH corresponding to the high temperature level TLH, the average refresh interval tREFIM corresponding to the medium temperature level TLM, and the average refresh interval tREFIIL corresponding to the low temperature level TLL can be equal to each other.

[0062] For example, refer to Figure 2The described refresh window tREFW can be 16 ms at the high-temperature level TLH, 32 ms at the medium-temperature level TLM, and 64 ms at the low-temperature level TLL. Conversely, the average refresh intervals tREFIH, tREFIM, and tREFIL can all be set to 3.9 μs, regardless of whether it is the high-temperature level TLH, the medium-temperature level TLM, or the low-temperature level TLL. In this case, the number of refresh commands included in their respective refresh windows tREFW can be 8192 for the high-temperature level TLH, 2 × 8192 for the medium-temperature level TLM, and 4 × 8192 for the low-temperature level TLL.

[0063] Thus, under the variable hammer control mode (VHCM), the memory controller can maintain the average refresh interval tREFI, regardless of whether it corresponds to the first temperature level of the higher temperature range or the second temperature level of the lower temperature range.

[0064] and Figure 5 A comparison of the fixed hammer control mode FHCM shows that when the temperature level corresponds to a lower temperature range... Figure 6 In the example embodiment, the memory controller operating in Variable Hammer Control Mode (VHCM) can pass more refresh commands (REF) in the refresh window (tREFW). With the increased number of refresh commands (REF), the hammer rate (NH / NN) can vary under VHCM (number of hammer executions per unit NH relative to number of normal executions per unit NN).

[0065] In some example embodiments, in the Variable Hammer Control Mode (VHCM), the refresh controller can change the unit normal execution count NN such that the unit normal execution count NN corresponding to the second temperature level is less than the unit normal execution count NN corresponding to the first temperature level, and the unit hammer execution count NH is maintained regardless of whether it is the first or the second temperature level. For example, refer to... Figure 6 When the temperature level corresponds to a lower temperature range, the refresh controller can reduce the number of normal executions per unit NN, making the number of normal executions per unit NN four for the high temperature level TLH, two for the medium temperature level TLM, and one for the low temperature level TLL. Conversely, the number of hammer executions per unit NH can remain one regardless of whether it is the high temperature level TLH, the medium temperature level TLM, or the low temperature level TLL.

[0066] In some example embodiments, in the Variable Hammer Control Mode (VHCM), the refresh controller can change the unit normal execution number NN such that the unit normal execution number NN corresponding to the second temperature level is less than the unit normal execution number NN corresponding to the first temperature level, and change the unit hammer execution number NH such that the unit hammer execution number NH corresponding to the second temperature level is greater than the unit hammer execution number NH corresponding to the first temperature level.

[0067] For example, refer to Figure 7 When the temperature level corresponds to a lower temperature range, the refresh controller can reduce the number of normal executions per unit NN, so that the number of normal executions per unit NN is four for the high temperature level TLH, two for the medium temperature level TLM, and one for the low temperature level TLL. When the temperature level corresponds to a lower temperature range, the number of normal executions per unit NH can be increased, so that the number of normal executions per unit NN is one for the high temperature level TLH, three for the medium temperature level TLM, and four for the low temperature level TLL.

[0068] In this way, the refresh controller can change the hammer rate NH / NN in the variable hammer control mode (VHCM), such that the hammer rate NH / NN corresponding to the second temperature level (i.e., the lower temperature range) is higher than the hammer rate NH / NN corresponding to the first temperature level (i.e., the higher temperature range). Therefore, by using a variable hammer rate NH / NN according to the operating temperature, data loss due to hammer attacks (i.e., frequent access to memory cells or word lines) stored in memory cells can be effectively prevented. This improves the operational reliability of memory devices and memory systems.

[0069] In some example embodiments, under the variable hammer control mode (VHCM), the refresh controller can change the hammer rate NH / NN based on temperature information provided from a temperature sensor.

[0070] In some example embodiments, the refresh controller can change the hammer rate NH / NN based on the hammer control information HCINF provided from the memory controller. The memory controller can use the mode register set (MRS) to write commands that transmit the hammer control information HCINF based on temperature information provided from the memory device, and the memory device can store the hammer control information HCINF in the storage mode register set (see...). Figure 9 The mode register included in 412). See reference... Figure 4 The description states that the hammer control information HCINF may include mode information MD and hammer rate information HMRT.

[0071] Figure 8 This is a block diagram illustrating a memory system according to an example embodiment.

[0072] Reference Figure 8The memory system 10 may include a memory controller 200 and a memory device 400. The memory controller 200 and the memory device 400 may include various interfaces for communicating with each other. These interfaces may be connected via a control bus 21 for transmitting commands (CMD), addresses (ADDR), clock signals (CLK), etc., and a data bus 22 for transmitting data (DATA). According to some standards for memory devices, the address (ADDR) may be included in the command (CMD). The memory controller 200 may generate commands (CMD) to control the memory device 400, and data may be written to or read from the memory device 400 under the control of the memory controller 200.

[0073] Memory device 400 may include a refresh controller RFCON 100, a hammer address manager HMMAG 300, and a temperature sensor TSEN 700. The hammer address manager 300 can comprehensively manage access addresses for multiple memory banks of memory device 400 and can provide hammer addresses for hammer refresh operations from the access addresses, where the hammer addresses are the addresses that are frequently accessed. The refresh controller 100 can generate hammer refresh address signals based on the hammer addresses, where the hammer refresh address signals represent the rows (or sacrificial word lines) that are physically adjacent to the row (or hammer word line) corresponding to the hammer address.

[0074] Temperature sensor 700 provides temperature information by measuring the operating temperature of the memory cell array included in memory device 400. Temperature sensor 700 can convert analog temperature information into a digital temperature code TCODE and provide the temperature code TCODE to memory controller 200 and / or refresh controller 100. Memory controller 200 can generate hammer control information HCINF based on the temperature code TCODE and can provide the hammer control information HCINF to memory device 400.

[0075] Figure 9 This is a block diagram illustrating a memory device according to an example embodiment.

[0076] Reference Figure 9 The memory device 400 may include control logic 410, address register 420, memory bank control logic 430, row selection circuitry 460 (or row decoder), column decoder 470, memory cell array 480, sense amplifier unit 485, input / output (I / O) gating circuitry 490, data input / output (I / O) buffer 495, refresh controller 100, hammer address manager 300, temperature sensor TSEN 700, and code generator CGEN 800. As used herein, "cell" may be referred to as "circuit".

[0077] The memory cell array 480 may include multiple memory bank arrays 480a to 480h. The row selection circuit 460 may include multiple memory bank row selection circuits 460a to 460h respectively coupled to the memory bank arrays 480a to 480h. The column decoder 470 may include multiple memory bank column decoders 470a to 470h respectively coupled to the memory bank arrays 480a to 480h. The sense amplifier unit 485 may include multiple memory bank sense amplifiers 485a to 485h respectively coupled to the memory bank arrays 480a to 480h.

[0078] Address register 420 can receive address ADDR, including bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from memory controller 200. Address register 420 can provide the received bank address BANK_ADDR to memory control logic 430, the received row address ROW_ADDR to row selection circuit 460, and the received column address COL_ADDR to column decoder 470.

[0079] The memory bank control logic 430 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. One of the memory bank row selection circuits 460a to 460h corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal, and one of the memory bank column decoders 470a to 470h corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal.

[0080] The row address ROW_ADDR from address register 420 can be applied to the bank row selection circuits 460a to 460h. An active bank row selection circuit 460a to 460h can decode the row address ROW_ADDR and activate the word line corresponding to the row address ROW_ADDR. For example, the active bank row selection circuit 460 can apply a word line drive voltage to the word line corresponding to the row address ROW_ADDR.

[0081] Column decoder 470 may include a column address latch. The column address latch may receive a column address COL_ADDR from address register 420 and may temporarily store the received column address COL_ADDR. In some example embodiments, in burst mode, the column address latch may generate a column address incremented from the received column address COL_ADDR. The column address latch may apply the temporarily stored or generated column address to memory column decoders 470a to 470h.

[0082] One of the active memory column decoders 470a to 470h can decode column address COL_ADDR and can control I / O gate circuit 490 to output data corresponding to column address COL_ADDR.

[0083] I / O gating circuit 490 may include a circuit system for gating input / output data. I / O gating circuit 490 may also include a read data latch for storing data output from memory arrays 480a to 480h and a write driver for writing data to memory arrays 480a to 480h.

[0084] Data to be read from one of the memory arrays 480a to 480h can be coupled to a memory sense amplifier 485a to 485h from which the data will be read and sensed, and can be stored in a read data latch. The data stored in the read data latch can be provided to the memory controller 200 via a data I / O buffer 495. Data DQ to be written to one of the memory arrays 480a to 480h can be provided from the memory controller 200 to the data I / O buffer 495. A write driver can write data DQ to one of the memory arrays 480a to 480h.

[0085] Control logic 410 can control the operation of memory device 400. For example, control logic 410 can generate control signals for memory device 400 to perform write operations, read operations, or refresh operations. Control logic 410 can be based on... Figure 8 The memory controller 200 transmits commands (CMD) that generate internal command signals such as the active signal IACT, the precharge signal IPRE, the refresh signal IREF, the read signal IRD, and the write signal IWR. The control logic 410 may include a command decoder 411 that decodes the commands (CMD) received from the memory controller 200 and a mode register set 412 that sets the operating mode of the memory device 400.

[0086] Although Figure 9 The control logic 410 and address register 420 are shown to be separate from each other, but the control logic 410 and address register 420 can be implemented as a single integrated circuit. Furthermore, although... Figure 9 The diagram shows that the command CMD and address ADDR are set to separate signals, but the command CMD and address ADDR can be set to a combined signal (as specified in the LPDDR5 standard).

[0087] The hammer address manager 300 can comprehensively manage access addresses for the plurality of memory arrays 480a to 480h based on the bank address BANK_ADDR and the row address ROW_ADDR, and can provide a hammer address HADD for hammer refresh operations in the access addresses, where the hammer address HADD is the address that is accessed intensively. The refresh controller 100 can generate a hammer refresh address signal based on the hammer address HADD, where the hammer refresh address signal represents the row (e.g., the interfering word line) that is physically adjacent to the row (e.g., the hammer word line) corresponding to the hammer address HADD.

[0088] Temperature sensor 700 can generate temperature information TINF by measuring the operating temperature of memory cell array 480. Code generator 800 can generate temperature code TCODE by converting the temperature information TINF. Temperature sensor 700 may be an on-chip sensor integrated adjacent to memory cell array 480 or other types of temperature sensors. Temperature information TINF may be an analog signal, and code generator 800 may include an analog-to-digital converter for converting the analog signal into digital data. In some example embodiments, code generator 800 may include... Figure 8 The temperature sensor 700 or the memory controller 200 are used in the system.

[0089] Reference Figure 8 and Figure 9 In some example embodiments, the temperature code TCODE may be stored in a mode register in the mode register set 412 and may be provided to the memory controller 200 via the data bus 22 via an MRS read command. In some example embodiments, the temperature code TCODE may be provided to the memory controller 200 via a different signal line than the control bus 21 and the data bus 22.

[0090] As described above, the memory controller 200 can generate hammer control information HCINF, including mode information MD and hammer rate information HMRT, based on the temperature code TCODE. The memory controller 200 can transmit the hammer control information HCINF to the memory device 400 via the data bus 22 using an MRS write command. The control logic 410 in the memory device 400 can store the hammer control information HCINF in a mode register of the mode register set 412. The control logic 410 can provide the hammer control information HCINF (that is, the mode information MD and the hammer rate information HMRT) to the refresh controller 100. The refresh controller 100 can change the hammer rate NH / NN in the variable hammer control mode VHCM based on the hammer control information HCINF, as described above.

[0091] Figure 10 It is shown Figure 9A block diagram of an example embodiment of a refresh controller 100 included in a memory device 400.

[0092] Reference Figure 10 The refresh controller 100 may include a timing controller 110, a refresh counter 120, an address generator 130, and a hammer rate adjuster 170.

[0093] Hammer rate adjuster 170 can determine the hammer rate NH / NN relative to the unit normal execution number NN based on temperature information TINF and / or hammer control information HCINF. Hammer rate adjuster 170 can provide the unit normal execution number NN and the unit hammer execution number NH corresponding to the determined hammer rate NH / NN to timing controller 110. (Refer to the following...) Figure 11 An example embodiment of hammer rate adjuster 170 is described. Hammer rate adjuster 170 may receive temperature code TCODE instead of temperature information TINF.

[0094] The timing controller 110 can generate a counter refresh signal CREF (representing the timing of receiving the refresh command REF), a hammer refresh signal HREF (representing the timing of the normal refresh operation), and a hammer refresh signal HREF (representing the timing of the hammer refresh operation) based on the refresh signal IEF (representing the timing of receiving the refresh command REF), the number of normal executions per unit NN, and the number of hammer executions per unit NH. See below for reference. Figures 12 to 15 As described, the timing controller 110 can selectively activate the counter refresh signal CREF or the hammer refresh signal HREF.

[0095] Reference Figure 10 In some example embodiments, timing controller 110 may be included in refresh controller 100. In other example embodiments, timing controller 110 may be omitted from refresh controller 100, and the counter refresh signal CREF and hammer refresh signal HREF may be provided from other control logic in memory device 400.

[0096] Refresh counter 120 can generate a refresh address signal CRFADD in response to a refresh signal CREF. The refresh address signal CRFADD can indicate a sequential address change. For example, refresh counter 120 can increment the value of the refresh address signal CRFADD each time the refresh signal CREF is activated. Increasing the value of the refresh address signal CRFADD allows for sequential selection of word lines in the memory cell array 480 of the memory device 400 for refresh operations.

[0097] Address generator 130 can store the hammer address HADD provided from hammer address manager 300, and can generate the hammer refresh address signal HRFADD synchronously with the hammer refresh signal HREF. The hammer refresh address signal HRFADD can represent the address of the row that is physically adjacent to the row corresponding to the hammer address HADD. Address generator 130 may include hammer address storage 140 and mapper 150.

[0098] Hammer address memory 140 can store the hammer address HADD provided from hammer address manager 300. Mapper 150 can generate a hammer refresh address signal HRFADD based on the hammer address HADD provided from hammer address memory 140. In some example embodiments, hammer address memory 140 may be omitted, and mapper 150 may receive the hammer address HADD directly from hammer address manager 300. (Refer to the following...) Figure 19 As described, the hammer refresh address signal HRFADD can represent the address of the row in memory device 400 that is physically adjacent to the row in memory device 400 corresponding to the hammer address HADD.

[0099] Figure 11 This is a flowchart illustrating a method for controlling the refresh of a memory device according to an example embodiment.

[0100] Reference Figure 10 and Figure 11 The refresh controller 100 can determine whether the current operating mode (MD) is a fixed hammer control mode (FHCM) or a variable hammer control mode (VHCM) based on the mode information (S10).

[0101] When the current operating mode is Fixed Hammer Control Mode (FHCM), the hammer rate adjuster 170 can provide a fixed unit normal execution number NN and a unit hammer execution number NH to the timing controller 110 (S20). See reference... Figure 5 As described, during each refresh cycle time tRFC in the fixed hammer control mode FHCM, the memory device can perform a normal refresh operation NRO corresponding to a fixed number of normal executions NN and a hammer refresh operation HRO corresponding to a fixed number of hammer executions NH (S80).

[0102] When the current operating mode (MD) is the variable hammer control mode (VHCM), the hammer rate adjuster 170 can receive temperature information TINF and hammer rate information HMRT (S30), and determine the unit normal execution number NN, the target hammer execution number TNH, and the available hammer execution number ANH (S40). The target hammer execution number TNH represents the number of hammer refresh operations (HROs) to be executed during the refresh cycle time tRFC. The available hammer execution number ANH represents the number of hammer refresh operations (HROs) that can be executed during the refresh cycle time tRFC.

[0103] The target hammer execution number TNH can be determined based on the hammer rate information HMRT included in the hammer control information HCINF.

[0104] The memory controller 200 can determine the hammer rate information HMRT based on the operating temperature of the memory cell array 480 and / or the importance of the data stored in the memory cell array 480. For example, a larger hammer rate information HMRT value may represent a larger number of hammer refresh operations HRO to be executed during each refresh cycle time tRFC. The available hammer execution count ANH may correspond to the difference between the number of normal executions per unit NN and the total number of refresh operations that can be executed during each refresh cycle time tRFC.

[0105] The hammer rate adjuster 170 can compare the target hammer execution count TNH with the available hammer execution count ANH (S50). When the target hammer execution count TNH is greater than the available hammer execution count ANH (S50: Yes), the hammer rate adjuster 170 can determine the available hammer execution count ANH as the unit hammer execution count NH (S60), and when the target hammer execution count TNH is equal to or less than the available hammer execution count ANH (S50: NO), it can determine the target hammer execution count TNH as the unit hammer execution count NH (S70). See reference... Figure 6 and Figure 7 As described, in the variable hammer control mode (VHCM), the memory device can perform a normal refresh operation NRO (corresponding to a unit number of normal executions NN) and a hammer refresh operation HRO (corresponding to a unit number of hammer executions NH) during each refresh cycle time tRFC (S80).

[0106] Figures 12 to 15 This is a timing diagram illustrating an example embodiment of a variable hammer control mode for a memory device according to an example embodiment. For ease of illustration, Figures 12 to 15 The operation corresponding to an average refresh interval tREFI between two adjacent refresh commands REF is shown.

[0107] Reference Figures 10 to 15 The timing controller 110 can generate a refresh clock signal RFCLK in response to a refresh signal IREF representing the timing of receiving a refresh command REF. The refresh clock signal RFCLK can toggle the number of refresh operations that can be performed within the refresh cycle time tRFC. For each of the high temperature level TLH, medium temperature level TLM, and low temperature level TLL, the timing controller 110 can synchronously generate a counter refresh signal CREF (representing the timing of a normal refresh operation NRO) and a hammer refresh signal HREF (representing the timing of a hammer refresh operation HRO) with the refresh clock signal RFCLK. The number of toggles of the counter refresh signal CREF can correspond to a unit of normal execution count NN. The number of toggles of the hammer refresh signal HREF can correspond to a unit of hammer execution count NN.

[0108] Figure 12 and Figure 13 The operation corresponds to the above reference. Figure 6 The description of the operation under the variable hammer control mode (VHCM) and Figure 14 and Figure 15 The operation corresponds to the above reference. Figure 7 The description of the operation in the Variable Hammer Control Mode (VHCM) is as follows. In the following text, the details may be omitted. Figure 6 and Figure 7 Repeated description.

[0109] Reference Figure 12 In some example embodiments, the timing controller 110 may change the operating interval representing the time interval between two adjacent refresh operations, such that the operating interval tRFOIM (corresponding to the medium temperature level TLM) is longer than the operating interval tRFOIH (corresponding to the high temperature level TLM), and the operating interval tRFOIL (corresponding to the low temperature level TLL) is longer than the operating interval tRFOIM (corresponding to the medium temperature level TLM). Therefore, the timing controller 110 in the refresh controller 100 may change the operating interval such that the operating interval corresponding to the second temperature level (i.e., the lower temperature range) is longer than the operating interval corresponding to the first temperature level (i.e., the higher temperature range).

[0110] Reference Figure 12 The refresh cycle times tRFCH (corresponding to high temperature level TLH), tRFCM (corresponding to medium temperature level TLM), and tRFCL (corresponding to low temperature level TLL) can be equal to each other. Therefore, in the variable hammer control mode VHCM, the timing controller 110 can maintain the refresh cycle time regardless of the temperature level.

[0111] Reference Figure 12 In some example embodiments, the timing controller 110 can maintain operating intervals such that operating interval tRFOIH (corresponding to high temperature level TLH), operating interval tRFOIM (corresponding to medium temperature level TLM), and operating interval tRFOIL (corresponding to low temperature level TLL) are equal to each other. Therefore, in the variable hammer control mode VHCM, the timing controller 110 can maintain operating intervals regardless of the temperature level.

[0112] Reference Figure 13The refresh cycle time tRFCM (corresponding to the medium temperature level TLM) can be shorter than the refresh cycle time tRFCH (corresponding to the high temperature level THL), and the refresh cycle time tRFCL (corresponding to the low temperature level TLL) can be shorter than the refresh cycle time tRFCM (corresponding to the medium temperature level TLM). Therefore, the timing controller 110 can reduce the refresh cycle time for temperature levels in the lower temperature range. In other words, in the variable hammer control mode VHCM, the timing controller 110 can change the refresh cycle time such that the refresh cycle time tRFC corresponding to the second temperature level (i.e., the lower temperature range) is shorter than the refresh cycle time tRFC corresponding to the first temperature level (i.e., the higher temperature range). The time loss for refresh operations can be reduced by decreasing the refresh cycle time tRFC according to the temperature level, and the performance of the memory device and memory system can be improved.

[0113] Reference Figure 14 In some example embodiments, a normal refresh operation NRO (corresponding to a unit normal execution number NN) can be performed, and then a hammer refresh operation HRO (corresponding to a unit hammer execution number NH) can be performed after the normal refresh operation NRO.

[0114] Reference Figure 15 In some other example embodiments, the order of the Normal Refresh Operation (NRO) and the Hammer Refresh Operation (HRO) may be changed.

[0115] In the following text, refer to Figures 16 to 18 describe Figure 9 Example implementation of the hammer address manager 300.

[0116] Figure 16 It is shown Figure 9 A block diagram of an example embodiment of the hammer address manager 300 included in the memory device 400, and Figure 17 and Figure 18 It is shown Figure 16 A diagram of an example embodiment of the access memory 320 included in the hammer address manager 300.

[0117] Reference Figure 16 The hammer address manager 300 may include an access memory 320 and a storage controller 340.

[0118] Access memory 320 can store information about the hammer address HADD that is accessed intensively or frequently. (See reference...) Figure 17In some example embodiments, the access memory 320a may include a plurality of memory cells SU1 to SUk. Each memory cell SUi (i = 1 to k) may include: a bank register BREGI for storing the bank address of each access address; a row register RREGI for storing the row address of each access address; and a counter register CREGI for storing each access count value.

[0119] The storage controller 340 can control access to the memory 320 based on the access address signals BANK_ADDR and ROW_ADDR transmitted from the memory controller 200 to the memory device 400. The access address may include the bank address signal BANK_ADDR and the row address signal ROW_ADDR. The storage controller 340 can determine and provide the hammer address HADD from the stored access addresses based on the access count value. The management scheme for the hammer address HADD used by the storage controller 340 can be determined according to different memory systems.

[0120] Reference Figure 18 In some example embodiments, accessing the memory 320b may include a plurality of memory blocks SBK_A 321, SBK_B 322, SBK_C 323 and SBK_D 324, and each of memory blocks 321 to 324 may include a plurality of memory cells SU1 to SUk. Figure 18 A non-limiting example of an access memory 320b corresponding to four memory banks A, B, C, and D is shown, but the number of memory blocks may vary depending on the configuration of the memory device. For example, if the memory device has a single-bank structure, the access memory 320b may include only one memory block 321. Memory blocks 321 to 324 may have substantially the same configuration; therefore, only memory block 321 will be described.

[0121] Each of the storage units SU1 to SUk may include address registers AREG1 to AREGk that store the accessed row address and count registers CREG1 to CREGk that store the access count value corresponding to the row address.

[0122] Figure 16 The storage controller 340 can control access to the memory 320 based on access address signals passed from the refresh controller 100 to the memory device. The access address signals may include a bank address (BADD) and a row address (XADD). If the memory device has a single memory bank, the bank address (BADD) may be omitted. The storage controller 340 can determine and provide the hammer address (HADD) in the stored access address based on an access count value.

[0123] Figure 19This is a diagram illustrating a portion of a memory cell array used to describe data loss due to word line coupling.

[0124] Figure 19 The diagram illustrates five word lines WLs-2, WLs-1, WLs, WLs+1, and WLs+2, three bit lines BLp-1, BLp, and BLp+1, and a memory cell MC coupled to the word lines WLs-2, WLs-1, WLs, WLs+1, and WLs+2, and the bit lines BLp-1, BLp, and BLp+1. The five word lines WLs-2, WLs-1, WLs, WLs+1, and WLs+2 extend in the row direction (e.g., the X direction) and are arranged sequentially along the column direction (e.g., the Y direction). The three bit lines BLp-1, BLp, and BLp+1 extend in the column direction and are arranged sequentially along the row direction.

[0125] In the example embodiment, the intermediate word line WLs may correspond to the densely accessed hammer address HADD. It should be understood that a densely accessed word line or hammer word line refers to a word line with a relatively high number of activations and / or a relatively high activation frequency (e.g., greater than a predetermined threshold or greater than other access addresses). Whenever a hammer word line (e.g., the intermediate word line WLs) is accessed, the hammer word line WLs is enabled and precharged, and the voltage level of the hammer word line WLs increases and decreases. Word line coupling can cause the voltage levels of adjacent word lines WLs-2, WLs-1, WLs+1, and WLs+2 to fluctuate with the voltage level of the hammer word line WLs. Therefore, the cell voltage of the memory cell MC coupled to adjacent word lines WLs-2, WLs-1, WLs+1, and WLs+2 may be affected. As the word line WLs is accessed more frequently, the cell charge of the memory cell MC connected to the adjacent word lines WLs-2, WLs-1, WLs+1, and WLs+2 may be lost more quickly.

[0126] Figure 10The address generator 130 can provide hammer refresh address signals HRFADD representing addresses HRFADDa, HRFADDb, HRFADDc, and HRFADDd of rows (e.g., word lines WLs-1, WLs+1, WLs-2, and WLs+2) physically adjacent to the row (e.g., the middle word line WLs) of hammer address HADD. Hammer refresh operations for adjacent word lines WLs-1, WLs+1, WLs-2, and WLs+2 can be performed based on (e.g., in response to) the hammer refresh address signals HRFADD to reduce or potentially prevent the loss of data stored in memory cells MC. Hammer refresh operations can be performed for the two word lines WLs-1 and WLs+1 immediately adjacent to the hammer word line WLs, or for the four word lines WLs-2, WLs-1, WLs+1, and WLs+2 including the next adjacent word lines WLs-2 and WLs+2.

[0127] Figure 20 This is a block diagram illustrating a memory device according to an example embodiment. Figure 20 This describes an example embodiment for comprehensively managing access addresses for multiple memory banks, and Figure 20 The middle part is omitted Figure 9 Some of the components.

[0128] Reference Figure 20 The memory device 501 has a memory cell array comprising a plurality of memory banks 531, 532, 533 and 534 (BNK1 to BNK4) in a multi-bank configuration. The refresh controller 101 according to an example embodiment may include a timing controller 111, a refresh counter 121, and an address generator including a plurality of sub-address generators 131, 132, 133 and 134.

[0129] The timing controller 111 can generate selectively activated counter refresh signals CREF and HREF based on the refresh signal IEF. The refresh counter 121 can generate a counter refresh address signal CRFADD in response to the counter refresh signal CREF, such that the counter refresh address signal CRFADD indicates a sequential address change. Sub-address generators 131, 132, 133, and 134 can receive a hammer address HADD provided from the hammer address manager 300 and generate hammer refresh address signals HRFADD1, HRFADD2, HRFADD3, and HRFADD4 corresponding to memory banks 531, 532, 533, and 534, respectively. The counter refresh signal CREF, the hammer refresh signal HREF, and the counter refresh address signal CRFADD can be jointly provided to memory banks 531, 532, 533, and 534, for example, to the corresponding row selection circuits 541, 542, 543, and 544. In some example embodiments, reference will be made below. Figure 21Described, the hammer refresh address signals HRFADD1, HRFADD2, HRFADD3, and HRFADD4 provided to memory banks 531, 532, 533, and 534 may be the same. In some other example embodiments, reference will be made below. Figure 22 Described, the hammer refresh address signals HRFADD1, HRFADD2, HRFADD3 and HRFADD4 provided to memory banks 531, 532, 533 and 534 can be determined independently.

[0130] Figure 21 and Figure 22 This is a diagram used to describe the hammer refresh operation of a memory device according to an example embodiment.

[0131] Reference Figure 20 and Figure 21 At the activation time point th of the hammer refresh signal HREF, the hammer refresh address signal HRFADD, representing the refresh address Rap, can be jointly provided to memory banks 531, 532, 533, and 534. Therefore, memory cells included in rows with addresses corresponding to the hammer refresh address signal HRFADD can be refreshed simultaneously in all memory banks 531, 532, 533, and 534.

[0132] Reference Figure 20 and Figure 22 At the activation time th of the hammer refresh signal HREF, hammer refresh address signals HRFADD1, HRFADD2, HRFADD3, and HRFADD4, representing refresh addresses RAa, Rab, Rac, and Rad respectively, can be provided to memory banks 531, 532, 533, and 534. Therefore, in each memory bank 531, 532, 533, and 534 corresponding to their respective hammer refresh address signals HRFADD1, HRFADD2, HRFADD3, and HRFADD4, memory cells included in rows with different refresh addresses RAa, Rab, Rac, and Rad can be refreshed simultaneously.

[0133] Figure 23 and Figure 24 This is a diagram illustrating a stacked memory device according to an example embodiment.

[0134] Reference Figure 23 The semiconductor memory device 900 may include a first semiconductor integrated circuit layer LA1 (910) to a k-th semiconductor integrated circuit layer LAk (920), wherein it is assumed that the bottommost first semiconductor integrated circuit layer LA1 is an interface or control chip, and it is assumed that the other semiconductor integrated circuit layers LA2 to LAk are slave chips including a core memory chip. The slave chips may form the aforementioned plurality of memory storage blocks.

[0135] The first semiconductor integrated circuit layer LA1 to the k-th semiconductor integrated circuit layer LAk can transmit and receive signals between the layers via substrate through-holes (TSVs, e.g., silicon through-holes). The bottommost first semiconductor integrated circuit layer LA1, which serves as an interface or control chip, can communicate with an external memory controller through conductive structures formed on its external surface.

[0136] Each of the first semiconductor integrated circuit layers LA1 910 to the k-th semiconductor integrated circuit layers LAk 920 may include a memory region 921 and peripheral circuitry 922 for driving the memory region 921. For example, the peripheral circuitry 922 may include row drivers for word lines for driving the memory, column drivers for bit lines for driving the memory, data input-output circuitry for controlling data input-output, a command buffer for receiving commands from external sources and buffering commands, and an address buffer for receiving addresses from external sources and buffering addresses.

[0137] The first semiconductor integrated circuit layer LA1 910 may also include control circuitry. The control circuitry may control access to memory region 921 based on command and address signals from the memory controller, and may generate control signals for accessing memory region 921.

[0138] Each of the semiconductor integrated circuit layers LA2 to LAk corresponding to the slave layer may include the refresh control circuit described above. The refresh control circuit may selectively execute either the fixed hammer control mode FHCM or the variable hammer control mode VHCM as described above.

[0139] Figure 24 An example high-bandwidth memory (HBM) organization is shown. (See reference...) Figure 24 The HBM 1100 can be stacked with multiple DRAM semiconductor dies 1120, 1130, 1140, and 1150. The stacked HBM structure can be optimized through multiple independent interfaces (i.e., channels). Each DRAM stack can support up to eight channels according to the HBM standard. Figure 24 An example stack is shown, comprising four DRAM semiconductor dies 1120, 1130, 1140 and 1150, with each DRAM semiconductor die supporting two channels, CHANNEL0 and CHANNEL1.

[0140] Each channel provides independent access to a separate set of DRAM memory. A request from one channel can bypass access to data attached to different channels. Channels are timed independently and do not require synchronization.

[0141] The HBM 1100 may also include an interface die 1110 or a logic die at the bottom of the stacked structure to provide signal routing and other functions. Some functions used in the DRAM semiconductor dies 1120, 1130, 1140, and 1150 may be implemented in the interface die 1110.

[0142] Each of the DRAM semiconductor dies 1120, 1130, 1140, and 1150 may include the refresh control circuit described above. The refresh control circuit may selectively execute either the fixed hammer control mode (FHCM) or the variable hammer control mode (VHCM) as described above.

[0143] Figure 25 This is a block diagram illustrating a mobile system according to an example embodiment.

[0144] Reference Figure 25 The mobile system 1200 may include an application processor (AP) 1210, a connectivity unit 1220, a volatile memory device (VM) 1230, a non-volatile memory device (NVM) 1240, a user interface 1250, and a power supply 1260. In some embodiments, the mobile system 1200 may be, for example, a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, or other types of electronic devices.

[0145] Application processor 1210 can execute applications, such as web browsers, game applications, video players, etc. Connection unit 1220 can perform wired or wireless communication with external devices. Volatile memory device 1230 can store data processed by application processor 1210, or can operate as working memory. Non-volatile memory device 1240 can store a startup image for booting mobile system 1200. User interface 1250 may include at least one input device (such as a keypad, touchscreen, etc.) and at least one output device (such as a speaker, display device, etc.). Power supply 1260 can supply power voltage to mobile system 1200.

[0146] As described above, the memory device according to the example embodiment may include a refresh controller RFCON 100 and a hammer address manager HMMAG 300. The hammer address manager 300 can comprehensively manage access addresses for the plurality of memory banks and provide hammer addresses from the access addresses for hammer refresh operations, where the hammer addresses are addresses that are frequently accessed. The refresh controller 100 can generate hammer refresh address signals based on the hammer addresses, where the hammer refresh address signals represent rows that are physically adjacent to the row corresponding to the hammer address. According to the example embodiment, the refresh control circuitry can selectively execute either a fixed hammer control mode (FHCM) or a variable hammer control mode (VHCM) as described above.

[0147] In some example embodiments, the hammer address manager 300 may be included in the memory controller of the application processor 1210, and the refresh controller 100 may be included in the volatile memory device 1230.

[0148] As described above, the memory system and the method for controlling the refresh of the memory device according to the example embodiment can effectively prevent data loss due to hammer attacks, and can improve the operational reliability of the memory device and memory system by changing the hammer rate (representing the ratio of the number of hammer executions per unit to the number of normal executions per unit) based on temperature information.

[0149] The embodiments described herein can be applied to any memory device and system including a memory device that employs refresh operations. For example, the embodiments can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMC), mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptops, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Things (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, server systems, automotive devices, and the like.

[0150] As described above, the exemplary embodiments can provide a memory device and a memory system capable of efficiently performing hammer refresh operations. The exemplary embodiments can provide a method for controlling the refresh of a memory device capable of efficiently performing hammer refresh operations.

[0151] The memory system and method for controlling the refresh of the memory device according to the example embodiment can effectively prevent data loss due to hammer attacks and enhance the operational reliability of the memory device and memory system by changing the hammer rate (representing the ratio of the number of hammer executions per unit to the number of normal executions per unit) based on temperature information.

[0152] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limitation. In some instances, unless expressly indicated otherwise, it will be apparent to those skilled in the art upon filing this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A memory system, comprising: The memory controller is configured to periodically generate refresh commands at an average refresh interval; as well as A memory device configured to perform a normal refresh operation and a hammer refresh operation during a refresh cycle time starting from the time point at which each refresh command is received, suppressing the generation of other commands during the refresh cycle time, performing the normal refresh operation by sequentially selecting multiple word lines one by one during the refresh period, and performing the hammer refresh operation by selecting an interfering word line that is physically adjacent to a hammer word line that is accessed more frequently than other word lines, wherein the memory device includes: A memory cell array comprising memory cells connected to the plurality of word lines; A temperature sensor, configured to provide temperature information by measuring the operating temperature of the memory cell array; and A refresh controller is configured to control the normal refresh operation and the hammer refresh operation, and is configured to change the hammer rate of the number of hammer executions per unit of the hammer refresh operation performed during the refresh cycle time relative to the number of normal executions per unit of the normal refresh operation performed during the refresh cycle time.

2. The memory system according to claim 1, wherein: The memory controller is configured to set a first temperature level and a second temperature level, wherein the operating temperature of the memory cell array is higher at the first temperature level than at the second temperature level. The memory controller is configured to maintain the average refresh interval in variable hammer control mode regardless of the first temperature level and the second temperature level.

3. The memory system according to claim 2, wherein, The refresh controller is configured to change the hammer rate based on temperature information provided from the temperature sensor in the variable hammer control mode.

4. The memory system according to claim 2, wherein: The memory controller is configured to transmit hammer control information using mode register set write commands based on temperature information provided from the memory device. The memory device is configured to store the hammer control information in a mode register, and The refresh controller is configured to change the hammer rate in the variable hammer control mode based on hammer control information stored in the mode register.

5. The memory system according to claim 2, wherein, The refresh controller is configured to change the hammer rate in the variable hammer control mode such that the hammer rate corresponding to the second temperature level is higher than the hammer rate corresponding to the first temperature level.

6. The memory system according to claim 2, wherein: The refresh controller is configured to change the unit normal execution count in the variable hammer control mode such that the unit normal execution count corresponding to the second temperature level is less than the unit normal execution count corresponding to the first temperature level, and The refresh controller is configured to maintain the number of unit hammers executed regardless of the first temperature level and the second temperature level in the variable hammer control mode.

7. The memory system according to claim 6, wherein, The refresh controller is configured to change the operation interval, which represents the time interval between two adjacent refresh operations, such that the operation interval corresponding to the second temperature level is longer than the operation interval corresponding to the first temperature level.

8. The memory system according to claim 7, wherein, The memory controller is configured to maintain the refresh cycle time regardless of the first temperature level and the second temperature level in the variable hammer control mode.

9. The memory system according to claim 6, wherein, The refresh controller is configured to maintain an operating interval regardless of the first temperature level and the second temperature level in the variable hammer control mode, the operating interval representing the time interval between two adjacent refresh operations.

10. The memory system according to claim 9, wherein, The memory controller is configured to change the refresh cycle time in the variable hammer control mode such that the refresh cycle time corresponding to the second temperature level is shorter than the refresh cycle time corresponding to the first temperature level.

11. The memory system according to claim 2, wherein: The refresh controller is configured to change the unit normal execution count in the variable hammer control mode such that the unit normal execution count corresponding to the second temperature level is less than the unit normal execution count corresponding to the first temperature level, and The refresh controller is configured to change the number of hammer executions per unit in the variable hammer control mode, such that the number of hammer executions per unit corresponding to the second temperature level is greater than the number of hammer executions per unit corresponding to the first temperature level.

12. The memory system according to claim 2, wherein, The refresh controller is configured to compare the target number of hammer executions for hammer refresh operations to be performed during the refresh cycle time with the available number of hammer executions for hammer refresh operations that can be performed during the refresh cycle time, and to determine the available number of hammer executions as the unit hammer executions when the target number of hammer executions is greater than the available number of hammer executions, and to determine the target number of hammer executions as the unit hammer executions when the target number of hammer executions is less than the available number of hammer executions.

13. The memory system according to claim 2, wherein, The memory controller is configured to change the average refresh interval in a fixed hammer control mode, such that the average refresh interval corresponding to the second temperature level is longer than the average refresh interval corresponding to the first temperature level.

14. The memory system according to claim 13, wherein, The refresh controller is configured to maintain the unit normal execution count and the unit hammer execution count regardless of the first temperature level and the second temperature level in the fixed hammer control mode.

15. The memory system according to claim 13, wherein: The memory controller is configured to use mode register set write commands to transmit hammer control information representing the variable hammer control mode or the fixed hammer control mode. The memory device is configured to store the hammer control information in a mode register, and The refresh controller is configured to change the hammer rate in the variable hammer control mode based on the hammer control information stored in the mode register.

16. A method for controlling the refresh of a memory device, the method comprising: Temperature information is provided by measuring the operating temperature of the memory cell array included in the memory device; It periodically receives refresh commands from the memory controller at an average refresh interval; During the refresh period, a normal refresh operation is performed by sequentially selecting multiple character lines one by one; Hammer refresh operation is performed by selecting the disturbed word line that is physically adjacent to the hammer word line that is accessed more frequently than other word lines. as well as Based on the temperature information, the hammer rate is adjusted by changing the number of hammers executed per unit during the refresh cycle time relative to the number of normal executions per unit during the normal refresh cycle time.

17. The method of claim 16, further comprising: In variable hammer control mode, the average refresh interval is maintained regardless of the first temperature level and the second temperature level, wherein the operating temperature of the memory cell array is higher at the first temperature level than at the second temperature level. as well as In the fixed hammer control mode, the average refresh interval is changed so that the average refresh interval corresponding to the second temperature level is shorter than the average refresh interval corresponding to the first temperature level.

18. The method according to claim 17, wherein, The steps of changing the hammer rate include: In the variable hammer control mode, the hammer rate is changed so that the hammer rate corresponding to the second temperature level is higher than the hammer rate corresponding to the first temperature level.

19. The method according to claim 17, wherein, The steps of changing the hammer rate include: In the fixed hammer control mode, the number of normal unit executions and the number of unit hammer executions are maintained regardless of the first temperature level and the second temperature level.

20. A memory device, comprising: A memory cell array comprising memory cells connected to multiple word lines; A temperature sensor is configured to provide temperature information by measuring the operating temperature of the memory cell array; as well as A refresh controller is configured to control normal refresh operations and hammer refresh operations, performing the normal refresh operation by sequentially selecting the plurality of word lines one by one during a refresh period, and performing the hammer refresh operation by selecting an interfering word line that is physically adjacent to a hammer word line that is accessed more frequently than other word lines. The refresh controller is also configured to, based on the temperature information, change the hammer rate of the number of hammer executions per unit of hammer refresh operation performed during the refresh cycle time relative to the number of normal executions per unit of normal refresh operation performed during the refresh cycle time.

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