Memory system including memory devices and operating method thereof

Abstract

The present disclosure relates to a memory system including: a memory device adapted to: perform a program cycle in stages, the program cycle including a program operation and a program verify operation on each page within a selected storage block among a plurality of storage blocks; update a maximum number of program cycles for the selected storage block by comparing a number of program cycles performed on each page until a program verify operation on the page is processed as pass with a current maximum number of program cycles for the selected storage block; and store the updated maximum number of program cycles for the selected storage block as program pass information for the selected storage block; and a controller adapted to manage the selected storage block as a bad block based on the program pass information for the selected storage block.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0159710, filed on November 25, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The various embodiments of this disclosure generally relate to a memory device. More specifically, the embodiments relate to a memory device that manages bad blocks based on the number of programming cycles, and a memory system including the memory device. Background Technology

[0004] The computing environment paradigm has shifted towards ubiquitous computing, enabling the use of computing systems virtually anytime, anywhere. Consequently, the demand for portable electronic devices such as mobile phones, digital cameras, and laptops has grown rapidly. These devices typically include memory systems that use memory devices as data storage devices. Data storage devices can serve as either the main memory unit or secondary memory unit in portable electronic devices.

[0005] Because they lack mechanical drive components, these data storage devices offer advantages such as excellent stability and durability, fast information access speeds, and low power consumption. Furthermore, compared to hard disk drives, data storage devices can have faster data access rates and lower power consumption. Examples of data storage devices with these advantages include Universal Serial Bus (USB) memory devices, multi-interface memory cards, and solid-state drives (SSDs). Summary of the Invention

[0006] Various embodiments of this disclosure relate to a memory device and a memory system including the memory device, which can prevent programming failures by updating the maximum number of programming loops executed in stages and managing bad blocks based on the updated maximum number of programming loops.

[0007] According to an embodiment of the disclosure, a memory system can include a memory device adapted to: perform a program cycle on each page in a selected memory block among a plurality of memory blocks in stages, the program cycle including a program operation and a program verify operation on each page; update a maximum number of program cycles for the selected memory block by comparing a number of program cycles performed on each page until a program verify operation on the page is processed as pass with a current maximum number of program cycles for the selected memory block; and store the updated maximum number of program cycles for the selected memory block as program pass information for the selected memory block; and a controller adapted to manage the selected memory block as a bad block based on the program pass information for the selected memory block.

[0008] According to an embodiment of the disclosure, a memory system can include a controller; a memory device including at least one memory block including a plurality of pages; a check circuit adapted to verify a program pass or a program fail of a selected page among the plurality of pages and output a pass signal and a fail signal; an update circuit adapted to increase a count value of the selected page in response to the fail signal and update a maximum count value of the memory block by comparing the count value of the selected page with a current maximum count value of the memory block; and a storage circuit adapted to store the updated maximum count value of the memory block as program pass information for the memory block.

[0009] According to an embodiment of the disclosure, an operating method of a memory system can include programming a selected page among a plurality of pages included in at least one memory block and verifying a program pass or a program fail of the selected page; increasing a count value of the selected page based on the verifying result and updating a maximum count value of the memory block by comparing the count value of the selected page with a current maximum count value of the memory block; and managing the memory block as a bad block based on the updated maximum count value of the memory block.

[0010] According to an embodiment of the disclosure, a memory system can include a memory device adapted to perform one or more program cycles on each page within a target memory block according to an incremental step pulse programming (ISPP) scheme; and a controller adapted to treat the target memory block as a bad block when a number of program cycles on a page within the target memory block is greater than a first threshold value and when a maximum number among a number of program cycles on a single page among all pages within the target memory block is greater than a second threshold value, wherein the first threshold value is greater than the second threshold value, and wherein the number of program cycles on the page is a number of program cycles on the page until a last success among the program cycles on the page. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a block diagram illustrating a data processing system including a memory system according to an embodiment of the disclosure.

[0012] Figure 2 is a block diagram illustrating Figure 1 a memory device illustrated in FIG. 1.

[0013] Figure 3 is a block diagram illustrating Figure 2 control logic illustrated in FIG. 1.

[0014] Figure 4 is a flowchart illustrating an operation of a memory system according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0015] Various embodiments of the disclosure are described below with reference to the accompanying drawings in order to describe the disclosure in detail so that a person of ordinary skill in the art to which the disclosure pertains can easily practice the technical spirit of the disclosure. However, the disclosure is not limited to the embodiments disclosed below, and can be implemented in various other forms. The disclosed embodiments are provided so as to make the disclosure complete and to enable those skilled in the art to practice the invention.

[0016] Figure 1 is a block diagram illustrating a data processing system 100 including a memory system 120 according to an embodiment of the disclosure. Referring to Figure 1 , the data processing system 100 can include a host 110 and a memory system 120.

[0017] The host 110 can include, for example, a portable electronic device such as a mobile phone, an MP3 player, and a laptop computer, or a non-portable electronic device such as a desktop computer, a game machine, a television (TV), a projector, etc.

[0018] The host 110 also includes at least one operating system (OS) that can generally manage and control functions and operations performed in the host 110. The OS can provide interoperability between the host 110 interfacing with the memory system 120 and a user requiring and using the memory system 120. The OS can support functions and operations corresponding to a request of the user. As an example and not by way of limitation, the OS can be classified as a general-purpose operating system and a mobile operating system according to mobility of the host 110. The general-purpose operating system can be classified as a personal operating system and an enterprise operating system according to system requirements or an environment of the user. The personal operating system including Windows and Chrome can be used to support general-purpose services. However, the enterprise operating system including Windows server, Linux, Unix, etc. can be used to specifically ensure and support high performance. Further, the mobile operating system can include Android, iOS, Windows mobile, etc. The mobile operating system can be used to support services or functions for mobility (e.g., power saving functions). The host 110 can include a plurality of operating systems. The host 110 can run a plurality of operating systems interlocked with the memory system 120 corresponding to a request of the user. The host 110 can transmit a plurality of commands corresponding to a request of the user to the memory system 120, thereby performing operations corresponding to the commands within the memory system 120. Later, reference is made to FIG. 2. Figure 4 Processing a plurality of commands in the memory system 120 is described.

[0019] The memory system 120 can operate or perform specific functions or operations in response to a request from the host 110, and in particular, can store data to be accessed by the host 110. The memory system 120 can be used as a main memory system or an auxiliary memory system of the host 110. According to a protocol of a host interface, the memory system 120 can be implemented with any one of various types of storage devices that can be electrically coupled with the host 110. Non-limiting examples of the applicable storage devices include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro- MMC, a secure digital (SD) card, a mini-SD, a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, etc.

[0020] The memory system 110 can be configured as a part of, for example, a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet PC, a wireless phone, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3-dimensional (3D) TV, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, or one of various components configured for a computing system.

[0021] The storage device for the memory system 120 can be implemented with volatile memory devices such as dynamic random access memory (DRAM) and static RAM (SRAM) and / or non-volatile memory devices such as read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM), and flash memory.

[0022] The memory system 120 can include a controller 130 and a memory device 140. The memory device 140 can store data to be accessed by the host 110. The controller 130 can control data storage in the memory device 140.

[0023] The controller 130 can control overall operations of the memory device 140 such as read operations, write operations, program operations, and erase operations. For example, the controller 130 can control the memory device 140 in response to a request from the host 110. The controller 130 can provide data read from the memory device 140 to the host 110. The controller 130 can store data provided by the host 110 into the memory device 140.

[0024] In an embodiment, the controller 130 can include a host interface 150, a memory interface 160, a processor 170, a memory 180, and a bad block manager 190. All configurations 150, 160, 170, 180, and 190 included in the controller 130 can share signals transmitted inside the controller 130 through an internal bus BUS.

[0025] The host interface 150 can interface the host 110 and the memory system 120 in response to a protocol of the host 110. The host interface 150 can perform an operation of switching commands and data transmitted between the host 110 and the memory system 120.

[0026] The host interface 150 can process commands and data provided from the host 110, and can communicate with the host 110 through at least one of various interface protocols such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect express (PCI-e or PCIe), a small computer system interface (SCSI), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), an enhanced small disk interface (ESDI), and an electronic integrated drive (IDE). According to an embodiment, the host interface 150 can exchange data with the host 110, which can be implemented through firmware called a host interface layer (HIL).

[0027] The memory interface 160 can serve as an interface of processing commands and data transferred between the controller 130 and the memory device 140 to allow the controller 130 to control the memory device 140 in response to a request transferred from the host 110. In the case when the memory device 140 is a flash memory, and particularly, when the memory device 140 is a NAND flash memory, the memory interface 160 can generate a control signal for the memory device 140, and can process data input to or output from the memory device 140 under the control of the processor 170. The memory interface 160 can provide an interface for processing commands and data between the controller 130 and the memory device 140 (e.g., operations of a NAND flash interface, particularly, operations between the controller 130 and the memory device 140). According to an embodiment, the memory interface 160 can be implemented through firmware called a flash interface layer (FIL) that is a component for exchanging data with the memory device 140.

[0028] The processor 170 can be implemented with a microprocessor or a central processing unit (CPU). The memory system 120 can include one or more processors 170. The processor 170 can control overall operations of the memory system 120. As an example and not a limitation, the processor 170 can control a program operation or a read operation of the memory device 140 in response to a write request or a read request input from the host 110. According to an embodiment, the processor 170 can use or run firmware to control overall operations of the memory system 120. Herein, the firmware can be referred to as a flash translation layer (FTL). The FTL can perform operations as an interface between the host 110 and the memory device 140. The host 110 can transmit a request for a write operation and a read operation to the memory device 140 through the FTL.

[0029] For example, when performing an operation requested from the host 110 in the memory device 140, the controller 130 uses a processor 170 implemented with a microprocessor or a central processing unit (CPU) or the like. The processor 170 interfaced with the memory device 140 can process instructions or commands corresponding to input commands from the host 110. The controller 130 can perform foreground operations as command operations corresponding to commands input from the host 110, such as a program operation corresponding to a write command, a read operation corresponding to a read command, an erase / discard operation corresponding to an erase / discard command, and a parameter setting operation corresponding to a set parameter command or a set feature command having a set command.

[0030] For another example, the controller 130 can perform background operations on the memory device 140 through the processor 170. As an example and not a limitation, the background operations for the memory device 140 include a garbage collection (GC) operation, a wear leveling (WL) operation, a mapping clean-up operation, and a bad block management operation of checking or searching for bad blocks.

[0031] The garbage collection operation can include an operation of copying and processing data stored in a random memory block among the memory blocks MEMORY BLOCK<0,1,2,…> of the memory device 140 to another random memory block. The wear leveling operation can include an operation of exchanging and processing stored data between the memory blocks MEMORY BLOCK<0,1,2,…> of the memory device 140. The mapping clean-up operation can include an operation of storing mapping data stored in the controller 130 in the memory blocks MEMORY BLOCK<0,1,2,…> of the memory device 140. The bad block management operation can include an operation of checking and processing bad blocks among the memory blocks MEMORY BLOCK<0,1,2,…> of the memory device 140.

[0032] The controller 130 can generate and manage log data through the processor 170 implemented as a microprocessor or a central processing unit (CPU) in response to an operation of accessing the memory blocks MEMORY BLOCK<0,1,2,…> of the memory device 140. The operation of accessing the memory blocks MEMORY BLOCK<0,1,2,…> of the memory device 140 can include a foreground operation or a background operation performed on the memory blocks MEMORY BLOCK<0,1,2,…> of the memory device 140.

[0033] The memory 180, which is a working memory of the memory system 120 and the controller 130, can store data for driving the memory system 120 and the controller 130. More specifically, when the controller 130 controls the memory device 140 in response to a request of the host 110, the memory 180 can store firmware driven by the processor 170 and data required to drive the firmware, for example, metadata.

[0034] In addition, the memory 180, which is a buffer memory of the memory system 120 and the controller 130, can temporarily store write data transmitted from the host 110 to the memory device 140 and read data transmitted from the memory device 140 to the host 110. The memory 180 can include a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, and a mapping buffer / cache for storing the write data and the read data.

[0035] The memory 180 can be implemented with a volatile memory. The memory 180 can be implemented with a static random access memory (SRAM), a dynamic random access memory (DRAM), or both.

[0036] Although Figure 2 The memory 180 is illustrated as being included in the controller 130, but the present disclosure is not limited thereto. The memory 180 can be included outside the controller 130, and the controller 130 can input and output data to the memory 180 through a separate memory interface (not shown).

[0037] The bad block manager 190 can perform a bad block management operation on the memory device 140. According to an embodiment, the controller 130 can request program pass information PPI and program fail information PFI from the memory device 140. The bad block manager 190 can check and process a bad block among the memory blocks MEMORY BLOCK<0,1,2,…> of the memory device 140 based on the program pass information PPI and the program fail information PFI.

[0038] The program failure information PFI can indicate a target memory block for which the number of program cycles for a page is equal to or greater than a first threshold TH1. The bad block manager 190 can designate the target memory block for which the number of program cycles is equal to or greater than the first threshold TH1 as a bad block based on the program failure information PFI.

[0039] The program pass information PPI can indicate a maximum number of program cycles for a target memory block. The bad block manager 190 can compare the maximum number of program cycles with a second threshold TH2 that is smaller than the first threshold TH1 by a predetermined size. When a comparison result indicates that the maximum number of program cycles is equal to or greater than the second threshold TH2, the bad block manager 190 can designate the target memory block as a bad block.

[0040] The memory device 140 can operate as a storage medium of the memory system 120.

[0041] The memory device 140 can be a non-volatile memory device and can maintain data stored therein even when power is not supplied. The memory device 140 can store data provided from the host 110 through a write operation, while providing stored data to the host 110 through a read operation.

[0042] In an embodiment of the disclosure, the memory device 140 is implemented as a non-volatile memory such as a flash memory, such as a NAND flash memory, a NOR flash memory, or the like. Alternatively, the memory device 140 can be implemented by at least one of a phase change random access memory (PCRAM), a ferroelectric random access memory (FRAM), a spin transfer torque magnetic random access memory (STT-RAM), and a spin transfer moment magnetic random access memory (STT-MRAM), or the like.

[0043] The memory device 140 can include a plurality of memory blocks MEMORY BLOCK<0, 1, 2, …>. Each of the memory blocks MEMORY BLOCK<0, 1, 2, …> included in the memory device 140 can include a plurality of pages P<0, 1, 2, 3, 4, …>. Further, although not specifically shown in the drawings, each of the pages P<0, 1, 2, 3, 4, …> can include a plurality of memory cells.

[0044] Each of the memory blocks MEMORY BLOCK<0, 1, 2, …> included in the memory device 140 can be classified as a single layer cell (SLC) memory block and a multi layer cell (MLC) memory block according to the number of bits that can be stored or represented in a single memory cell included therein.

[0045] The memory device 140 can include a plurality of memory blocks. The plurality of memory blocks can be any one of different types of memory blocks such as a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, etc., according to the number of bits that can be stored or represented in one memory cell. Here, the SLC memory block includes a plurality of pages implemented by memory cells each storing one bit of data. The SLC memory block can have high data I / O operation performance and high endurance. The MLC memory block includes a plurality of pages implemented by memory cells each storing multiple bits (e.g., two or more bits) of data. The MLC memory block can have greater storage capacity for the same space compared to the SLC memory block. The MLC memory block can be highly integrated from the perspective of storage capacity. In an embodiment, the memory device 140 can be implemented with MLC memory blocks such as MLC memory blocks, triple-level cell (TLC) memory blocks, quad-level cell (QLC) memory blocks, and combinations thereof. The MLC memory block can include a plurality of pages implemented by memory cells each capable of storing 2 bits of data. The triple-level cell (TLC) memory block can include a plurality of pages implemented by memory cells each capable of storing 3 bits of data. The quad-level cell (QLC) memory block can include a plurality of pages implemented by memory cells each capable of storing 4 bits of data. In another embodiment, the memory device 140 can be implemented with blocks including a plurality of pages implemented by memory cells each capable of storing 5 bits or more of data.

[0046] Hereinafter, the operation of the memory device 140 generating the program pass information PPI and the program failure information PFI will be described in detail.

[0047] Figure 2 is a block diagram illustrating Figure 1 the memory device 140 shown. Figure 2 is a block diagram illustrating Figure 1 the memory cell array circuit of the memory block MEMORY BLOCK<0,1,2,…> of the memory device 140.

[0048] The memory device 140 can include a memory cell array 210, a row decoder 220, a read / write circuit 230, a column decoder 240, and control logic 250. Each of the memory blocks MEMORY BLOCK<0,1,2,…> can be implemented as the memory cell array 210 in the memory device 140. The memory cell array 210 can include a plurality of cell strings 260 respectively coupled to bit lines BL0, BL1, BL2, …, and BLm-1.

[0049] Each of the cell strings 260 can include at least one drain select transistor DST and at least one source select transistor SST. Each of the bit lines BL0, BL1, BL2, …, and BLm-1 can be coupled to one end of the drain select transistor DST. One end of the source select transistor SST can be coupled to a common source line CSL. A plurality of memory cells MC0, MC1, MC2, …, and MCm-1 or a plurality of memory cell transistors can be coupled in series between the select transistors DST and SST. Each of the word lines WL0, WL1, …, WLn-2, and WLn-1 can be coupled to the memory cells MC0, MC1, MC2, …, and MCm-1 arranged in a row direction, e.g., control gates of the memory cells MC0, MC1, MC2, …, and MCm-1.

[0050] As an example, Figure 2 The memory blocks MEMORY BLOCK<0, 1, 2, …> are shown to each include NAND flash memory cells. However, the plurality of memory blocks MEMORY BLOCK<0, 1, 2, …> included in the memory device 140 according to an embodiment is not limited to NAND flash memory, and can be implemented as, for example, NOR type flash memory, hybrid flash memory that mixes at least two or more types of memory cells, 1-NAND flash memory in which a controller is embedded in a memory chip, etc. In addition, the memory device 140 according to an embodiment can be implemented as a charge-trapping flash (CTF) memory in which a charge storage layer is composed of a dielectric layer and a flash memory device in which a charge storage layer is composed of a conductive floating gate.

[0051] The row decoder 220 can select one of the word lines of the selected memory block based on the address ADD. The row decoder 220 can apply a word line voltage generated by a voltage supply unit (not shown) to the selected word line of the selected memory block. For example, during a program operation, the row decoder 220 can apply a program voltage Vpgm and a verify voltage Vvfy to the selected word line, and a pass voltage Vpass to the unselected word line.

[0052] The read / write circuit 230 can include a page buffer, and operate as a sense amplifier or a write driver according to an operation mode. For example, during a program operation, the read / write circuit 230 can receive data to be programmed from an external circuit, and transfer a bit line voltage corresponding to the received data to the bit lines BL0, BL1, BL2, …, and BLm-1 of the memory cell array 210. During a read operation, the read / write circuit 230 can read data stored in the selected memory cell through the bit lines BL0, BL1, BL2, …, and BLm-1, latch the read data, and output the latched data to the outside.

[0053] The column decoder 240 can address the bit lines BL0, BL1, BL2, …, and BLm-1 of the memory cell array 210. The column decoder 240 can transfer data received from the outside to the read / write circuit 230 or output data stored therein to the outside.

[0054] The control logic 250 can perform a program loop in stages, each program loop including a program operation and a program verify operation on a target memory block. The control logic 250 can perform the program operation according to an incremental step pulse programming (ISPP) scheme, based on which the program voltage applied to a set of among the word lines WL0, WL1, …, WLn-2, and WLn-1, for example, the program voltage applied to a target page during the program operation on the target page within the target memory block of the memory cell array 210, is increased by a predetermined amount each time the number of program loops increases. According to the ISPP method, after the program operation is performed in each program loop, the control logic 250 can perform a program verify operation that checks whether the threshold voltage of the programmed memory cell reaches a target level. According to the result of the program verify operation, the control logic 250 can perform another program loop by increasing the level of the program voltage.

[0055] The control logic 250 can store the maximum number of program loops performed on the target memory block as program pass information PPI. The control logic 250 can compare the number of program loops performed on the current target page with the current maximum number of program loops stored as the program pass information PPI of the target memory block including the current target page, and update the maximum number of program loops to the number of program loops on the target page when the number of program loops performed on the current target page is greater than the current maximum number of program loops.

[0056] According to an embodiment, when the program operation is completely performed on the target memory block, that is, when the program operation on all pages within the target memory block is completed, the control logic 250 can transfer the program pass information PPI to the controller 130. At this time, the program pass information PPI of the target memory block can include the address ADD of the target memory block and the maximum number of program loops corresponding to the target memory block.

[0057] Additionally, the control logic 250 can store program failure information PFI indicating that a program operation performed on a page within the target memory block in the target memory block has failed. As described above, the program failure information PFI can indicate that a number of program loops on the page within the target memory block is equal to or greater than the first threshold TH1. When the program operation on the page has failed, i.e., when the number of program loops on the page within the target memory block is equal to or greater than the first threshold TH1, the control logic 250 can transmit the program failure information PFI of the target memory block to the controller 130.

[0058] Figure 3 is a block diagram illustrating Figure 2 the control logic 250. Referring to Figure 3 , the control logic 250 can include a check circuit 310, an update circuit 320, and a storage circuit 330.

[0059] The control logic 250 can control the read / write circuit 230 to perform a program verify operation. The read / write circuit 230 can be coupled to the memory cells MC0, MC1, MC2, …, and MCm-1 of a target page on which a program operation is performed within a target memory block through the bit lines BL0, BL1, BL2, …, and BLm-1, and detect the program state of the memory cells MC0, MC1, MC2, …, and MCm-1 of the target page. The read / write circuit 230 can include a plurality of page buffers corresponding to the bit lines BL0, BL1, BL2, …, and BLm-1.

[0060] During the program verify operation, the plurality of page buffers can store verify data according to the program state of the memory cells MC0, MC1, MC2, …, and MCm-1 of the target page, and then change the potential of the corresponding sense node SN to a low level and a high level. For example, when the program state of the memory cells MC0, MC1, MC2, …, and MCm-1 of the target page is determined to pass, the potential of the sense node SN can remain at a low level, and when the program state of the memory cells MC0, MC1, MC2, …, and MCm-1 of the target page is determined to fail, the potential of the sense node SN can change to a high level.

[0061] The inspection circuit 310 can verify the program pass or program fail of the memory cells MC0, MC1, MC2, …, and MCm-1 of the target page and output the pass signal PS and the fail signal FS of the target page. The inspection circuit 310 can count the number of memory cells among the memory cells MC0, MC1, MC2, …, and MCm-1 of the target page, of which the program state is determined as pass or fail. The inspection circuit 310 can compare the counted number of memory cells with a reference value and output the pass signal PS and the fail signal FS of the target page.

[0062] For example, the inspection circuit 310 can perform a counting operation in response to the high-level potential of the sensing node SN. That is, the inspection circuit 310 can count the number of sensing nodes SN having a high-level potential and compare the counted number of sensing nodes SN with a reference value. When the counted number is less than the reference value, the inspection circuit 310 can verify the memory cells MC0, MC1, MC2, …, and MCm-1 of the target page as program pass and can output the pass signal PS of the target page. When the counted number is equal to or greater than the reference value, the inspection circuit 310 can verify the memory cells MC0, MC1, MC2, …, and MCm-1 of the target page as program fail and can output the fail signal FS of the target page.

[0063] At this time, the control logic 250 can determine whether to terminate or continue the program loop of the program operation on the target page according to the program verification result of the inspection circuit 310. When the inspection circuit 310 outputs the pass signal PS of the target page, the control logic 250 can terminate the program loop of the memory cells MC0, MC1, MC2, …, and MCm-1 of the target page. On the other hand, when the inspection circuit 310 outputs the fail signal FS of the target page, the control logic 250 can perform control to perform another program loop on the target page by increasing the level of the program voltage.

[0064] The update circuit 320 can increase the count value CNT of the target page and update the program pass information PPI of the target memory block including the target page every time the number of program loops on the target page is increased. The update circuit 320 can increase the count value CNT of the target page in response to the fail signal FS of the target page and can update the maximum count value CNT’ of the target memory block by comparing the increased count value CNT of the target page with the current maximum count value MCNT of the target memory block including the target page. The storage circuit 330 can store the updated maximum count value CNT’ of the target memory block as the program pass information PPI of the target memory block.

[0065] The update circuit 320 can include a counter 322, a first comparator 324, and a second comparator 326. The counter 322 can perform a counting operation in response to the fail signal FS of the target page. That is, each time the check circuit 310 outputs the fail signal FS of the target page, the counter 322 can increase the count value CNT of the target page.

[0066] The first comparator 324 can compare the count value CNT of the target page with a first threshold TH1 in response to the pass signal PS of the target page, and output a first comparison signal COM1 of the target storage block including the target page. When the pass signal PS of the target page is activated and the count value CNT of the target page is equal to or greater than the first threshold TH1, the first comparator 324 can activate the first comparison signal COM1 of the target storage block.

[0067] The second comparator 326 can compare the count value CNT of the target page with a current maximum count value MCNT of the target storage block including the target page in response to the pass signal PS of the target page and the first comparison signal COM1 of the target storage block, and can output a second comparison signal COM2 of the target storage block. When the pass signal PS of the target page is activated and the count value CNT of the target page is less than the first threshold TH1, the second comparator 326 can compare the count value CNT of the target page with the current maximum count value MCNT of the target storage block. When the comparison result indicates that the count value CNT of the target page is equal to or greater than the current maximum count value MCNT of the target storage block, the second comparator 326 can activate the second comparison signal COM2 of the target storage block.

[0068] At this time, the storage circuit 330 can store the input address ADD of the target storage block and the maximum count value CNT' of the target storage block as the program pass information PPI of the target storage block in response to the second comparison signal COM2 of the target storage block. The maximum count value CNT' of the target storage block can indicate the count value CNT of the target page that is equal to or greater than the current maximum count value MCNT of the target storage block including the target page. When a subsequent program operation is performed on the target storage block, the maximum count value CNT' corresponding to the current program operation on the target storage block can be provided to the update circuit 320 as the current maximum count value MCNT of the target storage block. When a subsequent program operation is performed on the target storage block, the storage circuit 330 can provide the maximum count value CNT' corresponding to the current program operation on the target storage block to the update circuit 320 as the current maximum count value MCNT of the target storage block based on the program pass information PPI of the target storage block.

[0069] Whenever the programming verification result is a failure, the update circuit 320 can increase the count value CNT of the target page, and when the programming verification result is a pass, the update circuit 320 compares the count value CNT of the target page with the first threshold TH1. When the comparison result indicates that the count value CNT of the target page is less than the first threshold TH1, the update circuit 320 can compare the count value CNT of the target page with the current maximum count value MCNT of the target storage block and generate a second comparison signal COM2, and the storage circuit 330 can store the maximum count value CNT' of the target storage block as the programming pass information PPI of the target storage block in response to the second comparison signal COM2. Accordingly, when the count value CNT of the target page is less than the first threshold TH1, the larger value between the count value CNT of the target page and the current maximum count value MCNT of the target storage block can be updated as the maximum count value CNT' of the target storage block in the programming pass information PPI of the target storage block.

[0070] The target storage block can be managed as a bad block based on the programming pass information PPI of the target storage block stored in the storage circuit 330. When the maximum count value CNT' of the target storage block in the programming pass information PPI of the target storage block is equal to or greater than a second threshold TH2, the target storage block can be designated as a bad block. In this case, the second threshold TH2 can be less than the first threshold TH1 by a predetermined size.

[0071] When the comparison result indicates that the count value CNT of the target page is equal to or greater than the first threshold TH1, the update circuit 320 can generate a first comparison signal COM1. The storage circuit 330 can store the input address ADD of the target storage block including the target page as the programming failure information PFI in response to the first comparison signal COM1. The target storage block can be designated as a bad block based on the programming failure information PFI stored in the storage circuit 330.

[0072] Although it is shown that the control logic 250 is included in the same chip as the memory cell array 210, the present disclosure is not limited thereto. For example, the control logic 250 can be implemented as a chip separate from the memory cell array 210, i.e., a flash translation layer (FTL) provided to the controller 130.

[0073] Figure 4 is a flowchart illustrating an operation of the memory system 120 according to an embodiment of the present disclosure.

[0074] In operation S410, the memory device 140 can perform a programming operation on a target page within a target storage block. In operation S420, the memory device 140 can perform a verification operation of a programming cycle on the target page.

[0075] In operation S430, the memory device 140 can increase the count value CNT of the target page based on the result of the verification operation of S420, compare the count value CNT of the target page with the current count value MCNT of the target memory block, and update the maximum count value CNT' of the target memory block.

[0076] Specifically, when the verification result indicates a programming failure (i.e., "Fail" in operation S420), the memory device 140 can perform operation S431. That is, the memory device 140 can increase the count value CNT of the target page in operation S431, and can perform operation S410 of another programming cycle of the target page based on the increased count value CNT of the target page. On the other hand, when the verification result indicates a programming pass (i.e., "Pass" in operation S420), the memory device 140 can compare the count value CNT of the target page with the first threshold TH1 and the current maximum count value MCNT of the target memory block.

[0077] In operation S432, the memory device 140 can compare the count value CNT of the target page with the first threshold TH1. When the comparison result indicates that the count value CNT of the target page is less than the first threshold TH1 (i.e., "Yes" in operation S432), the memory device 140 can perform operation S433. That is, the memory device 140 can compare the count value CNT of the target page with the current maximum count value MCNT of the target memory block. On the other hand, when the comparison result indicates that the count value CNT of the target page is equal to or greater than the first threshold TH1 (i.e., "No" in operation S432), the memory device 140 or the controller 130 can perform operation S443. That is, the target memory block can be designated as a bad block.

[0078] In operation S433, when the comparison result indicates that the count value CNT of the target page is equal to or greater than the current maximum count value MCNT of the target memory block (i.e., "Yes" in operation S433), the memory device 140 can perform operation S434. That is, in operation S434, the memory device 140 can store the count value CNT of the target page as the maximum count value CNT' of the target memory block. On the other hand, when the comparison result indicates that the count value CNT of the target page is less than the current maximum count value MCNT of the target memory block (i.e., "No" in operation S433), the memory device 140 can perform operation S441.

[0079] In operation S440, the controller 130 and the memory device 140 can manage the target memory block as a bad block based on the updated maximum count value CNT' of the target memory block.

[0080] In operation S441, the memory device 140 can check whether the programming operation on all pages included in the target memory block is completed. When the check result indicates that the programming operation on all pages within the target memory block is completed (i.e., "Yes" in operation S441), the memory device 140 can provide the controller 130 with the programming pass information PPI block of the target memory block, and the controller 130 can perform operation S442. On the other hand, when the check result indicates that the programming operation on all pages within the target memory block is not completed (i.e., "No" in operation S441), the memory device 140 can perform operation S410 on another page within the target memory block.

[0081] In operation S442, the controller 130 can compare the updated maximum count value CNT' of the target memory block with the second threshold TH2. When the comparison result indicates that the updated maximum count value CNT' of the target memory block is equal to or greater than the second threshold TH2 (i.e., "Yes" in operation S442), the controller 130 can perform operation S443. That is, the target memory block can be designated as a bad block. In this case, the second threshold TH2 can be smaller than the first threshold TH1 by a predetermined size.

[0082] According to an embodiment of the disclosure, when the number of programming cycles performed on a target page included in a target memory block is equal to or greater than a first threshold TH1, the target memory block can be determined as a bad block. Further, when the number of programming cycles on all pages within the target memory block is less than the first threshold TH1, the number of programming cycles on each page within the target memory block can be compared with the current maximum number of programming cycles of the target memory block to update the maximum number of programming cycles of the target memory block. The updated maximum number of programming cycles of the target memory block can be compared with a second threshold TH2 that is smaller than the first threshold TH1 by a predetermined size. That is, a memory block in which the number of programming cycles on all pages is less than the first threshold TH1 but the maximum number of programming cycles is close to the first threshold TH1 can be managed as a bad block to prevent programming failure.

[0083] According to an embodiment of the disclosure, a memory device can manage the maximum number of programming cycles of a target memory block during a programming operation on each page within the target memory block. A memory system including the memory device can detect in advance a memory block in which the probability of programming failure is high among a plurality of memory blocks, and process the detected memory block as a bad block, thereby preventing the occurrence of programming failure.

[0084] While the present disclosure has been described with reference to specific embodiments, it is to be understood that the disclosed embodiments are illustrative of the present disclosure and not limiting. For example, while the disclosed embodiments have described a controller managing bad blocks of a memory device, a plurality of memory blocks can be designated as bad blocks by control logic included in the memory device. Further, those skilled in the art will appreciate that various adaptations, changes, and modifications can be made to the embodiments without departing from the spirit and scope of the present disclosure.

[0085] While various embodiments of the disclosed technology have been described with reference to specific details, it is to be understood that various modifications, additions and substitutions can be made and fall within the spirit and scope of the disclosed technology as defined in the accompanying claims.

Claims

1. A memory system comprising: a memory device: performing a program loop in stages, the program loop including a program operation and a program verify operation on each page within a selected memory block among a plurality of memory blocks, updating a maximum number of program loops of the selected memory block by comparing a number of program loops on each page that have been performed until a program verify operation on the page is processed as pass with a current maximum number of program loops of the selected memory block, and storing the updated maximum number of program loops of the selected memory block as program pass information of the selected memory block; and a controller managing the selected memory block as a bad block based on the program pass information of the selected memory block, wherein the memory device further compares the number of program loops on each page with a first threshold, and wherein when the number of program loops on each page is less than the first threshold, the memory device updates a larger number between the number of program loops on each page and the current maximum number of program loops of the selected memory block as the maximum number of program loops of the selected memory block.

2. The memory system of claim 1, wherein the controller manages the selected memory block as the bad block by: comparing the maximum number of program loops of the selected memory block with a second threshold, and designating the selected memory block as the bad block when the maximum number of program loops of the selected memory block is equal to or greater than the second threshold.

3. The memory system of claim 2, wherein the second threshold is less than the first threshold by a predetermined size.

4. The memory system of claim 1, wherein when a number of program loops on one page among pages within the selected memory block is equal to or greater than the first threshold, the memory device further transmits an address of the selected memory block as program fail information to the controller.

5. The memory system of claim 4, wherein the controller manages the selected memory block as the bad block by designating the selected memory block as the bad block based on the program fail information.

6. The memory system of claim 1, wherein when the program loop is completely performed on all pages included in the selected memory block, the memory device further transmits the program pass information of the selected memory block to the controller.

7. The memory system of claim 1, wherein the program pass information includes an address of the selected memory block and the maximum number of program loops of the selected memory block.

8. A memory system comprising: a controller; a memory device including: at least one memory block including a plurality of pages; a check circuit verifying a program pass or a program fail of a page selected among the plurality of pages and outputting a pass signal and a fail signal; an update circuit that increases a count value of the selected page in response to the failure signal, and updates a maximum count value of the memory block by comparing the count value of the selected page with a current maximum count value of the memory block; and a storage circuit that stores the updated maximum count value of the memory block as program pass information of the memory block, wherein the update circuit further compares the count value of the selected page with a first threshold value, and wherein when the count value of the selected page is less than the first threshold value, the update circuit updates a higher value between the count value of the selected page and the current maximum count value of the memory block as the maximum count value of the memory block.

9. The memory system of claim 8, wherein when the updated maximum count value is equal to or greater than a second threshold value that is smaller than the first threshold value by a predetermined size, the controller designates the at least one memory block as a bad block.

10. The memory system of claim 8, wherein when the count value is equal to or greater than the first threshold value, the controller designates the at least one memory block as a bad block.

11. The memory system of claim 8, wherein the update circuit comprises: a counter that increases the count value of the selected page in response to the failure signal; a first comparator that compares the count value of the selected page with the first threshold value in response to the pass signal, and outputs a first comparison signal; and a comparator that compares the count value of the selected page with the current maximum count value of the memory block in response to the pass signal, and outputs a second comparison signal.

12. The memory system of claim 11, wherein the storage circuit stores an address of the memory block and the count value of the selected page as the program pass information of the memory block in response to the second comparison signal.

13. The memory system of claim 11, wherein the storage circuit stores an address of the memory block as program failure information of the memory block in response to the first comparison signal.

14. An operating method of a memory system, comprising: programming a selected page among a plurality of pages included in at least one memory block, and verifying program pass or program failure of the selected page; increasing a count value of the selected page based on a verification result, and updating a maximum count value of the memory block by comparing the count value of the selected page with a current maximum count value of the memory block; and managing the memory block as a bad block based on the updated maximum count value of the memory block, wherein updating the maximum count value includes: increasing the count value of the selected page when the verification result indicates the program failure; comparing the count value of the selected page with a first threshold value and the current maximum count value of the memory block when the verification result indicates the program pass; and When the comparison result indicates that the count value of the selected page is less than the first threshold value and equal to or greater than the current maximum count value of the storage block, the count value of the selected page is stored as the maximum count value of the storage block. 15.The operating method of claim 14, wherein managing the storage block as the bad block comprises: When the plurality of pages are completely programmed, comparing the updated maximum count value of the storage block with a second threshold value; and When the comparison result indicates that the updated maximum count value of the storage block is equal to or greater than the second threshold value, designating the storage block as the bad block. 16.The operating method of claim 15, wherein the second threshold value is less than the first threshold value by a predetermined size.

17. The method of operation of claim 15, wherein managing the storage block as the bad block further comprises: When the comparison result indicates that the count value of the selected page is equal to or greater than the first threshold value, designating the storage block as the bad block.

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