Three-dimensional memory devices, manufacturing methods, and memory systems

Abstract

Embodiments of the present application disclose a three-dimensional memory device, a manufacturing method and a memory system. The method comprises the following steps: providing a substrate; the substrate comprises a substrate, a stack structure and a channel structure penetrating through the stack structure, the stack structure being located on the substrate and comprising gate layers and insulating layers which are alternately stacked; the gate layers comprise a top selection gate layer located at the top of the stack structure; the channel structure comprises a memory layer, a channel layer and a channel oxide which are sequentially arranged along a radial direction from outside to inside; a plurality of top selection gate cuts penetrating through the top selection gate layer are formed; the top selection gate cuts are filled to form a top selection gate cut line; the top selection gate cut line divides the stack structure into a plurality of storage areas; wherein the top selection gate cut line partially penetrates through a first channel structure and is in contact with the channel oxide in the first channel structure; the first channel structure is a channel structure located in different storage areas and adjacent to each other.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a three-dimensional memory device, a manufacturing method and a memory system. BACKGROUND

[0002] In the current 3D NAND structure, the integration density is improved by arranging the memory cells three-dimensionally on the substrate. The gate is divided into three parts, i.e., a bottom select gate, a middle select gate and a top select gate (TSG). A top select gate cut (TSG Cut) is usually arranged in the memory area to separate the top select gate of the memory area into two parts. A dummy channel structure (DCH) is arranged below the top select gate cut. The top select gate cut formed on the dummy channel structure will cause the waste of the channel structure position, which finally leads to the significant decrease of the storage density. How to further improve the storage density is a problem to be solved. SUMMARY

[0003] Therefore, the main purpose of the present application is to provide a three-dimensional memory device, a manufacturing method and a memory system.

[0004] To achieve the above purpose, the technical scheme of the present application is as follows:

[0005] The present application provides a manufacturing method of a three-dimensional memory device, which comprises the following steps:

[0006] providing a substrate; the substrate comprises a substrate, a stack structure located on the substrate and comprising gate layers and insulating layers which are alternately stacked, and a channel structure penetrating through the stack structure; the gate layers comprise a top select gate layer located at the top of the stack structure; the channel structure comprises a memory layer, a channel layer and a channel oxide which are sequentially arranged along the radial direction from the outside to the inside;

[0007] forming a plurality of top select gate cuts penetrating through the top select gate layer;

[0008] filling the top select gate cuts to form a top select gate cut line; the top select gate cut line divides the stack structure into a plurality of memory areas; wherein the top select gate cut line partially penetrates through a first channel structure and contacts the channel oxide in the first channel structure; the first channel structure is a channel structure located in different memory areas and adjacent to each other.

[0009] In the above scheme, the step of forming the top select gate cut comprises:

[0010] etching the top select gate layer and the first channel structure to remove the memory layer and part of the channel layer of the first channel structure located in the top select gate layer to form a plurality of first cutouts;

[0011] remove the channel layer of the first channel structure located in the top select gate layer through the first cutouts to form a plurality of top select gate cutouts.

[0012] In the above solution, an inner diameter of the first cutout is greater than a distance between adjacent channel structures located in different memory areas.

[0013] In the above solution, the step of forming the top select gate cutout comprises:

[0014] etching the top select gate layer located between the first channel structures to form a plurality of first cutouts;

[0015] remove the memory layer and the channel layer of the first channel structure located in the top select gate layer through the first cutouts to form a plurality of top select gate cutouts.

[0016] In the above solution, an inner diameter of the first cutout is greater than a distance between adjacent first channel structures and less than a distance between channel oxides of adjacent first channel structures.

[0017] In the above solution, the top select gate cutlines extend in a first direction parallel to the substrate; the top select gate cutlines are spaced apart in a second direction parallel to the substrate; and the first direction is perpendicular to the second direction.

[0018] In the above solution, the channel structures between adjacent top select gate cutlines have the same number of rows.

[0019] The embodiments of the present application also provide a three-dimensional memory device, comprising:

[0020] a substrate comprising a substrate, a stack structure comprising gate layers and insulating layers alternately stacked on the substrate, and channel structures penetrating through the stack structure; the gate layers comprise a top select gate layer located at a top of the stack structure; the channel structures comprise a memory layer, a channel layer, and a channel oxide sequentially arranged from outside to inside in a radial direction;

[0021] a plurality of top select gate cutlines penetrating through the top select gate layer to divide the stack structure into a plurality of memory areas;

[0022] the top select gate cutlines partially pass through first channel structures and contact the channel oxides in the first channel structures; the first channel structures are channel structures located in different memory areas and adjacent to each other.

[0023] In the above aspect, the top select gate cutline extends in a first direction parallel to the substrate; the top select gate cutline is spaced apart in a second direction parallel to the substrate; and the first direction is perpendicular to the second direction.

[0024] In the above aspect, the channel structures between adjacent top select gate cutlines have the same number of rows.

[0025] In the above aspect, the material of the top select gate cutline includes an insulating material.

[0026] In the above aspect, the top select gate cutline includes an air gap formed therein by the insulating material.

[0027] In the above aspect, a projection of the top select gate cutline on the substrate partially overlaps a projection of the first channel structure on the substrate.

[0028] Embodiments of the present application also provide a memory system, comprising:

[0029] at least one three-dimensional memory device as described in any of the above aspects; and

[0030] a controller coupled to the three-dimensional memory device and configured to control the three-dimensional memory device.

[0031] The manufacturing method of the three-dimensional memory device provided by the embodiments of the present application includes: providing a substrate; the substrate includes a substrate, a stack structure located on the substrate and alternately stacked by gate layers and insulating layers, and a channel structure penetrating through the stack structure; the gate layers include a top select gate layer located at the top of the stack structure; the channel structure includes a memory layer, a channel layer and a channel oxide arranged in turn from the outside to the inside in the radial direction; a plurality of top select gate cutouts penetrating through the top select gate layer are formed; the top select gate cutouts are filled to form a top select gate cutline; the top select gate cutline divides the stack structure into a plurality of storage areas; wherein the top select gate cutline partially passes through a first channel structure and contacts the channel oxide in the first channel structure; and the first channel structure is a channel structure located in different storage areas and adjacent to each other. The top select gate cutline formed by the method provided by the present application only partially passes through the part of the top select gate layer in the first channel structure, without damaging the function of the first channel structure itself, so that the top select gate cutline can be formed without introducing a dummy channel structure, thereby improving the storage density. Furthermore, the channel oxide in the first channel structure directly contacts the top select gate cutline, which to some extent reduces the leakage problem caused by the loss of gate control of the channel layer in the first channel structure. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a schematic diagram of a top view of a three-dimensional memory device in the related art; Figure 1 ;

[0033] Figure 2 is a schematic diagram of a top view of a three-dimensional memory device in the related art; Figure 2 ;

[0034] Figure 3 is a schematic diagram of a cross-sectional view of a three-dimensional memory device according to an embodiment of the present application;

[0035] Figure 4 is a schematic diagram of a top view of a three-dimensional memory device according to an embodiment of the present application;

[0036] Figure 5 is a schematic diagram of a flowchart of a manufacturing method of a three-dimensional memory device according to an embodiment of the present application;

[0037] Figures 6A-6E is a schematic diagram of a cross-sectional view of an exemplary process of a manufacturing method of a three-dimensional memory device according to an embodiment of the present application;

[0038] Figure 7 is a schematic diagram of a partial top view of a three-dimensional memory device according to an embodiment of the present application; Figure 6E ;

[0039] Figures 8A-8F is a schematic diagram of a cross-sectional view of an exemplary process of a manufacturing method of a three-dimensional memory device according to another embodiment of the present application;

[0040] Figure 9 is a schematic diagram of a partial cross-sectional view of a three-dimensional memory device according to an embodiment of the present application; Figure 8F ;

[0041] Figure 10 is a block diagram of a memory system according to an exemplary embodiment of the present application;

[0042] Figure 11A is a schematic diagram of a memory card according to an exemplary embodiment of the present application;

[0043] Figure 11B is a schematic diagram of a solid state drive (SSD) according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0044] The technical solutions of the present application will be described in further detail below in conjunction with the drawings and examples. Although the exemplary implementation methods of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0045] The present application will be described in further detail below in conjunction with the drawings and examples. Although the exemplary implementation methods of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0046] In the embodiments of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0047] In the embodiments of the present application, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Furthermore, the layer can be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal plane at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface.

[0048] It should be noted that the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0049] Please refer to Figure 1 , Figure 1 is a top view structure schematic of a three-dimensional memory device provided in the related art Figure 1 . The three-dimensional memory device includes a plurality of gate line slits 10 (GLS) extending in the X direction, a stack structure and a channel structure 22 between two adjacent gate line slits 10 forming a block structure 20, and a TSG CUT 21 extending in the X direction in the block structure 20, which divides the block structure 20 into two storage areas (fingers) 20a, so that the TSG of one storage area 20a can be controlled individually. As shown in Figure 1 , there are nine rows of channel structures in the Y direction in one block structure 20, and the position of the middle row of channel structures is sacrificed to be a dummy channel structure 23 due to the existence of the TSG Cut. Figure 2 shows a top view structure schematic of a three-dimensional memory device in the related art Figure 2In addition, a plurality of (equal to or greater than 2) TSG cuts 105 can be arranged between two adjacent GLSs 101 to divide the block structure 102 into a plurality (>2) of storage areas 102a. Figure 2 The method of arranging a plurality of TSG cuts between adjacent GLSs can increase more rows of channel structures 104 in the Y direction in one block structure 102, and the channel structures 104 in each storage area can be controlled individually. However, since each TSG cut needs a row of channel structures as dummy channel structures 103, the problem of affecting the storage density still exists. Here, the X direction is the first direction, and the Y direction is the second direction.

[0050] Based on this, in an embodiment of the present application, a three-dimensional memory device is provided, please refer to Figure 3 , Figure 3 The cross-sectional structure schematic diagram of the three-dimensional memory device provided in the embodiment of the present application. The three-dimensional memory device includes a substrate and a stack structure 300 and a channel structure penetrating the stack structure, which are located on the substrate and are alternately stacked by gate layers 320 and insulating layers 310, the gate layers 320 include a top select gate layer located at the top of the stack structure 300, and the channel structure includes a memory layer 420, a channel layer 410 and a channel oxide 424 arranged in turn from outside to inside along the radial direction of the channel hole. A plurality of top select gate tangents 425 penetrate the top select gate layer to divide the stack structure 300 into a plurality of storage areas. The above-mentioned three-dimensional memory device makes the top select gate tangents directly formed between the first channel structures 400, and does not damage the function of the first channel structure itself, avoiding the problem of area waste caused by occupying a row of channel structure positions to form the top select gate tangents, and improving the storage density of the device. Specifically, please refer to the top view structure schematic diagram of the three-dimensional memory device provided in the embodiment of the present application Figure 4 In the embodiment of the present application, the channel structure includes a first channel structure and a second channel structure, the first channel structure 400 is a channel structure located in different storage areas 402a and adjacent to each other, and the second channel structure 430 is a channel structure other than the first channel structure 400, i.e. the channel structure not penetrated by the top select gate tangents 425. The top select gate tangents 425 between the adjacent gate line gaps 401 are formed between the first channel structures 400, Figure 4 (A)-(C) in the figure respectively give examples of arranging 1-3 top select gate tangents between adjacent gate line gaps 401. Generally, the more top select gate tangents arranged between adjacent gate line gaps, the greater the storage density of the device, and the number of top select gate tangents can be selected according to the needs in actual application. It should be noted that, Figure 3The first trench structure is only schematically shown.

[0051] The inventor further improves the top select gate cut line through research and analysis of the three-dimensional memory device in the above-mentioned embodiments of the present application, so that the finally formed top select gate cut line directly contacts the channel oxide of the channel structure located in different storage areas and adjacent to each other, to a certain extent, reducing the leakage problem caused by the partial channel layer losing the control of the gate due to the top select gate cut line penetrating the top select gate layer.

[0052] The embodiment of the present application provides a manufacturing method of a three-dimensional memory device, Figure 5 The implementation flowchart of the manufacturing method of the three-dimensional memory device provided by the embodiment of the present application is shown in the figure, Figures 6A-6E The cross-sectional schematic view of the exemplary process of the manufacturing method of the three-dimensional memory device of the embodiment of the present application is shown in the figure, Figure 7 The manufacturing method of the three-dimensional memory device is described in combination with 6A-6E and Figure 6E The partial top view schematic diagram of the three-dimensional memory device is shown in the figure, and the manufacturing method of the three-dimensional memory device is described in combination with 6A-6E and Figure 7 It should be noted that, Figures 6A-8E The cross-sectional view along the ZOY plane is shown in the figure, Figure 7 The cross-sectional view along the XOY plane is shown in the figure. As shown in Figure 5 , Figures 6A-6E and Figure 7 The specific steps of the manufacturing method of the three-dimensional memory device include:

[0053] Step S501: providing a substrate; the substrate includes a substrate, a stack structure 500 located on the substrate and alternately stacked by a gate layer 520 and an insulating layer 510, and a channel structure penetrating the stack structure 500; the gate layer includes a top select gate layer located at the top of the stack structure; the channel structure includes a memory layer 620, a channel layer 610 and a channel oxide 624 arranged in turn along the radial direction from the outside to the inside;

[0054] Step S502: forming a plurality of top select gate cutouts 626 penetrating the top select gate layer;

[0055] Step S503: filling the top select gate cutout 626 to form a top select gate cut line 627; the top select gate cut line divides the stack structure into a plurality of storage areas; wherein the top select gate cut line partially penetrates a first channel structure 600 and contacts the channel oxide 624 in the first channel structure 600; the first channel structure 600 is a channel structure located in different storage areas and adjacent to each other.

[0056] In the embodiments of the present application, the channel structures include first channel structures and second channel structures, and the first channel structures and the second channel structures are identical in structure and function. The first channel structures are channel structures located in different storage regions and adjacent to each other, i.e., channel structures intersected by the top selection gate cut line. The second channel structures are channel structures other than the first channel structures, i.e., channel structures not intersected by the top selection gate cut line. It should be noted that, Figures 6A-6E and Figure 7 only the first channel structures are shown in

[0057] In some embodiments, the substrate (not shown) can be a semiconductor substrate. The semiconductor substrate can be a single-element semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a silicon-germanium substrate, etc.), or a silicon-on-insulator substrate, a germanium-on-insulator (GeOI) substrate, etc. The material of the insulating layer 510 can be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The material of the gate layer 520 can be a conductive material such as tungsten, cobalt, copper, nickel, etc., or can be polysilicon, doped silicon, or any combination thereof. The gate layer 520 can also be a dummy gate layer, and the material thereof can be, for example, a silicon nitride layer. The dummy gate layer can be replaced by a gate layer at an appropriate time. The deposition of the dummy gate layer and the insulating layer can include various methods such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD) methods such as Molecular Beam Epitaxy (MBE), thermal oxidation, evaporation, sputtering, etc. The deposition is performed alternately on the substrate to form a stack structure.

[0058] In some embodiments, referring to Figure 6A , the memory layer 620, the channel layer 610, and the channel oxide 624 are sequentially arranged along the radial direction of the first channel structure 600 from the outside to the inside. The memory layer 620 can include a blocking layer 623, a charge trapping layer 622, and a tunneling layer 621 sequentially arranged along the radial direction of the channel hole from the outside to the inside. The materials of the blocking layer 623 and the tunneling layer 621 can be silicon oxide, and the material of the charge trapping layer 622 can be silicon nitride. The channel oxide 624 arranged in the channel layer 610 can act as a support, and the material of the channel layer 610 can include semiconductor materials such as monocrystalline silicon and polycrystalline silicon. One or more thin film deposition processes such as ALD, CVD, PVD, etc. or any combination thereof can be used to form the memory layer 620, the channel layer 610, and the channel oxide 624 in the channel hole.

[0059] Specifically, the step S502 of forming the top select gate cutouts further includes etching the top select gate layer and the first channel structure to remove the first channel structure in the memory layer 620 and the partial channel layer 610 of the top select gate layer, to form a plurality of first cutouts 625, specifically as shown in Figure 6B The inner diameter of the first cutout 625 is greater than the distance between the channel structures in different memory areas and adjacent to each other. Specifically, in the step of forming the plurality of first cutouts 625, the top select gate layer can be etched by using, for example, a dry etching process, and the depth of the first cutout is controlled to the number of select gate layers required for optimal device performance, for example, between 1 layer and 10 layers of stacked structure, by adjusting the process parameters of etching. Then, the barrier layer 623, the charge trapping layer 622, the tunneling layer 621 and the partial channel layer 610 in the memory layer are etched in sequence, and the etching method can be dry etching, which can be, for example, plasma etching. In the embodiments of the present application, please refer to Figure 6C The channel layer of the first channel structure in the top select gate layer is removed by the first cutout 625 to form a plurality of top select gate cutouts 626, specifically, the channel layer can be removed by etching process, for example, dry etching process.

[0060] In some embodiments, please refer to Figure 6D The top select gate cutouts 626 are filled to form the top select gate cutlines 627. The insulating material filling the top select gate cutouts can be silicon oxide, and the flatness of the structure after filling may not be good according to different forming methods (for example: CVD, ALD, spin coating method, etc.), and when the flatness is not good, the planarization process can be performed by chemical mechanical polishing (CMP) process.

[0061] In the embodiments of the present application, the top select gate cutlines 627 extend in a first direction parallel to the substrate; the top select gate cutlines 627 are spaced apart in a second direction parallel to the substrate; wherein the first direction and the second direction are perpendicular to each other. In some embodiments, the top select gate cutlines divide the top select gate into a plurality of isolated regions, and the number of rows of channel structures between adjacent top select gate cutlines in the second direction is the same. In a specific embodiment, the number of rows can be 4 rows. Here, the X direction is the first direction, and the Y direction is the second direction.

[0062] In the embodiments of the present application, the top select gate cutlines 627 can include air gaps 628, please refer to Figure 6E, the air gap 628 is formed in the top select gate cut by the insulating material. In some embodiments, the top select gate cut is partially treated by vacuum when being filled, and is in a vacuum state to form an air gap, so that the storage areas of the three-dimensional memory device are electrically isolated from each other by the air gap. Since the air gap has a lower dielectric constant, the isolation between the storage areas of the memory can be more effective, so that the overall working performance of the memory is better.

[0063] Figure 6E A cross-sectional structure of a three-dimensional memory device formed by the method is shown in FIG. 6. Figure 5 A cross-sectional structure of a three-dimensional memory device formed by the method is shown in FIG. 6. Figure 6E and Figure 7 As shown in FIG. 6, the three-dimensional memory device includes a substrate including a substrate, a stack structure 500 located on the substrate and including gate layers 520 and insulating layers 510 stacked alternately, and a channel structure penetrating through the stack structure; the gate layers 520 include a top select gate layer located at the top of the stack structure 500; the channel structure includes, in order from the outside to the inside in the radial direction, a memory layer 620, a channel layer 610, and a channel oxide 624; a plurality of top select gate cuts 627 penetrating through the top select gate layer to divide the stack structure 500 into a plurality of storage areas; the top select gate cut 627 partially penetrates through the first channel structure 600 and contacts the channel oxide 624 in the first channel structure; and the first channel structure is a channel structure located in different storage areas and adjacent to each other.

[0064] In an embodiment of the present application, the top select gate cut is partially overlapped with the first channel structure in the substrate. In some embodiments, the depth of the top select gate cut in the third direction perpendicular to the stack structure can be controlled by the process parameters of etching (for example: etching time, gas flow, ratio, pressure, temperature, etc.), for example, in the case of a certain etching rate, the longer the etching time, the deeper the top select gate cut formed in the third direction. In an embodiment of the present application, the depth of the top select gate cut can be controlled to the number of select gate layers required for optimal device performance, for example, between 1 and 10 layers of the stack structure, by adjusting the process parameters of etching. The etching method can be dry etching, which can be, for example, plasma etching.

[0065] An embodiment of the present application also provides a manufacturing method of a three-dimensional memory device, Figure 5 An implementation flowchart of the manufacturing method of the three-dimensional memory device provided by an embodiment of the present application is shown in FIG. 8. Figures 8A-8F A cross-sectional schematic diagram of an exemplary process of the manufacturing method of the three-dimensional memory device of an embodiment of the present application is shown in FIG. 9. Figure 9 An embodiment of the present application also provides a manufacturing method of a three-dimensional memory device, Figure 8Fa partial cross-sectional view of the three-dimensional memory device, and a method of manufacturing the three-dimensional memory device incorporating 8A-8F and Figure 9 The following description is provided in the context of the embodiments described below. It is to be appreciated that the embodiments described below are merely illustrative of the principles of the application. Figures 8A-8F Fig. 8A is a partial cross-sectional view of the three-dimensional memory device along the ZOY plane, Figure 9 Fig. 8B is a partial cross-sectional view of the three-dimensional memory device along the XOY plane. As shown in Figs. 8A and 8B, the three-dimensional memory device includes a substrate, a stack structure 700 and a channel structure 800. Figure 5 Figures 8A-8F Figure 9 The method of manufacturing the three-dimensional memory device includes the following steps:

[0066] Step S501: providing a substrate; the substrate includes a substrate, a stack structure 700 and a channel structure 800, the stack structure 700 is located on the substrate and includes gate layers 720 and insulating layers 710 which are alternately stacked, the gate layers include a top select gate layer located at the top of the stack structure, the channel structure 800 includes, in order from the outside to the inside along the radial direction, a memory layer 820, a channel layer 810 and a channel oxide 824.

[0067] Step S502: forming a plurality of top select gate cuts 826 which penetrate the top select gate layer.

[0068] Step S503: filling the top select gate cuts 826 to form top select gate cut lines 827; the top select gate cut lines divide the stack structure into a plurality of memory areas; wherein the top select gate cut lines partially pass through a first channel structure 800 and contact the channel oxide 824 in the first channel structure 800; the first channel structure 800 is a channel structure located in different memory areas and adjacent to each other.

[0069] In the embodiments of the present application, the channel structure includes a first channel structure and a second channel structure, and the first channel structure and the second channel structure are the same in structure and function. The first channel structure is a channel structure located in different memory areas and adjacent to each other, i.e., a channel structure which is penetrated by the top select gate cut line; the second channel structure is a channel structure other than the first channel structure, i.e., a channel structure which is not penetrated by the top select gate cut line. It should be noted that Figures 8A-8E Figure 9 Only the first channel structure is shown in Figs. 8A-8F.

[0070] ​​​In some embodiments, the substrate (not shown) may be a semiconductor substrate. The semiconductor substrate may be a single-element semiconductor material substrate (e.g., a silicon substrate, germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon substrate, etc.), or a silicon-on-insulator substrate, germanium-on-insulator (GeOI) substrate, etc. The material of the insulating layer 710 may be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The material of the gate layer 720 may be a conductive material such as tungsten, cobalt, copper, nickel, etc., or polycrystalline silicon, doped silicon, or any combination thereof. The gate layer 720 may also be a dummy gate layer, the material of which may be, for example, a silicon nitride layer. The dummy gate layer may be replaced with the gate layer when appropriate. The deposition method of the dummy gate layer and the insulating layer may include various methods such as CVD, ALD, or PVD such as MBE, thermal oxidation, evaporation, sputtering, etc., which are sequentially deposited alternately on the substrate to form a stacked structure.

[0071] In some embodiments, please refer to Figure 8A Along the radial direction of the first channel structure 800, from the outside to the inside, are sequentially disposed a memory layer 820, a channel layer 810, and a channel oxide 824. The memory layer 820 may include a barrier layer 823, a charge trapping layer 822, and a tunneling layer 821, sequentially disposed along the radial direction of the channel via. The barrier layer 823 and the tunneling layer 821 may be made of silicon oxide, and the charge trapping layer 822 may be made of silicon nitride. The channel oxide 824 disposed within the channel layer 810 can act as a support, and the material of the channel layer 810 may include semiconductor materials such as monocrystalline silicon and polycrystalline silicon. The memory layer 820, the channel layer 810, and the channel oxide 824 can be formed in the channel via using one or more thin-film deposition processes, such as ALD, CVD, PVD, or any combination thereof.

[0072] Specifically, step S502 of forming the top select gate notch further includes: etching the top select gate layer located between the first channel structures to form a plurality of first notches 825. In a specific example, the top select gate layer located between the first channel structures and the barrier layer of the first channel structures are etched to form a plurality of first notches 825. Figure 8B As shown, the inner diameter of the first notch 825 is larger than the distance between the memory layers 820 of adjacent first channel structures 800, and smaller than the distance between the channel oxides 824 of adjacent first channel structures 800. The memory layer 820 of the first channel structure located at the top select gate layer is removed through the first notch 825 to form an intermediate stage notch 826' (e.g., Figure 8C (as shown), and then continue removing the channel layer to form multiple top select gate cutouts 826 (as shown). Figure 8DThe first cutout can be formed by exposing, lithography and etching using a patterned mask. The etching method can be dry etching, which can be plasma etching for example.

[0073] In some embodiments, referring to Figure 8E The top select gate cut 826 is filled to form the top select gate cutline 827. The insulating material filling the top select gate cut can be silicon oxide, and the filling method can be CVD, ALD, spin coating, etc. The filling method can result in poor flatness of the structure surface, and the CMP process can be used to planarize the structure surface.

[0074] In the embodiments of the present application, the top select gate cutline 827 extends in a first direction parallel to the substrate, and the top select gate cutline 827 is spaced apart in a second direction parallel to the substrate, and the first direction is perpendicular to the second direction. In some embodiments, the top select gate cutline divides the top select gate into a plurality of isolated regions, and the number of rows of channel structures between adjacent top select gate cutlines in the second direction is the same. In a specific embodiment, the number of rows can be 4 rows. Here, the X direction is the first direction, and the Y direction is the second direction.

[0075] In the embodiments of the present application, the top select gate cutline 827 can include an air gap 828, referring to Figure 8F The air gap 828 is formed in the top select gate cutline by the insulating material. In some embodiments, the top select gate cut is partially treated by vacuum during filling, and the air gap is formed in the vacuum state. The storage area and the storage area of the three-dimensional memory device are electrically isolated by the air gap. Since the air gap has a lower dielectric constant, the isolation between the storage areas of the memory is more effective, and the overall performance of the memory is better.

[0076] Figure 8F Another cross-sectional structure schematic diagram of a three-dimensional memory device formed by the method is shown, as shown in Figure 5 Another cross-sectional structure schematic diagram of a three-dimensional memory device formed by the method is shown, as shown in Figure 8F and Figure 9As shown, the three-dimensional memory device includes a substrate including a stack structure 700 and a channel structure 800 penetrating the stack structure 700 on a substrate, the stack structure 700 including a top select gate layer 720 on a top of the stack structure 700, the channel structure 800 including a memory layer 820, a channel layer 810, and a channel oxide 824 arranged in a radial direction from outside to inside in sequence, a plurality of top select gate tangs 827 penetrating the top select gate layer 720 to divide the stack structure 700 into a plurality of memory regions, the top select gate tangs 827 partially penetrating the first channel structure 800 and contacting the channel oxide 824 in the first channel structure, the first channel structure being a channel structure located in different memory regions and adjacent to each other.

[0077] In embodiments of the present application, the top select gate tangs have a depth in a third direction perpendicular to the stack structure that is controlled by process parameters of etching (e.g., etching time, gas flow, ratio, pressure, temperature, etc.). For example, in the case of a constant etching rate, the longer the etching time, the deeper the top select gate tangs in the third direction. In an embodiment of the present application, the depth of the top select gate tangs can be controlled to a number of select gate layers required for optimal device performance, for example, between 1 and 10 layers of the stack structure, by adjusting the process parameters of etching. The etching method can be dry etching, which can be, for example, plasma etching.

[0078] Figure 10 A block diagram of an exemplary memory system 100 having a three-dimensional memory device is shown in accordance with some aspects of the present application. The memory system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage. As shown in FIG. 1, the system 100 can include a host 1008 and a memory system 1002 including one or more three-dimensional memory devices 1004 and a controller 1006, the three-dimensional memory device 1004 including an array of memory cells and a plurality of page buffers. The host 1008 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 1008 can be configured to send data to or receive data from the three-dimensional memory device 1004. Figure 10 As shown in FIG. 1, the system 100 can include a host 1008 and a memory system 1002 including one or more three-dimensional memory devices 1004 and a controller 1006, the three-dimensional memory device 1004 including an array of memory cells and a plurality of page buffers. The host 1008 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 1008 can be configured to send data to or receive data from the three-dimensional memory device 1004.

[0079] The three-dimensional memory device 1004 can be any three-dimensional memory device of the present application. According to some embodiments, a controller 1006 is coupled to the three-dimensional memory device 1004 and to a host 1008, and is configured to control the three-dimensional memory device. The controller 1006 can manage data stored in the three-dimensional memory device and communicate with the host 1008. In some embodiments, the controller 1006 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile telephones, etc. In some embodiments, the controller 1006 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc. and enterprise storage. The controller 1006 can be configured to control operations of the three-dimensional memory device 1004, such as read, erase, and program operations. The controller 1006 can also be configured to manage various functions related to data stored or to be stored in the three-dimensional memory device 1004, including but not limited to bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the controller 1006 is also configured to process error-correcting codes (ECC) related to data read from or written to the three-dimensional memory device 1004. The controller 1006 can also perform any other suitable functions, such as formatting the three-dimensional memory device 1004. The controller 1006 can communicate with external devices (e.g., the host 1008) according to a particular communication protocol. For example, the controller 1006 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0080] The controller 1006 and the one or more three-dimensional memory devices 1004 can be integrated into various types of storage devices, such as included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 1002 can be implemented and packaged into different types of end electronic products. In as Figure 11AIn one example shown, controller 1006 and a single three-dimensional storage device 1004 can be integrated into memory card 1102. Memory card 1102 may include PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 1102 may also include a connection between memory card 1102 and host computer (e.g., Figure 10 The memory card connector 1104 is coupled to the host 1008. In such a... Figure 11B In another example shown, the controller 1006 and multiple three-dimensional storage devices 1004 can be integrated into the SSD 1106. The SSD 1106 may also include a connection between the SSD 1106 and a host (e.g., Figure 10 The SSD connector 1108 is coupled to the host 1008. In some embodiments, the storage capacity and / or operating speed of the SSD 1106 is greater than the storage capacity and / or operating speed of the memory card 1102.

[0081] This application provides a three-dimensional memory device, a manufacturing method, and a memory system. The method includes: providing a substrate; the substrate includes a substrate, a stacked structure on the substrate consisting of alternating gate layers and insulating layers, and a channel structure penetrating the stacked structure; the gate layer includes a top select gate layer located on top of the stacked structure; the channel structure includes a memory layer, a channel layer, and a channel oxide arranged radially from the outside to the inside; forming a plurality of top select gate cutouts penetrating the top select gate layer; filling the top select gate cutouts to form top select gate tangents; the top select gate tangents dividing the stacked structure into a plurality of memory regions; wherein the top select gate tangents partially pass through a first channel structure and contact the channel oxide in the first channel structure; the first channel structure is an adjacent channel structure located in different memory regions. The top select gate tangents formed by the method provided in this application only partially pass through the portion of the first channel structure located in the top select gate layer, without destroying the function of the first channel structure itself. Therefore, top select gate tangents can be formed without introducing a dummy channel structure, thereby improving memory density. Furthermore, the channel oxide in the first channel structure is in direct contact with the top select gate tangent, which to some extent reduces the leakage problem caused by the loss of gate control in the channel layer of the first channel structure.

[0082] It should be understood that the term "in one embodiment" or "in some embodiments" throughout the specification means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the application. Therefore, appearances of the phrase "in one embodiment" or "in some embodiments" in various places throughout the specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of steps in the above-described processes does not necessarily mean that the steps are executed in the order as described. The execution order of the steps should be determined according to the function and internal logic of the steps, and should not constitute any limitation on the implementation process of the embodiments of the application. The sequence numbers of the above-described embodiments of the application are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0083] The above description is merely illustrative of the application, and the scope of the application is not limited thereto. Any modifications or replacements of the application within the technical scope disclosed by the application should be covered within the scope of the application. Therefore, the scope of the application should be determined by the scope of the claims.

Claims

1. A method for manufacturing a three-dimensional memory device, characterized by, The method comprises: providing a substrate; the substrate comprises a substrate, a stack structure and a channel structure penetrating through the stack structure, the stack structure being alternately stacked by gate layers and insulating layers on the substrate; the gate layers comprise a top select gate layer located at the top of the stack structure; the channel structure comprises a memory layer, a channel layer and a channel oxide arranged in turn along a radial direction from outside to inside; forming a plurality of top select gate cuts penetrating through the top select gate layer; filling the top select gate cuts to form top select gate cut lines; the top select gate cut lines divide the stack structure into a plurality of memory areas; wherein the top select gate cut lines partially pass through a first channel structure and contact the channel oxide in the first channel structure; the first channel structure is a channel structure located in different memory areas and adjacent to each other.

2. The method of claim 1, wherein, The step of forming the top select gate cut comprises: etching the top select gate layer and the first channel structure to remove the memory layer and part of the channel layer of the first channel structure located in the top select gate layer to form a plurality of first cuts; removing the channel layer of the first channel structure located in the top select gate layer through the first cut to form a plurality of top select gate cuts.

3. The method of claim 2, wherein, The inner diameter of the first cut is greater than the distance between the channel structures located in different memory areas and adjacent to each other.

4. The method of claim 1, wherein, The step of forming the top select gate cut comprises: etching the top select gate layer between the first channel structures to form a plurality of first cuts; removing the memory layer and the channel layer of the first channel structure located in the top select gate layer through the first cut to form a plurality of top select gate cuts.

5. The method of claim 4, wherein, The inner diameter of the first cut is greater than the distance between the memory layers of adjacent first channel structures and less than the distance between the channel oxides of adjacent first channel structures.

6. The method of claim 1, wherein, The top select gate cut lines extend in a first direction parallel to the substrate; the top select gate cut lines are spaced apart in a second direction parallel to the substrate; wherein the first direction and the second direction are perpendicular to each other.

7. The method of claim 1, wherein, The number of rows of channel structures between adjacent top select gate cut lines is the same.

8. A three-dimensional memory device, comprising: Comprise: a substrate; the substrate comprises a substrate, a stack structure and a channel structure penetrating through the stack structure, the stack structure being alternately stacked by gate layers and insulating layers on the substrate; the gate layers comprise a top select gate layer located at the top of the stack structure; the channel structure comprises a memory layer, a channel layer and a channel oxide arranged in turn along a radial direction from outside to inside; a plurality of top select gate cut lines penetrating through the top select gate layer to divide the stack structure into a plurality of memory areas; the top select gate cut lines partially pass through a first channel structure and contact the channel oxide in the first channel structure; the first channel structure is a channel structure located in different memory areas and adjacent to each other.

9. The three-dimensional memory device of claim 8, wherein, The top select gate cut lines extend in a first direction parallel to the substrate; the top select gate cut lines are spaced apart in a second direction parallel to the substrate; wherein the first direction and the second direction are perpendicular to each other.

10. The three-dimensional memory device of claim 8, wherein, The channel structures between adjacent ones of the top select gate cutlines have the same number of rows.

11. The three-dimensional memory device of claim 8, wherein, The material of the top select gate cutlines comprises an insulating material.

12. The three-dimensional memory device of claim 11, wherein, The top select gate cutlines comprise an air gap formed therein by the insulating material.

13. The three-dimensional memory device of claim 8, wherein: A footprint of the top select gate cutlines on the substrate partially overlaps a footprint of the first channel structures on the substrate.

14. A memory system, characterized by comprising: Comprising: at least one three-dimensional memory device as claimed in any one of claims 8 to 13; and a controller coupled to the three-dimensional memory device and configured to control the three-dimensional memory device.

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