Semiconductor packaging device and preparation method thereof

Abstract

The present application discloses a semiconductor packaging device and a preparation method thereof, belonging to the field of semiconductor packaging technology. The preparation method first provides a first intermediate, the first intermediate includes a chip and a plurality of first conductive blocks, the first main surface of the chip has a plurality of chip electrodes, the first conductive blocks are located at the chip electrode position and are electrically connected to the chip electrodes; then a temporary carrier is placed on a horizontal plane, and the first intermediate is arranged opposite to the temporary carrier, a plurality of conductive pads arranged at intervals are formed on the temporary carrier, and one end of a first conductive block away from the chip faces a conductive pad; then the first conductive block and the corresponding conductive pad are bonded by a thermal compression bonding process; then the temporary carrier is removed. The present application can improve the packaging yield and the reliability of semiconductor packaging devices.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging device and a preparation method thereof. Background Art

[0002] In the field of semiconductor packaging technology, when fan-out packaging is performed on a chip, the back of the chip is usually adhered to a carrier, and then the chip and the carrier are sealed with a molding compound and compression molded to complete the plastic encapsulation process. The conductive pins on the front of the chip are then exposed by front-side grinding, and other processes such as rewiring are then performed to electrically connect the conductive pins of the chip and the package pins to complete the fan-out packaging.

[0003] However, during the plastic encapsulation process, due to the bonding method between the chip and the temporary carrier, the chip may shift (die shift) after being pressed into shape, resulting in a decrease in the yield of subsequent processes such as rewiring and an increase in the probability of damage to the chip's electrical connection lines, thereby reducing the packaging yield and the reliability of semiconductor packaging devices. Summary of the invention

[0004] The main technical problem solved by the present application is to provide a semiconductor packaging device and a preparation method thereof, which can improve the packaging yield and the reliability of the semiconductor packaging device.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a method for preparing a semiconductor packaging device, comprising:

[0006] Providing a first intermediate, the first intermediate comprising a chip and a plurality of first conductive blocks, the first main surface of the chip having a plurality of chip electrodes, the first conductive blocks being located at the positions of the chip electrodes and being electrically connected to the chip electrodes;

[0007] Placing a temporary carrier on a horizontal plane, and arranging the first intermediate body and the temporary carrier opposite to each other; wherein a plurality of conductive pads arranged at intervals are formed on the temporary carrier, and an end of one of the first conductive blocks away from the chip faces one of the conductive pads;

[0008] Bonding the first conductive block and the corresponding conductive pad by using a thermal compression bonding process;

[0009] The temporary carrier plate is removed.

[0010] Optionally, before the step of removing the temporary carrier plate, the method further includes:

[0011] An underfill is formed between the chip and the temporary carrier, and the underfill covers the side surfaces of the first conductive block.

[0012] Optionally, after the step of forming an underfill between the chip and the temporary carrier, the method further includes:

[0013] A plastic encapsulation layer is formed on the side of the temporary carrier where the conductive pad is formed; the plastic encapsulation layer at least covers the bottom filler and the side surface of the chip.

[0014] Optionally, there are multiple first intermediates, and the plastic encapsulation layer continuously covers all the first intermediates; and the preparation method further comprises:

[0015] Part of the plastic encapsulation layer located between adjacent first intermediate bodies is cut off to obtain a plurality of the semiconductor package devices.

[0016] Optionally, before the step of placing the temporary carrier on a horizontal plane and arranging the first intermediate body opposite to the temporary carrier, the method further comprises:

[0017] Forming a first insulating layer on a surface of one side of the temporary carrier and patterning the layer to form a plurality of first openings;

[0018] A first metal layer is formed on a side of the first insulating layer away from the temporary carrier and patterned to form a plurality of the conductive pads; one of the conductive pads contacts the temporary carrier through one of the first openings.

[0019] Optionally, after the step of removing the temporary carrier, the method further includes:

[0020] A second metal layer is formed on a side of the conductive pad away from the chip and patterned to form a redistribution layer; the redistribution layer includes a plurality of redistribution electrodes, and one of the redistribution electrodes is electrically connected to at least one of the conductive pads.

[0021] Optionally, after the step of forming and patterning a second metal layer on a side of the conductive pad and the first insulating layer facing away from the first intermediate body, the method further includes:

[0022] forming a second insulating layer on a side of the first insulating layer away from the chip and patterning the layer to form a plurality of second openings, wherein one redistribution electrode is exposed from one of the second openings;

[0023] A plurality of second conductive blocks are formed on a side of the second insulating layer away from the chip, and one of the second conductive blocks is electrically connected to one of the redistribution electrodes via one of the second openings.

[0024] In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a semiconductor packaging device, the semiconductor packaging device is prepared by the semiconductor packaging device preparation method described in the above technical solution, and the semiconductor packaging device comprises:

[0025] A first intermediate body, the first intermediate body comprising a chip and a plurality of first conductive blocks, the first main surface of the chip having a plurality of chip electrodes, the first conductive blocks being located at the positions of the chip electrodes and being electrically connected to the chip electrodes;

[0026] A plurality of conductive pads are located at an end of the first conductive block away from the chip, and one of the conductive pads is electrically connected to a corresponding first conductive block.

[0027] Optionally, the semiconductor packaging device further includes:

[0028] A first insulating layer is located at an end of the first conductive block away from the chip, a plurality of first openings are formed on the first insulating layer, and one of the conductive pads is electrically connected to the corresponding first conductive block through one of the first openings;

[0029] An underfill is located between the first insulating layer and the chip, and the underfill covers the side surfaces of the first conductive block.

[0030] Optionally, the semiconductor packaging device further includes:

[0031] a redistribution layer, comprising a plurality of redistribution electrodes, wherein one of the redistribution electrodes is electrically connected to at least one of the conductive pads;

[0032] a second insulating layer, located on a side of the first insulating layer away from the chip, a plurality of second openings being formed on the second insulating layer, and one of the redistribution electrodes being exposed from one of the second openings;

[0033] A plurality of second conductive blocks are located on a side of the second insulating layer away from the chip, and one of the second conductive blocks is electrically connected to one of the redistribution electrodes via one of the second openings.

[0034] The beneficial effects of the present application are as follows: the preparation method of the semiconductor packaging device provided by the present application first provides a first intermediate, the first intermediate includes a chip and a plurality of first conductive blocks, the first main surface of the chip has a plurality of chip electrodes, the first conductive blocks are located at the chip electrode positions and are electrically connected to the chip electrodes; then a temporary carrier is placed on a horizontal plane, and the first intermediate is arranged opposite to the temporary carrier, a plurality of conductive pads arranged at intervals are formed on the temporary carrier, and one end of a first conductive block away from the chip faces a conductive pad; then the first conductive block and the corresponding conductive pad are bonded by a thermocompression bonding process; then the temporary carrier is removed. The present application places the chip front side downward toward the temporary carrier, and uses a thermocompression bonding process to first bond the first conductive block on the chip with the conductive pad on the temporary carrier, which can improve the alignment accuracy of the first conductive block and the conductive pad, reduce the probability of chip displacement, and reduce the probability of damage to the electrical connection line of the chip, thereby improving the packaging yield and the reliability of the semiconductor packaging device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0036] Figure 1 A schematic diagram of a process of an embodiment of a method for preparing a semiconductor packaging device of the present application;

[0037] Figure 2a for Figure 1 A structural schematic diagram corresponding to an implementation method of step S11;

[0038] Figure 2b for Figure 1 A structural schematic diagram corresponding to an implementation method of step S12;

[0039] Figure 2c for Figure 1 A structural schematic diagram corresponding to an implementation method of step S13;

[0040] Figure 3 for Figure 1 A structural schematic diagram corresponding to an implementation method of step S14;

[0041] Figure 4 A schematic diagram of another embodiment of the method for preparing a semiconductor packaging device of the present application;

[0042] Figure 5 It is a structural schematic diagram corresponding to an implementation method of step S24 in FIG2 ;

[0043] Figure 6 It is a structural schematic diagram corresponding to an implementation method of step S25 in FIG2 ;

[0044] Figure 7 A schematic diagram of another embodiment of the method for preparing a semiconductor packaging device of the present application;

[0045] Figure 8 for Figure 7 A structural schematic diagram corresponding to an implementation method of step S35;

[0046] Fig. 9 for Figure 7 A structural schematic diagram corresponding to an implementation method of step S36 in FIG.

[0047] Fig.10 A schematic diagram of another embodiment of the method for preparing a semiconductor packaging device of the present application;

[0048] Fig.11a for Fig.10 A structural schematic diagram corresponding to an implementation method of step S41 in FIG. 1 ;

[0049] Fig.11b for Fig.10 A structural schematic diagram corresponding to an implementation method of step S42;

[0050] Fig.12 A schematic diagram of another embodiment of the method for preparing a semiconductor packaging device of the present application;

[0051] Fig.13 for Fig.12 A structural schematic diagram corresponding to an implementation method of step S51;

[0052] Fig.14 A schematic diagram of another embodiment of the method for preparing a semiconductor packaging device of the present application;

[0053] Fig.15 for Fig.14 A structural schematic diagram corresponding to an implementation method of step S62;

[0054] Fig.16 for Fig.14 A structural schematic diagram corresponding to an implementation method of step S63;

[0055] Fig.17 This is a schematic structural diagram of another embodiment of the semiconductor packaging device of the present application. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0057] See also Figure 1 , Figure 1 This is a flow chart of an embodiment of a method for preparing a semiconductor packaging device of the present application. The method for preparing a semiconductor packaging device includes the following steps.

[0058] Step S11, providing a first intermediate body, the first intermediate body comprising a chip and a plurality of first conductive blocks, the first main surface of the chip having a plurality of chip electrodes, the first conductive blocks being located at the chip electrode positions and electrically connected to the chip electrodes.

[0059] See also Figure 2a , Figure 2a for Figure 1 The structural schematic diagram corresponding to the first embodiment of step S11 in the embodiment of the present invention first provides a first intermediate 111, the first intermediate 111 includes a chip 11 and a plurality of first conductive blocks 12, the first main surface of the chip 11 has a plurality of chip electrodes 110, and the first conductive blocks 12 are located at the positions of the chip electrodes 110 and are electrically connected to the chip electrodes 110. The first conductive blocks 12 may include copper pillars and / or solder balls, and are prepared by electroplating. The first conductive blocks 12 may be directly prepared on a wafer, and then a plurality of first intermediates 111 may be obtained by cutting.

[0060] Step S12, placing a temporary carrier on a horizontal plane, and arranging the first intermediate body and the temporary carrier opposite to each other; wherein a plurality of conductive pads arranged at intervals are formed on the temporary carrier, and an end of a first conductive block away from the chip faces a conductive pad.

[0061] Please combine Figure 2a See also Figure 2b , Figure 2b for Figure 1 In the structural diagram corresponding to the embodiment of step S12, after providing the first intermediate body 111, the temporary carrier 200 is placed on a horizontal plane, and the first intermediate body 111 and the temporary carrier 200 are arranged opposite to each other. A plurality of conductive pads 112 arranged at intervals are formed on the temporary carrier 200, and one end of a first conductive block 12 away from the chip 11 faces a conductive pad 112. Figure 2aThe first intermediate body 111 is turned over to face the first main surface of the chip 11 downward, and the first conductive blocks 12 are aligned with the conductive pads 112. The arrangement of the conductive pads 112 on the temporary carrier 200 may be consistent with the arrangement of the first conductive blocks 12 on the first main surface of the chip 11.

[0062] Step S13, bonding the first conductive block and the corresponding conductive pad by using a thermal compression bonding process.

[0063] Please combine Figure 2b See also Figure 2c , Figure 2c for Figure 1 In the structural schematic diagram corresponding to the first embodiment of step S13, after the first intermediate body 111 and the temporary carrier 200 are arranged relative to each other, the first conductive block 12 and the corresponding conductive pad 112 are bonded by a thermocompression bonding process. During the thermocompression bonding process, the chip 11 is subjected to a force in a vertical direction, which avoids the impact of the molding compound on the chip in a non-vertical direction during the plastic encapsulation process, so that the first conductive block 12 on the chip 11 is smoothly electrically connected to the corresponding conductive pad 112 without deviation.

[0064] Step S14, removing the temporary carrier board.

[0065] Please combine Figure 2b See also Figure 3 , Figure 3 for Figure 1 A structural schematic diagram corresponding to an implementation method of step S14, after thermocompression bonding, the temporary carrier 200 is removed to obtain a semiconductor package device, wherein the surface of the conductive pad 112 facing away from the chip 11 is exposed, so that it can be electrically connected to other devices, or further processed by plastic encapsulation, redistribution, etc.

[0066] In this embodiment, the chip 11 is placed with its front side facing downward toward the temporary carrier 200, and a thermal compression bonding process is used to first bond the first conductive block 12 on the chip 11 to the conductive pad 112 on the temporary carrier 200. This can improve the alignment accuracy between the first conductive block 12 and the conductive pad 112, reduce the probability of chip 11 shifting, and reduce the probability of the electrical connection circuit of the chip 11 being damaged, thereby improving the packaging yield and the reliability of the semiconductor packaging device.

[0067] In one embodiment, see Figure 4 , Figure 4 This is a flow chart of another embodiment of a method for preparing a semiconductor packaging device of the present application. The method for preparing a semiconductor packaging device includes the following steps.

[0068] Step S21, providing a first intermediate body, the first intermediate body comprising a chip and a plurality of first conductive blocks, the first main surface of the chip having a plurality of chip electrodes, the first conductive blocks being located at the chip electrode positions and electrically connected to the chip electrodes.

[0069] Step S22, placing a temporary carrier on a horizontal plane, and arranging the first intermediate body and the temporary carrier opposite to each other; wherein a plurality of conductive pads arranged at intervals are formed on the temporary carrier, and an end of a first conductive block away from the chip faces a conductive pad.

[0070] Step S23 , bonding the first conductive block and the corresponding conductive pad by using a thermal compression bonding process.

[0071] Steps S21-S23 are consistent with the above-mentioned steps S11-S13 and will not be repeated here.

[0072] Step S24, forming an underfill between the chip and the temporary carrier, wherein the underfill covers the side surfaces of the first conductive block.

[0073] Please combine Figure 2c See also Figure 5 , Figure 5 for Figure 4 Step S24 is a schematic diagram of a structure corresponding to an embodiment of the present invention. After the thermal compression bonding, that is, in Figure 2c On the basis of the structure shown, an underfill 113 is further formed between the chip 11 and the temporary carrier 200. The longitudinal section of the underfill 113 is trapezoidal and covers the side of the first conductive block 12. It can protect the first conductive block 12 and make the overall structure of the device more stable.

[0074] Step S25, removing the temporary carrier board.

[0075] Please combine Figure 5 See also Figure 6 , Figure 6 for Figure 4 Step S25 is a schematic diagram of a structure corresponding to an embodiment. After the bottom fill 113 is formed, the temporary carrier 200 is further removed to obtain the following Figure 6 In the semiconductor package device shown, the conductive pad 112 is exposed on a surface of a side facing away from the chip 11, so that it can be electrically connected to other devices or further subjected to other processes such as redistribution.

[0076] In this embodiment, the chip 11 is placed with its front side facing downward toward the temporary carrier 200, and a thermal compression bonding process is used to first bond the first conductive block 12 on the chip 11 to the conductive pad 112 on the temporary carrier 200. An underfill 113 is formed between the chip 11 and the temporary carrier 200, which can reduce the probability of displacement of the chip 11 and the probability of damage to the electrical connection lines of the chip 11, thereby improving the packaging yield and the reliability of the semiconductor packaging device, and improving the structural stability of the semiconductor packaging device.

[0077] In one embodiment, see Figure 7 , Figure 7 This is a flow chart of another embodiment of a method for preparing a semiconductor packaging device of the present application. The method for preparing a semiconductor packaging device includes the following steps.

[0078] Step S31, providing a first intermediate body, the first intermediate body comprising a chip and a plurality of first conductive blocks, the first main surface of the chip having a plurality of chip electrodes, the first conductive blocks being located at the chip electrode positions and electrically connected to the chip electrodes.

[0079] Step S32, placing a temporary carrier on a horizontal plane, and arranging the first intermediate body and the temporary carrier opposite to each other; wherein a plurality of conductive pads arranged at intervals are formed on the temporary carrier, and an end of a first conductive block away from the chip faces a conductive pad.

[0080] Step S33 , bonding the first conductive block and the corresponding conductive pad by using a thermal compression bonding process.

[0081] Step S34, forming an underfill between the chip and the temporary carrier, wherein the underfill covers the side surfaces of the first conductive block.

[0082] Steps S31-S34 are consistent with the above-mentioned steps S21-S24 and will not be repeated here.

[0083] Step S35, forming a plastic encapsulation layer on the side of the temporary carrier where the conductive pad is formed; the plastic encapsulation layer at least covers the underfill and the side surface of the chip.

[0084] Please combine Figure 5 See also Figure 8 , Figure 8 for Figure 7 The structural diagram corresponding to the implementation method of step S35 in Figure 5 On the basis of the structure shown in the figure, a plastic encapsulation layer 114 is further formed on the side of the temporary carrier 200 where the conductive pad 112 is formed. The plastic encapsulation layer 114 at least covers the bottom filler 113 and the side surface of the chip 11. Figure 8 The schematic diagram shows that the plastic encapsulation layer 114 covers the side surface of the underfill 113 , the side surface of the chip 11 , and the second main surface, where the second main surface is the surface opposite to the first main surface.

[0085] In the process of forming the plastic encapsulation layer 114, a stable bond has been formed between the first intermediate body 111 and the conductive pad 112, and the bottom filler 113 further stabilizes the overall structure, which can resist the impact of the plastic encapsulation material on the chip 11 and reduce the probability of the chip 11 shifting during the plastic encapsulation process. In addition, when the plastic encapsulation layer 114 covers the second main surface of the chip 11, the plastic encapsulation layer 114 can balance the packaging stress of the first main surface, thereby reducing the probability of the chip 11 warping.

[0086] Step S36, removing the temporary carrier board.

[0087] Please combine Figure 8 See also Fig. 9 , Fig. 9 for Figure 7 The structural diagram corresponding to the embodiment of step S36 in the above embodiment, after the plastic encapsulation layer 114 is formed, the temporary carrier 200 is further removed to obtain the following Fig. 9 In the semiconductor package device shown, the conductive pad 112 is exposed on a surface of a side facing away from the chip 11, so that it can be electrically connected to other devices or further subjected to other processes such as redistribution.

[0088] In this embodiment, the chip 11 is placed with its front side facing downward toward the temporary carrier 200, and a thermocompression bonding process is used to first bond the first conductive block 12 on the chip 11 to the conductive pad 112 on the temporary carrier 200. An underfill 113 is formed between the chip 11 and the temporary carrier 200, and a plastic encapsulation layer 114 is formed to wrap the underfill 113 and the chip 11, which can reduce the probability of chip 11 shifting and the probability of the electrical connection circuits of the chip 11 being damaged, thereby improving the packaging yield and the reliability of the semiconductor packaging device, and further improving the structural stability of the semiconductor packaging device.

[0089] It can be understood that in the above embodiment, if there are multiple first intermediate bodies 111, the plastic encapsulation layer 114 formed in the above step S35 continuously covers all the first intermediate bodies 111, and after removing the temporary carrier 200, it is also necessary to cut off part of the plastic encapsulation layer 114 located between adjacent first intermediate bodies 111, so as to obtain multiple first intermediate bodies 111. Fig. 9 The semiconductor package device is shown.

[0090] In one embodiment, see Fig.10 , Fig.10 This is a flow chart of another embodiment of the method for preparing a semiconductor packaging device of the present application. The method includes steps S11-S14, or steps S21-S25, or steps S31-S36 in the above-mentioned embodiments, and before step S11, or step S21, or step S31, that is, before placing the temporary carrier 200 on a horizontal surface, it also includes the following steps.

[0091] In step S41 , a first insulating layer is formed on a surface of one side of the temporary carrier and patterned to form a plurality of first openings.

[0092] See also Fig.11a , Fig.11a for Fig.10 The schematic diagram of the structure corresponding to the first embodiment of step S41 is as follows: first, a first insulating layer 115 is formed on one side surface of the temporary carrier 200 and patterned to form a plurality of first openings M. The first insulating layer 115 may be made of an inorganic insulating layer, such as silicon oxide, silicon nitride, etc., or an organic insulating layer, such as polyimide, photoresist, etc.

[0093] The temporary carrier 200 may be a glass disc having the same shape as the wafer, and can be simultaneously hot-pressed and bonded to a plurality of first intermediate bodies 111. A desorbable intermediate layer 201 may be first bonded on the surface of the temporary carrier 200 to improve the bonding force of the first insulating layer 115 on the temporary carrier 200. The temporary carrier 200 is then removed by debonding.

[0094] In step S42, a first metal layer is formed on a side of the first insulating layer away from the temporary carrier and patterned to form a plurality of conductive pads; one conductive pad is in contact with the temporary carrier through one first opening.

[0095] Please combine Fig.11a See also Fig.11b , Fig.11b for Fig.10 The structural schematic diagram corresponding to an implementation method of step S42 further forms a first metal layer on the side of the first insulating layer 115 away from the temporary carrier 200 and performs patterning to form a plurality of conductive pads 112, wherein a conductive pad 112 contacts the temporary carrier 200 through a first opening.

[0096] In this embodiment, the conductive pad 112 is limited by the patterned first insulating layer 115, so that during the hot pressing bonding process between the conductive pad 112 and the first conductive block 12 on the surface of the chip 11, the probability of the conductive pad 112 shifting and thus causing the chip 11 to shift is reduced, thereby improving the packaging yield and the selectivity of the semiconductor packaging device.

[0097] In one embodiment, see Fig.12 , Fig.12This is a flow chart of another embodiment of the method for preparing a semiconductor packaging device of the present application. The method includes steps S11-S14, or steps S21-S25, or steps S31-S36 in the above-mentioned embodiments, and after step S14, or step S25, or step S36, that is, after removing the temporary carrier 200, it also includes the following steps.

[0098] Step S51, forming a second metal layer on the side of the conductive pad away from the chip and patterning it to form a redistribution layer; the redistribution layer includes a plurality of redistribution electrodes, and one redistribution electrode is electrically connected to at least one conductive pad.

[0099] See also Fig.13 , Fig.13 for Fig.12 The structural diagram corresponding to the implementation method of step S51 in the embodiment of FIG. Fig. 9 The semiconductor package device shown in FIG. Fig. 9 Based on the device shown, a second metal layer is further formed on the side of the conductive pad 112 facing away from the chip 11 and patterned to form a redistribution layer 116 ; the redistribution layer 116 includes a plurality of redistribution electrodes (not shown), and one redistribution electrode is electrically connected to at least one conductive pad 112 .

[0100] It is understandable that in some application scenarios, the redistribution electrodes correspond to the conductive pads 112 one by one. In some application scenarios, some conductive pads 112 need to be connected in series and are connected to the same redistribution electrode. Fig.13 The schematic diagram shows that two adjacent conductive pads 112 on the left are connected to the same redistribution electrode.

[0101] In the semiconductor packaging device prepared in this embodiment, the first conductive block 12 on the surface of the chip 11 is bonded to the conductive pad 112 by a thermal compression bonding process, which reduces the probability of chip 11 shifting, and improves packaging yield and device reliability.

[0102] In one embodiment, see Fig.14 , Fig.14 This is a flow chart of another embodiment of the method for preparing a semiconductor packaging device of the present application. The method includes steps S11-S14, or steps S21-S25, or steps S31-S36 in the above-mentioned embodiments, and after step S14, or step S25, or step S36, that is, after removing the temporary carrier 200, it also includes the following steps.

[0103] Step S61, forming a second metal layer on the side of the conductive pad away from the chip and patterning it to form a redistribution layer; the redistribution layer includes a plurality of redistribution electrodes, and one redistribution electrode is electrically connected to at least one conductive pad.

[0104] Step S61 is the same as the above-mentioned step S51 and will not be described again here.

[0105] Step S62 , forming a second insulating layer on a side of the first insulating layer away from the chip and patterning the layer to form a plurality of second openings, with a redistribution electrode exposed from one of the second openings.

[0106] Please combine Fig.13 See also Fig.15 , Fig.15 for Fig.14 The structural diagram corresponding to the implementation method of step S62 in Fig.13 Based on the device shown, a second insulating layer 117 is further formed on the side of the first insulating layer 115 away from the chip 11 and patterned to form a plurality of second openings N, with a redistribution electrode exposed from a second opening N. The material and formation method of the second insulating layer 117 can be consistent with those of the first insulating layer 115 .

[0107] Step S63, forming a plurality of second conductive blocks on a side of the second insulating layer away from the chip, wherein one second conductive block is electrically connected to one redistribution electrode via one second opening.

[0108] Please combine Fig.15 See also Fig.16 , Fig.16 for Fig.14 In the structural schematic diagram corresponding to an embodiment of step S63, after forming the patterned second insulating layer 117, a plurality of second conductive blocks 118 are further formed on the side of the second insulating layer 117 away from the chip 11, and each second conductive block 118 is electrically connected to a redistribution electrode via a second opening N. The material and formation method of the second conductive block 118 can be consistent with the first conductive block 12.

[0109] Among them, the positions of the redistribution electrodes and the second conductive blocks can be adjusted according to actual product requirements to achieve fan-out packaging of the chip 11.

[0110] In the semiconductor packaging device prepared in this embodiment, the first conductive block 12 on the surface of the chip 11 is bonded to the conductive pad 112 by a thermal compression bonding process, which reduces the probability of chip 11 shifting, and improves packaging yield and device reliability.

[0111] Based on the same inventive concept, the present application also provides a semiconductor packaging device, which is prepared by the method for preparing a semiconductor packaging device described in any of the above embodiments. Please continue to refer to Figure 3 , Figure 6 , Fig. 9 , Fig.13 , Fig.15 and Fig.16 , the above figures all show an embodiment of the semiconductor package device of the present application, and the semiconductor package device includes a first intermediate body 111 and a plurality of conductive pads 112. The first intermediate body 111 includes a chip 11 and a plurality of first conductive blocks 12, the first main surface of the chip 11 has a plurality of chip electrodes 110, and the first conductive blocks 12 are located at the positions of the chip electrodes 110 and are electrically connected to the chip electrodes 110. The plurality of conductive pads 112 are located at one end of the first conductive block 12 away from the chip 11, and one conductive pad 112 is electrically connected to one corresponding first conductive block 12.

[0112] In this embodiment, the reliability of the semiconductor package device is improved.

[0113] In some embodiments, please refer to Figure 6 , Fig. 9 , Fig.13 , Fig.15 and Fig.16 The semiconductor package device of the present application further includes a first insulating layer 115 and an underfill 113. The first insulating layer 115 is located at an end of the first conductive block 12 away from the chip 11, and a plurality of first openings are formed on the first insulating layer 115. A conductive pad 112 is electrically connected to a corresponding first conductive block 12 through a first opening. The underfill 113 is located between the first insulating layer 115 and the chip 11, and covers the side of the first conductive block 12.

[0114] In this embodiment, the reliability of the semiconductor package device is improved.

[0115] In some embodiments, please refer to Fig.16 , the semiconductor package device of the present application further includes a redistribution layer 116, a second insulating layer 117 and a plurality of second conductive blocks 118. The redistribution layer 116 includes a plurality of redistribution electrodes, and one redistribution electrode is electrically connected to at least one conductive pad 112. The second insulating layer 117 is located on the side of the first insulating layer 115 away from the chip 11, and a plurality of second openings are formed on the second insulating layer 117, and one redistribution electrode is exposed from one of the second openings. The plurality of second conductive blocks 118 are located on the side of the second insulating layer 117 away from the chip 11, and one second conductive block 118 is electrically connected to one redistribution electrode through one second opening.

[0116] In this embodiment, the reliability of the semiconductor package device is improved.

[0117] In some embodiments, it is also possible to Fig.16The above steps S61-S62 are further repeated based on the device shown in FIG. Fig.17 As shown, Fig.17 This is a schematic diagram of the structure of another embodiment of the semiconductor packaging device of the present application, that is, a combination of multiple insulation layers and rewiring layers is formed, and the position of the rewiring electrode can be set as needed, and then a second conductive block 118 is formed on the outermost surface for electrical connection with other devices.

[0118] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for preparing a semiconductor packaging device, characterized in that: include: Providing a first intermediate, the first intermediate comprising a chip and a plurality of first conductive blocks, the first main surface of the chip having a plurality of chip electrodes, the first conductive blocks being located at the positions of the chip electrodes and being electrically connected to the chip electrodes; Placing a temporary carrier on a horizontal plane, and arranging the first intermediate body and the temporary carrier opposite to each other; wherein a plurality of conductive pads arranged at intervals are formed on the temporary carrier, and an end of one of the first conductive blocks away from the chip faces one of the conductive pads; Bonding the first conductive block and the corresponding conductive pad by using a thermal compression bonding process; removing the temporary carrier plate; Before the step of placing the temporary carrier on a horizontal plane and arranging the first intermediate body opposite to the temporary carrier, the method further includes: forming a first insulating layer on a surface of one side of the temporary carrier and patterning the first insulating layer to form a plurality of first openings; forming a first metal layer on a side of the first insulating layer away from the temporary carrier and patterning the first metal layer to form a plurality of conductive pads; one conductive pad contacts the temporary carrier through one of the first openings; And, after the step of removing the temporary carrier, it also includes: forming a second metal layer on the side of the conductive pad away from the chip and patterning it to form a redistribution layer; the redistribution layer includes a plurality of redistribution electrodes, and one of the redistribution electrodes is electrically connected to at least one of the conductive pads.

2. The preparation method according to claim 1, characterized in that: Before the step of removing the temporary carrier, the method further comprises: An underfill is formed between the chip and the temporary carrier, and the underfill covers the side surfaces of the first conductive block.

3. The preparation method according to claim 2, characterized in that: After the step of forming an underfill between the chip and the temporary carrier, the method further includes: A plastic encapsulation layer is formed on the side of the temporary carrier where the conductive pad is formed; the plastic encapsulation layer at least covers the bottom filler and the side surface of the chip.

4. The preparation method according to claim 3, characterized in that: The number of the first intermediates is multiple, and the plastic sealing layer continuously covers all the first intermediates; the preparation method further comprises: Part of the plastic encapsulation layer located between adjacent first intermediate bodies is cut off to obtain a plurality of the semiconductor package devices.

5. The preparation method according to claim 1, characterized in that: After the step of forming and patterning a second metal layer on a side of the conductive pad and the first insulating layer away from the first intermediate body, the method further includes: forming a second insulating layer on a side of the first insulating layer away from the chip and patterning the layer to form a plurality of second openings, wherein one redistribution electrode is exposed from one of the second openings; A plurality of second conductive blocks are formed on a side of the second insulating layer away from the chip, and one of the second conductive blocks is electrically connected to one of the redistribution electrodes via one of the second openings.

6. A semiconductor packaging device, characterized in that: The semiconductor package device is prepared by the method for preparing a semiconductor package device according to any one of claims 1 to 5, and the semiconductor package device comprises: A first intermediate body, the first intermediate body comprising a chip and a plurality of first conductive blocks, the first main surface of the chip having a plurality of chip electrodes, the first conductive blocks being located at the positions of the chip electrodes and being electrically connected to the chip electrodes; A plurality of conductive pads, located at one end of the first conductive block away from the chip, and one of the conductive pads is electrically connected to a corresponding first conductive block; A first insulating layer is located at an end of the first conductive block away from the chip, a plurality of first openings are formed on the first insulating layer, and one of the conductive pads is electrically connected to the corresponding first conductive block through one of the first openings; The redistribution layer includes a plurality of redistribution electrodes, and one of the redistribution electrodes is electrically connected to at least one of the conductive pads.

7. The semiconductor package device according to claim 6, characterized in that: The semiconductor package device further comprises: An underfill is located between the first insulating layer and the chip, and the underfill covers the side surfaces of the first conductive block.

8. The semiconductor package device according to claim 7, characterized in that: The semiconductor package device further comprises: a second insulating layer, located on a side of the first insulating layer away from the chip, a plurality of second openings being formed on the second insulating layer, and one of the redistribution electrodes being exposed from one of the second openings; A plurality of second conductive blocks are located on a side of the second insulating layer away from the chip, and one of the second conductive blocks is electrically connected to one of the redistribution electrodes via one of the second openings.

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