A method for extracting sidewall capacitance of a trench MOS structure

Abstract

A method for extracting the sidewall capacitance of a trench MOS structure. The method comprises the following steps: step 1, determining the total capacitance-voltage curve of the trench MOS structure to be measured and two groups of trench MOS structures prepared in advance, the total capacitance including the branch capacitances corresponding to the trench bottom, the trench top mesa and the trench sidewall; one group of trench MOS structures is different from the trench MOS structure to be measured in the trench bottom width, and the other group is different from the trench MOS structure to be measured in the trench top mesa width; step 2, determining the branch capacitance corresponding to the trench sidewall of the trench MOS structure to be measured under a specified bias voltage according to the total capacitance-voltage curve; step 3, adjusting the specified bias voltage and repeating step 2 to obtain the branch capacitance corresponding to the trench sidewall of the trench MOS structure to be measured under different bias voltages, so as to generate a sidewall capacitance-voltage characteristic curve. The method can improve the extraction accuracy of the sidewall capacitance of the trench MOS structure.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a method for extracting the sidewall capacitance of a trench MOS structure. Background Technology

[0002] A trench MOS structure comprises three branched MOS structures: the top mesa of the trench, the sidewalls of the trench, and the MOS structure corresponding to the bottom of the trench. A traditional method for quantifying the sidewall capacitance-voltage characteristics of a trench MOS structure involves selecting a specific epitaxial wafer with the same crystal orientation as the corresponding sidewall of the trench. A planar MOS capacitor structure corresponding to the crystal orientation of the sidewall in the trench MOS structure is then fabricated on this epitaxial wafer, and the capacitance-voltage characteristic curve of the fabricated planar MOS structure is measured. However, this traditional method has the following drawbacks.

[0003] Since trench MOS structures are typically built upon dry etching processes, which inevitably cause etching damage to the trench bottom and sidewalls, this damage further affects the quality and electrical properties of the oxide layer formed at these locations in subsequent processes. However, traditional methods only fabricate planar MOS capacitor structures on epitaxial wafers without trench etching. Therefore, they fail to account for the impact of etching on the electrical characteristics of the sidewalls during the actual fabrication of trench MOS structures. Consequently, traditional methods cannot accurately extract the sidewall capacitance-voltage characteristics of trench MOS structures. Therefore, improving the extraction accuracy of sidewall capacitance in trench MOS structures has become a pressing technical problem in this field. Summary of the Invention

[0004] The purpose of this invention is to provide a method for extracting the sidewall capacitance of a trench MOS structure, thereby improving the extraction accuracy of the sidewall capacitance of the trench MOS structure.

[0005] To achieve the above objectives, embodiments of the present invention provide a method for extracting the sidewall capacitance of a trench MOS structure, comprising:

[0006] Step 1: Determine the total capacitance-voltage characteristic curves of the trench MOS structure to be tested and the two pre-prepared sets of trench MOS structures. The total capacitance includes the trench bottom, the top mesa of the trench, and the branch capacitance corresponding to the trench sidewalls. Each of the two sets of trench MOS structures includes multiple trench MOS structures. The trench bottom width of one set of trench MOS structures is different from that of the trench MOS structure to be tested, and the top mesa width of the other set of trench MOS structures is different from that of the trench MOS structure to be tested.

[0007] Step 2: Based on the total capacitance-voltage curves of the trench MOS structure to be tested and the two pre-prepared trench MOS structures, determine the branch capacitance corresponding to the trench sidewall of the trench MOS structure to be tested under a specified bias voltage.

[0008] Step 3: Adjust the specified bias voltage and repeat step 2 to obtain the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test under different bias voltages, so as to generate the sidewall capacitance-voltage characteristic curve.

[0009] In one embodiment, step 2 includes the following sub-steps:

[0010] Based on the total capacitance-voltage characteristic curves of the trench MOS structure to be tested and the two pre-prepared trench MOS structures, a first curve showing the change of the total capacitance of the trench MOS structure with the width of the top mesa of the trench and a second curve showing the change with the width of the bottom of the trench are determined under a specified bias voltage.

[0011] Based on the first curve, the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero is determined, and based on the second curve, the total capacitance of the trench MOS structure when the width of the bottom of the trench is zero is determined.

[0012] Based on the total capacitance of the trench MOS structure under test under the specified bias voltage, the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero, and the total capacitance of the trench MOS structure when the width of the bottom mesa of the trench is zero, the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test is determined.

[0013] In one embodiment, the specified bias voltage and the different bias voltages are both within the accumulation region bias voltage range.

[0014] In one embodiment, the total capacitance has the following relationship with the branch capacitances corresponding to the bottom of the trench, the top platform of the trench, and the sidewalls of the trench:

[0015] C total =C top +C side +C bottom

[0016] Among them, C total For the total capacitance, C top C is the branch capacitor corresponding to the top platform of the trench. side C is the branch capacitance corresponding to the trench sidewall. bottom This refers to the branch capacitor corresponding to the bottom of the trench.

[0017] In one embodiment, the branch capacitances corresponding to the bottom of the trench, the top platform of the trench, and the sidewalls of the trench are calculated using the following formula:

[0018]

[0019]

[0020]

[0021] in,

[0022]

[0023]

[0024]

[0025] C top(ox) C side(ox) And C bottom(ox) These represent the oxide layer capacitances of the three branch MOS structures contained in the trench MOS structure, where ε0 is the vacuum dielectric constant, and ε Oxide Where is the relative permittivity of the oxide layer, L is the length of the trench MOS electrode, and t is the relative permittivity of the oxide layer. ox-top t ox-side and t ox-bottom These represent the oxide layer thicknesses in the three branch MOS structures within the trench MOS structure, W. top W side and W bottom These represent the top mesa width, sidewall width, and bottom width of the trench in the trench MOS structure, respectively, and N represents the number of trenches contained in a single test pattern area.

[0026] In one embodiment, under a specified bias voltage, the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test is calculated using the following formula:

[0027]

[0028] in,

[0029]

[0030]

[0031]

[0032] The branch capacitance corresponding to the trench sidewall of the trench MOS structure under test is [missing information]. This represents the total capacitance of the trench MOS structure when the width of the top mesa is zero. This represents the total capacitance of the trench MOS structure when the trench bottom width is zero. The total capacitance of the trench MOS structure under test under the specified bias voltage is given by Bx1Ty1, ​​where x1 represents the bottom width of the trench and y1 represents the top mesa width of the trench MOS structure under test.

[0033] This invention also provides a system for extracting the sidewall capacitance of a trench MOS structure, comprising:

[0034] The total capacitance-voltage characteristic curve generation module is used to determine the total capacitance-voltage characteristic curves of the trench MOS structure under test and two pre-prepared sets of trench MOS structures. The total capacitance includes the trench bottom, the top mesa of the trench, and the branch capacitance corresponding to the trench sidewalls. Each of the two sets of trench MOS structures includes multiple trench MOS structures. The trench bottom width of one set of trench MOS structures is different from that of the trench MOS structure under test, and the top mesa width of the other set of trench MOS structures is different from that of the trench MOS structure under test.

[0035] A branch capacitance determination module is used to determine, based on the total capacitance-voltage curves of the trench MOS structure under test and two pre-prepared sets of trench MOS structures, the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test at a specified bias voltage; and

[0036] The sidewall capacitance-voltage characteristic curve generation module is used to obtain the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test under different bias voltages by adjusting the specified bias voltage, so as to generate the sidewall capacitance-voltage characteristic curve.

[0037] In one embodiment, the branch capacitance determination module includes:

[0038] The first determining submodule is used to determine, based on the total capacitance-voltage characteristic curves of the trench MOS structure to be tested and two pre-prepared trench MOS structures, a first curve showing the change of the total capacitance of the trench MOS structure with the width of the top mesa of the trench under a specified bias voltage, and a second curve showing the change of the total capacitance with the width of the bottom of the trench.

[0039] The second determining submodule is used to determine the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero, based on the first curve, and to determine the total capacitance of the trench MOS structure when the width of the bottom of the trench is zero, based on the second curve; and

[0040] The branch capacitance determination submodule is used to determine the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test based on the total capacitance of the trench MOS structure under test under the specified bias voltage, the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero, and the total capacitance of the trench MOS structure when the width of the bottom of the trench is zero.

[0041] This invention also provides an electronic device, comprising:

[0042] One or more processors;

[0043] Storage device for storing one or more programs.

[0044] When the one or more programs are executed by the one or more processors, the one or more processors implement the extraction method described in any of the above embodiments.

[0045] This invention also provides a computer-readable storage medium storing executable instructions thereon, which, when executed by a processor, cause the processor to implement the extraction method described in any of the above embodiments.

[0046] As can be seen from the technical solution provided by the present invention above, the method provided by the present invention combines capacitance theory with process structural parameters to analyze the influence of the trench bottom width and the trench top mesa width on the total capacitance of the trench MOS structure. Therefore, it is not necessary to add an additional epitaxial wafer to fabricate a planar MOS structure corresponding to the crystal orientation of the trench MOS sidewall. At the same time, it can accurately extract the sidewall capacitance-voltage curve in the trench MOS structure without destroying the trench MOS structure and keeping all the characteristics of the sidewall oxide layer unchanged. It is not only suitable for high-frequency capacitance-voltage testing, but also for quasi-static capacitance-voltage testing. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a flowchart of the method for extracting the sidewall capacitance of a trench MOS structure provided in an embodiment of the present invention;

[0049] Figure 2 (a) is a simplified model of a trench MOS cell, and (b) is an equivalent circuit diagram of a trench MOS cell.

[0050] Figure 3 This is a block diagram of the method for extracting the sidewall capacitance of a trench MOS structure provided in an embodiment of the present invention;

[0051] Figure 4In the middle (a), the trench MOS structure to be tested is shown; (b) and (c) are a group of trench MOS structures with different trench top mesa widths from the trench MOS structure to be tested; and (d) and (e) are a group of trench MOS structures with different trench bottom widths from the trench MOS structure to be tested.

[0052] Figure 5 In Figures (a) and (b), the total capacitance of each trench MOS structure varies with the bias voltage.

[0053] Figure 6 In the diagram, (a) represents the first curve, and (b) represents the second curve.

[0054] Figure 7 These are the total capacitance-voltage characteristic curves of the trench MOS structure when the width of the top mesa is zero, and the total capacitance-voltage characteristic curves of the trench MOS structure when the width of the bottom mesa is zero.

[0055] Figure 8 This is the sidewall capacitance-voltage characteristic curve of the trench MOS structure under test. Detailed Implementation

[0056] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. After reading the present invention, any modifications of the present invention in various equivalent forms by those skilled in the art fall within the scope defined by the appended claims.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0058] refer to Figure 1 As shown, a method for extracting the sidewall capacitance of a trench MOS structure provided by an embodiment of the present invention may include the following steps:

[0059] Step 1: Determine the total capacitance-voltage characteristic curves of the trench MOS structure to be tested and the two pre-prepared trench MOS structures. The total capacitance includes the trench bottom, the top mesa of the trench, and the branch capacitance corresponding to the trench sidewalls. Each of the two sets of trench MOS structures includes multiple trench MOS structures. The trench bottom width of one set of trench MOS structures is different from that of the trench MOS structure to be tested, and the top mesa width of the other set of trench MOS structures is different from that of the trench MOS structure to be tested.

[0060] Specifically, a "trench" can also be called a "channel." Two sets of trench MOS structures have the same trench etching depth as the trench MOS structure under test. The trench MOS structure under test can be labeled Bx1Ty1. A set of trench MOS structures with different trench bottom widths from the trench MOS structure under test can be labeled Bx2Ty1 and Bx3Ty1. ​​A set of trench MOS structures with different trench top mesa widths from the trench MOS structure under test can be labeled Bx1Ty2 and Bx1Ty3. Here, the letter "B" represents the trench bottom, the letter "T" represents the trench top mesa, "x1" represents the trench bottom width in micrometers, and "y1, y2, y3" represent the trench top mesa widths in micrometers.

[0061] For details, please refer to Figure 2 As shown, the total capacitance has the following relationship with the branch capacitances at the bottom of the trench, the top of the trench, and the sidewalls of the trench:

[0062] C total =C top +C side +C bottom (1)

[0063] Among them, C total For the total capacitance, C top C is the branch capacitor corresponding to the top platform of the trench. side C is the branch capacitance corresponding to the trench sidewall. bottom This refers to the branch capacitor corresponding to the bottom of the trench.

[0064] Specifically, the branch capacitances corresponding to the bottom of the trench, the top platform of the trench, and the sidewalls of the trench can be calculated using the following formula:

[0065]

[0066]

[0067]

[0068] in,

[0069]

[0070]

[0071]

[0072] C top(ox) C side(ox) And C bottom(ox) These represent the oxide layer capacitances of the three branch MOS structures contained in the trench MOS structure, where ε0 is the vacuum dielectric constant, and εOxide Where is the relative permittivity of the oxide layer, L is the length of the trench MOS electrode, and t is the relative permittivity of the oxide layer. ox-top t ox-side and t ox-bottom These represent the oxide layer thicknesses in the three branch MOS structures within the trench MOS structure, W. top W side and W bottom These represent the top mesa width, sidewall width, and bottom width of the trench in the trench MOS structure, respectively, and N represents the number of trenches contained in a single test pattern area.

[0073] Based on formulas (1) to (4) above, the total capacitance of the trench MOS structure varies with the width of the top mesa, the width of the trench sidewall, and the width of the trench bottom as follows:

[0074] C total =B top ·W top +B top ·W side +B top ·W bottom (8)

[0075] Using formula (8), the total capacitance of trench MOS structures of different specifications can be expressed as follows:

[0076]

[0077]

[0078]

[0079]

[0080]

[0081] It should also be noted that when the trench MOS structure operates in the depletion region mode, a wide space charge region is generated near the oxide layer within the semiconductor. At the top and bottom corners of the trench, the space charge regions of different branch capacitors will influence each other. Therefore, the total capacitance of the MOS cannot be understood as the sum of the parallel connections of the branch capacitors at the top of the trench, the sidewalls of the trench, and the bottom of the trench. Thus, the trench MOS structure needs to operate in the accumulation region mode, so the specified bias voltage and different bias voltages must be within the accumulation region bias voltage range.

[0082] Step 2: Based on the total capacitance-voltage curves of the trench MOS structure to be tested and the two pre-prepared trench MOS structures, determine the branch capacitance corresponding to the trench sidewall of the trench MOS structure to be tested under a specified bias voltage.

[0083] For details, please refer to Figure 3 As shown, step 2 may include the following sub-steps 201 to 203:

[0084] Sub-step 201: Based on the total capacitance-voltage characteristic curves of the trench MOS structure to be tested and the two pre-prepared trench MOS structures, determine the first curve of the total capacitance of the trench MOS structure as a function of the width of the top mesa of the trench under a specified bias voltage, and the second curve of the total capacitance as a function of the width of the bottom mesa of the trench.

[0085] Sub-step 202: Based on the first curve, determine the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero (i.e., the intercept of the first curve on the vertical axis), and based on the second curve, determine the total capacitance of the trench MOS structure when the width of the bottom of the trench is zero (i.e., the intercept of the second curve on the vertical axis).

[0086] Sub-step 203: Based on the total capacitance of the trench MOS structure under test under the specified bias voltage, the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero, and the total capacitance of the trench MOS structure when the width of the bottom of the trench is zero, determine the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test.

[0087] Specifically, under a specified bias voltage, the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test is calculated using the following formula:

[0088]

[0089] in,

[0090]

[0091]

[0092] The branch capacitance corresponding to the trench sidewall of the trench MOS structure under test is [missing information]. This represents the total capacitance of the trench MOS structure when the width of the top mesa is zero. This represents the total capacitance of the trench MOS structure when the trench bottom width is zero. The total capacitance of the trench MOS structure under test under the specified bias voltage is given by Bx1Ty1, ​​where x1 represents the bottom width of the trench and y1 represents the top mesa width of the trench MOS structure under test.

[0093] Step 3: Adjust the specified bias voltage and repeat step 2 to obtain the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test under different bias voltages, so as to generate the sidewall capacitance-voltage characteristic curve.

[0094] This invention also provides a system for extracting the sidewall capacitance of a trench MOS structure, comprising:

[0095] The total capacitance-voltage characteristic curve generation module is used to determine the total capacitance-voltage characteristic curves of the trench MOS structure under test and two pre-prepared sets of trench MOS structures. The total capacitance includes the trench bottom, the top mesa of the trench, and the branch capacitance corresponding to the trench sidewalls. Each of the two sets of trench MOS structures includes multiple trench MOS structures. The trench bottom width of one set of trench MOS structures is different from that of the trench MOS structure under test, and the top mesa width of the other set of trench MOS structures is different from that of the trench MOS structure under test.

[0096] A branch capacitance determination module is used to determine, based on the total capacitance-voltage curves of the trench MOS structure under test and two pre-prepared sets of trench MOS structures, the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test at a specified bias voltage; and

[0097] The sidewall capacitance-voltage characteristic curve generation module is used to obtain the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test under different bias voltages by adjusting the specified bias voltage, so as to generate the sidewall capacitance-voltage characteristic curve.

[0098] In one embodiment, the branch capacitance determination module includes:

[0099] The first determining submodule is used to determine, based on the total capacitance-voltage characteristic curves of the trench MOS structure to be tested and two pre-prepared trench MOS structures, a first curve showing the change of the total capacitance of the trench MOS structure with the width of the top mesa of the trench under a specified bias voltage, and a second curve showing the change of the total capacitance with the width of the bottom of the trench.

[0100] The second determining submodule is used to determine the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero, based on the first curve, and to determine the total capacitance of the trench MOS structure when the width of the bottom of the trench is zero, based on the second curve; and

[0101] The branch capacitance determination submodule is used to determine the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test based on the total capacitance of the trench MOS structure under test under the specified bias voltage, the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero, and the total capacitance of the trench MOS structure when the width of the bottom of the trench is zero.

[0102] This invention also provides an electronic device, comprising:

[0103] One or more processors;

[0104] Storage device for storing one or more programs.

[0105] When the one or more programs are executed by the one or more processors, the one or more processors implement the extraction method described in any of the above embodiments.

[0106] This invention also provides a computer-readable storage medium storing executable instructions thereon, which, when executed by a processor, cause the processor to implement the extraction method described in any of the above embodiments.

[0107] The technical solution of the present invention will be further illustrated below through a specific embodiment.

[0108] refer to Figure 4 As shown, Figure 4 In the diagram, (a) is the trench MOS structure under test, (b) and (c) are a group of trench MOS structures with different trench top mesa widths from the trench MOS structure under test, and (d) and (e) are a group of trench MOS structures with different trench bottom widths from the trench MOS structure under test.

[0109] According to formula (8), we can obtain:

[0110]

[0111]

[0112]

[0113]

[0114]

[0115] By selecting a bias voltage range to operate each trench MOS structure in the accumulation region mode, high-frequency (100kHz) capacitance-voltage curves of each trench MOS structure were obtained. For details, please refer to [reference needed]. Figure 5 As shown.

[0116] Under the same bias voltage (e.g., V) bias =10V), plot the total capacitance of the trench MOS structure as a function of the width of the top mesa (W) of the trench. top The first curve changes with the width of the trench bottom (W) and the second curve changes with the width of the trench bottom (W). bottom The second curve shows the change. See reference for details. Figure 6As shown in (a) and (b).

[0117] Based on the first and second curves, determine the voltage (V) at the corresponding test voltage. bias =10V), when the width of the top mesa and the width of the bottom of the trench are both zero, the theoretical values ​​of the high-frequency capacitance of the trench MOS structure satisfy the following relationships:

[0118]

[0119]

[0120] Substituting formulas (22) and (23) into formula (17), the value of V under the specified bias voltage can be obtained. bias =10V), the sidewall capacitance of the trench MOS structure with a trench bottom width of 3μm, a trench top mesa width of 5μm, and a trench sidewall width of 6μm (twice the trench etching depth) satisfies the following relationship:

[0121]

[0122] Since the above process only represents a specific bias voltage (V) bias By repeating the above steps within different bias voltage ranges for the trench MOS structure operating in the accumulation region mode (=10V), the high-frequency capacitance value at these values ​​can be obtained. This yields the total capacitance-voltage characteristic curves of the trench MOS structure when the top mesa width is zero, and the total capacitance-voltage characteristic curves when the bottom width is zero. For details, please refer to [reference needed]. Figure 7 As shown.

[0123] Finally, the total capacitance-voltage curve can be obtained from the trench MOS structure with a bottom width of 3μm, a top mesa width of 5μm, and a sidewall width of 6μm (twice the trench etching depth). Figure 5 Curve C in total(B3T5) Separate the sidewall capacitance-voltage curves; see reference for details. Figure 8 As shown.

[0124] The various embodiments described in this specification are presented in a progressive manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0125] The above descriptions are merely a few embodiments of the present invention. Although the embodiments disclosed in the present invention are as described above, the content is only for the purpose of facilitating the understanding of the technical solution of the present invention and is not intended to limit the present invention. Any person skilled in the art to which this invention pertains may make any modifications and changes in the form and details of the embodiments without departing from the spirit and scope disclosed in the present invention. However, the patent protection scope of the present invention shall still be determined by the scope defined in the appended claims.

Claims

1. A method for extracting the sidewall capacitance of a trench MOS structure, characterized in that, include: Step 1: Determine the total capacitance-voltage characteristic curves of the trench MOS structure to be tested and the two pre-prepared sets of trench MOS structures. The total capacitance includes the trench bottom, the top mesa of the trench, and the branch capacitance corresponding to the trench sidewalls. Each of the two sets of trench MOS structures includes multiple trench MOS structures. The trench bottom width of one set of trench MOS structures is different from that of the trench MOS structure to be tested, and the top mesa width of the other set of trench MOS structures is different from that of the trench MOS structure to be tested. Step 2: Based on the total capacitance-voltage curves of the trench MOS structure under test and the two pre-prepared trench MOS structures, determine the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test under a specified bias voltage. This step includes: based on the total capacitance-voltage characteristic curves of the trench MOS structure under test and the two pre-prepared trench MOS structures, determining a first curve showing the change in the total capacitance of the trench MOS structure with the width of the top mesa of the trench and a second curve showing the change in the width of the bottom mesa of the trench under a specified bias voltage; based on the first curve, determining the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero, and based on the second curve, determining the total capacitance of the trench MOS structure when the width of the bottom mesa of the trench is zero; based on the total capacitance of the trench MOS structure under test, the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero, and the total capacitance of the trench MOS structure when the width of the bottom mesa of the trench is zero under the specified bias voltage, determining the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test. Step 3: Adjust the specified bias voltage and repeat step 2 to obtain the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test under different bias voltages, so as to generate the sidewall capacitance-voltage characteristic curve.

2. The extraction method according to claim 1, characterized in that, The specified bias voltage and the different bias voltages are all within the bias voltage range of the accumulation region.

3. The extraction method according to claim 1, characterized in that, The total capacitance has the following relationship with the branch capacitances corresponding to the bottom of the trench, the top platform of the trench, and the sidewalls of the trench: C total = C top + C side + C bottom Among them, C total For the total capacitance, C top C is the branch capacitor corresponding to the top platform of the trench. side C is the branch capacitance corresponding to the trench sidewall. bottom This refers to the branch capacitor corresponding to the bottom of the trench.

4. The method according to claim 3, characterized in that, The branch capacitances corresponding to the bottom of the trench, the top platform of the trench, and the sidewalls of the trench are calculated using the following formula: in, C top(ox) C side(ox) And C bottom(ox) These represent the oxide layer capacitances of the three branch MOS structures contained in the trench MOS structure, where ε0 is the vacuum dielectric constant, and ε Oxide Where is the relative permittivity of the oxide layer, L is the length of the trench MOS electrode, and t is the relative permittivity of the oxide layer. ox-top t ox-side and t ox-bottom These represent the oxide layer thicknesses in the three branch MOS structures within the trench MOS structure, W. top W side and W bottom These represent the top mesa width, sidewall width, and bottom width of the trench in the trench MOS structure, respectively, and N represents the number of trenches contained in a single test pattern area.

5. The extraction method according to claim 4, characterized in that, Under a specified bias voltage, the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test is calculated using the following formula: in, The branch capacitance corresponding to the trench sidewall of the trench MOS structure under test is [missing information]. This represents the total capacitance of the trench MOS structure when the width of the top mesa is zero. This represents the total capacitance of the trench MOS structure when the trench bottom width is zero. The total capacitance of the trench MOS structure under test at the specified bias voltage. The trench bottom width of the trench MOS structure under test is x1, and the top mesa width is y1. The specific process for calculating the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test includes: Based on the first curve and the second curve, determine the total capacitance of the trench MOS structure when the width y1 of the top mesa of the trench is zero under the corresponding test voltage. The total capacitance of the trench MOS structure when the trench bottom width x1 is zero. ; Based on the relationship between the total capacitance of a trench MOS structure and the widths of the top mesa, sidewalls, and bottom of the trench, the total capacitance of the trench MOS structure under test is calculated using the trench bottom width x1 and top mesa width y1, according to the specified bias voltage. ; Width of the top platform of the trench Total capacitance of the trench MOS structure when zero and the width of the bottom of the trench Total capacitance of the trench MOS structure when zero Substitute the total capacitance of the trench MOS structure under test at the specified bias voltage. The branch capacitance corresponding to the trench sidewall of the trench MOS structure under test is obtained. .

6. A system for extracting the sidewall capacitance of a trench MOS structure, characterized in that, include: The total capacitance-voltage characteristic curve generation module is used to determine the total capacitance-voltage characteristic curves of the trench MOS structure under test and two pre-prepared sets of trench MOS structures. The total capacitance includes the trench bottom, the top mesa of the trench, and the branch capacitance corresponding to the trench sidewalls. Each of the two sets of trench MOS structures includes multiple trench MOS structures. The trench bottom width of one set of trench MOS structures is different from that of the trench MOS structure under test, and the top mesa width of the other set of trench MOS structures is different from that of the trench MOS structure under test. A branch capacitance determination module is used to determine, based on the total capacitance-voltage curves of the trench MOS structure under test and two pre-prepared sets of trench MOS structures, the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test at a specified bias voltage. This step includes: determining, based on the total capacitance-voltage characteristic curves of the trench MOS structure under test and the two pre-prepared sets of trench MOS structures, a first curve showing the change in the total capacitance of the trench MOS structure with the width of the top mesa of the trench, and a second curve showing the change in the total capacitance with the width of the bottom of the trench, at a specified bias voltage; determining, based on the first curve, the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero, and based on the second curve, the total capacitance of the trench MOS structure when the width of the bottom of the trench is zero; and determining, based on the total capacitance of the trench MOS structure under test, the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero, and the total capacitance of the trench MOS structure when the width of the bottom of the trench is zero, at the specified bias voltage, the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test; and The sidewall capacitance-voltage characteristic curve generation module is used to obtain the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test under different bias voltages by adjusting the specified bias voltage, so as to generate the sidewall capacitance-voltage characteristic curve.

7. The extraction system according to claim 6, characterized in that, The branch capacitance determination module includes: The first determining submodule is used to determine, based on the total capacitance-voltage characteristic curves of the trench MOS structure to be tested and two pre-prepared trench MOS structures, a first curve showing the change of the total capacitance of the trench MOS structure with the width of the top mesa of the trench under a specified bias voltage, and a second curve showing the change of the total capacitance with the width of the bottom of the trench. The second determining submodule is used to determine the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero, based on the first curve, and to determine the total capacitance of the trench MOS structure when the width of the bottom of the trench is zero, based on the second curve; and The branch capacitance determination submodule is used to determine the branch capacitance corresponding to the trench sidewall of the trench MOS structure under test based on the total capacitance of the trench MOS structure under test under the specified bias voltage, the total capacitance of the trench MOS structure when the width of the top mesa of the trench is zero, and the total capacitance of the trench MOS structure when the width of the bottom of the trench is zero.

8. An electronic device, comprising: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the extraction method according to any one of claims 1-5.

9. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to implement the extraction method according to any one of claims 1-5.

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