Semiconductor chip including through electrode and semiconductor package including the same

Abstract

The present disclosure relates to a semiconductor chip including a through electrode and a semiconductor package including the same. The semiconductor chip can include a main body portion having a front surface and a rear surface, a pair of through electrodes penetrating the main body portion, an insulating layer disposed on the rear surface of the main body portion and the pair of through electrodes, and a rear connection electrode disposed on the insulating layer and connected with the pair of through electrodes at the same time, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

Description

Technical Field

[0001] This patent document relates to semiconductor technology, and more specifically, to a semiconductor chip including a through electrode and a semiconductor package including the semiconductor chip. Background Technology

[0002] Electronic products demand increasingly larger amounts of data processing while their size is shrinking. Therefore, semiconductor chips used in these products also require thinness and small dimensions. Furthermore, semiconductor packages that embed multiple semiconductor chips have been manufactured.

[0003] Multiple semiconductor chips can be stacked vertically and electrically connected to each other through vias passing through each semiconductor chip. Summary of the Invention

[0004] In an embodiment, the semiconductor chip may include: a body portion having a front surface and a rear surface; an insulating layer disposed on the rear surface of the body portion; a pair of through electrodes penetrating the body portion and the insulating layer; and a rear connecting electrode disposed on the insulating layer and simultaneously connected to the pair of through electrodes, wherein the distance between the pair of through electrodes is greater than twice the thickness of the insulating layer.

[0005] In another embodiment, the semiconductor chip may include: a body portion having a front surface and a rear surface; an insulating layer disposed on the rear surface of the body portion; a pair of through electrodes penetrating the body portion and the insulating layer; a metal-containing thin film layer disposed on the insulating layer and simultaneously connected to the pair of through electrodes; and a rear connection electrode disposed on and connected to the metal-containing thin film layer, wherein the metal-containing thin film layer includes an undercut formed below the sidewall of the rear connection electrode due to a recess in the metal-containing thin film layer, and wherein the width of the rear connection electrode is equal to or greater than the sum of the width of the pair of through electrodes, the distance between the pair of through electrodes, and the width of the undercut.

[0006] In another embodiment, the semiconductor package may include: a first semiconductor chip and a second semiconductor chip, the first semiconductor chip and the second semiconductor chip being stacked in a vertical direction, and each of the first semiconductor chip and the second semiconductor chip includes: a body portion having a front surface and a rear surface; an insulating layer disposed on the rear surface of the body portion; a pair of through electrodes penetrating the body portion and the insulating layer; a rear connection electrode disposed on the insulating layer and simultaneously connected to the pair of through electrodes; a wiring portion disposed on the front surface of the body portion; and a front connection electrode disposed on the wiring portion, wherein the rear connection electrode of the first semiconductor chip is connected to the front connection electrode of the second semiconductor chip, and wherein the distance between the pair of through electrodes is greater than twice the thickness of the insulating layer. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view illustrating a semiconductor chip according to an embodiment of the present disclosure.

[0008] Figures 2A to 2G This is a cross-sectional view illustrating a method for manufacturing a semiconductor chip according to an embodiment of the present disclosure.

[0009] Figure 2H It is used with Figure 2C A comparison diagram.

[0010] Figure 3 This is a cross-sectional view illustrating a semiconductor chip according to another embodiment of the present disclosure.

[0011] Figure 4 This is a cross-sectional view illustrating a semiconductor chip according to another embodiment of the present disclosure.

[0012] Figure 5 This is a cross-sectional view illustrating a semiconductor chip according to another embodiment of the present disclosure.

[0013] Figure 6A and Figure 6B This is a cross-sectional view illustrating a semiconductor chip according to another embodiment of the present disclosure.

[0014] Figure 7 This is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0015] Figure 8 A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment is shown.

[0016] Figure 9 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment is shown. Detailed Implementation

[0017] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0018] The accompanying drawings are not necessarily drawn to scale. In some cases, the scale of at least some structures in the drawings may be exaggerated in order to clearly illustrate specific features of the described embodiments. When a particular example of a multilayer structure with two or more layers is represented in the drawings or description, the relative positioning of these layers or the order of their arrangement reflects a particular implementation of the described or illustrated example, and different relative positioning or order of layer arrangement are possible. Furthermore, the illustrated multilayer structure may not reflect all layers present in that particular multilayer structure (e.g., one or more additional layers may exist between two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0019] In the following description of the implementation, when a parameter is referred to as “predetermined,” it may be intended to mean that the value of the parameter is predetermined when it is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or it may be set during the execution of the process or algorithm.

[0020] Figure 1 This is a cross-sectional view illustrating a semiconductor chip according to an embodiment of the present disclosure.

[0021] Reference Figure 1 The semiconductor chip 100 in this embodiment may include a main body portion 110, a wiring portion 120, a through electrode 130, a rear connection electrode 140, a front connection electrode 150, and a bonding layer 160.

[0022] The main body portion 110 may be formed of a semiconductor material such as silicon or germanium, and may have a front surface 111, a rear surface 112, and side surfaces that connect them to each other. The front surface 111 of the main body portion 110 may refer to the active surface on which the wiring portion 120 is disposed, and the rear surface 112 of the main body portion 110 may refer to the surface located on the opposite side of the front surface 111.

[0023] Wiring portion 120 may be formed on the front surface 111 of body portion 110. Wiring portion 120 may include circuit / wiring structures electrically connected to through electrode 130. For ease of description, the circuit / wiring structure is simply illustrated as lines in wiring portion 120, but is not limited thereto. In this case, the circuit / wiring structure may be implemented in various ways depending on the type of semiconductor chip 100. For example, when semiconductor chip 100 includes volatile memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static RAM) or non-volatile memory such as NAND flash memory, RRAM (Resistive RAM), PRAM (Phase Change RAM), MRAM (Magnetoresistive RAM), or FRAM (Ferroelectric RAM), the circuit / wiring structure may include a memory cell array having multiple memory cells.

[0024] A through electrode 130 may be formed in the body portion 110. The through electrode 130 may have a cylindrical shape extending from the front surface 111 to the rear surface 112 to penetrate the body portion 110. As an example, the through electrode 130 may be a TSV (Through Silicon Via). The through electrode 130 may include various conductive materials. As an example, the through electrode 130 may include a metal or a compound of the metal such as copper (Cu), tin (Sn), silver (Ag), tungsten (W), nickel (Ni), ruthenium (Ru), or cobalt (Co). One end of the through electrode 130 may be connected to a portion of the wiring portion 120, and the other end of the through electrode 130 may be connected to the rear connection electrode 140.

[0025] In this configuration, the through-electrode 130 may include a signal through-electrode 130S for transmitting signals and a power through-electrode 130P for providing power. The signals may include various signals required to drive the semiconductor chip 100. As an example, when the semiconductor chip 100 includes memory, signals (e.g., data input / output signals (DQ), command / address signals (CA), or chip select signals (CS)) may be moved through the signal through-electrode 130S. Furthermore, the power supply may include various levels of power supply voltage or ground voltage required to drive the semiconductor chip 100. In this embodiment, one signal through-electrode 130S and six power through-electrodes 130P are illustrated, but this disclosure is not limited thereto, and the number of signal through-electrodes 130S and the number of power through-electrodes 130P may vary. In the horizontal direction, i.e., in a direction parallel to the front surface 111 and the rear surface 112 of the body portion 110, the width of the through-electrode 130 may be constant. That is, the width of each signal through-electrode 130S and the width of each power through-electrode 130P may be the same. For example, when the through electrode 130 has a cylindrical shape, the cross-sectional diameter of the signal through electrode 130S and the cross-sectional diameter of the power through electrode 130P can be substantially the same.

[0026] A rear connection electrode 140 may be formed on the rear surface 112 of the body portion 110. The rear connection electrode 140 can connect the through electrode 130 to another component, such as another semiconductor chip to be placed on the rear surface 112 of the semiconductor chip 100. As an example, the rear connection electrode 140 may include conductive bumps. The rear connection electrode 140 may include various metallic materials such as copper, nickel, or combinations thereof, and may have a single-layer or multi-layer structure.

[0027] The post-connection electrode 140 may include a signal post-connection electrode 140S connected to the signal pass-through electrode 130S, a power post-connection electrode 140P connected to the power pass-through electrode 130P, and a dummy post-connection electrode 140D not connected to the pass-through electrode 130.

[0028] The signal post-connection electrode 140S can be configured to overlap and connect with each signal through electrode 130S. One signal post-connection electrode 140S and one signal through electrode 130S can correspond to each other.

[0029] The power supply connection electrode 140P can be configured to be simultaneously connected to a pair of power supply through electrodes 130P. That is, one power supply connection electrode 140P and two power supply through electrodes 130P can correspond to each other. The pair of power supply through electrodes 130P can be spaced apart from each other using the portion of the main body portion 110 located between the pair of power supply through electrodes 130P.

[0030] The dummy connection electrode 140D can be in a floating state. The dummy connection electrode 140D serves to maintain process stability in processes involving multiple stacked semiconductor chips (described later) and to improve heat dissipation characteristics in semiconductor packages with multiple stacked semiconductor chips. This will be described in more detail in the relevant sections. The dummy connection electrode 140D can be omitted if necessary.

[0031] A front connection electrode 150 may be formed on the wiring portion 120. The front connection electrode 150 may be electrically connected to another component (e.g., a substrate to be disposed on the front surface 111 of the semiconductor chip 100 or another semiconductor chip). The front connection electrode 150 may include conductive bumps. The front connection electrode 150 may include various metallic materials such as copper, nickel, or combinations thereof, and may have a single-layer structure or a multi-layer structure.

[0032] The front connecting electrode 150 can be electrically connected to the wiring portion 120. Furthermore, the front connecting electrode 150 can be electrically connected to the through electrode 130 via the wiring portion 120. That is, unlike the rear connecting electrode 140, the front connecting electrode 150 may not directly contact the through electrode 130.

[0033] The bonding layer 160 may be formed on the surface of the front connection electrode 150 opposite to the surface that contacts the wiring portion 120. When multiple semiconductor chips 100 are stacked in a vertical direction (i.e., in a direction perpendicular to the front surface 111 and the rear surface 112 of the body portion 110), the bonding layer 160 may bond to the rear connection electrode 140. The bonding layer 160 may include a solder material having a hemispherical shape, a spherical shape, or a similar shape. However, this embodiment is not limited to this, and various modifications can be made to the shape and material of the bonding layer 160.

[0034] In the horizontal direction, the widths of the signal post-connection electrode 140S, the power post-connection electrode 140P, the dummy post-connection electrode 140D, and the front connection electrode 150 are represented by reference numerals WS, WP, WD, and WF, respectively. The width WS of the signal post-connection electrode 140S can be greater than or equal to the width of the signal through electrode 130S. The widths WS of the signal post-connection electrode 140S, WD of the dummy post-connection electrode 140D, and WF of the front connection electrode 150 can be the same. On the other hand, the width WP of the power post-connection electrode 140P can be greater than the widths WS of the signal post-connection electrode 140S, WD of the dummy post-connection electrode 140D, and WF of the front connection electrode 150. This is because the width WP of the power supply connection electrode 140P must be large enough to overlap with the pair of power supply through electrodes 130P and the space between them, while there is no such limitation on the width WS of the signal connection electrode 140S, the width WD of the dummy connection electrode 140D, and the width WF of the front connection electrode 150. However, this disclosure is not limited thereto, and the width / size of the connection electrodes 140P, 140D, 140S, and 150 can be modified in various ways.

[0035] Although the widths / dimensions of the signal post-connection electrode 140S, the power post-connection electrode 140P, and the dummy post-connection electrode 140D differ, the pitch of the post-connection electrodes 140 (i.e., the distance between the center of any one of the post-connection electrodes 140 and the center of the adjacent post-connection electrode 140) can be substantially constant. For example, as shown, the pitch P1 between two adjacent power post-connection electrodes 140P, the pitch P2 between adjacent power post-connection electrodes 140P and the dummy post-connection electrode 140D, and the pitch P3 between adjacent power post-connection electrodes 140P and the signal post-connection electrode 140S can have fixed values. Furthermore, the pitch P4 of the front connection electrode 150 can also be substantially the same as the pitch of the post-connection electrodes 140.

[0036] According to the semiconductor chip 100 described above, since a power supply connection electrode 140P is simultaneously in contact with a pair of power supply through electrodes 130P, the resistance of the power supply path through the power supply connection electrode 140P and the pair of power supply through electrodes 130P can be reduced. As a result, power can be supplied easily and stably.

[0037] Figures 2A to 2G This is a cross-sectional view illustrating a method for manufacturing a semiconductor chip according to an embodiment of the present disclosure. For ease of description, based on... Figure 1 These cross-sectional views are shown for a portion of the semiconductor chip (see A1).

[0038] Reference Figure 2AThe following structure can be formed on a carrier substrate (not shown), comprising: an initial body portion 210 having a front surface 211 and an initial rear surface 212, and having an initial through electrode 230 formed therein; a wiring portion 220 disposed on the front surface 211 of the initial body portion 210; and a front connecting electrode 250 and a bonding layer 260 disposed on the wiring portion 220. This structure can be attached to the carrier substrate using an adhesive material. The method for forming this structure will be described in more detail below.

[0039] First, an initial body portion 210 with a front surface 211 and an initial rear surface 212 can be provided. The initial rear surface 212 can be larger than... Figure 1 The rear surface 112 has a greater distance from the front surface 211, therefore, the initial body portion 210 can be larger than... Figure 1 The main body 110 has a greater thickness.

[0040] Subsequently, the initial body portion 210 can be etched to form a hole 213 in the initial body portion 210. The hole 213 can be formed from the front surface 211 of the initial body portion 210 toward the initial rear surface 212 to a predetermined depth. The depth of the hole 213 can be less than the thickness of the initial body portion 210.

[0041] Subsequently, the via 213 can be filled with a conductive material to form an initial through electrode 230. The initial through electrode 230 may include an initial power through electrode 230P and an initial signal through electrode 230S. At this time, it is possible to base the initial insulating layer (see...) Figure 2C 280 in the middle) and / or insulation layer (see 280) and / or insulation layer Figure 2E The thickness of the 280A electrode in the figure determines the distance DP between a pair of initial power through electrodes 230P to be connected to a power source. This will be described in more detail in the relevant section.

[0042] Subsequently, a wiring portion 220 can be formed on the front surface 211 of the initial main body portion 210 in which the initial through electrode 230 is formed, and then a front connection electrode 250 and a bonding layer 260 can be formed on the wiring portion 220. Thus, a structure disposed on a carrier substrate can be obtained.

[0043] Reference Figure 2B A portion of the initial body portion 210 can be removed to form a body portion 210A with a thickness less than that of the initial body portion 210. In other words, a process for thinning the initial body portion 210 can be performed.

[0044] A thinning process can be performed on the initial rear surface 212 of the initial body portion 210. Therefore, the body portion 210A can have a front surface 211 and a rear surface 212A. The distance between the rear surface 212A and the front surface 211 can be shorter than the distance between the initial rear surface 212 and the front surface 211. Furthermore, the thinning process can be performed by grinding, chemical mechanical polishing (CMP), and / or etch-back. Additionally, a thinning process can be performed such that a portion of the initial through electrode 230 protrudes from the rear surface 212A of the body portion 210A.

[0045] Reference Figure 2C An initial insulating layer 280 may be formed on the rear surface 212A of the main body portion 210A and on the portion of the initial through electrode 230 that protrudes from the rear surface 212A of the main body portion 210A.

[0046] The initial insulating layer 280 can be transformed into an insulating layer by a planarization process described later (see below). Figure 2E (280A in the example), and this insulating layer can be used to protect the semiconductor chip and prevent current leakage due to metal diffusion between the through electrodes. This will be described in more detail in the relevant section.

[0047] The initial insulating layer 280 can be formed by various deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The initial insulating layer 280 may comprise silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Furthermore, in this embodiment, the initial insulating layer 280 may have a single-layer structure, but this disclosure is not limited thereto. In another embodiment, the initial insulating layer 280 may have a multilayer structure.

[0048] The initial insulating layer 280 can be formed to have a substantially uniform thickness along its lower contour. The thickness of the initial insulating layer 280 is indicated by reference numeral T1. In this case, the distance DP between a pair of initial power through electrodes 230P can have a value greater than twice the thickness T1 of the initial insulating layer 280. This is to ensure that space can be formed between the portions of the pair of initial power through electrodes 230P that protrude from the rear surface 212A of the body portion 210A. (The last sentence appears to be incomplete and possibly refers to a different context.) Figure 2H A comparison will be made to describe this in more detail.

[0049] Figure 2H It is used with Figure 2C A comparison diagram. Figure 2H The distance DP' between a pair of initial power through electrodes 230P is shown. Figure 2C The distance DP shown is short, that is, the distance DP' is less than twice the thickness T1 of the initial insulation layer 280.

[0050] Reference Figure 2H When the distance DP' between a pair of initial power through electrodes 230P is relatively narrow, the initial insulating layer 280 may not be deposited to the desired thickness between the pair of initial power through electrodes 230P. This is because, before the initial insulating layer 280 is deposited to the desired thickness, the upper part of the space between the portions of the pair of initial power through electrodes 230P protruding above the rear surface 212A of the body portion 210A is used as an insulating material barrier to form the initial insulating layer 280, resulting in undesirable voids V in the initial insulating layer 280 formed in this space.

[0051] In this case, when performing the planarization process (described later), it may be necessary to pass through a pair of power electrodes (see...). Figure 2E The problem is that the insulating layer formed on the rear surface 212A of the main body portion 210A between 230PA) is absent or thinner than expected.

[0052] Return to reference Figure 2C In this embodiment, in order to solve Figure 2H The problem described herein is that the distance DP between a pair of initial power through electrodes 230P can be set to a value having a thickness T1 greater than twice that of the initial insulating layer 280.

[0053] Reference Figure 2D A sacrificial layer 290 can be formed on the initial insulating layer 280.

[0054] The sacrificial layer 290 prevents process defects from occurring during the planarization process, which will be described later. Without the sacrificial layer 290... Figure 2C If the resulting structure undergoes a planarization process, pressure may concentrate on the protruding portion of the initial through electrode 230, and therefore, the protruding portion may crack. The cracked portion, being a conductive material, can cause various defects within the semiconductor chip. A sacrificial layer 290 can prevent this pressure concentration. The sacrificial layer 290 can be formed to have a thickness sufficient to cover the protruding portion of the initial through electrode 230.

[0055] Reference Figure 2E , can be Figure 2D The resulting structure undergoes a planarization process. This planarization process can be performed using polishing methods such as chemical mechanical polishing.

[0056] In this case, a planarization process can be performed until the initial insulating layer 280 formed on the rear surface 212A of the body portion 210A is exposed. As a result, substantially all of the sacrificial layer 290 can be removed during the planarization process. Additionally, the portion of the initial through electrode 230 located above the upper surface of the initial insulating layer 280 formed on the rear surface 212A of the body portion 210A can be removed (see...). Figure 2D (A2 in the original text) to form the through electrode 230A. Alternatively, this portion of the initial insulating layer 280 along the initial through electrode 230 may be removed (see A2 in the original text). Figure 2D The portion formed by the side and top surfaces of A2 in the middle is used to form an insulating layer 280A.

[0057] As a result, an insulating layer 280A can be formed on the rear surface 212A of the main body portion 210A, and a through electrode 230A penetrating the insulating layer 280A and the main body portion 210A can be formed. The through electrode 230A may include a signal through electrode 230SA and a power through electrode 230PA. One end of the through electrode 230A can be electrically connected to the wiring portion 220 as described above, and the other end and / or upper surface of the through electrode 230A can form a flat surface with the upper surface of the insulating layer 280A when exposed from the insulating layer 280A.

[0058] Furthermore, the planarization process can be performed by using the upper surface of the initial insulating layer 280 formed on the rear surface 212A of the body portion 210A as a planarization stop layer (e.g., a polishing stop layer). Therefore, during this planarization process, it can be assumed that the loss in the initial insulating layer 280 formed on the rear surface 212A of the body portion 210A is small, or even if loss exists, it is negligible. Therefore, the thickness of the insulating layer 280A is indicated by reference numeral T1, which is equal to the thickness of the initial insulating layer 280.

[0059] Reference Figure 2F An initial metal-containing thin film layer 292 can be formed on the insulating layer 280A. The initial metal-containing thin film layer 292 can include a metal such as copper (Cu) or titanium (Ti) or a compound of such metal, and can have a single-layer or multi-layer structure. As an example, the initial metal-containing thin film layer 292 can have a multi-layer structure including a barrier layer and a seed layer disposed on the barrier layer. The barrier layer can include a metal or metal compound such as Ti, TiW, TiN, or NiV, and the seed layer can include a metal such as Cu. In this case, the barrier layer can be used to prevent metal diffusion between the through electrodes 230A, and the seed layer can be used as a seed during subsequent electroplating.

[0060] Subsequently, a photoresist pattern 294 can be formed on the initial metal-containing thin film layer 292 to provide spaces in which the power post-connection electrode 240P and the signal post-connection electrode 240S are to be formed, and electroplating can then be performed. As a result, the power post-connection electrode 240P and the signal post-connection electrode 240S can be formed in the spaces provided by the photoresist pattern 294. The power post-connection electrode 240P can be connected to a pair of power through electrodes 230PA, and the signal post-connection electrode 240S can be connected to a signal through electrode 230SA. For reference, although not shown in the figure, a dummy post-connection electrode not connected to the through electrode 230A can also be formed in this process (see...). Figure 1 (140D).

[0061] Reference Figure 2G In removing the photoresist pattern ( Figure 2F After step 294), the portion of the initial metal thin film layer 292 not covered by the power supply post-connection electrode 240P and the signal post-connection electrode 240S can be removed. As a result, a metal thin film layer 292A can be formed. The metal thin film layer 292A can be disposed below each of the power supply post-connection electrode 240P and the signal post-connection electrode 240S, and can be connected to each of the power supply post-connection electrode 240P and the signal post-connection electrode 240S. Specifically, the metal thin film layer 292A below the power supply post-connection electrode 240P can be simultaneously connected to a pair of power supply through electrodes 230PA.

[0062] In this case, this portion of the initial metal-containing thin film layer 292 can be removed by an isotropic etching method such as wet etching. Therefore, the metal-containing thin film layer 292A can have a side surface that is recessed inward compared to the side surface of each of the power supply post-connection electrode 240P and the signal post-connection electrode 240S. The space formed below each of the power supply post-connection electrode 240P and the signal post-connection electrode 240S by the recessed side surface of the metal-containing thin film layer 292A will hereinafter be referred to as the undercut U of the metal-containing thin film layer 292A.

[0063] In this case, the width WP of the power supply connection electrode 240P can be equal to or greater than the sum of the width WP' of a pair of power supply through electrodes 230PA, the distance DP between the pair of power supply through electrodes 230PA, and the width WU of the undercut U.

[0064] Furthermore, even if the undercut U is formed, the pair of power supply electrodes 230PA can be exposed without passing through the undercut U. The upper surfaces of the pair of power supply electrodes 230PA can be completely covered by the metal thin film layer 292A. For this purpose, the position of the side surface of the metal thin film layer 292A can be farther from the center of the power supply connection electrode 240P than the side surface of each of the pair of power supply electrodes 230PA.

[0065] As a result, it is possible to manufacture such as Figure 2G The semiconductor chip shown. Figure 2G Semiconductor chips can be used with Figure 1 The semiconductor chips are basically the same. Figure 2G In a semiconductor chip, the main body 210A, the wiring portion 220, the through electrode 230A having a power supply through electrode 230PA and a signal through electrode 230SA, the power supply rear connection electrode 240P, the signal rear connection electrode 240S, the front connection electrode 250, and the bonding layer 260 can respectively correspond to Figure 1 The semiconductor chip 100 includes a main body portion 110, a wiring portion 120, a through electrode 130 having a power through electrode 130P and a signal through electrode 130S, a power back connection electrode 140P, a signal back connection electrode 140S, a front connection electrode 150, and a bonding layer 160.

[0066] also, Figure 2G The semiconductor chip may further include an insulating layer 280A disposed on the rear surface 212A of the body portion 210A. A through electrode 230A may be formed to penetrate the body portion 210A and the insulating layer 280A, and a power supply post-connection electrode 240P and a signal post-connection electrode 240S may be formed on the insulating layer 280A to connect to the through electrode 230A. Furthermore, a metal-containing thin film layer 292A having an undercut U may be further interposed between the power supply through electrode 230PA and the power supply post-connection electrode 240P, and between the signal through electrode 230SA and the signal post-connection electrode 240S.

[0067] Here, the distance DP between the pair of power supply electrodes 230PA can be greater than twice the thickness T1 of the insulating layer 280A. Furthermore, the width WP of the power supply connection electrode 240P connected to the pair of power supply electrodes 230PA can be equal to or greater than the sum of the width WP' of the pair of power supply electrodes 230PA, the distance DP between the pair of power supply electrodes 230PA, and the width WU of the undercut U.

[0068] right Figure 2G The detailed description of the components shown has already been described in the manufacturing method and will therefore be omitted.

[0069] Figure 3This is a cross-sectional view illustrating a semiconductor chip according to another embodiment of the present disclosure. For ease of description, this cross-sectional view is based on... Figure 2G The image shows a magnified view of a semiconductor chip. The following text will focus on... Figure 2G The differences are described.

[0070] Reference Figure 3 In the semiconductor chip of this embodiment, the power supply electrode 330PA may include a conductive post 332PA and a spacer insulating layer 334PA surrounding the sidewalls of the conductive post 332PA. The conductive post 332PA may include a metal or a compound of the metal such as copper (Cu), tin (Sn), silver (Ag), tungsten (W), nickel (Ni), ruthenium (Ru), or cobalt (Co). The spacer insulating layer 334PA may be disposed between the conductive post 332PA and the body portion 310A to insulate them from each other. The spacer insulating layer 334PA may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. Here, the width WP' of the power supply electrode 330PA may be considered as the sum of the width of the conductive post 332PA and the width of the spacer insulating layer 334PA.

[0071] The undescribed reference numerals 380A, 392A, and 340P can respectively denote the insulating layer, the metal thin film layer, and the power supply connection electrode.

[0072] Furthermore, although not shown, the signal pass-through electrode may also have a structure in which the spacer insulating layer surrounds the sidewall of the conductive post.

[0073] Figure 4 This is a cross-sectional view showing a semiconductor chip according to another embodiment of the present disclosure. For ease of description, this cross-sectional view is based on... Figure 2G The image shows a magnified view of a semiconductor chip. The following text will focus on... Figure 2G The differences are described.

[0074] Reference Figure 4 In the semiconductor chip of this embodiment, the thickness T2 of the insulating layer 480A between a pair of power supply electrodes 430PA can be less than the thickness T1 of the insulating layer 480A outside the pair of power supply electrodes 430PA. The reason is as follows.

[0075] The above planarization process can be performed (refer to...) Figure 2ETo maintain the thickness of the initial insulating layer, polishing is stopped when the upper surface of the initial insulating layer is exposed. In this case, in a process that exposes the entire upper surface of the initial insulating layer with a relatively large area outside the pair of power through electrodes 430PA, the initial insulating layer with a relatively narrow area between the pair of power through electrodes 430PA may be over-polished. As a result, an insulating layer 480A with a thickness difference, as shown in the figure, can be obtained.

[0076] A metal-containing thin film layer 292A can be formed on the insulating layer 480A along the contour of the insulating layer 480A. Therefore, a step height may occur in the metal-containing thin film layer 292A. That is, the metal-containing thin film layer 292A may have a relatively low upper / lower surface between a pair of power through electrodes 430PA, and a relatively high upper / lower surface in the remaining areas.

[0077] The undescribed reference numerals 410A and 440P can respectively denote the main body and the electrode connected to the power supply.

[0078] Figure 5 This is a cross-sectional view showing a semiconductor chip according to another embodiment of the present disclosure. For ease of description, this cross-sectional view is based on... Figure 2G The image shows a magnified view of a semiconductor chip. The following text will focus on... Figure 2G The differences are described.

[0079] Reference Figure 5 In the semiconductor chip of this embodiment, the insulating layer 580A may have a multilayer structure. For example, the insulating layer 580A may have a stacked structure of a first insulating layer 582A and a second insulating layer 584A.

[0080] In this configuration, the first insulating layer 582A can be formed along the rear surface of the main body portion 510A and the side surface of the portion of the power supply electrode 530PA that protrudes from the rear surface of the main body portion 510A. The second insulating layer 584A can be formed to fill the space defined by the first insulating layer 582A. Therefore, the first insulating layer 582A can be inserted between the second insulating layer 584A and the power supply electrode 530PA, and between the second insulating layer 584A and the rear surface of the main body portion 510A.

[0081] The first insulating layer 582A and the second insulating layer 584A can be formed of different insulating materials. For example, when the first insulating layer 582A is silicon nitride, the second insulating layer 584A can be silicon oxide, and vice versa.

[0082] The undescribed reference numeral 550P may indicate the electrode connected after the power supply.

[0083] Figure 6A and Figure 6B This is a cross-sectional view showing a semiconductor chip according to another embodiment of the present disclosure. For ease of description, this cross-sectional view is based on... Figure 2G The image shows a magnified view of a semiconductor chip. The following text will focus on... Figure 2G The differences are described.

[0084] Reference Figure 6A In the semiconductor chip of this embodiment, the positions of the metal thin film layer 692A and the power supply connection electrode 640P are movable. Even in this case, the power supply connection electrode 640P can be simultaneously connected to a pair of power supply through electrodes 630PA, and the pair of power supply through electrodes 630PA may not be exposed. The metal thin film layer 692A can cover the upper surface of the pair of power supply through electrodes 630PA to avoid unnecessary exposure, which prevents metal ions from moving through them and causing a short circuit.

[0085] Therefore, even if the metal thin film layer 692A moves, it can only move until one sidewall of one of the pair of power-through electrodes 630PA aligns with one sidewall of the metal thin film layer 692A. Otherwise, at least a portion of the power-through electrode 630PA might be unnecessarily exposed, or the power-after connection electrode 640P might not be able to connect to the pair of power-through electrodes 630PA simultaneously.

[0086] Reference Figure 6B In the semiconductor chip of this embodiment, the power supply electrode 630PA may include a conductive post 632PA and a spacer insulating layer 634PA surrounding the sidewall of the conductive post 632PA.

[0087] In this configuration, the metal-containing thin film layer 692A can be moved until one sidewall of the conductive pillar 632PA aligns with one sidewall of the metal-containing thin film layer 692A. The upper surface of the spacer insulating layer 634PA can then be exposed by the metal-containing thin film layer 692A.

[0088] The aforementioned semiconductor chips can be stacked vertically to achieve a single semiconductor package. (Refer to...) Figure 7 This will be described exemplarily.

[0089] Figure 7 This is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure. The semiconductor package may include a plurality of semiconductor chips stacked in a vertical direction. Each of the plurality of semiconductor chips may include a semiconductor chip substantially identical to one of the semiconductor chips in the above-described embodiments.

[0090] Reference Figure 7The semiconductor package of this embodiment may include a substrate 700 and a plurality of semiconductor chips 710, 720, 730, 740, and 750 stacked on the substrate 700 in a vertical direction. In this embodiment, five semiconductor chips 710, 720, 730, 740, and 750 are stacked, but this disclosure is not limited thereto, and the number of semiconductor chips stacked in the vertical direction can be modified in various ways. For ease of description, the five semiconductor chips 710, 720, 730, 740, and 750 will be referred to as the first semiconductor chip 710, the second semiconductor chip 720, the third semiconductor chip 730, the fourth semiconductor chip 740, and the fifth semiconductor chip 750 based on their distance from the substrate 700.

[0091] The substrate 700 may be a layer having circuitry and / or wiring structures to connect a stacked structure of multiple semiconductor chips 710, 720, 730, 740, and 750 to external components. For example, the substrate 700 may include a substrate such as a printed circuit board (PCB), an interposer, or a redistribution layer. Alternatively, when the multiple semiconductor chips 710, 720, 730, 740, and 750 are memory chips, the substrate 700 may be a semiconductor chip having logic circuitry supporting the operation of these memory chips (e.g., read operations to read data from memory chips or write operations to write data to memory chips).

[0092] The substrate 700 may have an upper surface on which a plurality of semiconductor chips 710, 720, 730, 740 and 750 are disposed, and a lower surface on which external connection terminals 780 for connecting semiconductor packages to external components are disposed and located on the opposite side of the upper surface.

[0093] Except for the fifth semiconductor chip 750, which is located at the topmost part of the first to fifth semiconductor chips 710, 720, 730, 740 and 750, each of the first to fourth semiconductor chips 710, 720, 730 and 740 can be substantially the same as one of the semiconductor chips in the above embodiments.

[0094] In other words, the first semiconductor chip 710 may include a main body portion 711 having a front surface and a rear surface, a wiring portion 712 disposed on the front surface of the main body portion 711, a through electrode 713 penetrating the main body portion 711, a rear connection electrode 714 disposed on the rear surface of the main body portion 711 and connected to the through electrode 713, a front connection electrode 715 disposed on the wiring portion 712, and a bonding layer 716 disposed on the front connection electrode 715. The through electrode 713 may include a signal through electrode 713S and a power through electrode 713P. The rear connection electrode 714 may include a signal rear connection electrode 714S, a power rear connection electrode 714P, and a dummy rear connection electrode 714D.

[0095] The second semiconductor chip 720 may include a main body portion 721 having a front surface and a rear surface, a wiring portion 722 disposed on the front surface of the main body portion 721, a through electrode 723 penetrating the main body portion 721, a rear connection electrode 724 disposed on the rear surface of the main body portion 721 and connected to the through electrode 723, a front connection electrode 725 disposed on the wiring portion 722, and a bonding layer 726 disposed on the front connection electrode 725. The through electrode 723 may include a signal through electrode 723S and a power through electrode 723P. The rear connection electrode 724 may include a signal rear connection electrode 724S, a power rear connection electrode 724P, and a dummy rear connection electrode 724D. The bonding layer 726 may be bonded to the rear connection electrode 714 of the first semiconductor chip 710.

[0096] Since each of the third semiconductor chip 730 and the fourth semiconductor chip 740 has the same structure as the second semiconductor chip 720, their detailed description will be omitted. The third semiconductor chip 730 may include a body portion 731, a wiring portion 732, a through electrode 733 having a signal through electrode 733S and a power through electrode 733P, a rear connection electrode 734 having a signal rear connection electrode 734S, a power rear connection electrode 734P, and a dummy rear connection electrode 734D, a front connection electrode 735, and a bonding layer 736. The fourth semiconductor chip 740 may include a body portion 741, a wiring portion 742, a through electrode 743 having a signal through electrode 743S and a power through electrode 743P, a rear connection electrode 744 having a signal rear connection electrode 744S, a power rear connection electrode 744P, and a dummy rear connection electrode 744D, a front connection electrode 745, and a bonding layer 746.

[0097] Because the fifth semiconductor chip 750 is located at the top, it may not include the through electrode and the rear connection electrode. That is, as shown in the figure, the fifth semiconductor chip 750 may include a main body portion 751 having a front surface and a rear surface, a wiring portion 752 disposed on the front surface of the main body portion 751, a front connection electrode 755 disposed on the wiring portion 752, and a bonding layer 756 disposed on the front connection electrode 755.

[0098] In this embodiment, the front connection electrodes 715, 725, 735, 745, and 755 and the rear connection electrodes 714, 724, 734, and 744 in the first to fifth semiconductor chips 710, 720, 730, 740, and 750 can have the same dimensions. However, contrary to what is shown, the dimensions of the front connection electrodes 715, 725, 735, 745, and 755 and the rear connection electrodes 714, 724, 734, and 744 can be different from those shown. Figure 1 Make similar adjustments.

[0099] The spaces between the first semiconductor chip 710 and the substrate layer 700, between the first semiconductor chip 710 and the second semiconductor chip 720, between the second semiconductor chip 720 and the third semiconductor chip 730, between the third semiconductor chip 730 and the fourth semiconductor chip 740, and between the fourth semiconductor chip 740 and the fifth semiconductor chip 750 can be filled with a filler material 760. The filler material 760 can be formed by allowing underfill material to flow into the space through capillary action and then curing it.

[0100] Furthermore, the substrate 700 and the first to fifth semiconductor chips 710, 720, 730, 740, and 750 may be surrounded by a molding layer 770. That is, the molding layer 770 may be formed to cover the first to fifth semiconductor chips 710, 720, 730, 740, and 750 on the upper surface of the substrate 700. The molding layer 770 may include various molding materials such as EMC (epoxy molding compound). For example, when the filler material 760 is omitted, the molding layer 770 may be formed to fill the spaces between the first semiconductor chip 710 and the substrate 700, between the first semiconductor chip 710 and the second semiconductor chip 720, between the second semiconductor chip 720 and the third semiconductor chip 730, between the third semiconductor chip 730 and the fourth semiconductor chip 740, and between the fourth semiconductor chip 740 and the fifth semiconductor chip 750.

[0101] The semiconductor package according to this embodiment can realize a highly integrated semiconductor package. Furthermore, power can be easily supplied to multiple semiconductor chips 710, 720, 730, 740, and 750 stacked in the vertical direction.

[0102] According to the above embodiments of the present disclosure, a semiconductor chip with through electrodes and a semiconductor package having the semiconductor chip can be provided, which can enhance operating characteristics and improve process margin.

[0103] Figure 8 A block diagram illustrating an electronic system of a memory card 7800 including at least one of semiconductor packages according to various embodiments is shown. The memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. The memory 7810 and memory controller 7820 can store data or read out stored data. At least one of the memory 7810 and memory controller 7820 may include at least one of semiconductor packages according to the described embodiments.

[0104] The memory 7810 may include a non-volatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 such that stored data or stored data can be read in response to a read / write request from the host 7830.

[0105] Figure 9 A block diagram illustrating an electronic system 8710 comprising at least one of the semiconductor packages according to the various embodiments described is shown. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be interconnected via a bus 8715 providing a path for data movement.

[0106] In implementations, controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. Controller 8711 or memory 8713 may include one or more semiconductor packages according to various embodiments of this disclosure. Input / output device 8712 may include at least one selected from keypad, keyboard, display device, and touchscreen. Memory 8713 is a means for storing data. Memory 8713 may store data and / or commands to be executed by controller 8711.

[0107] The memory 8713 may include volatile memory devices such as DRAM and / or non-volatile memory devices such as flash memory. For example, flash memory can be installed in information processing systems such as mobile terminals or desktop computers. Flash memory can constitute a solid-state drive (SSD). In this case, the electronic system 8710 can stably store large amounts of data in the flash memory system.

[0108] The electronic system 8710 may also include an interface 8714 configured to transmit data to and receive data from a communication network. The interface 8714 may be of wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0109] The electronic system 8710 can be implemented as a mobile system, personal computer, industrial computer, or logic system performing various functions. For example, the mobile system can be any of a personal digital assistant (PDA), portable computer, tablet computer, mobile phone, smartphone, wireless phone, laptop computer, memory card, digital music system, and information sending / receiving system.

[0110] If electronic system 8710 represents a device capable of performing wireless communication, then electronic system 8710 can be used in communication systems using technologies such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0111] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of this teaching as defined by the appended claims.

[0112] Cross-references to related applications

[0113] This application claims priority to Korean Patent Application No. 10-2020-0159887, filed on November 25, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor chip, the semiconductor chip comprising: The main body portion has a front surface and a rear surface; An insulating layer is disposed on the rear surface of the main body portion; A pair of through electrodes, the pair of through electrodes penetrating the main body portion and the insulating layer; A rear connection electrode, wherein the rear connection electrode is disposed on the insulating layer and is simultaneously connected to the pair of through electrodes; and A front connection electrode is disposed on the front surface of the main body portion. The front connecting electrode is simultaneously connected to the pair of through electrodes. The distance between the pair of through electrodes is greater than twice the thickness of the insulating layer.

2. The semiconductor chip according to claim 1, wherein, The pair of through electrodes receive power.

3. The semiconductor chip according to claim 2, further comprising: A signal-penetrating electrode, the signal-penetrating electrode penetrating the main body and the insulating layer, wherein the signal-penetrating electrode transmits a signal; and A signal post-connection electrode is disposed on the insulating layer and connected to the signal through electrode.

4. The semiconductor chip according to claim 1, further comprising: A dummy post-connection electrode is disposed on the insulating layer, wherein the dummy post-connection electrode is in an electrically floating state.

5. The semiconductor chip according to claim 1, wherein, The thickness of the insulating layer includes a first thickness outside the pair of through electrodes and a second thickness between the pair of through electrodes. Wherein, the second thickness is less than the first thickness, and The distance between the pair of through electrodes is greater than twice the first thickness.

6. The semiconductor chip according to claim 1, wherein, The insulating layer includes a first insulating layer and a second insulating layer, and The first insulating layer is formed between the second insulating layer and each of the pair of through electrodes and between the second insulating layer and the rear surface of the body portion.

7. The semiconductor chip according to claim 1, further comprising: A metal thin film layer is inserted between the rear connecting electrode and the pair of through electrodes, wherein the metal thin film layer is simultaneously connected to the pair of through electrodes.

8. The semiconductor chip according to claim 7, wherein, The metal-containing thin film layer includes an undercut portion formed below the sidewall of the rear connection electrode due to the recess of the metal-containing thin film layer.

9. The semiconductor chip according to claim 7, wherein, One sidewall of the metal thin film layer is aligned with one sidewall of one of the two through electrodes.

10. The semiconductor chip according to claim 1, wherein, Each of the pair of through electrodes includes a conductive post and a spacer insulating layer surrounding the sidewalls of the conductive post.

11. The semiconductor chip of claim 10, further comprising: A metal-containing thin film layer is inserted between the rear connection electrode and the pair of through electrodes, wherein the metal-containing thin film layer is simultaneously connected to the pair of through electrodes, and In this configuration, one sidewall of the metal thin film layer is aligned with one sidewall of the conductive pillar.

12. A semiconductor chip, the semiconductor chip comprising: The main body portion has a front surface and a rear surface; An insulating layer is disposed on the rear surface of the main body portion; A pair of through electrodes, the pair of through electrodes penetrating the main body portion and the insulating layer; A metal thin film layer is disposed on the insulating layer and simultaneously connected to the pair of through electrodes; A rear connection electrode, wherein the rear connection electrode is disposed on and connected to the metal-containing thin film layer; and A front connection electrode is disposed on the front surface of the main body portion. The front connecting electrode is simultaneously connected to the pair of through electrodes. The metal-containing thin film layer includes an undercut portion formed below the sidewall of the rear connection electrode due to the recess of the metal-containing thin film layer. Wherein, the width of the rear connecting electrode is equal to or greater than the sum of the widths of the pair of through electrodes, the distance between the pair of through electrodes, and the width of the undercut portion, and The distance between the pair of through electrodes is greater than twice the thickness of the insulating layer.

13. The semiconductor chip according to claim 12, wherein, The pair of through electrodes receive power.

14. The semiconductor chip of claim 13, further comprising: A signal-penetrating electrode, the signal-penetrating electrode penetrating the main body and the insulating layer, wherein the signal-penetrating electrode transmits a signal; and A signal post-connection electrode is disposed on the insulating layer and connected to the signal through electrode.

15. The semiconductor chip according to claim 12, further comprising: A dummy post-connection electrode is disposed on the insulating layer, wherein the dummy post-connection electrode is in an electrically floating state.

16. The semiconductor chip according to claim 12, wherein, One sidewall of the metal thin film layer is aligned with one sidewall of one of the two through electrodes.

17. The semiconductor chip according to claim 12, wherein, Each of the pair of through electrodes includes a conductive post and a spacer insulating layer surrounding the sidewalls of the conductive post.

18. The semiconductor chip according to claim 17, wherein, One sidewall of the metal thin film layer is aligned with one sidewall of the conductive pillar.

19. A semiconductor package comprising: A first semiconductor chip and a second semiconductor chip are stacked vertically. Each of the first semiconductor chip and the second semiconductor chip includes: The main body portion has a front surface and a rear surface; An insulating layer is disposed on the rear surface of the main body portion; A pair of through electrodes, the pair of through electrodes penetrating the main body portion and the insulating layer; A rear connection electrode is disposed on the insulating layer and simultaneously connected to the pair of through electrodes; A wiring portion, the wiring portion being disposed on the front surface of the main body portion; and A front connection electrode is disposed on the wiring portion and is simultaneously connected to the pair of through electrodes. Wherein, the rear connection electrode of the first semiconductor chip is connected to the front connection electrode of the second semiconductor chip, and The distance between the pair of through electrodes is greater than twice the thickness of the insulating layer.

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