Display panel manufacturing method and display panel

Abstract

The present application discloses a method for manufacturing a display panel and a display panel. The present application simultaneously forms two first through holes, a first opening and a first opening through the same light mask, and simultaneously forms two second through holes, a second opening located in the first opening, and a second opening located in the first opening through the same light mask, which can reduce the complexity of the manufacturing process of the LTPO display panel, reduce the number of light masks, and reduce costs.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to a method for manufacturing a display panel and a display panel. Background Art

[0002] Organic Light Emitting Display (OLED) panels and other types of display panels have been widely used in people's lives, such as display screens of mobile phones and computers. Low-temperature polycrystalline oxide (LTPO) display technology combines two thin-film transistors, low-temperature polycrystalline silicon (LTPS) and indium gallium zinc oxide (IGZO), so that the display panel has the characteristics of strong driving capability and low power consumption, and is suitable for both high-frequency display and low-frequency display. It has become an increasingly popular technology in display panels.

[0003] However, LTPO display panels have problems such as complex structure of the display panel, complicated manufacturing process, large number of masks and high cost. Summary of the invention

[0004] The present application provides a method for manufacturing a display panel and a display panel, which can solve the problems of complicated manufacturing process, large number of masks and high cost caused by the complex structure of the LTPO display panel.

[0005] The present application provides a method for manufacturing a display panel, wherein the display panel includes a display area and a non-display area, wherein the non-display area includes a bending area, and the method includes the following steps:

[0006] Step S100, providing a substrate, forming a light shielding layer on the substrate, forming a buffer layer on the light shielding layer, forming a P-type semiconductor layer and a first gate of a P-type transistor, and an N-type semiconductor layer and a second gate of an N-type transistor on the buffer layer, and forming an interlayer insulating layer on the second gate;

[0007] Step S200: simultaneously forming two first through holes corresponding to the P-type transistor, as well as a first opening and a first opening, wherein the first opening is located in the bending region;

[0008] Step S300: forming two second through holes corresponding to the N-type transistor, a second opening located in the first opening, and a second opening located in the first opening;

[0009] Step S400: forming a source-drain metal layer, and patterning the source-drain metal layer to form a first source and a first drain of the P-type transistor, a second source and a second drain of the N-type transistor, and a connecting electrode; wherein the first source and the first drain are respectively connected to the P-type semiconductor layer through two of the first through holes, the second source and the second drain are respectively connected to the N-type semiconductor layer through two of the second through holes, and the connecting electrode is connected to the light-shielding layer through the first opening and the second opening.

[0010] Optionally, in some embodiments of the present application, in the step S400, the connecting electrode is connected to one of the first source and the first drain, or / and the connecting electrode is connected to one of the second source and the second drain.

[0011] Optionally, in some embodiments of the present application, step S100 includes the following steps:

[0012] Step S110: providing a substrate, forming a light shielding layer on the substrate, and forming a buffer layer on the light shielding layer;

[0013] Step S120: forming the P-type semiconductor layer on the buffer layer, forming a first gate insulating layer on the P-type semiconductor layer, and forming the first gate on the first gate insulating layer;

[0014] Step S130: forming a first insulating layer on the first gate, forming a capacitor metal layer on the first insulating layer, and patterning the capacitor metal layer to form a capacitor electrode plate of a storage capacitor and a third gate of the N-type transistor;

[0015] Step S140: forming a second gate insulating layer on the third gate, forming the N-type semiconductor layer on the second gate insulating layer, forming a third gate insulating layer on the N-type semiconductor layer, forming the second gate on the third gate insulating layer, and forming the interlayer insulating layer on the second gate.

[0016] Optionally, in some embodiments of the present application, in the step S200, the first through hole penetrates the interlayer insulating layer to the surface of the P-type semiconductor layer away from the substrate, and the first opening and the first opening penetrate the interlayer insulating layer to the surface of the buffer layer away from the substrate.

[0017] Optionally, in some embodiments of the present application, in step S300, the second through hole penetrates the interlayer insulating layer to the surface of the N-type semiconductor layer away from the substrate, the second opening penetrates the buffer layer to the surface of the light-shielding layer away from the substrate, and the second opening penetrates the buffer layer to the surface of the substrate close to the light-shielding layer.

[0018] Optionally, in some embodiments of the present application, in the step S300, the width of the second opening is smaller than the width of the first opening, and the width of the second opening is smaller than the width of the first opening.

[0019] Optionally, in some embodiments of the present application, the center of the orthographic projection of the first opening on the substrate overlaps with the center of the orthographic projection of the second opening on the substrate;

[0020] A center of an orthographic projection of the first opening on the substrate overlaps with a center of an orthographic projection of the second opening on the substrate.

[0021] Optionally, in some embodiments of the present application, the P-type semiconductor layer is a polysilicon material, and the N-type semiconductor layer is an oxide semiconductor material.

[0022] Optionally, in some embodiments of the present application, between the step S300 and the step S400, the following further comprises: step S500: filling an organic layer in the first opening and the second opening;

[0023] After step S400, the method further includes: step S600: forming a light-emitting device layer and a packaging layer.

[0024] Accordingly, an embodiment of the present application further provides a display panel, wherein the display panel is manufactured by using any of the above-mentioned display panel manufacturing methods.

[0025] In an embodiment of the present application, a method for manufacturing a display panel and a display panel are provided. The display panel includes a display area and a non-display area, and the non-display area includes a bending area. The method for manufacturing the display panel includes at least the following steps: step S100, providing a substrate, forming a light shielding layer on the substrate, forming a buffer layer on the light shielding layer, forming a P-type semiconductor layer and a first gate of a P-type transistor, and an N-type semiconductor layer and a second gate of an N-type transistor on the buffer layer, and forming an interlayer insulating layer on the second gate; step S200: simultaneously forming two first through holes corresponding to the P-type transistor, as well as a first opening, a first opening, and a first The opening is located in the bending area; step S300: forming two second through holes corresponding to the N-type transistor, a second opening located in the first opening, and a second opening located in the first opening; step S400: forming a source-drain metal layer, patterning the source-drain metal layer to form a first source and a first drain of the P-type transistor, a second source and a second drain of the N-type transistor, and a connecting electrode; wherein the first source and the first drain are respectively connected to the P-type semiconductor layer through two first through holes, the second source and the second drain are respectively connected to the N-type semiconductor layer through two second through holes, and the connecting electrode is connected to the light shielding layer through the first opening and the second opening. The present application simultaneously forms two first through holes, a first opening, and a first opening through the same mask (step S200), and simultaneously forms two second through holes, a second opening located in the first opening, and a second opening located in the first opening through the same mask (step S300), which can reduce the complexity of the manufacturing process of the LTPO display panel, reduce the number of masks, and reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A schematic top view of a display panel provided in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of a first process step of a method for manufacturing a display panel provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of a first process of a method for manufacturing a display panel provided in an embodiment of the present application;

[0031] Figure 5A schematic diagram of a second process of a method for manufacturing a display panel provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of a third process of a method for manufacturing a display panel provided in an embodiment of the present application;

[0033] Figure 7 A schematic diagram of a fourth process of a method for manufacturing a display panel provided in an embodiment of the present application;

[0034] Figure 8 A schematic diagram of a second process step of a method for manufacturing a display panel provided in an embodiment of the present application;

[0035] Fig. 9 A schematic diagram of a third process step of a method for manufacturing a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0037] The present application provides a method for manufacturing a display panel, the display panel includes a display area and a non-display area, the non-display area includes a bending area, and the method for manufacturing the display panel includes at least the following steps: step S100, providing a substrate, forming a light shielding layer on the substrate, forming a buffer layer on the light shielding layer, forming a P-type semiconductor layer and a first gate of a P-type transistor, and an N-type semiconductor layer and a second gate of an N-type transistor on the buffer layer, and forming an interlayer insulating layer on the second gate; step S200: simultaneously forming two first through holes corresponding to the P-type transistor, as well as a first opening and a first opening, the first opening being located at the bending area; Folding area; Step S300: forming two second through holes corresponding to the N-type transistor, a second opening located in the first opening, and a second opening located in the first opening; Step S400: forming a source and drain metal layer, patterning the source and drain metal layer to form a first source and a first drain of the P-type transistor, a second source and a second drain of the N-type transistor, and a connecting electrode; wherein the first source and the first drain are respectively connected to the P-type semiconductor layer through two first through holes, the second source and the second drain are respectively connected to the N-type semiconductor layer through two second through holes, and the connecting electrode is connected to the light shielding layer through the first opening and the second opening. The present application also provides a display panel manufactured using the aforementioned display panel manufacturing method. The specific embodiments of the present application are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0038] Embodiment 1

[0039] See also Figure 1 and Figure 2 , Figure 1 A schematic top view of a display panel 100 provided in an embodiment of the present application; Figure 2 A schematic diagram of the cross-sectional structure of a display panel 100 provided in an embodiment of the present application.

[0040] See also Figure 1 , Figure 2 In order to facilitate understanding of the manufacturing method of the display panel in the subsequent embodiments of the present application, this embodiment illustrates the structure of a display panel 100. The manufacturing method of the display panel provided in the present application can also manufacture Figure 1 and Figure 2 Display panel outside the illustrated structure.

[0041] See also Figure 1 , Figure 1 A display panel 100 is shown. The display panel 100 includes a display area AA and a non-display area BB. The non-display area BB includes a bending area BB1.

[0042] Specifically, in some implementations, the bending area BB1 can be bent to the non-display side of the display panel 100 to facilitate reducing the frame. The non-display side is the side opposite to the light emitting direction of the display panel 100, or the non-display side is the side away from human eye observation.

[0043] See also Figure 2 , Figure 2 Hint Figure 1 The cross-section of the dashed line HK, Figure 3 Only a partial structure of the display panel 100 is shown, and the display panel 100 may further include a light emitting device layer and an encapsulation layer ( Figure 2 not shown).

[0044] See also Figure 2 The layer structure of the display panel 100 includes: a substrate 11, a light shielding layer 12, a buffer layer 13, a P-type semiconductor layer 14, a first gate insulating layer 15, a first gate 16, a first insulating layer 17, a capacitor metal layer 18, a second gate insulating layer 19, an N-type semiconductor layer 20, a third gate insulating layer 21, a second gate 22, an interlayer insulating layer 23, a source and drain metal layer 24, a first planarizing layer 25, a transition metal layer 26, a second planarizing layer 27, an anode 28, and a pixel definition layer 29.

[0045] Specifically, the display panel includes a P-type transistor (P-type thin film transistor) and an N-type transistor (N-type thin film transistor). The structure of the display panel 100 is not limited to Figure 2 The film layer structure shown, for example, the P-type transistor 101 and the N-type transistor 102 are not limited to top-gate transistors or bottom-gate transistors; for example, the display panel 100 may not include the first planar layer 25; for example, other film layers may be included between the buffer layer 13 and the substrate 11.

[0046] Specifically, the substrate 11 can be a rigid substrate or a flexible substrate. When the substrate 11 is a rigid substrate, the material of the substrate 11 can be glass; when the substrate 11 is a flexible substrate, the material of the substrate 11 can be a composite structure of multiple film layers, for example, the substrate 11 includes a first flexible film layer, an inorganic layer, and a second flexible film layer.

[0047] Specifically, the structure of the display panel 100 may further include a filling layer 30 , which is located in the first opening 71 and the second opening 72 in the bending area BB1 , so as to improve the bending performance of the bending area BB1 .

[0048] Specifically, the structure of the display panel 100 may be any structure applicable to the method for manufacturing a display panel of the present application.

[0049] Embodiment 2

[0050] See also Figures 3 to 9 , Figure 3 A schematic diagram of a first process step of a method for manufacturing a display panel 100 provided in an embodiment of the present application; Figure 4 A schematic diagram of a first process of a method for manufacturing a display panel 100 provided in an embodiment of the present application; Figure 5 A schematic diagram of a second process of a method for manufacturing a display panel 100 provided in an embodiment of the present application; Figure 6 A third process schematic diagram of a method for manufacturing a display panel 100 provided in an embodiment of the present application; Figure 7 A schematic diagram of a fourth process of a method for manufacturing a display panel 100 provided in an embodiment of the present application; Figure 8 A schematic diagram of a second process step of a method for manufacturing a display panel 100 provided in an embodiment of the present application; Fig. 9 A third process step schematic diagram of a method for manufacturing a display panel 100 provided in an embodiment of the present application.

[0051] An embodiment of the present application provides a method for manufacturing a display panel, and the method for manufacturing a display panel includes at least the following steps: step S100, step S200, step S300, and step S400.

[0052] Step S100, providing a substrate, forming a light shielding layer on the substrate, forming a buffer layer on the light shielding layer, forming a P-type semiconductor layer and a first gate of a P-type transistor, and an N-type semiconductor layer and a second gate of an N-type transistor on the buffer layer, and forming an interlayer insulating layer on the second gate.

[0053] Specifically, Figure 4 As shown, a substrate 11 is provided, a light shielding layer 12 is formed on the substrate 11, a buffer layer 13 is formed on the light shielding layer 12, a P-type semiconductor layer 14 and a first gate 16 of a P-type transistor 101, and an N-type semiconductor layer 20 and a second gate 22 of an N-type transistor 102 are formed on the buffer layer 13, and an interlayer insulating layer 23 is formed on the second gate 22.

[0054] Step S200: simultaneously forming two first through holes corresponding to the P-type transistor, as well as a first opening and a first opening, wherein the first opening is located in the bending region.

[0055] Specifically, Figure 5 As shown, two first through holes 51 corresponding to the P-type transistor 101 , as well as a first opening 61 and a first opening 71 are formed simultaneously. The first opening 71 is located in the bending area BB1 .

[0056] Step S300: forming two second through holes corresponding to the N-type transistor, a second opening located in the first opening, and a second opening located in the first opening.

[0057] Specifically, Figure 6 As shown, two second through holes 81 corresponding to the N-type transistor 102 , a second opening 62 located in the first opening 61 , and a second opening 72 located in the first opening 71 are formed.

[0058] Step S400: forming a source-drain metal layer, and patterning the source-drain metal layer to form a first source and a first drain of a P-type transistor, a second source and a second drain of an N-type transistor, and a connecting electrode; wherein the first source and the first drain are connected to the P-type semiconductor layer through two first through holes, respectively, the second source and the second drain are connected to the N-type semiconductor layer through two second through holes, respectively, and the connecting electrode is connected to the light shielding layer through the first opening and the second opening.

[0059] Specifically, Figure 7 As shown, a source-drain metal layer 24 is formed, and the source-drain metal layer 24 is patterned to form a first source 241 and a first drain 242 of the P-type transistor 101, a second source 243 and a second drain 244 of the N-type transistor 102, and a connecting electrode 245; wherein the first source 241 and the first drain 242 are respectively connected to the P-type semiconductor layer 14 through two first through holes 51, the second source 243 and the second drain 244 are respectively connected to the N-type semiconductor layer 20 through two second through holes 81, and the connecting electrode 245 is connected to the light shielding layer 12 through the first opening 61 and the second opening 62.

[0060] In some embodiments, in step S400 , the connection electrode 245 is connected to one of the first source 241 and the first drain 242 , or / and the connection electrode 245 is connected to one of the second source 243 and the second drain 244 .

[0061] Specifically, the connecting electrode 245 is connected to one of the first source 241 and the first drain 242, or / and the connecting electrode 245 is connected to one of the second source 243 and the second drain 244 (not shown in the figure), which can shield the polarized charges on the substrate 11 and improve the stability and other performance of the P-type transistor 101 and / or the N-type transistor 102.

[0062] In some embodiments, Figure 8 Step S100 at least includes the following steps: step S110, step S120, step S130, step S140, which are described in detail herein. Figure 1 Detailed process of some manufacturing steps of the display panel as an example.

[0063] Step S110: providing a substrate, forming a light shielding layer on the substrate, and forming a buffer layer on the light shielding layer.

[0064] Specifically, combined Figure 4As shown, a substrate 11 is provided, a light shielding layer 12 is formed on the substrate 11 , and a buffer layer 13 is formed on the light shielding layer 12 .

[0065] Step S120: forming a P-type semiconductor layer on the buffer layer, forming a first gate insulating layer on the P-type semiconductor layer, and forming a first gate on the first gate insulating layer.

[0066] Specifically, combined Figure 4 As shown, a P-type semiconductor layer 14 is formed on the buffer layer 13 , a first gate insulating layer 15 is formed on the P-type semiconductor layer 14 , and a first gate 16 is formed on the first gate insulating layer 15 .

[0067] Step S130: forming a first insulating layer on the first gate, forming a capacitor metal layer on the first insulating layer, and patterning the capacitor metal layer to form a capacitor electrode plate of the storage capacitor and a third gate of the N-type transistor.

[0068] Specifically, combined Figure 4 As shown, a first insulating layer 17 is formed on the first gate 16 , a capacitor metal layer 18 is formed on the first insulating layer 17 , and the capacitor metal layer 18 is patterned to form a capacitor electrode plate 181 of the storage capacitor and a third gate 182 of the N-type transistor 102 .

[0069] Specifically, in the pixel driving circuit of the display panel 100, the capacitor electrode plate 181 and the first gate 16 form a storage capacitor. The pixel driving circuit of the organic light emitting display panel can be a 2T1C, 7T1C, 8T2C or other structure, which will not be described in detail here.

[0070] Step S140: forming a second gate insulating layer on the third gate, forming an N-type semiconductor layer on the second gate insulating layer, forming a third gate insulating layer on the N-type semiconductor layer, forming a second gate on the third gate insulating layer, and forming an interlayer insulating layer on the second gate.

[0071] Specifically, combined Figure 4 As shown, a second gate insulating layer 19 is formed on the third gate 182, an N-type semiconductor layer 20 is formed on the second gate insulating layer 19, a third gate insulating layer 21 is formed on the N-type semiconductor layer 20, a second gate 22 is formed on the third gate insulating layer 21, and an interlayer insulating layer 23 is formed on the second gate 22.

[0072] It should be noted that step S110, step S120, step S130 and step S140 illustrate the manufacturing process of a part of the film layer structure of the array substrate in the display panel 100. Figure 1When the structure is shown, the manufacturing process of the array substrate in the display panel 100 may further include other processes besides step S110, step S120, step S130 and step S140.

[0073] In some embodiments, Figure 5 As shown, in step S200 , the first through hole 51 penetrates the interlayer insulating layer 23 to the surface of the P-type semiconductor layer 14 away from the substrate 11 , and the first opening 61 and the first opening 71 penetrate the interlayer insulating layer 23 to the surface of the buffer layer 13 away from the substrate 11 .

[0074] In some embodiments, Figure 6 As shown, in step S300, the second through hole 81 penetrates the interlayer insulating layer 23 to the surface of the N-type semiconductor layer 20 away from the substrate 11, the second opening 62 penetrates the buffer layer 13 to the surface of the light-shielding layer 12 away from the substrate 11, and the second opening 72 penetrates the buffer layer 13 to the surface of the substrate 11 close to the light-shielding layer 12.

[0075] Specifically, through Figure 5 and Figure 6 The first through hole 51, the second through hole 81, the first opening 61 and the second opening 62, the first opening 71 and the second opening 72 are arranged as follows: Figure 2 and Figure 7 As shown, the first source 241 and the first drain 242 can be connected to the P-type semiconductor layer 14, the second source 243 and the second drain 244 can be connected to the N-type semiconductor layer 20, the connecting electrode 245 can be connected to the light shielding layer 12, and the filling layer 30 can be connected to the substrate 11.

[0076] In some embodiments, in step S300 , the width of the second opening 62 is smaller than the width of the first opening 61 , and the width of the second opening 72 is smaller than the width of the first opening 71 .

[0077] Specifically, the inner diameter width of the second opening 62 is smaller than the inner diameter width of the first opening 61 , and the inner diameter width of the second opening 72 is smaller than the inner diameter width of the first opening 71 .

[0078] In some embodiments, the center of the orthographic projection of the first opening 61 on the substrate 11 overlaps with the center of the orthographic projection of the second opening 62 on the substrate 11; the center of the orthographic projection of the first opening 71 on the substrate 11 overlaps with the center of the orthographic projection of the second opening 72 on the substrate 11.

[0079] In some embodiments, the P-type semiconductor layer is a polysilicon material, and the N-type semiconductor layer is an oxide semiconductor material.

[0080] In some embodiments, between step S300 and step S400, the following step is further included: step S500, filling the first opening and the second opening with an organic layer; and after step S400, the following step is further included: step S600, forming a light-emitting device layer and an encapsulation layer.

[0081] Specifically, Fig. 9 As shown, step S500 is further included between step S300 and step S400, and step S600 is further included after step S400.

[0082] Step S500 : filling the first opening and the second opening with an organic layer.

[0083] Specifically, an organic layer is filled in the first opening 71 and the second opening 72 to form a filling layer 30 , and then the source-drain metal layer 24 can be conveniently formed during step S400 , so that the source-drain metal layer 24 will not be formed and remain in the first opening 71 and the second opening 72 .

[0084] Step S600: forming a light-emitting device layer and a packaging layer.

[0085] Specifically, the structure of the display panel 100 further includes a light emitting device layer and an encapsulation layer ( Figure 2 (not shown), therefore step S600 is also included after step S400.

[0086] The present application can reduce the complexity of the manufacturing process of the LTPO display panel, reduce the number of masks, and reduce costs by simultaneously forming a through hole, an opening, and simultaneously forming two first through holes, a first opening, and a first opening through step S200, and simultaneously forming two second through holes, a second opening located in the first opening, and a second opening located in the first opening through step S300.

[0087] The present application simultaneously forms two first through holes, a first opening and a first opening through the same photomask (step S200), and simultaneously forms two second through holes, a second opening located in the first opening, and a second opening located in the first opening through the same photomask (step S300), which can reduce the complexity of the manufacturing process of the LTPO display panel, reduce the number of masks, and reduce costs.

[0088] Embodiment 3

[0089] The embodiment of the present application further provides a display panel 100 , and the display panel 100 is manufactured by using the display panel manufacturing method of any one of the above embodiments.

[0090] Specifically, for example, the display panel 100 includes Figure 2 The film structure of the display panel 100 is not limited to Figure 2 The film structure shown.

[0091] The manufacturing method of the display panel and the display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for manufacturing a display panel, wherein the display panel comprises a display area and a non-display area, wherein the non-display area comprises a bending area, wherein: The steps include: Step S100, providing a substrate, forming a light shielding layer on the substrate, forming a buffer layer on the light shielding layer, forming a P-type semiconductor layer and a first gate of a P-type transistor, and an N-type semiconductor layer and a second gate of an N-type transistor on the buffer layer, and forming an interlayer insulating layer on the second gate; Step S200: simultaneously forming two first through holes corresponding to the P-type transistor, as well as a first opening and a first opening, wherein the first opening is located in the bending region; Step S300: forming two second through holes corresponding to the N-type transistor, a second opening located in the first opening, and a second opening located in the first opening; Step S400: forming a source-drain metal layer, and patterning the source-drain metal layer to form a first source and a first drain of the P-type transistor, a second source and a second drain of the N-type transistor, and a connecting electrode; wherein the first source and the first drain are respectively connected to the P-type semiconductor layer through two of the first through holes, the second source and the second drain are respectively connected to the N-type semiconductor layer through two of the second through holes, and the connecting electrode is connected to the light shielding layer through the first opening and the second opening; Wherein, in the step S200, the first through hole penetrates the interlayer insulating layer to the surface of the P-type semiconductor layer away from the substrate, and the first opening and the first opening penetrate the interlayer insulating layer to the surface of the buffer layer away from the substrate; in the step S300, the second through hole penetrates the interlayer insulating layer to the surface of the N-type semiconductor layer away from the substrate, the second opening penetrates the buffer layer to the surface of the shading layer away from the substrate, and the second opening penetrates the buffer layer to the surface of the substrate close to the shading layer.

2. The method for manufacturing a display panel according to claim 1, wherein: In the step S400, the connection electrode is connected to one of the first source and the first drain, or / and the connection electrode is connected to one of the second source and the second drain.

3. The method for manufacturing a display panel according to claim 1, wherein: The step S100 includes the following steps: Step S110: providing a substrate, forming a light shielding layer on the substrate, and forming a buffer layer on the light shielding layer; Step S120: forming the P-type semiconductor layer on the buffer layer, forming a first gate insulating layer on the P-type semiconductor layer, and forming the first gate on the first gate insulating layer; Step S130: forming a first insulating layer on the first gate, forming a capacitor metal layer on the first insulating layer, and patterning the capacitor metal layer to form a capacitor electrode plate of a storage capacitor and a third gate of the N-type transistor; Step S140: forming a second gate insulating layer on the third gate, forming the N-type semiconductor layer on the second gate insulating layer, forming a third gate insulating layer on the N-type semiconductor layer, forming the second gate on the third gate insulating layer, and forming the interlayer insulating layer on the second gate.

4. The method for manufacturing a display panel according to claim 1, wherein: In the step S300, the inner diameter width of the second opening is smaller than the inner diameter width of the first opening, and the inner diameter width of the second opening is smaller than the inner diameter width of the first opening.

5. The method for manufacturing a display panel according to claim 1, wherein: The center of the orthographic projection of the first opening on the substrate overlaps with the center of the orthographic projection of the second opening on the substrate; A center of an orthographic projection of the first opening on the substrate overlaps with a center of an orthographic projection of the second opening on the substrate.

6. The method for manufacturing a display panel according to claim 1, wherein: The P-type semiconductor layer is made of polysilicon material, and the N-type semiconductor layer is made of oxide semiconductor material.

7. The method for manufacturing a display panel according to claim 1, wherein: The method further includes between step S300 and step S400: step S500: filling an organic layer in the first opening and the second opening; After step S400, the method further includes: step S600: forming a light-emitting device layer and a packaging layer.

8. A display panel, characterized in that: The display panel is manufactured by using the method for manufacturing a display panel according to any one of claims 1 to 7.

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