Integrated chip, ferroelectric field effect transistor (FEFET) device and forming method thereof

Abstract

The present disclosure relates to a ferroelectric field effect transistor (FeFET) device. In some embodiments, the FeFET device includes a ferroelectric layer having a first side and a second side opposite to the first side, and a gate electrode arranged along the first side of the ferroelectric layer. The FeFET device also includes an OS channel layer arranged along the second side opposite to the first side of the ferroelectric layer and a pair of source / drain regions arranged on opposite sides of the OS channel layer. The FeFET device also includes a 2D contact layer arranged along the OS channel layer. The OS channel layer has a first doping type, and the 2D contact layer has a second doping type different from the first doping type. Embodiments of the present application provide an integrated chip, a ferroelectric field effect transistor (FEFET) device, and a method for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated chips, ferroelectric field effect transistor (FEFET) devices, and methods of forming the same. Background Art

[0002] A ferroelectric field-effect transistor (FeFET) is a field-effect transistor that includes a ferroelectric material sandwiched between a gate electrode and a source-drain conductive region of the device (the channel). The permanent electric field polarization in the ferroelectric allows this type of device to maintain the transistor's state (on or off) in the absence of any electrical bias, and can therefore be used as a non-volatile memory. Summary of the Invention

[0003] In some embodiments, the present disclosure relates to a FeFET device. The FeFET device includes a ferroelectric layer having a first side and a second side opposite the first side, and a gate electrode disposed along the first side of the ferroelectric layer. The FeFET device also includes an OS channel layer disposed along the second side of the ferroelectric layer opposite the first side, and a pair of source / drain regions disposed on opposite sides of the OS channel layer. The FeFET device also includes a 2D contact layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contact layer has a second doping type different from the first doping type.

[0004] In other embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an interconnect structure disposed above a substrate. The interconnect structure includes a lower metal layer and an upper metal layer stacked above the lower metal layer. A FeFET device is inserted between the lower metal layer and the upper metal layer. The FeFET device includes a gate electrode disposed above the lower metal layer, a ferroelectric layer disposed above the gate electrode, and an oxide semiconductor (OS) channel layer disposed above the ferroelectric layer. The FeFET device also includes a pair of source / drain regions disposed on opposite sides of the OS channel layer and a 2D contact layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contact layer has a second doping type different from the first doping type.

[0005] In other embodiments, the present disclosure relates to a method for forming a FeFET device. The method includes forming a lower metal layer of an interconnect structure above a substrate, and forming a stack of gate electrodes, ferroelectric layers, and oxide semiconductor (OS) channel layers stacked on each other above the lower metal layer. The method also includes forming a 2D contact layer along the OS channel layer. The OS channel layer has a first doping type, and the 2D contact layer has a second doping type different from the first doping type. The method also includes forming a pair of source / drain regions on opposite sides of the OS channel layer, and forming an upper metal layer of an interconnect structure having metal vias contacting the pair of source / drain regions.

[0006] Embodiments of the present application provide two-dimensional (2D) materials for oxide semiconductor (OS) ferroelectric field effect transistor (FEFET) devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. Indeed, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 Cross-sectional views of some embodiments of ferroelectric field effect transistor (FeFET) devices having a two-dimensional (2D) contact layer disposed along an oxide semiconductor (OS) channel layer are shown.

[0009] Figure 2 Cross-sectional views of some additional embodiments of FeFET devices with a 2D contact layer disposed along an OS channel layer are shown.

[0010] Figure 3-Figure 6 Cross-sectional views of some additional embodiments of FeFET devices with a 2D contact layer disposed along an OS channel layer are shown.

[0011] Figure 7 Schematic diagram showing some embodiments of a stack of 2D contact layers and OS channel layers for a FeFET device.

[0012] Figures 8A-8C Schematic diagrams illustrating some embodiments of the operation of a FeFET device having a 2D contact layer disposed along an OS channel layer.

[0013] Figure 9-Figure 26 Cross-sectional views illustrating some embodiments of methods of forming an integrated chip including a FeFET device having a 2D contact layer disposed along an OS channel layer.

[0014] Figure 27 Flowchart illustrating some embodiments of a method of forming an integrated chip including a FeFET device having a 2D contact layer disposed along an OS channel layer. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numbers and / or letters in various examples. This repetition is merely for simplicity and clarity and does not, in itself, represent a relationship between the various embodiments and / or configurations discussed. However, the components described in one figure may be incorporated into the embodiments described in association with another figure as additional embodiments when applicable, and may not be repeated for simplicity reasons.

[0016] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0017] Ferroelectric field-effect transistors (FeFETs) are used in advanced electronic devices, including logic and memory components, due to their low operating power. During operation of a FeFET device, applying a gate voltage to the gate electrode generates an electric field that causes a dipole moment to form within the ferroelectric material. Depending on the value of the gate voltage, the direction of the dipole moment (i.e., polarization) can be in one of two opposite directions. Since the threshold voltage of a FeFET device (e.g., the minimum gate-source voltage that forms a conductive path between the source and drain regions) depends on the polarization within the ferroelectric material, the different polarizations effectively separate the threshold voltage of the FeFET device into two different values ​​corresponding to different data states.

[0018] For example, in a p-type FeFET (e.g., a FeFET device that uses holes as the majority carriers between the source and drain regions and has an n-type doped channel / substrate region), a positive gate voltage creates an electric field that imparts a first polarization to the ferroelectric material toward the channel region and causes electrons to accumulate within the channel region. The electrons enhance the first polarization within the ferroelectric material and impart a first threshold voltage to the FeFET device, corresponding to a first data state (e.g., a logic "0"). Alternatively, a negative gate voltage creates an electric field that imparts a second polarization to the ferroelectric material toward the gate electrode and causes holes to accumulate within the channel region. The holes enhance the second polarization within the ferroelectric material and impart a second threshold voltage to the FeFET device, corresponding to a second data state (e.g., a logic "0"). The difference between the first and second thresholds defines the memory window of the FeFET device (e.g., the difference in threshold voltages corresponding to the first and second data states). The permanent electric field polarization in the ferroelectric material enables the FeFET device to retain its data state in the absence of any electrical bias. Therefore, FeFET devices can be used as unit cells for random access nonvolatile memories.

[0019] One direction to advance more flexible integration schemes is to insert memory into interconnect structures such as back-end-of-line (BEOL) processes to expand the application of non-volatile logic memory solutions. In this case, low-leakage oxide semiconductor (OS) materials can be used in the channel region of FeFET non-volatile memories. However, OS materials lack a large number of different types of charge carriers (holes and electrons). For example, when a positive gate voltage is applied to the gate electrode, the channel region including the n-type OS channel layer can accumulate electrons to enhance the first polarization within the ferroelectric material, but when a negative gate voltage is applied to the gate electrode, the n-type OS channel layer has almost no positive charge and, therefore, cannot accumulate holes within the ferroelectric material to enhance the second polarization opposite to the first polarization. When the negative gate voltage is removed, the ferroelectric material will revert to the remanent polarization and result in unsuccessful data switching and state retention.

[0020] In view of the above, in some embodiments, the present disclosure relates to a FeFET device including a two-dimensional (2D) contact layer disposed along an OS channel layer and an associated manufacturing method. The FeFET device can be used as a unit cell of a non-volatile memory. The OS channel layer enhances the first polarization state of the ferroelectric material. The 2D contact layer provides supplementary charge carriers, thereby enhancing the second polarization state of the ferroelectric material. Therefore, by enhancing the OS channel layer and the 2D contact layer, the FeFET device can successfully achieve data switching and state retention of two data states. In some embodiments, the FeFET device includes a gate electrode disposed along a first side of the ferroelectric layer and an OS channel layer disposed along a second side of the ferroelectric layer opposite to the first side. The OS channel layer has a first doping type (e.g., an n-type semiconductor). A pair of source / drain regions are disposed on opposite sides of the OS channel layer. The 2D contact layer is disposed along the OS channel layer and has a second doping type (e.g., a p-type semiconductor) different from the first doping type. During operation, a write voltage is applied to the gate electrode to generate an electric field to polarize the ferroelectric layer. When the electric field causes the ferroelectric layer to have a first polarization along a first direction, the first type of charge carriers accumulate in the OS channel layer and enhance and / or strengthen the first polarization. When the electric field causes the ferroelectric layer to have a second polarization in a second direction, the second type of charge carriers in the 2D contact layer will act to enhance and / or strengthen the second polarization. Therefore, by arranging the 2D contact layer along the OS channel layer, the polarization switching of the ferroelectric layer between different data states is further enhanced and / or strengthened. In some embodiments, the 2D contact layer is at least partially heavily doped and is arranged between the source / drain region and the OS channel layer, thereby also helping to reduce the contact resistance of the source / drain region.

[0021] Figure 1A cross-sectional view of a FeFET device 100 according to some embodiments is shown. The FeFET device 100 is disposed over a substrate 122 and can be incorporated into an interconnect structure 120. The FeFET device 100 includes a ferroelectric layer 104 having a first side 104a and a second side 104b. An OS channel layer 106 is disposed along the first side 104a of the ferroelectric layer 104. A gate electrode 102 is disposed along the second side 104b of the ferroelectric layer 104. A pair of source / drain regions 108, 110 are disposed at opposite ends of the OS channel layer 106. A 2D contact layer 112 is disposed along the OS channel layer 106. In some embodiments, the OS channel layer 106 is of a first doping type (e.g., n-type), while the 2D contact layer 112 is of a second doping type (e.g., p-type). The OS channel layer 106 provides a first type (e.g., electron) of carrier charge to enhance the first polarization state of the ferroelectric layer 104, thereby helping to achieve successful data programming and state retention of the first data state (e.g., data state "1"). The 2D contact layer 112 provides a second type (e.g., hole) of carrier charge to supplement the carrier charge provided by the OS channel layer 106, thereby enhancing the second polarization state of the ferroelectric layer 104 to help achieve successful data programming and state retention of the second data state (e.g., data state "0"). Figures 8A-8C Examples of associated more detailed operations.

[0022] In some embodiments, the 2D contact layer 112 is disposed on the upper surface of the OS channel layer 106. In some embodiments, the 2D contact layer 112 is disposed between and in contact with the bottom surfaces of the pair of source / drain regions 108, 110 and the upper surface of the OS channel layer 106. Therefore, the 2D contact layer 112 also reduces the contact resistance between the source / drain regions 108, 110 and the OS channel layer 106. In some embodiments, the 2D contact layer 112 covers the bottom and sidewall surfaces of the pair of source / drain regions 108, 110 and is not present in the intermediate region of the OS channel layer 106 between the pair of source / drain regions 108, 110.

[0023] In some embodiments, the ferroelectric layer 104 is or is composed of a material having a dielectric crystal that exhibits an electric polarization with a direction that can be controlled by an electric field. For example, in some embodiments, the ferroelectric layer 104 may include hafnium oxide (HfO2), hafnium zinc oxide (HfZnO2), or the like. In some embodiments, the OS channel layer 106 is or is composed of an n-type oxide semiconductor material, such as indium gallium zinc oxide (IGZO) or gallium oxide (Ga2O3), which has more free electrons than holes. In some embodiments, the 2D contact layer 112 is or is composed of a single layer or multilayer of a two-dimensional material, which is a crystalline solid composed of a single layer of atoms. Two-dimensional materials are derived from a single element or a compound of two or more elements. For example, the 2D contact layer 112 may include a p-type single element two-dimensional material (such as graphene, borophene) or a composite two-dimensional material (such as molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), molybdenum ditelluride (MoTe2), or other transition metal dichalcogenides (TMDs) with more holes than free electrons). In other embodiments, the OS channel layer 106 is or consists of a p-type doped semiconductor or oxide semiconductor, and the 2D contact layer 112 is or consists of an n-type doped material. Using a two-dimensional material as the 2D contact layer 112 is beneficial because the work function of the two-dimensional material can be precisely designed to obtain the desired n- or p-type material and can be obtained by direct growth under specific conditions or through an implantation process.

[0024] In some embodiments, the OS channel layer 106 may have a thickness of about 1×10 16 at / cm 3 to about 1×10 18 at / cm 3 The 2D contact layer 112 may have a doping concentration in the range of about 1×10 18 at / cm 3 and about 1×10 21 at / cm 3 The source / drain regions 108, 110 may have a doping concentration in the range of about 1×10 18 at / cm 3 and about 1×10 20 at / cm 3In some embodiments, the ferroelectric layer 104 may have a thickness in a range between about 1 nanometer (nm) and about 15 nm. The source / drain regions 108, 110 may have a thickness in a range between about 10 nm and about 50 nm, respectively. In some embodiments, the OS channel layer 106 may have a thickness in a range between about 3 nm and about 20 nm. In some embodiments, the 2D contact layer 112 may have a thickness in a range between about 0.1 nm and about 5 nm. The thickness and / or doping concentration of the 2D contact layer 112 and / or the OS channel layer 106 provide good switching modulation of the FeFET device and mitigate the channel current flowing through the 2D contact layer 112.

[0025] In some embodiments, the interconnect structure 120 includes a lower metal layer 124 disposed below the FeFET device 100, an upper metal layer 128 disposed above the FeFET device 100, and a dielectric layer 126 surrounding the FeFET device 100. In some embodiments, the gate electrode 102 directly contacts or is electrically coupled to a metal line of the lower metal layer 124. The gate electrode 102 is or is composed of a conductive material such as titanium, titanium nitride, tungsten, tungsten nitride, copper, gold, zinc, aluminum, etc. The ferroelectric layer 104 can be disposed above or directly on the gate electrode 102. The OS channel layer 106 can be disposed above or directly on the ferroelectric layer 104. In some embodiments, the source / drain regions 108 and 110 directly contact or are electrically coupled to corresponding metal lines of the upper metal layer 128 through contacts, vias, and / or other intermediate metal lines. The source / drain regions 108, 110 are or consist of a metal, such as titanium, titanium nitride, tungsten, tungsten nitride, copper, gold, zinc, aluminum, or the like. The sidewalls of the source / drain regions 108, 110 may be separated from the dielectric layer 126 by a 2D contact layer 112. The dielectric layer 126 is or consists of a stack of one or more dielectric materials, such as an oxide (e.g., silicon oxide, silicon dioxide, or the like), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like. Alternatively, the FeFET device 100 may be a front-end-of-line (FEOL) transistor or a memory cell disposed on the substrate 122. The source / drain regions 108, 110 may be electrically coupled to a bit line and a source line of a memory array, and the gate electrode 102 may be electrically coupled to a word line of the memory array.

[0026] Figure 2 1 shows a cross-sectional view of a FeFET device 100 according to some additional embodiments. Figure 1 Some components of the FeFET device 100 shown in FIG are incorporated herein and are not repeated. Figure 2As further shown, in some embodiments, a 2D contact layer 112 is disposed between and in contact with the OS channel layer 106 and the side surfaces of the source / drain regions 108, 110. The 2D contact layer 112 may cover the top surface of the OS channel layer 106. The 2D contact 112 may not be present on the sidewalls of the source / drain regions 108, 110. In some embodiments, the end portions 112e of the 2D contact layer 112 below the source / drain regions 108, 110 are more heavily doped than the middle portion 112m of the 2D contact layer 112 between the source / drain regions 108, 110. Thus, the end portions 112e of the 2D contact layer 112 help reduce the source / drain contact resistance, while the middle portion 112m of the 2D contact layer is resistive and does not short-circuit the OS channel layer 106. For example, the end portions 112e of the 2D contact layer 112 may have a resistance of about 1×10 18 at / cm 3 and about 1×10 21 at / cm 3 The doping concentration of the middle portion 112m of the 2D contact layer may be in the range of about 1×10 16 at / cm 3 and about 1×10 18 at / cm 3 The doping concentration is within the range between .

[0027] In some alternative embodiments not shown in the figures, the 2D contact layer 112 is disposed between the OS channel layer 106 and the ferroelectric layer 104. In this case, the 2D contact layer 112 may have a thickness of about 1×10 16 at / cm 3 and about 1×10 18 at / cm 3 The doping concentration is within the range between .

[0028] It should be understood that although Figure 1 and Figure 2 Some embodiments of the FeFET device 100 are provided including a 2D contact layer 112 disposed along the OS channel layer 106, but the FeFET device structure is not limited to Figure 1 and Figure 2 The structure is shown with respect to the positions of the gate electrode 102 and the source / drain regions 108 , 110 . Figure 3-Figure 6 Additional examples of various device architectures with different locations of the gate electrode 102 and source / drain regions 108, 110 are provided. Other device architectures (e.g., FinFET, GAA (gate all around), nanostructures, nanosheets, nanowires, etc.) with different shapes and locations of the gate electrode and source / drain regions are also applicable. For simplicity, contacts and interconnect structures are not shown. Figure 3-Figure 6, but the FeFET device 100 may be a front-end-of-line (FEOL) transistor or memory cell disposed on the substrate 122 , or a transistor or memory cell of a random access memory inserted into a back-end-of-line (BEOL) interconnect structure.

[0029] like Figure 3 As shown, the FeFET device 100 can be a top-gate device, in which the gate electrode 102 is at least partially laterally interposed between the source / drain regions 108 and 110. In some embodiments, the ferroelectric layer 104 is disposed between opposing sidewalls of the source / drain regions 108 and 110. The ferroelectric layer 104 can directly contact opposing sidewalls of the source / drain regions 108 and 110. In some embodiments, a 2D contact layer 112 is disposed between and in contact with the ferroelectric layer 104 and the OS channel layer 106. The 2D contact layer 112 can cover side surfaces of the ferroelectric layer 104 and the OS channel layer 106. The source / drain regions 108 and 110 can have bottom surfaces covered by the 2D contact layer 112. In some embodiments, an end portion 112e of the 2D contact layer 112 below the source / drain regions 108 and 110 is more heavily doped than a middle portion 112m of the 2D contact layer 112 between the source / drain regions 108 and 110. Thus, the end portions 112e of the 2D contact layer 112 contribute to reducing the source / drain contact resistance, while the middle portion 112m of the 2D contact layer is resistive and does not short the OS channel layer 106. In some embodiments, the end portions 112e of the 2D contact layer 112 below the source / drain regions 108, 110 are more heavily doped than the middle portion 112m of the 2D contact layer 112 below the ferroelectric layer 104. Thus, the end portions 112e of the 2D contact layer 112 contribute to reducing the source / drain contact resistance, while the middle portion 112m of the 2D contact layer is resistive and does not short the OS channel layer 106. For example, the end portions 112e of the 2D contact layer 112 may have a resistance of about 1×10 18 at / cm 3 and about 1×10 21 at / cm 3 The doping concentration of the middle portion 112m of the 2D contact layer may be in the range of about 1×10 16 at / cm 3 and about 1×10 18 at / cm 3 The doping concentration is within the range between .

[0030] like Figure 4As shown, the FeFET device 100 can have source / drain regions 108, 110, which include a lower lateral portion and an upper lateral portion connected by a vertical portion. The vertical portions of the source / drain regions 108, 110 can be disposed along the sidewalls of the OS channel layer 106, and the upper portions of the source / drain regions 108, 110 can be disposed along the upper surface of the OS channel layer 106. The 2D contact layer 112 can be conformally disposed between and in contact with the lower surfaces of the source / drain regions 108, 110 and the sidewalls and upper surface of the OS channel layer 106. The ferroelectric layer 104 can be disposed in the middle portion of the upper surface of the OS channel layer 106 that is not covered by the 2D contact layer 112 and / or the source / drain regions 108, 110. The ferroelectric layer 104 may contact the 2D contact layer 112 and sidewalls of the source / drain regions 108, 110 and may further extend above the upper surfaces of the source / drain regions 108, 110. The gate electrode 102 may be disposed above the ferroelectric layer 104 and may also extend laterally above the source / drain regions 108, 110.

[0031] like Figure 5 As shown, the 2D contact layer 112 may be conformally disposed along and in contact with the lower and upper side surfaces of the ferroelectric layer 104 connected by the vertical sidewalls of the ferroelectric layer 104. The OS channel layer 106 may be disposed on the ferroelectric layer 104 and have sidewalls that contact the 2D contact layer 112 and the sidewalls of the source / drain regions 108, 110. The OS channel layer 106 may further extend above the upper surfaces of the source / drain regions 108, 110.

[0032] like Figure 6 As shown, the FeFET device 100 may have additional device components, such as dual gate electrodes 102-1 and 102-2 disposed on opposite sides of the OS channel layer 106. A first ferroelectric layer 104-1 and a second ferroelectric layer 104-2 may be disposed between and separate the OS channel layer 106 and the dual gate electrodes 102-1 and 102-2, respectively. A 2D contact layer 112 may be conformally disposed along and in contact with the lower side of the first ferroelectric layer 104-1 and the upper side of the OS channel layer 106, which are connected by the vertical sidewalls of the OS channel layer 106.

[0033] Figure 7A schematic diagram illustrating a stack of 2D contact layers 112a, 112b, ..., 112n and OS channel layers 106a, 106b, ..., 106n of a FeFET device according to some embodiments. As an alternative to having a 2D contact layer disposed along one side of the OS channel layer, one or more 2D contact layers may be disposed on both sides of the OS channel layer or inserted within the stack of OS channel layers. The 2D contact layer provides a complementary carrier charge (e.g., holes) different from the majority carrier charge (e.g., electrons) of the OS channel layer to facilitate successful data programming and state retention of two data states (e.g., data state "0" and data state "1").

[0034] Figure 8A-8B A schematic diagram illustrating the operation of a p-type FeFET device including a 2D contact layer 112 disposed along an OS channel layer 106 according to some embodiments is shown. The p-type FeFET device uses holes as majority carriers flowing between source / drain regions 108, 110 and includes an n-type doped channel / substrate region. The p-type FeFET device includes a ferroelectric layer 104 disposed between a gate electrode 102 of an n-type oxide semiconductor and an OS channel layer 106. The source / drain regions 108, 110 are disposed at opposite ends of the OS channel layer 106. The 2D contact layer 112 is disposed along the OS channel layer 106 and includes a p-type two-dimensional material. Although the device structure of the back-gate FeFET structure (similar to the 2D contact layer covering the bottom and sidewall surfaces of the source / drain regions 108, 110) is Figure 1 structure) for Figure 8A-8B However, it is understood that other FeFET structures (such as those similar to Figure 2-Figure 6 It should also be understood that n-type FeFET structures also have similar operating principles, but with the opposite charge type.

[0035] like Figure 8A As shown in the cross-sectional diagram, the positive gate voltage V G Applied to the gate electrode 102. Positive gate voltage V G Positive charge carriers 202 (i.e., holes) are accumulated on the surface of the gate electrode 102 facing the ferroelectric layer 104. The positive charge carriers 202 form an electric field that polarizes the ferroelectric layer 104 to the first polarization 204. The electric field further causes negative charge carriers 206 to accumulate in the OS channel layer 106. The negative charge carriers 206 enhance the first polarization 204 in the ferroelectric layer 104, thereby providing a first threshold voltage for the FeFET device. Even when the positive gate voltage V G When removed, the first polarization 204 remains within the ferroelectric layer 104, as does the first threshold voltage. Thus, the p-type FeFET device is programmed to the first data state (eg, logic "1").

[0036] like Figure 8B As shown in the cross-sectional diagram, the negative gate voltage -V G Applied to the gate electrode 102. Negative gate voltage -V G Negative charge carriers 216 are accumulated along the surface of the gate electrode 102 facing the ferroelectric layer 104. The negative charge carriers 216 form an electric field that polarizes the ferroelectric layer 104 to a second polarization 218. The n-type oxide semiconductor material of the OS channel layer 106 lacks positive charge carriers and therefore cannot fully enhance the second polarization 218 within the ferroelectric layer 104. Without the 2D contact layer 112, when the negative gate voltage -V G When removed, the second polarization 218 is not effectively maintained.

[0037] In response to the second polarization 218, the 2D contact layer 112 provides positive charge carriers 220 that accumulate along the bottom of the 2D contact layer 112 facing the OS channel layer 106. The positive charge carriers 220 enhance the second polarization 218 within the ferroelectric layer 104, thereby maintaining the positive charge carriers 220 even after the negative gate voltage -V is removed. G The p-type FeFET device is programmed to the second data state (eg, logic “0”).

[0038] The polarization state of the ferroelectric layer 104 can be measured by the conductance in the channel of the p-type FeFET device. During a read operation, a drain voltage is applied between the source / drain regions 108, 110. A read gate voltage is applied to the gate electrode 102. The read gate voltage can be between a first threshold voltage for the first data state and a second threshold voltage for the second data state, such that the read gate voltage turns on the p-type FeFET in one of the data states but not in the other. Therefore, the data state can be read by the drain current flowing between the source / drain regions 108, 110.

[0039] Figure 8C A schematic diagram showing an exemplary Id-Vg programming curve for a FeFET device is shown. Figure 8A The positive gate voltage V associated with the first programming process G When the ferroelectric layer of the FeFET device has the first polarization, the FeFET device will have a first threshold voltage. Even if the positive gate voltage V is removed G , the negative charge carriers in the OS channel layer also enhance the first polarization in the ferroelectric layer. Therefore, the FeFET device stores the first data state (e.g., logic "1"). Line 236 shows the response to the above and Figure 8B The negative gate voltage of the associated second programming process or the erase process of the first programming process is -V GWhen the ferroelectric layer of the FeFET device has a second polarization, the FeFET device will have a second threshold voltage. Even if the negative gate voltage -V is removed G , the positive charge carriers in the 2D contact layer also enhance the second polarization in the ferroelectric layer. Therefore, the FeFET device erases the first data state or stores the second data state (e.g., logic "0"). As shown by line 234, for comparison, for a FeFET device without a 2D contact layer provided along the OS channel layer, in response to a negative gate voltage -V G The drain current may not be able to achieve or maintain the second polarization in the ferroelectric layer. As a result, the FeFET device may not be able to erase the first state or program the second state.

[0040] Figures 9-16 Cross-sectional views 900-1600 of some embodiments of methods for forming a back-gate FeFET device having a 2D contact layer disposed along an OS channel layer are shown. Figures 9-16 It is method-dependent, but it should be understood that Figures 9-16 The disclosed structure is not limited to the present method, but can exist independently as a structure independent of the present method.

[0041] like Figure 9 As shown in cross-sectional view 900 of FIG. , a substrate 122 is provided. In various embodiments, substrate 122 may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies located on the wafer, as well as any other type of semiconductor and / or epitaxial layers associated therewith. In some embodiments, various FEOL devices are formed in substrate 122, followed by the formation of middle-of-line (MOL) contacts and one or more metal layers of a BEOL interconnect structure. For example, metal layers designated M0, M1, M2, etc., may be formed above the FEOL devices on substrate 122. In some embodiments, a lower metal layer 124 and a first dielectric layer 126a surrounding the lower metal layer 124 are formed above substrate 122. In some embodiments, the lower metal layer 124 may be formed using a damascene process (e.g., a single damascene process or a dual damascene process), wherein a patterning process is performed to form trenches and / or vias in the first dielectric layer 126a, followed by a metal fill process. The lower metal layer 124 may be one of the metal layers of the BEOL interconnect structure.

[0042] like Figure 10As shown in cross-sectional view 1000 of FIG, a gate electrode 102 and a second dielectric layer 126b surrounding the gate electrode 102 are formed over the substrate 122. In some embodiments, the gate electrode 102 is formed directly on the metal line of the lower metal layer 124. In various embodiments, the gate electrode 102 can be formed by one or more deposition processes (e.g., an ALD process, a CVD process, a PE-CVD process, a PVD process, etc.) followed by a patterning process. The gate electrode 102 can include one or more conductive materials. In some embodiments, the one or more conductive materials can include and / or be metals such as titanium, titanium nitride, tungsten, tungsten nitride, copper, gold, zinc, aluminum, etc. A deposition process is then performed to form the second dielectric layer 126b, followed by a planarization process to remove excess portions of the second dielectric layer 126b over the gate electrode 102. Alternatively, the gate electrode 102 can also be formed by a damascene process (e.g., a single damascene process or a dual damascene process), wherein a patterning process is performed to form trenches and / or vias in the second dielectric layer 126b, followed by a metal filling process.

[0043] like Figure 11As shown in the cross-sectional view 1100 of FIG, a stack of device layers is formed on the gate electrode 102. In some embodiments, a ferroelectric layer 104 may be formed above the gate electrode 102, and an OS channel layer 106 may be formed above the ferroelectric layer 104. The ferroelectric layer 104 and the OS channel layer 106 may be formed by a deposition process and a subsequent patterning process. The ferroelectric layer 104 and the OS channel layer 106 may be formed to have sidewalls that are aligned with each other and further aligned with the sidewalls of the gate electrode 102. In some embodiments, the ferroelectric layer 104 may be formed of one or more ferroelectric materials, such as hafnium oxide, hafnium zinc oxide, etc. In various embodiments, the ferroelectric layer 104 may be formed by one or more deposition processes (e.g., ALD process, CVD process, PE-CVD process, PVD process, etc.). The OS channel layer 106 may be formed of one or more oxide semiconductor materials having a first type semiconductor (e.g., an n-type semiconductor with electrons as majority carriers or a p-type semiconductor with holes as majority carriers). In some embodiments, the one or more oxide semiconductor materials may include one or more n-type oxide semiconductors, such as indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium tungsten oxide (IWO), indium tungsten zinc oxide (IWZO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In other embodiments, the one or more oxide semiconductor materials may include one or more p-type oxide semiconductors, such as tin oxide (SnO), nickel oxide (NiO), copper oxide (Cu2O), NaNbO2, etc. In various embodiments, the OS channel layer 106 may be formed by one or more deposition processes (e.g., ALD process, CVD process, PE-CVD process, PVD process, etc.). In some embodiments, the ferroelectric layer 104, the OS channel layer 106, and the gate electrode 102 are sequentially deposited and then patterned at one time, instead of Figure 10 and Figure 11 , where the ferroelectric layer 104 and the OS channel layer 106 are shown as being formed after the gate electrode 102 is formed.

[0044] like Figure 12 As shown in the cross-sectional view 1200 of FIG, a third dielectric layer 126c is formed over the stack of device layers. For example, the third dielectric layer 126c is formed over the second dielectric layer 126b and extends along the upper surface and sidewalls of the stack of device layers. In various embodiments, the third dielectric layer 126c can be formed by one or more deposition processes (e.g., an ALD process, a CVD process, a PE-CVD process, a PVD process, etc.) followed by a planarization process. Although not shown in the figure, an additional isolation process can be performed before forming the third dielectric layer 126c surrounding the stack of device layers.

[0045] like Figure 13As shown in cross-sectional view 1300 of FIG. 1 , source / drain contact holes 1302 a and 1302 b are formed through the third dielectric layer 126 c to reach the stack of device layers. In some embodiments, the source / drain contact holes 1302 a and 1302 b expose the upper surface of the OS channel layer 106. The source / drain contact holes 1302 a and 1302 b can be formed by a patterning process that is performed to pattern the third dielectric layer 126 c by selectively exposing the third dielectric layer 126 c to an etchant through the masking layer 1304. The etchant can include a dry etchant (e.g., having a fluorine chemistry, a chlorine chemistry, etc.).

[0046] like Figure 14 As shown in cross-sectional view 1400 , in some embodiments, a 2D contact layer 112 is formed on the exposed surface of the stack of device layers. In some embodiments, the 2D contact layer 112 is conformally formed along the upper surface of the OS channel layer 106 and extends along the sidewalls and sides of the third dielectric layer 126 c. The 2D contact layer 112 can be formed of a single layer or multiple layers of a two-dimensional material, which is a crystalline solid composed of a single layer of atoms. Two-dimensional materials are derived from a single element or a compound of two or more elements. The 2D contact layer 112 has a second doping type that is different from the first doping type of the OS channel layer 106. For example, the 2D contact layer 112 can include a p-type single-element two-dimensional material (such as graphene, borophene) or a composite two-dimensional material (such as MoS2, MoSe2, MoTe2, or other transition metal dichalcogenides (TMDs) having more holes than free electrons). In other embodiments, the OS channel layer 106 is or is formed of a p-type doped semiconductor or oxide semiconductor, while the 2D contact layer 112 is or is formed of an n-type doped material. In some embodiments, a 2D contact layer 112 is conformally formed on the exposed surface of the stack of device layers using a deposition technique (e.g., an ALD process, a CVD process, a PE-CVD process, etc.). Alternatively, the 2D contact layer 112 can be formed on a sacrificial substrate and then transferred to the exposed surface of the stack of device layers. In some embodiments, the 2D contact layer 112 can be inherently doped, while in other embodiments, the 2D contact layer 112 can be doped through an implantation process.

[0047] In some embodiments, instead of Figure 13-14A 2D contact layer 112 is formed in the source / drain contact holes 1302a, 1302b shown. The 2D contact layer 112 can be formed on the OS channel layer 106 before forming the third dielectric layer 126c. The 2D contact layer 112 can be deposited or transferred from a sacrificial substrate on the OS channel layer 106 after the deposition of the OS channel layer 106 and before the patterning process of the OS channel layer 106. The 2D contact layer 112 can then be patterned together with the stack of device layers. The 2D contact layer 112 can be formed to cover the entire top surface of the OS channel layer 106, as shown in FIG. Figure 2 shown.

[0048] like Figure 15 As shown in the cross-sectional view 1500, a conductive material is formed in the source / drain contact holes 1302a and 1302b (see Figure 14 In some embodiments, the conductive material may include a metal such as copper, tungsten, cobalt, or the like. In some embodiments, the conductive material may be deposited by one or more of a deposition process and a plating process. In some embodiments, a deposition process may be used to form a seed layer of the conductive material, and then an electroplating process may be used to fill the source / drain contact holes 1302 a and 1302 b. In some embodiments, after forming the conductive material, a planarization process may be performed to remove excess conductive material from above the third dielectric layer 126 c and define the source / drain regions 108 and 110.

[0049] like Figure 16 As shown in cross-sectional view 1600 of FIG, a fourth dielectric layer 126 d and an upper metal layer 128 are formed over the stack of device layers. Metal layers 124 and 128 together with dielectric layers 126 a, 126 b, 126 c, and 126 d form an interconnect structure 120. Dielectric layers 126 a, 126 b, 126 c, and 126 d can each be formed of one or more of the following: silicon dioxide, silicon nitride, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), a porous dielectric material, and the like. Although not shown in the figure, dielectric layers 126 a, 126 b, 126 c, and 126 d can be separated by one or more etch stop layers. One or more etch stop layers may be formed of a carbide (e.g., silicon carbide, silicon oxycarbide, etc.), a nitride (e.g., silicon nitride, silicon oxynitride, etc.), or the like. Dielectric layers 126a, 126b, 126c, and 126d are shown as examples and may be formed as fewer or more dielectric layers. In some embodiments, upper metal layer 128 is formed to be electrically coupled to source / drain regions 108 and 110, either directly or through conductive contacts and / or additional metal layers. In some embodiments, upper metal layer 128 may be formed by a damascene process (e.g., a single damascene process or a dual damascene process).

[0050] Figures 17-26 Cross-sectional views 1700-2600 of some embodiments of methods for forming a FeFET device having a 2D contact layer disposed along an OS channel layer are shown. Figures 17-26 It is method-dependent, but it should be understood that Figures 17-26 The disclosed structure is not limited to the present method, but can exist independently as a structure independent of the present method.

[0051] like Figure 17 As shown in cross-sectional view 1700 of FIG. , a substrate 122 is provided. In various embodiments, substrate 122 may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies located on the wafer, as well as any other type of semiconductor and / or epitaxial layers associated therewith. In some embodiments, various FEOL devices are formed in substrate 122, followed by the formation of middle-of-line (MOL) contacts and one or more metal layers of a BEOL interconnect structure. For example, metal layers designated M0, M1, M2, etc., may be formed above the FEOL devices on substrate 122. In some embodiments, a lower metal layer 124 and a first dielectric layer 126a surrounding the lower metal layer 124 are formed above substrate 122. In some embodiments, the lower metal layer 124 may be formed using a damascene process (e.g., a single damascene process or a dual damascene process), wherein a patterning process is performed to form trenches and / or vias in the first dielectric layer 126a, followed by a metal fill process. The lower metal layer 124 may be one of the metal layers of the BEOL interconnect structure.

[0052] like Figures 18-23 As shown in cross-sectional views 1800-2300 of FIG. 1 , a stack of device layers is formed over the lower metal layer 124 through a series of deposition and patterning processes. The stack of device layers may include an OS channel layer 106, a 2D contact layer 112, and a ferroelectric layer 104. The deposition and patterning processes may be performed in various ways, as exemplified in more detail below.

[0053] like Figure 18 As shown, in some embodiments, an OS channel precursor layer 106′ is formed over the lower metal layer 124. The OS channel precursor layer 106′ can be formed by one or more deposition processes (e.g., an ALD process, a CVD process, a PE-CVD process, a PVD process, etc.) using one or more oxide semiconductor materials having a first type semiconductor (e.g., an n-type semiconductor having electrons as majority carriers) such as indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium tungsten oxide (IWO), indium tungsten zinc oxide (IWZO), indium zinc oxide (IZO), zinc oxide (ZnO), etc.

[0054] like Figure 19 As shown, in some embodiments, the 2D material contact precursor layer 112' is formed above or directly on the OS channel precursor layer 106'. In some embodiments, the 2D material contact precursor layer 112' is conformally formed on the entire top surface of the OS channel precursor layer 106' using a single layer or multiple layers of a two-dimensional material (which is a crystalline solid composed of a single layer of atoms). In some embodiments, the 2D material contact precursor layer 112' is formed using a deposition technique (e.g., an ALD process, a CVD process, a PE-CVD process, an MBE process, etc.). Alternatively, the 2D material contact precursor layer 112' can be formed on a sacrificial substrate and then transferred to the OS channel precursor layer 106'. In some embodiments, the 2D material contact precursor layer 112' is inherently doped, while in other embodiments, the 2D material contact precursor layer 112' is doped by implantation. The two-dimensional material is derived from a single element or a compound of two or more elements. The 2D material contact precursor layer 112' has a second doping type that is different from the first doping type of the OS channel precursor layer 106'. For example, the 2D contact layer 112 may include a p-type single element two-dimensional material (such as graphene, borophene) or a composite two-dimensional material (such as MoS2, MoSe2, MoTe2, or other transition metal dichalcogenides (TMDs) having more holes than free electrons). In other embodiments, the OS channel precursor layer 106' is or is formed of a p-type doped semiconductor or oxide semiconductor, while the 2D material contact precursor layer 112' is or is formed of an n-type doped material.

[0055] like Figure 20 As shown, in some embodiments, the ferroelectric precursor layer 104' is formed above or directly on the 2D material contact precursor layer 112'. The ferroelectric precursor layer 104' can be formed using one or more ferroelectric materials (such as hafnium oxide, hafnium zinc oxide, etc.) through one or more deposition processes (e.g., ALD process, CVD process, PE-CVD process, PVD process, etc.).

[0056] like Figure 21 As shown, in some embodiments, the ferroelectric precursor layer 104', the 2D material contact precursor layer 112', and the OS channel precursor layer 106' are patterned by a first patterning process according to the mask layer 2102 to form the ferroelectric layer 104, the 2D contact layer 112, and the OS channel layer 106 having sidewalls aligned with each other. The first patterning process may include a series of dry and / or wet etching processes that remove the ferroelectric precursor layer 104', the 2D material contact precursor layer 112', and the OS channel precursor layer 106' (see Figure 20 ) is the excess portion not covered by the masking layer 2102.

[0057] like Figure 22 As shown, in some embodiments, a second dielectric layer 126b is formed over the first dielectric layer 126a and surrounds and over the ferroelectric layer 104, the 2D contact layer 112, and the OS channel layer 106. In various embodiments, the second dielectric layer 126b can be formed by one or more deposition processes (e.g., an ALD process, a CVD process, a PE-CVD process, a PVD process, etc.) followed by a planarization process. Prior to forming the second dielectric layer 126b surrounding and over the ferroelectric layer 104, the 2D contact layer 112, and the OS channel layer 106, an additional isolation process can be performed.

[0058] like Figure 23 As shown, in some embodiments, source / drain contact holes 2302a and 2302b are formed through the second dielectric layer 126b. In some embodiments, the source / drain contact holes 2302a and 2302b further extend through the ferroelectric layer 104 and are exposed at opposite sidewalls of the ferroelectric layer 104. The source / drain contact holes 2302a and 2302b can be formed by a patterning process that is performed to pattern the second dielectric layer 126b and the ferroelectric layer 104 according to the masking layer 2304 using a dry etching and / or wet etching process. The source / drain contact holes 2302a and 2302b can reach the 2D contact layer 112. In some embodiments, a doping process and / or an annealing process is performed on the exposed portion of the 2D contact layer 112 in the source / drain contact holes 2302 a and 2302 b to locally increase the doping concentration of the 2D contact layer 112. This causes the 2D contact layer 112 in the source / drain contact holes 2302 a and 2302 b to be more heavily doped compared to the middle region below the ferroelectric layer 104, thereby reducing the source / drain contact resistance. For example, a nitrogen annealing process may be performed on the 2D contact layer 112 in the source / drain contact holes 2302 a and 2302 b.

[0059] like Figure 24 As shown in the cross-sectional view 2400, a conductive material is formed in the source / drain contact holes 2302a and 2302b (see Figure 23 In some embodiments, the conductive material may include a metal such as copper, tungsten, cobalt, or the like. In some embodiments, the conductive material may be deposited by one or more of a deposition process and a plating process. In some embodiments, a deposition process may be used to form a seed layer of the conductive material, and then the source / drain contact holes 2302 a and 2302 b may be filled by an electroplating process. In some embodiments, after forming the conductive material, a planarization process may be performed to remove excess conductive material from above the second dielectric layer 126 b and define the source / drain regions 108 and 110.

[0060] like Figure 25As shown in the cross-sectional view 2500 of , a gate electrode 102 is formed in the second dielectric layer 126b reaching the upper surface of the ferroelectric layer 104. The gate electrode 102 can be formed by a patterning process to define a gate contact hole in the second dielectric layer 126b, and then a filling process of a conductive material is performed. The conductive material may include a metal such as copper, tungsten, cobalt, etc. In some embodiments, the conductive material can be deposited by one or more of a deposition process and a plating process. In some embodiments, a deposition process can be used to form a seed layer of the conductive material, and then a plating process can be performed. In some embodiments, after the conductive material is formed, a planarization process can be performed to remove excess conductive material from above the second dielectric layer 126b.

[0061] In some alternative embodiments (not shown), a filling process may be used to form the source / drain regions 108, 110 and the gate electrode 102 after simultaneous patterning of the source / drain contact holes and the gate contact hole. Figure 26 As shown in cross-sectional view 2600 of FIG, a third dielectric layer 126c and an upper metal layer 128 are formed above the stack of device layers. Metal layers 124, 128 and dielectric layers 126a, 126b, 126c together form an interconnect structure 120. Dielectric layers 126a, 126b, 126c can be formed of one or more of the following: silicon dioxide, silicon nitride, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials, etc. Although not shown in the figure, dielectric layers 126a, 126b, 126c can be separated by one or more etch stop layers. One or more etch stop layers can be formed of carbides (e.g., silicon carbide, silicon oxycarbide, etc.), nitrides (e.g., silicon nitride, silicon oxynitride, etc.), etc. The dielectric layers 126a, 126b, and 126c are shown as examples and may be formed with fewer or more dielectric layers. In some embodiments, the upper metal layer 128 is formed as a metal line or metal via that is electrically coupled to the source / drain regions 108, 110 and the gate electrode 102, either directly or through conductive contacts and / or additional metal layers. In some embodiments, the upper metal layer 128 may be formed by a damascene process (e.g., a single damascene process or a dual damascene process).

[0062] Figure 27 A flow chart illustrating some embodiments of a method 2700 of forming an integrated chip including a FeFET device having a 2D contact layer disposed along an OS channel layer.

[0063] Although the disclosed method 2700 is shown and described herein as a series of steps or events, it should be understood that the order of these steps or events shown should not be interpreted as limiting. For example, some steps can occur in different orders and / or occur simultaneously with other steps or events other than those shown and / or described herein. In addition, it is not required that all of the steps shown are used to implement one or more aspects or embodiments described herein. In addition, one or more of the steps described herein can be performed in one or more separate steps and / or stages.

[0064] At step 2702, a lower metal layer of an interconnect structure is formed over a substrate. Figure 9 or Figure 17 A cross-sectional view 900 or 1700 corresponding to some embodiments of step 2702 is shown.

[0065] At step 2704, a stack of device layers including a gate electrode, a ferroelectric layer, and an OS channel layer formed on the lower metal layer is formed. The stack of device layers can be formed by a series of deposition and patterning processes. The OS channel layer is of a first doping type (e.g., n-type, which has electrons as majority carriers). In some embodiments, the gate electrode is formed between the ferroelectric layer and the lower metal layer to form a back-gate FeFET device. In some alternative embodiments, the OS channel layer is formed closer to the lower metal layer, and then the ferroelectric layer and gate electrode are formed above the OS channel layer to form a front-gate FeFET device. Figure 10-11 Cross-sectional views 1000 - 1100 are shown corresponding to some embodiments of step 2704 . Figures 18-21 and Figure 25 Cross-sectional views 1800 - 2100 and 2500 are shown corresponding to some alternative embodiments of step 2704 .

[0066] At step 2706, a 2D contact layer is formed along the OS channel layer. The 2D contact layer is a second doping type different from the first doping type (e.g., p-type, which has holes as majority carriers). The 2D contact layer can be deposited or transferred from a sacrificial substrate. The 2D contact layer can be formed on the OS channel layer. In some embodiments, the 2D contact layer is formed to contact a portion of the upper surface of the OS channel layer and conformally along and covers the bottom surface and sidewall surface of the source / drain contact hole. In some alternative embodiments, the 2D contact layer is formed to cover the entire top surface of the OS channel layer. In some embodiments, a doping process and / or an annealing process is performed on the end of the 2D contact layer to locally increase the doping concentration of the 2D contact layer, so that the end of the 2D contact layer is more heavily doped than the middle region. Therefore, the source / drain contact resistance can be reduced without disconnecting the OS channel layer. Figure 14-15 Cross-sectional views 1400 - 1500 are shown corresponding to some embodiments of step 2706 . Figures 19-21Cross-sectional views 1900 - 2100 corresponding to some alternative embodiments of step 2706 are shown.

[0067] At step 2708, source / drain regions are formed on the opposite side of the OS channel layer contacting the 2D contact layer. The source / drain regions can be formed by etching source / drain contact holes in the interlayer dielectric and then filling the source / drain contact holes with a conductive material. Figure 15 or Figure 24 A cross-sectional view 1500 or 2400 corresponding to some embodiments of step 2708 is shown.

[0068] At step 2710, one or more additional metal layers of interconnect structures are formed over the stack of device layers. The one or more additional metal layers may be formed with metal lines or vias that are electrically coupled to the source / drain regions and / or gate electrodes, either directly or through additional conductive contacts. Figure 16 or Figure 26 A cross-sectional view 1600 or 2600 corresponding to some embodiments of step 2708 is shown.

[0069] Therefore, in some embodiments, the present disclosure relates to an integrated chip including a FeFET device having a 2D contact layer disposed along an oxide semiconductor layer configured to function as a channel (OS channel layer). The 2D contact layer has a second doping type (e.g., p-type or n-type) that is different from the first doping type (e.g., n-type or p-type) of the OS channel layer. In some embodiments, the 2D contact layer is disposed between and in contact with the source / drain region of the FeFET device and the OS channel layer, thereby not only providing supplementary carrier charge to enhance data programming of the FeFET device, but also serving to reduce the contact resistance between the source / drain region and the OS channel layer.

[0070] In some embodiments, the present disclosure relates to a FeFET device. The FeFET device includes a ferroelectric layer having a first side and a second side opposite the first side, and a gate electrode disposed along the first side of the ferroelectric layer. The FeFET device also includes an OS channel layer disposed along the second side of the ferroelectric layer opposite the first side, and a pair of source / drain regions disposed on opposite sides of the OS channel layer. The FeFET device also includes a 2D contact layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contact layer has a second doping type different from the first doping type.

[0071] In some embodiments, the 2D contact layer includes one or more of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), or molybdenum ditelluride (MoTe2). In some embodiments, the 2D contact layer is disposed between the pair of source / drain regions and the OS channel layer and in contact with the pair of source / drain regions and the OS channel layer. In some embodiments, the 2D contact layer covers the bottom surface and sidewall surfaces of the pair of source / drain regions. In some embodiments, the 2D contact layer covers the top surface of the OS channel layer. In some embodiments, the 2D contact layer has an end portion located below the source / drain region that is more heavily doped than the middle portion located between the source / drain regions. In some embodiments, the 2D contact layer is disposed between the OS channel layer and the ferroelectric layer and in contact with the OS channel layer and the ferroelectric layer. In some embodiments, the 2D contact layer covers the bottom surface of the source / drain region. In some embodiments, the first doping type is n-type and the second doping type is p-type. In some embodiments, the OS channel layer includes one or more of indium gallium zinc oxide, indium gallium zinc tin oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc oxide, and zinc oxide.

[0072] In other embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an interconnect structure disposed above a substrate. The interconnect structure includes a lower metal layer and an upper metal layer stacked above the lower metal layer. A FeFET device is inserted between the lower metal layer and the upper metal layer. The FeFET device includes a gate electrode disposed above the lower metal layer, a ferroelectric layer disposed above the gate electrode, and an oxide semiconductor (OS) channel layer disposed above the ferroelectric layer. The FeFET device also includes a pair of source / drain regions disposed on opposite sides of the OS channel layer and a 2D contact layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contact layer has a second doping type different from the first doping type.

[0073] In some embodiments, a 2D contact layer is disposed on the upper surface of the OS channel layer. In some embodiments, the 2D contact layer covers the bottom surface and sidewall surfaces of the pair of source / drain regions. In some embodiments, a pair of source / drain regions are coupled to a source line and a bit line, respectively, and the gate electrode is coupled to a word line. In some embodiments, the 2D contact layer comprises one or more of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), or molybdenum ditelluride (MoTe2). In some embodiments, the 2D contact layer is disposed between the ferroelectric layer and the OS channel layer and separates the ferroelectric layer and the OS channel layer. In some embodiments, the 2D contact layer has an end portion located below the source / drain region that is more heavily doped than a middle portion located between the source / drain regions. In some embodiments, the first doping type is n-type and the second doping type is p-type. In some embodiments, the OS channel layer comprises one or more of indium gallium zinc oxide, indium gallium zinc tin oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc oxide, and zinc oxide.

[0074] In other embodiments, the present disclosure relates to a method for forming a FeFET device. The method includes forming a lower metal layer of an interconnect structure above a substrate, and forming a stack of gate electrodes, ferroelectric layers, and oxide semiconductor (OS) channel layers stacked on each other above the lower metal layer. The method also includes forming a 2D contact layer along the OS channel layer. The OS channel layer has a first doping type, and the 2D contact layer has a second doping type different from the first doping type. The method also includes forming a pair of source / drain regions on opposite sides of the OS channel layer, and forming an upper metal layer of an interconnect structure having metal vias contacting the pair of source / drain regions.

[0075] The components of several embodiments have been discussed above so that those skilled in the art can better understand the various embodiments of the present invention. It will be appreciated by those skilled in the art that the present invention can be easily used as a basis to design or modify other processes and structures to achieve the same purpose and / or advantages as the embodiments described herein. It will also be appreciated by those skilled in the art that these equivalent structures do not depart from the spirit and scope of the present invention, and that various variations, replacements, and changes may be made without departing from the spirit and scope of the present invention.

Claims

1. A ferroelectric field effect transistor device, comprising: a ferroelectric layer having a first side and a second side opposite the first side; a gate electrode disposed along a first side of the ferroelectric layer; an oxide semiconductor channel layer disposed along a second side of the ferroelectric layer opposite to the first side, the oxide semiconductor channel layer having a first doping type; a pair of source / drain regions disposed on opposite sides of the oxide semiconductor channel layer; as well as a two-dimensional contact layer disposed along the oxide semiconductor channel layer, wherein the two-dimensional contact layer has a second doping type different from the first doping type, The two-dimensional contact layer is located between the pair of source / drain regions and the oxide semiconductor channel layer, and bottom surfaces of the pair of source / drain regions contact an upper surface of the two-dimensional contact layer.

2. The ferroelectric field effect transistor device according to claim 1, wherein: The two-dimensional contact layer includes one or more of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2) or molybdenum ditelluride (MoTe2).

3. The ferroelectric field effect transistor device according to claim 1, wherein: The two-dimensional contact layer is disposed between and in contact with the pair of source / drain regions and the oxide semiconductor channel layer.

4. The ferroelectric field effect transistor device according to claim 1, wherein: The two-dimensional contact layer covers bottom surfaces of the pair of source / drain regions.

5. The ferroelectric field effect transistor device according to claim 1, wherein: The two-dimensional contact layer covers a top surface of the oxide semiconductor channel layer.

6. The ferroelectric field effect transistor device according to claim 5, wherein: The two-dimensional contact layer has end portions located below the source / drain regions that are more heavily doped than a middle portion located between the source / drain regions.

7. The ferroelectric field effect transistor device according to claim 1, wherein: The oxide semiconductor channel layer has a thickness of 1×10 16 at / cm 3 to 1×10 18 at / cm 3 In the doping concentration range, the two-dimensional contact layer has a doping concentration of 1×10 18 at / cm 3 and 1×10 21 at / cm 3 The doping concentration is within a range between , and the oxide semiconductor channel layer has a thickness within a range between 3 nm and 20 nm, and the two-dimensional contact layer has a thickness within a range between 0.1 nm and 5 nm.

8. The ferroelectric field effect transistor device according to claim 7, wherein: The two-dimensional contact layer covers the bottom surface of the source / drain region.

9. The ferroelectric field effect transistor device according to claim 1, wherein: The first doping type is n-type, and the second doping type is p-type.

10. The ferroelectric field effect transistor device according to claim 1, wherein: The oxide semiconductor channel layer includes one or more of indium gallium zinc oxide, indium gallium zinc tin oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc oxide, and zinc oxide.

11. An integrated chip comprising: an interconnect structure disposed above the substrate, comprising a lower metal layer and an upper metal layer stacked above the lower metal layer; and A ferroelectric field effect transistor device, inserted between the lower metal layer and the upper metal layer, comprising: a gate electrode, disposed on the lower metal layer; a ferroelectric layer, disposed on the gate electrode; an oxide semiconductor channel layer, disposed above the ferroelectric layer, wherein the oxide semiconductor channel layer has a first doping type; a pair of source / drain regions disposed on opposite sides of the oxide semiconductor channel layer; and A two-dimensional contact layer separates the oxide semiconductor channel layer from the pair of source / drain regions and has a second doping type different from the first doping type.

12. The integrated chip according to claim 11, wherein: The two-dimensional contact layer is provided on an upper surface of the oxide semiconductor channel layer.

13. The integrated chip according to claim 11, wherein: The two-dimensional contact layer covers the bottom surface and sidewall surfaces of the pair of source / drain regions.

14. The integrated chip according to claim 11, wherein: The pair of source / drain regions are coupled to a source line and a bit line, respectively, and the gate electrode is coupled to a word line.

15. The integrated chip according to claim 11, wherein: The two-dimensional contact layer includes one or more of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2) or molybdenum ditelluride (MoTe2).

16. The integrated chip according to claim 11, wherein: The two-dimensional contact layer is a single-layer or multi-layer two-dimensional material composed of a single-layer of atoms and contacts the oxide semiconductor channel layer and the pair of source / drain regions.

17. The integrated chip according to claim 11, wherein: The two-dimensional contact layer has end portions located below the source / drain regions that are more heavily doped than a middle portion located between the source / drain regions.

18. The integrated chip according to claim 11, wherein: The first doping type is n-type, and the second doping type is p-type.

19. The integrated chip according to claim 11, wherein: The oxide semiconductor channel layer includes one or more of indium gallium zinc oxide, indium gallium zinc tin oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc oxide, and zinc oxide.

20. A method of forming a ferroelectric field effect transistor device, comprising: forming a lower metal layer of an interconnect structure over the substrate; forming a stack of a gate electrode, a ferroelectric layer, and an oxide semiconductor channel layer stacked on each other over the lower metal layer, the oxide semiconductor channel layer having a first doping type; forming a two-dimensional contact layer along the oxide semiconductor channel layer, wherein the two-dimensional contact layer has a second doping type different from the first doping type; forming a pair of source / drain regions on opposite sides of the oxide semiconductor channel layer; as well as forming an upper metal layer of an interconnect structure having metal vias contacting the pair of source / drain regions; The pair of source / drain regions has a bottom surface disposed on the two-dimensional contact layer.

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