Topological PN Junction, Its Preparation Method, and Method for Regulating Topological Quantum Transport Characteristics

Abstract

This application relates to the field of semiconductor devices, and discloses a topological PN junction, a preparation method thereof, and a method for regulating topological quantum transport characteristics. The topological PN junction includes a substrate, electrodes, a P-type region, and an N-type region; the P-type region is connected to one of the electrodes, the N-type region is connected to the other electrode, and a space charge region is formed between the N-type region and the P-type region; the P-type region is a topologically doped P-type semiconductor, and the N-type region is a topologically doped N-type semiconductor. This application provides a novel topological PN junction based on topological semiconductors, which can make full use of the advantages of semiconductors having an energy gap and being easy to regulate, and can effectively achieve the unidirectional opening of topological quantum transport characteristics.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, mainly to topological PN junctions, their preparation methods, and methods for regulating topological quantum transport characteristics. Background Art

[0002] In the semiconductor field, a PN junction is a common basic structural unit. A PN junction is formed by the close contact of a P-type semiconductor and an N-type semiconductor. A space charge region is formed at the junction of the P-type region and the N-type region, which constitutes the main part of the PN junction. A PN junction can be composed of only the same semiconductor material (i.e., a homojunction PN junction) or two different semiconductor materials (i.e., a heterojunction PN junction). The manufacturing process of a homojunction PN junction is relatively simple. A PN junction is a two-terminal device, and the voltage applied across the two ends of the PN junction is often referred to as the bias voltage. Generally, for a PN junction, when the voltage drop direction is from the P region to the N region, it is called a forward bias voltage, and when the voltage drop direction is from the N region to the P region, it is called a reverse bias voltage. Due to the concentration difference of different types of carriers (i.e., holes and electrons) between the P-type region and the N-type region, the diffusion of carriers causes a space charge region to form near the junction of the P-type region and the N-type region. The built-in electric field in the space charge region plays a role in hindering the diffusion of carriers. Applying a forward bias voltage to the PN junction weakens the built-in electric field and promotes the diffusion of majority carriers. At this time, the PN junction is in a low-resistance state; while applying a reverse bias voltage to the PN junction strengthens the built-in electric field and inhibits the diffusion of majority carriers. At this time, the PN junction is in a high-resistance state. Therefore, the main characteristic of a PN junction is unidirectional conductivity, that is, it conducts when a forward bias voltage is applied to the PN junction, and the forward bias voltage should be greater than the forward turn-on voltage; it cuts off when a reverse bias voltage is applied to the PN junction, and the reverse bias voltage should be less than the reverse breakdown voltage. PN junctions are important components that make up components such as diodes and transistors, and these components in turn make up the switching devices and logic devices in semiconductor integrated circuits. Silicon and germanium are common traditional semiconductor PN junction materials. However, due to the limitations of the material itself and related processes of traditional semiconductor materials, PN junctions made of traditional semiconductor materials have the problem of relatively high energy consumption, which poses a certain obstacle to the miniaturization of devices. In addition, PN junctions based on traditional semiconductor materials can only achieve the simple opening and closing of conductivity, while realizing new and efficient energy quantum devices requires PN junction materials to have more novel characteristics, such as spin, orbit, chirality, etc., to effectively develop multi-performance quantum devices. Therefore, finding new PN junction materials has important technical application value for improving, optimizing, and enriching the working performance of PN junctions, and for developing new integrated circuit components. The existing technology still needs to be improved and developed. Summary of the Invention

[0003] In view of the deficiencies of the above-mentioned prior art, the purpose of the present application is to provide a topological PN junction, a preparation method thereof, and a method for adjusting topological quantum transport characteristics, aiming to provide a new PN junction that can effectively achieve the unidirectional opening of topological quantum transport characteristics.

[0004] The technical solution of the present application is as follows:

[0005] A topological PN junction includes a substrate, electrodes, a P-type region, and an N-type region; the P-type region is connected to one of the electrodes, the N-type region is connected to the other electrode, and a space charge region is formed between the N-type region and the P-type region; wherein, the P-type region is a topologically doped semiconductor, and the N-type region is an N-type doped topologically doped semiconductor;

[0006] The energy band of the topologically doped semiconductor contains at least two topological energy band intersections, and at least one of the topological energy band intersections is contained in the conduction band of the topologically doped semiconductor, and at least one of the topological energy band intersections is contained in the valence band of the topologically doped semiconductor.

[0007] Based on the topological PN junction of the topologically doped semiconductor, the advantages of the semiconductor having an energy gap and being easy to control can be fully utilized, and the unidirectional opening of topological quantum transport characteristics can be effectively achieved.

[0008] For the topological PN junction described above, when the topological energy band intersection of the topologically doped semiconductor in the topological PN junction is located in the conduction band, the difference between the topological energy band intersection in the conduction band and the bottom of the conduction band is less than 1 eV;

[0009] When the topological energy band intersection of the topologically doped semiconductor in the topological PN junction is located in the valence band, the difference between the topological energy band intersection in the valence band and the top of the valence band is less than 1 eV;

[0010] The Fermi level of the topologically doped semiconductor in the P-type region of the topological PN junction is located in the valence band and the difference from the topological energy band intersection in the valence band is less than 1 eV;

[0011] The Fermi level of the topologically doped semiconductor in the N-type region of the topological PN junction is located in the conduction band and the difference from the topological energy band intersection in the conduction band is less than 1 eV.

[0012] If the number and position of the topological energy band intersections of the topologically doped semiconductor and the positions of the Fermi levels of the P-type region and the N-type region meet the above requirements, the unidirectional opening of topological quantum transport characteristics can be better achieved.

[0013] For the topological PN junction described above, the topologically doped semiconductor is tellurium.

[0014] The topological PN junction described above, wherein when the topological energy band intersection of the topological semiconductor in the topological PN junction is located in the conduction band, the difference between the topological energy band intersection in the conduction band and the bottom of the conduction band is less than 0.2 eV; when the topological energy band intersection of the topological semiconductor in the topological PN junction is located in the valence band, the difference between the topological energy band intersection in the valence band and the top of the valence band is less than 0.2 eV.

[0015] The topological PN junction described above, wherein the carrier concentration range of tellurium in the P-type region and the N-type region is 1e17 cm -3 ~1e19 cm -3 .

[0016] A method for regulating the topological quantum transport properties of the topological PN junction described above, which includes the following steps:

[0017] Applying a forward bias voltage to the topological PN junction to achieve the open state of the topological quantum transport properties of the topological PN junction;

[0018] Applying a reverse bias voltage to the topological PN junction to achieve the closed state of the topological quantum transport properties of the topological PN junction.

[0019] The method for regulating the topological quantum transport properties of the topological PN junction described above, wherein the forward bias voltage applied to the topological PN junction is greater than the forward turn-on voltage of the topological PN junction;

[0020] The reverse bias voltage applied to the topological PN junction is less than the reverse breakdown voltage of the topological PN junction.

[0021] The method for regulating the topological quantum transport properties of the topological PN junction described above, wherein the ratio of the reverse breakdown voltage to the forward turn-on voltage of the topological PN junction is greater than 10.

[0022] A method for preparing the topological PN junction described above, wherein when the topological PN junction is a planar topological PN junction, it includes the following steps:

[0023] Preparing a topological semiconductor thin film;

[0024] Performing P-type doping on the P-type region of the topological semiconductor thin film;

[0025] Performing N-type doping on the N-type region of the topological semiconductor thin film;

[0026] Performing annealing treatment on the topological PN junction;

[0027] Preparing electrodes at both ends of the topological semiconductor thin film;

[0028] When the topological PN junction is a vertical topological PN junction, it includes the following steps:

[0029] Fabricate the bottom electrode;

[0030] Fabricate a P-type doped topological semiconductor thin film;

[0031] Perform N-type doping on the P-type doped topological semiconductor thin film;

[0032] Fabricate the top electrode;

[0033] Anneal the topological PN junction.

[0034] The method for preparing the topological PN junction, wherein when the topological semiconductor is tellurium, in the process of fabricating the topological semiconductor thin film, physical vapor deposition method or solution method is adopted for fabrication;

[0035] In the process of performing P-type doping on the P-type region of the topological semiconductor thin film, the P-type doping method is ion implantation method or thermal diffusion method, and the elements for P-type doping are at least one of antimony, bismuth, arsenic, phosphorus, tin and lead;

[0036] In the process of performing N-type doping on the N-type region of the topological semiconductor thin film, the N-type doping method is surface chemical treatment method or atomic layer deposition method;

[0037] In the process of fabricating electrodes at both ends of the topological semiconductor thin film, electrode materials are deposited at both ends of the topological semiconductor thin film by evaporation coating technology;

[0038] In the process of fabricating the bottom electrode, bottom electrode materials are deposited by evaporation coating technology;

[0039] In the process of fabricating the P-type doped topological semiconductor thin film, physical vapor deposition method is adopted for fabrication;

[0040] In the process of performing N-type doping on the P-type doped topological semiconductor thin film, the N-type doping method is surface chemical treatment method;

[0041] In the process of fabricating the top electrode, top electrode materials are deposited by evaporation coating technology;

[0042] In the process of the annealing treatment, it is carried out in an inert gas atmosphere, the temperature is 200~350 °C, and the time is 10~60 min.

[0043] Beneficial effects: The topological PN junction provided by this application makes full use of the uniqueness of the combination of the topological quantum transport characteristics and semiconductor properties of topological semiconductors, and is expected to solve the material selection problem of topological PN junctions, achieve the unidirectional opening of topological quantum transport characteristics, and further realize high-performance topological electronic and optoelectronic devices based on topological PN junctions. The topological PN junction based on topological semiconductors in this application has easily effectively tunable topological quantum transport characteristics. The topological semiconductor materials used have strong compatibility with modern electronic industries and have practical feasibility. Description of the Drawings

[0044] Figure 1 It is a schematic energy band diagram of the topological semiconductor of the topological PN junction of this application.

[0045] Figure 2 It is a schematic diagram of the positions of the Fermi levels in the energy bands of the topological semiconductor of the topological PN junction of this application in the P-type region and the N-type region.

[0046] Figure 3 It is a schematic structural diagram of the planar topological PN junction in this application.

[0047] Figure 4 It is a schematic structural diagram of the vertical topological PN junction in this application.

[0048] Label description: 11, conduction band; 12, energy gap; 13, valence band; 14, topological energy band intersection in the conduction band; 15, bottom of the conduction band; 16, top of the valence band; 17, topological energy band intersection in the valence band; 21, position of the Fermi level in the N-type region; 22, position of the Fermi level in the P-type region; 31, P-type region; 32, space charge region; 33, N-type region; 34, electrode; 35, substrate. Detailed Description of the Invention

[0049] The topological PN junction provided by this application, its preparation method, and the method for adjusting topological quantum transport characteristics will be further described in detail below to make the purpose, technical solution, and effects of this application clearer and more definite. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0050] Topological semiconductors are a newly discovered type of topological materials in recent years. They contain Weyl fermions and exhibit various novel topological quantum transport properties, including longitudinal negative magnetoresistance effect, planar Hall effect, and logarithmic quantum oscillations. The longitudinal negative magnetoresistance effect is a negative magnetoresistance phenomenon that occurs when the external magnetic field direction is parallel to the current direction in the sample. The planar Hall effect is that when the external magnetic field direction and the current direction in the sample are both in the sample plane and neither parallel nor perpendicular to each other, the measured Hall voltage is not zero. The logarithmic quantum oscillation is that when the external magnetic field direction is perpendicular to the sample plane, the magnetoresistance or Hall resistance oscillates periodically with the logarithm of the magnetic field. The various topological quantum transport properties of topological semiconductors originate precisely from the Weyl fermions in topological semiconductors.

[0051] In this application, a topological PN junction is provided. This topological PN junction includes a substrate, electrodes, a P-type region, and an N-type region; the P-type region is connected to one electrode, the N-type region is connected to the other electrode, and a space charge region is formed between the N-type region and the P-type region; the P-type region is a thin film prepared from a P-type doped topological semiconductor, and the N-type region is a thin film prepared from an N-type doped topological semiconductor. In this application, the topological quantum transport properties are regulated by adjusting the bias voltage applied to the topological PN junction based on topological semiconductors. By changing the direction of the bias voltage, the topological transport properties can be controlled to rapidly change from the open state to the closed state.

[0052] Developing new topological PN junctions based on topological semiconductors can make full use of the advantages of semiconductors having an energy gap and being easy to regulate, and can effectively achieve the unidirectional opening of topological quantum transport properties. Combining various methods of regulating semiconductor properties such as gate voltage, optics, and microwaves, the topological quantum transport properties of topological PN junctions will be more effectively regulated in a wider range and more flexibly. It can be seen that developing topological PN junctions based on topological semiconductors provides a feasible path for improving and enriching the performance of semiconductor devices. Research and development of topological electronic and optoelectronic devices based on topological PN junctions can effectively reduce energy consumption and thus achieve device miniaturization, and may play an important role in the field of high-fault-tolerant topological quantum computing.

[0053] Furthermore, both the conduction band and valence band of the topological semiconductor in the topological PN junction contain at least one topological energy band intersection, that is, the conduction band of the topological semiconductor in the topological PN junction contains at least one topological energy band intersection, and the valence band of the topological semiconductor in the topological PN junction contains at least one topological energy band intersection.

[0054] As Figure 1 and Figure 2 shown, there is an energy gap 12 between the conduction band 11 and the valence band 13. The topological PN junction prepared from a topological semiconductor has the following characteristics:

[0055] When the topological band intersection of the topological semiconductor in the topological PN junction is located in the conduction band 11, the topological band intersection 14 in the conduction band is less than 1 eV different from the conduction band bottom 15;

[0056] When the topological band intersection of the topological semiconductor in the topological PN junction is located in the valence band 13, the topological band intersection 17 in the valence band is less than 1 eV different from the valence band top 16;

[0057] The Fermi level 22 of the topological semiconductor in the P-type region of the topological PN junction is located in the valence band and is less than 1 eV different from the topological band intersection 17 in the valence band;

[0058] The Fermi level 21 of the topological semiconductor in the N-type region of the topological PN junction is located in the conduction band and is less than 1 eV different from the topological band intersection 14 in the conduction band.

[0059] The topological band intersection of the topological semiconductor in the topological PN junction includes at least one of a Dirac point and a Weyl point.

[0060] In this application, the topological semiconductor is tellurium. By selecting tellurium as the material of the topological PN junction, there are topological band intersections as Weyl points in both the conduction band and the valence band of tellurium. Therefore, the topological band structure of tellurium conforms to the characteristics of the topological semiconductor, and can realize the organic combination of the topological quantum transport characteristics and the semiconductor properties. By utilizing the semiconductor properties, the preparation of the topological PN junction can be realized, thereby realizing the unidirectional opening of the topological quantum transport characteristics. The topological semiconductor is tellurium. Preferably, when the topological band intersection of the topological semiconductor in the topological PN junction is located in the conduction band 11, the topological band intersection 14 in the conduction band is less than 0.2 eV different from the conduction band bottom 15; when the topological band intersection of the topological semiconductor in the topological PN junction is located in the valence band 13, the topological band intersection 17 in the valence band is less than 0.2 eV different from the valence band top 16. The closer the topological band intersection 14 in the conduction band is to the conduction band bottom 15 and the closer the topological band intersection 17 in the valence band is to the valence band top 16, the more conducive it is for the topological semiconductor in the topological PN junction to realize the topological quantum transport characteristics.

[0061] Specifically, the topological PN junction includes a P-type region and an N-type region; the carrier concentration of tellurium in the P-type region and the N-type region is greater than 1e16 cm -3 , preferably, the carrier concentration range of tellurium in the P-type region and the N-type region is 1e17 cm -3 ~1e19 cm -3 . Different materials have different specificities, and the carrier concentration ranges of the P-type region and the N-type region when made into a PN junction are also different. In the solution of this application, by analyzing the position of the Fermi level of tellurium in the energy band, the carrier concentration ranges of the P-type region and the N-type region when tellurium is made into a PN junction are obtained.

[0062] In this application, a PN junction is fabricated using a material of topological semiconductors. The realized function is to add topological quantum transport characteristics to the basis of the unidirectional conductivity of a traditional PN junction, thereby achieving the unidirectional opening of topological quantum transport characteristics. To better achieve the unidirectional opening of topological quantum transport characteristics, this application further proposes preferred conditions, such as requirements for the position of the topological energy band intersection of the topological semiconductor and the Fermi energy level positions of the P-type region and the N-type region.

[0063] This application also provides a method for regulating the topological quantum transport characteristics of a topological PN junction, including the following steps:

[0064] Applying a forward bias voltage to the topological PN junction to achieve the open state of the topological quantum transport characteristics of the topological PN junction;

[0065] Applying a reverse bias voltage to the topological PN junction to achieve the closed state of the topological quantum transport characteristics of the topological PN junction.

[0066] Based on the topological PN junction of topological semiconductors, the unidirectional opening characteristic of topological quantum transport characteristics can be achieved, providing a practical and feasible method for effectively regulating topological quantum transport characteristics in the semiconductor field, and is expected to play an important role in the research and development of future high-performance topological electronic devices.

[0067] In this application, the topological quantum transport characteristics of the topological PN junction include at least one of a longitudinal negative magnetoresistance effect, a planar Hall effect, and logarithmic quantum oscillations.

[0068] Furthermore, the forward bias voltage applied to the topological PN junction is greater than the forward turn-on voltage of the topological PN junction; the reverse bias voltage applied to the topological PN junction is less than the reverse breakdown voltage of the topological PN junction.

[0069] Furthermore, the ratio of the reverse breakdown voltage to the forward turn-on voltage of the topological PN junction is greater than 10. The function realized by the PN junction is the unidirectional opening of conductivity (i.e., forward open and reverse closed), and the larger the voltage range of the reverse closed state, the better, so the larger the reverse breakdown voltage, the better.

[0070] To illustrate the feasibility of using tellurium to fabricate a topological PN junction, this application also provides a preparation method for the topological PN junction. The topological PN junction can be a planar topological PN junction or a vertical topological PN junction, and this application provides the preparation methods for these two types of topological PN junctions.

[0071] When the topological PN junction is a planar topological PN junction, the structure of the planar topological PN junction is as Figure 3 shown, including a substrate 35 and a topological semiconductor; electrodes 34 are arranged at both ends of the topological semiconductor, an N-type region 33 and a P-type region 31 are arranged between the electrodes 34, and a space charge region 32 is formed between the N-type region 33 and the P-type region 31.

[0072] When the topological PN junction is a planar topological PN junction, the preparation method of the topological PN junction may include the following steps:

[0073] (1) Prepare a topological semiconductor nanosheet (or topological semiconductor thin film): Use physical vapor deposition or solution method to prepare a topological semiconductor nanosheet.

[0074] The topological semiconductor nanosheet can be directly prepared on the corresponding area of the substrate of the topological PN junction, or prepared on other substrates and then transferred to the corresponding area of the substrate of the topological PN junction. Using physical vapor deposition or solution method to prepare topological semiconductor nanosheets can obtain topological semiconductor nanosheets with high crystal quality and different thicknesses.

[0075] (2) Perform P-type doping on the P-type region of the topological semiconductor nanosheet.

[0076] The P-type doping method can be ion implantation, thermal diffusion, surface chemical treatment, atomic layer deposition of dielectric, or gate voltage regulation. Preferably, ion implantation or thermal diffusion is used for P-type doping. The elements for P-type doping can be at least one of antimony, bismuth, arsenic, phosphorus, tin, and lead. Among them, arsenic has the most significant P-type doping effect on tellurium, and the doping concentration can reach 3e19cm -3 .

[0077] In the embodiment of the present application, the topological semiconductor nanosheet is tellurium. P-type doping makes the Fermi level of tellurium in the P-type region at least intersect with the valence band, and the doping concentration is greater than 1e16cm -3 , preferably controlled within the range of 1e17cm -3 ~1e19cm -3 . Moderate doping of other elements has little effect on the energy band structure of tellurium. Therefore, the topological quantum transport properties of tellurium are not significantly affected by the doping elements. The role of doping other elements is mainly to change the carrier concentration of tellurium and adjust the position of the Fermi level of tellurium.

[0078] (3) Perform N-type doping on the N-type region of the topological semiconductor nanosheet.

[0079] The N-type doping method can be ion implantation, thermal diffusion, surface chemical treatment, atomic layer deposition of dielectric, or gate voltage regulation.

[0080] Preferably, surface chemical treatment or atomic layer deposition is used. In the embodiment of the present application, the topological semiconductor nanosheet is tellurium. Surface chemical treatment or atomic layer deposition does not require doping other elements into tellurium, and mainly affects the position of the Fermi level of tellurium in the energy band by changing the surface of tellurium, and has little effect on the topological energy band structure and topological quantum transport properties of tellurium.

[0081] By depositing aluminum oxide on the N-type region of the topological semiconductor nanosheet through atomic layer deposition and combining with the gate voltage regulation method, a topological semiconductor nanosheet with a suitable N-type doping concentration can also be obtained. The atomic layer deposition method requires depositing a layer of aluminum oxide on the surface of tellurium, with a relatively high deposition temperature (~200 °C) and a relatively complex process.

[0082] The surface chemical treatment method can achieve a larger doping concentration and has a wide variety of optional doping compounds. The surface chemical treatment reagents can be at least one of sulfides (such as Na2S, NaHS, (NH4)2S, K2S, KHS, etc.), hydrazine (N2H4), hydroxides (TMAOH, TEAOH, TBAOH, bmimOH, NaOH, KOH, etc.), crown ether compounds (NaOH / 15, crown, NaCl / 15, crown, KOH / 18, crown, KCl / 18, crown, NaBH4 / 15, crown, NaHS / 15, crown, etc.), and the process is relatively simple. Therefore, the surface chemical treatment method is a better process choice.

[0083] In the embodiment of the present application, the topological semiconductor nanosheet is tellurium. Taking the use of Na2S for surface chemical treatment as an example, the process of N-type doping specifically includes the following steps:

[0084] Using Na2S with a purity of at least 99.9% and deionized water with a resistivity greater than 18 MΩ, prepare 200 mL of a 0.1 mol / L Na2S aqueous solution in a clean quartz beaker;

[0085] Using electron beam lithography technology to prepare a mask with a specific shape for the topological semiconductor nanosheet so that only the N-type region of the topological semiconductor nanosheet contacts the Na2S aqueous solution. After sealing the solution, place it in an incubator, set the temperature to 50 °C, and let it stand for 24 h;

[0086] After the reaction, rinse the topological semiconductor nanosheet 3 times with deionized water and dry the surface of the topological semiconductor nanosheet with high-purity nitrogen.

[0087] N-type doping makes the Fermi level of tellurium in the N-type region at least intersect with the conduction band, and the doping concentration is greater than 1e16 cm -3 Preferably, it is controlled within the range of 1e17 cm -3 ~1e19 cm -3 range.

[0088] (4) Anneal the topological PN junction.

[0089] Anneal the topological PN junction in an inert gas atmosphere using an annealing furnace. Selecting to anneal the topological semiconductor nanosheet in an inert gas atmosphere using an annealing furnace can effectively improve the quality of the PN junction.

[0090] In the embodiment of the present application, select to anneal the topological PN junction in an argon atmosphere. The annealing temperature range is 200~350 °C, and the annealing time range is 10~60 min.

[0091] (5)Fabricate electrodes.

[0092] In this step, deposit electrode materials at both ends of the topological semiconductor nanosheet through an evaporation coating technique. Among them, the electrode material can be one of palladium, gold, or nickel. Palladium or gold or nickel has a large work function (Pd 5.22~5.60 eV, Au 5.10~5.47 eV, Ni 5.04~5.35 eV), which is beneficial to forming a good ohmic contact with the tellurium nanosheet.

[0093] When the topological PN junction is a vertical topological PN junction, the structure of the vertical topological PN junction is as Figure 4 shown, and successively includes a substrate 35, a P-type region 31, a space charge region 32, and an N-type region 33 from bottom to top.

[0094] When the topological PN junction is a vertical topological PN junction, the preparation method of the topological PN junction includes the following steps:

[0095] (1)Fabricate the bottom electrode.

[0096] In this step, deposit the bottom electrode material on the substrate through an evaporation coating technique. Among them, the electrode material can be one of palladium, gold, or nickel. Palladium or gold or nickel has a large work function (Pd 5.22~5.60 eV, Au 5.10~5.47 eV, Ni 5.04~5.35 eV), which is beneficial to forming a good ohmic contact with the tellurium nanosheet.

[0097] (2)Fabricate a P-type doped topological semiconductor nanosheet (or a P-type doped topological semiconductor thin film): Use physical vapor deposition to fabricate a P-type doped topological semiconductor nanosheet and transfer it onto the electrode.

[0098] In the aforementioned P-type doping methods, only ion implantation or thermal diffusion requires doping with other elements, while physical vapor deposition or solution methods do not require doping with other elements and only need to adjust the growth conditions to achieve P-type doping. Generally, it is considered that introducing other elements may have unknown adverse effects, and achieving doping without introducing other elements is a better method. Therefore, physical vapor deposition or solution methods are better process choices. Considering that the solution method requires the use of various chemical reagents (such as Na2TeO3, polyvinylpyrrolidone, ammonia water, hydrazine hydrate, etc.) which may introduce impurity elements. And physical vapor deposition mainly uses tellurium vacancies formed during the growth process to achieve P-type doping, and the raw material is only tellurium powder. Therefore, physical vapor deposition is a more optimal process choice.

[0099] In the embodiments of the present application, the topological semiconductor nanosheet is tellurium. Preferably, the process of preparing a P-type doped topological semiconductor nanosheet specifically includes the following steps:

[0100] Using a single-zone tube furnace as the growth equipment, tellurium powder with a purity of at least 99.999% as the growth raw material, a SiO2 / Si substrate as the substrate, and argon with a purity of 99.999% as the carrier gas;

[0101] The substrate can be ultrasonically cleaned with acetone, ethanol, isopropanol, and deionized water in sequence for 10 min, and the surface is dried with high-purity nitrogen.

[0102] Place the growth raw material in the center of the reaction chamber of the single-zone tube furnace, place the substrate at the downstream position of the gas flow, and the spacing distance between the substrate and the growth raw material is 20 cm;

[0103] At room temperature, use a mechanical pump and a molecular pump to evacuate the reaction chamber of the single-zone tube furnace to 10 -4 Pa, then introduce argon into the reaction chamber, the flow rate is set to 100 sccm, the air pressure is set to 5 Pa, and it is maintained for 60 min; adjust the argon flow rate to 25 sccm, and the air pressure is set to 20 Pa;

[0104] The target growth temperature is set to 375 °C, linearly heated from room temperature to the target growth temperature at a heating rate of 5 °C / min, keep the growth temperature constant at 375 °C, set the growth time to 30 min. After the growth is completed, turn off the power of the single-zone tube furnace, and take out the substrate after natural cooling to room temperature.

[0105] (3) Perform N-type doping on the P-type doped topological semiconductor nanosheet.

[0106] It is the same as the preparation method of the planar topological PN junction.

[0107] When performing N-type doping on the surface of a topological semiconductor nanosheet by using a surface chemical treatment method, since the P-type doped topological semiconductor nanosheet obtained in step (2) is used, step (3) changes a part with a certain thickness under the surface of the topological semiconductor nanosheet from P-type to N-type, thereby realizing a PN junction. Among them, the thickness of the N-type doping should be less than the thickness of the topological semiconductor nanosheet. Preferably, the thickness of the N-type doping is equal to half of the thickness of the topological semiconductor nanosheet.

[0108] (4) Prepare the top electrode.

[0109] In this step, the top electrode material is deposited on the top of the tellurium nanosheet by an evaporation coating technique. The selection requirements for the top electrode material are the same as those for the bottom electrode material.

[0110] (5) Anneal the topological PN junction.

[0111] It is the same as the preparation method of the planar topological PN junction.

[0112] This application provides a topological PN junction, using a topological semiconductor as the material, providing a new type of PN junction, which has the following advantages compared with the prior art:

[0113] (1) This application makes full use of the characteristics of the combination of the topological quantum transport characteristics and semiconductor properties of the topological semiconductor, and can effectively regulate the topological quantum transport characteristics of the topological PN junction. The principle is simple, the controllability is strong, it is compatible with the modern electronics industry, and has practical feasibility;

[0114] (2) This application is expected to solve the problem of material selection for topological PN junctions and alleviate the technical problem that the topological quantum transport characteristics of topological materials have not been effectively applied and regulated in the semiconductor and microelectronics fields;

[0115] (3) The preparation method of the topological PN junction based on the topological semiconductor provided by this application, by optimizing the topological semiconductor material in the topological PN junction, gives play to the advantages of the combination of the topological quantum transport characteristics and semiconductor properties of the topological semiconductor, and enhances the controllability of the topological quantum transport characteristics; by optimizing the implementation method of P-type doping or N-type doping of the topological PN junction, a variety of feasible solutions are provided for effectively regulating the topological quantum transport characteristics;

[0116] (4) The topological PN junction based on the topological semiconductor provided by this application can realize a topological non-trivial state when a forward bias is applied and a topological trivial state when a reverse bias is applied, that is, it realizes the unidirectional opening characteristic of the topological quantum transport characteristics, providing a practical and feasible method for effectively regulating the topological quantum transport characteristics in the semiconductor field, and is expected to play an important role in the research and development of future high-performance topological electronic devices.

[0117] The present application will be further described below through specific embodiments.

[0118] Example 1

[0119] Prepare a planar topological PN junction:

[0120] 1. Select a SiO2 / Si substrate with a SiO2 layer thickness of 300 nm on the surface, ultrasonically clean it in acetone, ethanol, isopropanol, and deionized water in sequence, and dry the surface of the SiO2 / Si substrate with high-purity nitrogen.

[0121] 2. Prepare tellurium nanosheets by physical vapor deposition or solution method and transfer them onto the SiO2 / Si substrate in step 1. In the embodiment of the present application, the process parameters of physical vapor deposition can be: the growth equipment is a single-temperature zone tube furnace, the growth raw material is tellurium powder with a purity of at least 99.999%, and the substrate is SiO2 / Si. The growth raw material is placed in the center of the single-temperature zone tube furnace, the substrate is placed at the downstream position of the gas flow, and the distance from the growth raw material is 20 cm. The carrier gas is argon, the flow rate is 20 sccm, and the gas pressure is 9 Pa. The growth temperature is 350 °C, the heating-up time is 1 h, the growth time is 30 min, and after growth, it is naturally cooled to room temperature. Finally, the thickness of the prepared tellurium nanosheets is less than 100 nm.

[0122] 3. Etch the tellurium nanosheets into rectangles with an aspect ratio greater than 3 by argon plasma etching technology.

[0123] 4. Do P-type doping on the P-type region of the tellurium nanosheets by ion implantation or thermal diffusion method, and the doping concentration range is 1e17 cm -3 ~1e19 cm -3 .

[0124] 5. Do N-type doping on the N-type region of the tellurium nanosheets by surface chemical treatment method, and the doping concentration range is 1e17 cm -3 ~1e19 cm -3 : Use Na2S with a purity of at least 99.9% and deionized water with a resistivity greater than 18 MΩ to prepare 200 mL of a 0.1 mol / L Na2S aqueous solution in a clean quartz beaker; use electron beam lithography technology to prepare a mask with a specific shape on the tellurium nanosheets so that only the N-type region of the topological semiconductor nanosheets contacts the Na2S aqueous solution, seal the solution well and place it in an incubator, set the temperature at 50 °C, and let it stand for 24 h; after the reaction, rinse the tellurium nanosheets 3 times with deionized water and dry the surface of the tellurium nanosheets with high-purity nitrogen.

[0125] 6. Anneal the tellurium nanosheets in an argon atmosphere using an annealing furnace, the annealing treatment time is 20 min, the annealing temperature is 300 °C, and then take it out after natural cooling to room temperature.

[0126] 7. Deposit 100 nm thick palladium metal at both ends of the tellurium nanosheet as the electrode material through the evaporation coating technology.

[0127] 8. Place the topological PN junction device based on tellurium topological semiconductor obtained in the above steps in a low-temperature and strong magnetic field environment to measure the topological quantum transport characteristics of the topological PN junction, and achieve the unidirectional opening of the topological quantum transport characteristics. Test conditions: The temperature range can be selected from 2 to 200 K, and the magnetic field range can be selected from -14 T to 14 T.

[0128] Among them, in steps 3, 4, 5, and 7, it is necessary to prepare a mask with a certain shape on the tellurium nanosheet through electron beam lithography technology, so as to perform specific processing on a certain area of the tellurium nanosheet alone. This is the prior art and will not be elaborated here.

[0129] Example 2

[0130] Prepare a vertical topological PN junction:

[0131] 1. Select a SiO2 / Si substrate with a SiO2 layer thickness of 300 nm on the surface, ultrasonically clean it in acetone, ethanol, isopropanol, and deionized water in sequence, and dry the surface of the SiO2 / Si substrate with high-purity nitrogen.

[0132] 2. Deposit 100 nm thick nickel metal on a suitable area of the SiO2 / Si substrate as the bottom electrode material through the evaporation coating technology.

[0133] 3. Prepare a P-type doped topological semiconductor nanosheet by physical vapor deposition method and transfer it onto the electrode material on the surface of the SiO2 / Si substrate. Process for preparing the P-type doped topological semiconductor nanosheet: Use a single-temperature zone tube furnace as the growth equipment, use tellurium powder with a purity of at least 99.999% as the growth raw material, use the SiO2 / Si substrate as the substrate, and use argon with a purity of 99.999% as the carrier gas; the substrate can be ultrasonically cleaned in acetone, ethanol, isopropanol, and deionized water for 10 min in sequence, and the surface can be dried with high-purity nitrogen; place the growth raw material in the center of the reaction chamber of the single-temperature zone tube furnace, place the substrate at the downstream position of the gas flow, and the distance between the substrate and the growth raw material is 20 cm; at room temperature, use a mechanical pump and a molecular pump to evacuate the reaction chamber of the single-temperature zone tube furnace to 10 4Pa, then introduce argon gas into the reaction chamber with a flow rate set at 100 sccm, a pressure set at 5 Pa, and maintain for 60 min; adjust the argon gas flow rate to 25 sccm and the pressure to 20 Pa; set the target growth temperature at 375 °C, linearly heat from room temperature to the target growth temperature at a heating rate of 5 °C / min, keep the growth temperature constant at 375 °C, set the growth time to 30 min. After growth, turn off the power of the single-zone tube furnace, and take out the substrate after natural cooling to room temperature. Finally, the thickness of the prepared tellurium nanosheets is less than 100 nm, and the doping concentration is in the range of 1e17 cm -3 ~1e19 cm -3 .

[0134] 4. Etch the tellurium nanosheets into regular rectangles by argon plasma etching technology.

[0135] 5. Perform N-type doping on the surface area of the tellurium nanosheets using the surface chemical treatment method. The thickness of the N-type doping is equal to half of the thickness of the tellurium nanosheets, and the doping concentration range is in 1e17 cm -3 ~1e19 cm -3 : Use Na2S with a purity of at least 99.9% and deionized water with a resistivity greater than 18 MΩ to prepare 200 mL of a 0.1 mol / L Na2S aqueous solution in a clean quartz beaker; use electron beam lithography technology to prepare a mask with a specific shape on the tellurium nanosheets so that only the N-type region of the topological semiconductor nanosheets contacts the Na2S aqueous solution. Seal the solution and place it in an incubator, set the temperature at 50 °C, and let it stand for 24 h; after the reaction, rinse the tellurium nanosheets 3 times with deionized water and dry the surface of the tellurium nanosheets with high-purity nitrogen.

[0136] 6. Deposit 100 nm thick metallic nickel on the top of the tellurium nanosheets as the top electrode material by evaporation coating technology.

[0137] 7. Anneal the tellurium nanosheets in an argon atmosphere using an annealing furnace, and then take them out after natural cooling to room temperature.

[0138] Among them, in steps 2, 4, 5, and 6, it is necessary to prepare a mask with a certain shape on the tellurium nanosheets by electron beam lithography technology, so as to perform specific treatment on a certain area of the tellurium nanosheets alone. This is the prior art and will not be elaborated here.

[0139] 8. Place the topological PN junction device based on tellurium topological semiconductors obtained in the above steps in a low-temperature and high-magnetic field environment to measure the topological quantum transport characteristics of the topological PN junction and achieve the unidirectional opening of the topological quantum transport characteristics. Test conditions: The temperature range can be selected from 2 to 200 K, and the magnetic field range can be selected from -14 T to 14 T.

[0140] It should be understood that the application of the present application is not limited to the above examples. For those of ordinary skill in the art, improvements or transformations can be made according to the above description, and all such improvements and transformations shall fall within the protection scope of the appended claims of the present application.

Claims

1. A topological PN junction, comprising a substrate, electrodes, a P-type region and an N-type region; the P-type region is connected to one of the electrodes, the N-type region is connected to the other electrode, and a space charge region is formed between the N-type region and the P-type region; characterized in that, The P-type region is a topologically semiconductor doped with P-type, and the N-type region is a topologically semiconductor doped with N-type; The energy band of the topologically semiconductor contains at least two topological band intersections, and at least one of the topological band intersections is contained in the conduction band of the topologically semiconductor, and at least one of the topological band intersections is contained in the valence band of the topologically semiconductor; Applying a forward bias to the topological PN junction realizes the open state of the topological quantum transport characteristics of the topological PN junction; applying a reverse bias to the topological PN junction realizes the closed state of the topological quantum transport characteristics of the topological PN junction; The ratio of the reverse breakdown voltage to the forward turn-on voltage of the topological PN junction is greater than 10.

2. The topological PN junction according to claim 1, characterized in that, When the topological band intersection of the topologically semiconductor in the topological PN junction is located in the conduction band, the topological band intersection in the conduction band differs from the bottom of the conduction band by less than 1 eV; When the topological band intersection of the topologically semiconductor in the topological PN junction is located in the valence band, the topological band intersection in the valence band differs from the top of the valence band by less than 1 eV; The Fermi level of the topologically semiconductor in the P-type region of the topological PN junction is located in the valence band and differs from the topological band intersection in the valence band by less than 1 eV; The Fermi level of the topologically semiconductor in the N-type region of the topological PN junction is located in the conduction band and differs from the topological band intersection in the conduction band by less than 1 eV.

3. The topological PN junction according to claim 1, characterized in that, The topologically semiconductor is tellurium.

4. The topological PN junction according to claim 3, characterized in that, When the topological band intersection of the topologically semiconductor in the topological PN junction is located in the conduction band, the topological band intersection in the conduction band differs from the bottom of the conduction band by less than 0.2 eV; when the topological band intersection of the topologically semiconductor in the topological PN junction is located in the valence band, the topological band intersection in the valence band differs from the top of the valence band by less than 0.2 eV.

5. The topological PN junction according to claim 3, characterized in that, The carrier concentration range of tellurium in the P-type region and the N-type region is 1e17 cm -3 ~1e19 cm -3 .

6. A method for regulating the topological quantum transport characteristics of a topological PN junction as described in any one of claims 1 to 5, characterized in that, Including the following steps: Applying a forward bias to the topological PN junction realizes the open state of the topological quantum transport characteristics of the topological PN junction; Applying a reverse bias to the topological PN junction realizes the closed state of the topological quantum transport characteristics of the topological PN junction; The ratio of the reverse breakdown voltage to the forward turn-on voltage of the topological PN junction is greater than 10.

7. The method for adjusting the topological quantum transport characteristics of the topological PN junction according to claim 6, wherein The forward bias applied to the topological PN junction is greater than the forward turn-on voltage of the topological PN junction; The reverse bias applied to the topological PN junction is less than the reverse breakdown voltage of the topological PN junction.

8. A method for preparing a topological PN junction as described in any one of claims 1 to 5, characterized in that, When the topological PN junction is a planar topological PN junction, it includes the following steps: Preparing a topologically semiconductor thin film; Performing P-type doping on the P-type region of the topologically semiconductor thin film; Performing N-type doping on the N-type region of the topologically semiconductor thin film; Performing annealing treatment on the topological PN junction; Preparing electrodes at both ends of the topologically semiconductor thin film; When the topological PN junction is a vertical topological PN junction, it includes the following steps: Preparing a bottom electrode; Preparing a P-type doped topologically semiconductor thin film; Performing N-type doping on the P-type doped topologically semiconductor thin film; Preparing a top electrode; Performing annealing treatment on the topological PN junction.

9. The method for preparing a topological PN junction according to claim 8, wherein When the topologically semiconductor is tellurium, in the process of preparing the topologically semiconductor thin film, physical vapor deposition method or solution method is used for preparation; During the process of P-type doping the P-type region of the topological semiconductor thin film, the P-type doping method is ion implantation or thermal diffusion, and the element for P-type doping is at least one of antimony, bismuth, arsenic, phosphorus, tin, and lead; During the process of N-type doping the N-type region of the topological semiconductor thin film, the N-type doping method is surface chemical treatment or atomic layer deposition; During the process of fabricating electrodes at both ends of the topological semiconductor thin film, electrode materials are deposited at both ends of the topological semiconductor thin film through evaporation coating technology; During the process of fabricating the bottom electrode, bottom electrode materials are deposited through evaporation coating technology; During the process of fabricating the P-type doped topological semiconductor thin film, physical vapor deposition is used; During the process of N-type doping the P-type doped topological semiconductor thin film, the N-type doping method is surface chemical treatment; During the process of fabricating the top electrode, top electrode materials are deposited through evaporation coating technology; During the annealing process, it is carried out in an inert gas atmosphere at a temperature of 200 - 350 °C for a time of 10 - 60 min.

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